Viper12Adip Viper12As: Low Power Off Line Smps Primary Switcher
Viper12Adip Viper12As: Low Power Off Line Smps Primary Switcher
Viper12Adip Viper12As: Low Power Off Line Smps Primary Switcher
®
VIPer12AS
BLOCK DIAGRAM
DRAIN
ON/OFF
60kHz
REGULATOR OSCILLATOR
INTERNAL PWM
S LATCH
SUPPLY OVERTEMP.
R1 FF Q
DETECTOR
R2 R3 R4
VDD _ +
BLANKING
8/14.5V _ 0.23 V
+
OVERVOLTAGE
LATCH 230 Ω
R
+
S FF Q
42V _
1 kΩ
FB
SOURCE
PIN FUNCTION
Name Function
Power supply of the control circuits. Also provides a charging current during start up thanks to a high
voltage current source connected to the drain. For this purpose, an hysteresis comparator monitors the
VDD voltage and provides two thresholds:
VDD - VDDon: Voltage value (typically 14.5V) at which the device starts switching and turns off the start up
current source.
- VDDoff: Voltage value (typically 8V) at which the device stops switching and turns on the start up current
source.
SOURCE Power MOSFET source and circuit ground reference.
Power MOSFET drain. Also used by the internal high voltage current source during start up phase for
DRAIN charging the external VDD capacitor.
Feedback input. The useful voltage range extends from 0V to 1V, and defines the peak drain MOSFET
FB current. The current limitation, which corresponds to the maximum drain current, is obtained for a FB pin
shorted to the SOURCE pin.
VDD DRAIN
I FB
FB CONTROL
VDD VD
SOURCE
VFB
VIPer12A
CONNECTION DIAGRAM
FB 3 6 DRAIN FB 3 6 DRAIN
SO-8 DIP8
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VIPer12ADIP / VIPer12AS
THERMAL DATA
Symbol Parameter Max Value Unit
Thermal Resistance Junction-Pins for:
Rthj-case SO-8 25 °C/W
DIP8 15
Thermal Resistance Junction-Ambient for:
Rthj-amb SO-8 (See note 1) 55 °C/W
DIP8 (See note 1) 45
Note: 1. When mounted on a standard single-sided FR4 board with 200 mm² of Cu (at least 35 µm thick) connected to all DRAIN pins.
3/15
VIPer12ADIP / VIPer12AS
OSCILLATOR SECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
FOSC Oscillator Frequency VDD=VDDoff ... 35V; Tj=0 ... 100°C 54 60 66 kHz
Total Variation
OVERTEMPERATURE SECTION
Symbol Parameter Test Conditions Min. Typ. Max. Unit
4/15
VIPer12ADIP / VIPer12AS
C L D
C << Coss
FB CONTROL 300V
90%
SOURCE
tfv trv VIPer12A
10% t
IDD0
VDDhyst
VDD
VDDoff VDDon
IDDch
VDS = 100 V
Fsw = 0 kHz
VDD
VDDon
VDD DRAIN
5/15
VIPer12ADIP / VIPer12AS
100V
ID 4mH
IDpeak
SOURCE
IFB 47nF VIPer12A
VFB
FBsd ⋅ FB
I R
IDpeak
∆I Dpea k
IDlim GID = – -----------------------
∆I FB
IFB
0 IFBsd
VDD
VDDon Automatic
start up
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VIPer12ADIP / VIPer12AS
1.01
1
Normalized Frequency
0.99
0.98
0.97
-20 0 20 40 60 80 100 120
Temperature (°C)
1.04
1.03
Normalized Current Limitation
1.02
1.01
1
0.99
0.98
Vin = 100V
0.97
Vdd = 20V
0.96
0.95
0.94
-20 0 20 40 60 80 100 120
Temperature (°C)
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VIPer12ADIP / VIPer12AS
DCOUT
R1 T1 C1
C2 D2
D1
D3
T2
F1
AC IN C3
D4 ISO1
+
U1
C4
VDD DRAIN
-
FB
C5 CONTROL
C6 SOURCE
VIPerX2A
C7
R2
D5
U2
R3 Vcc R4
Vref
R5 R6
C8 C9
- +
C10
+ -
GND
R7 R8 R9
TSM101
R10
GND
8/15
VIPer12ADIP / VIPer12AS
FEEDBACK PIN PRINCIPLE OF OPERATION In a real application, the FB pin is driven with an
A feedback pin controls the operation of the optocoupler as shown on figure 9 which acts as a
device. Unlike conventional PWM control circuits pull up. So, it is not possible to really short this pin
which use a voltage input (the inverted input of an to ground and the above drain current value is not
operational amplifier), the FB pin is sensitive to achievable. Nevertheless, the capacitor C is
current. Figure 9 presents the internal current averaging the voltage on the FB pin, and when the
mode structure. optocoupler is off (start up or short circuit), it can be
assumed that the corresponding voltage is very
The Power MOSFET delivers a sense current Is close to 0 V.
which is proportional to the main current Id. R2
receives this current and the current coming from For low drain currents, the formula (1) is valid as
the FB pin. The voltage across R2 is then long as IFB satisfies IFB< IFBsd, where IFBsd is an
compared to a fixed reference voltage of about internal threshold of the VIPer12A. If IFB exceeds
0.23 V. The MOSFET is switched off when the this threshold the device will stop switching. This is
following equation is reached: represented on figure 4, and IFBsd value is
R 2 ⋅ ( IS + IFB ) = 0.23V specified in the PWM COMPARATOR SECTION.
Actually, as soon as the drain current is about 12%
By extracting IS: of Idlim, that is to say 50 mA, the device will enter
0.23V a burst mode operation by missing switching
I S = -------------- – I FB cycles. This is especially important when the
R2
converter is lightly loaded.
Using the current sense ratio of the MOSFET GID :
It is then possible to build the total DC transfer
I D = G ID ⋅ IS = G ID ⋅ -------------- – IFB
0.23V function between ID and IFB as shown on figure 10.
R2 This figure also takes into account the internal
The current limitation is obtained with the FB pin blanking time and its associated minimum turn on
shorted to ground (VFB = 0 V). This leads to a time. This imposes a minimum drain current under
negative current sourced by this pin, and which the device is no more able to control it in a
expressed by: linear way. This drain current depends on the
primary inductance value of the transformer and
0.23V the input voltage. Two cases may occur,
IFB = – --------------
R1 depending on the value of this current versus the
By reporting this expression in the previous one, it fixed 50 mA value, as described above.
is possible to obtain the drain current limitation
START UP SEQUENCE
IDlim:
This device includes a high voltage start up current
IDlim = G ID ⋅ 0.23V ⋅ ------ + ------
1 1
source connected on the drain of the device. As
R 2 R 1 soon as a voltage is applied on the input of the
converter, this start up current source is activated
Figure 9 : Internal Current Control Structure as long as VDD is lower than VDDon. When
reaching VDDon, the start up current source is
DRAIN
switched off and the device begins to operate by
60kHz Id
turning on and off its main power MOSFET. As the
OSCILLATOR
FB pin does not receive any current from the
optocoupler, the device operates at full current
+Vdd S
PWM
Q
capacity and the output voltage rises until reaching
LATCH
R
Figure 10 : IFB Transfer function
Secondary
feedback
IDpeak
0.23V Is
IFB IDlim
1 kΩ
FB
R1
C 230 Ω R2
9/15
VIPer12ADIP / VIPer12AS
VDD VDD
VDDon VDDovp
VDDoff VDDon
tss VDDoff
t
t
IFB VDS
t t
VOUT
OVERVOLTAGE THRESHOLD
An overvoltage detector on the VDD pin allows the
VIPer12A to reset itself when VDD exceeds
VDDovp. This is illustrated in figure 12, which shows
the whole sequence of an overvoltage event. Note
t
that this event is only latched for the time needed
by VDD to reach VDDoff, and then the device
resumes normal operation automatically.
the regulation point where the secondary loop
begins to send a current in the optocoupler. At this
point, the converter enters a regulated operation
where the FB pin receives the amount of current
needed to deliver the right power on secondary
side.
This sequence is shown in figure 11. Note that
during the real starting phase tss, the device
consumes some energy from the VDD capacitor,
waiting for the auxiliary winding to provide a
continuous supply. If the value of this capacitor is
too low, the start up phase is terminated before
receiving any energy from the auxiliary winding
and the converter never starts up. This is illustrated
also in the same figure in dashed lines.
10/15
VIPer12ADIP / VIPer12AS
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.25 0.003 0.009
a2 1.65 0.064
a3 0.65 0.85 0.025 0.033
b 0.35 0.48 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.25 0.5 0.010 0.019
c1 45 (typ.)
D 4.8 5 0.188 0.196
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 3.81 0.150
F 3.8 4 0.14 0.157
L 0.4 1.27 0.015 0.050
M 0.6 0.023
S 8 (max.)
L1 0.8 1.2 0.031 0.047
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1
VIPer12ADIP / VIPer12AS
P001
12/15
VIPer12ADIP / VIPer12AS
B
C Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A A 3.2
B 6
C (± 0.1) 0.6
REEL DIMENSIONS
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.05) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
Start
13/15
1
VIPer12ADIP / VIPer12AS
A C
Base Q.ty 20
Bulk Q.ty 1000
Tube length (± 0.5) 532
A 8.4
B B 11.2
C (± 0.1) 0.8
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1
VIPer12ADIP / VIPer12AS
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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