Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A.

del Alamo

December 19, 2005 - Final Exam

problem grade
1
Name:
2
Recitation:
3
4
total

General guidelines (please read carefully before starting):

• Make sure to write your name on the space designated above.

• Open book: you can use any material you wish.
• All answers should be given in the space provided. Please do not turn in any extra material.
If you need more space, use the back of the page.
• You have three hours to complete your exam.
• Make reasonable approximations and state them, i.e. quasi-neutrality, depletion approxima-
tion, etc.
• Partial credit will be given for setting up problems without calculations. NO credit will be
given for answers without reasons.
• Use the symbols utilized in class for the various physical parameters, i.e. µn , ID , E, etc.
• Every numerical answer must have the proper units next to it. Points will be subtracted for
answers without units or with wrong units.
• Use φ = 0 at no = po = ni as potential reference.
• Use the following fundamental constants and physical parameters for silicon and silicon dioxide
at room temperature:

ni = 1 × 1010 cm−3
kT /q = 0.025 V
q = 1.60 × 10−19 C
s = 1.05 × 10−12 F/cm
ox = 3.45 × 10−13 F/cm
 1. (28 points) This problem studies an amplifier designed to boost a high-frequency signal midway
along a 50-Ω cable. A block diagram of the cable and amplifier is shown below, together with the
corresponding circuit.

large large
Amplifier
50-Ω cable 50-Ω cable

VCC VCC

R cable

T2
cable
large
T1
+
RS=50 Ω large
vout RL=50 Ω
-
vin +
- I1 I2

VEE VEE

In studying the amplifier, make use of the following information:

• To avoid undesired reflections within the input and output cables, the amplifier must be
designed to have a 50 Ω input resistance and a 50 Ω output resistance. (To learn why, take
6.013!)
• The coupling capacitors in the block diagram and circuit isolate the biasing inside the amplifier
from the cables. Assume the capacitors are large enough to be short circuits for the purposes
of all small-signal modeling.
• Assume that both transistors in the amplifier exhibit the same forward current gain β, the
same base-emitter capacitance Cπ , and the same base-collector capacitance Cµ . When nu-
merical values are needed, let βF = 200, Cπ = 1 pF, and Cµ = 0.1 pF. Also, let the thermal
voltage Vth be 25 mV. For both transistors, ignore their small-signal collector-emitter output
resistance until Part 1i).
• Assume that the two bias current sources in the amplifier, I1 and I2 , are ideal (i.e. their
associated internal resistance is infinity).
1a) (4 points) The amplifier comprises two stages. For each of the following objectives, explain in
a few sentences why the amplifier might be well-suited to meeting the objective.

2 50-Ω Input Resistance:

2 50-Ω Output Resistance:

2 High Voltage Gain:

2 High Bandwidth:

1b) (10 points) Draw a small-signal circuit model of the entire amplifier including the Thevenin
equivalent of the input cable, and the equivalent resistive load of the output cable. (Again,
ignore the coupling capacitors.) Clearly label the value of each component in the amplifier
model in terms of R, I1 , I2, βF and Vth . If you choose to label the components with symbols
such as gm and Rπ , make sure to express those symbols in terms R, I1 , I2 , β and Vth . (Neat
drawing and appropriate expressions expected).
[this page intentionally left blank]
1c) (2 points) Analytically determine the input resistance of the amplifier. Express the result in
terms of R, I1 , I2 , βF , Vth , and RL.

1d) (2 points) What must be the numerical value of I1 so that the input resistance found in Part
(1c) is 50 Ω?
1e) (2 points) Analytically determine the output resistance of the amplifier. Express the result in
terms of R, I1 , I2 , βF , Vth , and RS.

1f ) (2 points) Assume that the amplifier has been designed to have a 50 Ω input resistance and
a 50 Ω output resistance. In this case, analytically determine the small-signal midband gain
of the amplifier from vin to vout . Express the results in terms of R, I1 , I2 , β, Vth and
RS = RL = 50 Ω. To determine the small-signal midband gain, assume that Cπ and Cµ are
open circuits.
1g) (2 points) What must be the values of R and I2 so that the output resistance is 50 Ω and the
voltage gain is 25? (Numerical values expected.)

1h) (2 points) Numerically estimate the bandwidth of the amplifier under the assumption that it
has been designed to provide a 50 Ω input resistance, a 50 Ω output resistance, and a midband
gain of 25.
1i) (2 points) Assume that the Early Voltage of both transistors is 100 V. In a few sentences, explain
why it is reasonable to ignore their collector-emitter output resistances during the analyses
above.
2. (21 points) The device structure shown below has four terminals (W, X, Y, Z) and could be
viewed as a n-channel MOSFET or a lateral npn bipolar transistor depending on the voltage applied
to the various terminals. When operated as a MOSFET, Cox = 6.9 × 10−7 F/cm2 , γ = 0.26 V 1/2,
and VT = 0.11 V .

W n+ polysilicon Y Z

Silicon Dioxide 5 nm

N d=1020cm-3 N d=1020cm-3 N a=1020cm -3

oxide

0 L y
p-Si N a=1017 cm-3

(2a) (4 points) If the device is to be operated as an n-channel MOSFET, identify the terminals
(answer W, X, Y, or Z in the space provided below):

Source: Drain: Gate: Body:

(2b) (3 points) If the device is to be operated as a lateral npn BJT, identify the terminals (answer
W, X, Y, or Z in the space provided below).

Emitter: Base: Collector:

(2c) (2 points) For the device shown above, what is the flatband voltage of the MOS capacitor formed
by connecting terminals W, Y and Z to ground and varying the voltage in terminal X? (Numerical
answer expected).
(2d) (2 points) We operate the device as a bipolar transistor with VXW biased at the flatband voltage
of the MOS capacitor. What is the collector current if the device is biased with VCE = 2 V and
VBE = 0.6 V ? (Numerical answer expected).

(2e) (2 points) What is the transit time of electrons across the base region of the BJT when the
device is biased as in (2d)? (Numerical answer expected).
(2f) (4 points) Now we operate the device as a bipolar transistor with VXW = 0 V . What is the
collector current if the device is biased with VCE = 2 V and VBE = 0.6 V ? (Numerical answer
expected).
(2g) (2 points) If the device is to be used as a lateral npn BJT in the forward active regime, what is
the maximum voltage you should bias the gate relative to the source (VGS )? Explain. (Numerical
answer and suitable explanation expected).

(2i) (2 points) If the device is to be used as an n-channel MOSFET in the saturation regime, what is
the maximum voltage you should bias the body relative to the source (VBS )? Explain. (Numerical
answer and suitable explanation expected).
 3. (23 points) Consider the following amplifier below.

+2.5V

M2 M 10

M6
RS +
vS -
R 35kΩ
M 12
VBIAS
M3 M7
100 µA

X
M 11

M4 M8
VOUT

IO

M5 M9
M1 M 13

-2.5V

These are the relevant technology parameters:

VT n = 1.0 V , µnCox = 100 µA/V 2 , λn = 0.01 V −1

VT p = −1.0 V , µp Cox = 50 µA/V 2 , λp = 0.01 V −1

The sizes of the devices are as follows (first number indicates width, second number indicates length,
both in microns):

M1 = M5 = M9 = 8/1
M4 = M8 = 8/1
M3 = M6 = M7 = 50/1
M2= M10 = 16/1
M11 = M12 = 25/1
M13=?

(3a) (1 points) In the circuit schematic above, trace the signal path from input to output? (Neat
line expected).
(3b) (6 points) List the transistors that perform the following functions:

(i) Signal Amplifier:

(ii) Current Supply or Sink:

(iii) Voltage Reference:

(3c) (2 points) Determine VBIAS (Numerical answer expected).

(3d) (2 points) If IO = 200 µA, what is W/L for M13? (Numerical answer expected).

(3e) (4 points) Estimate the voltage gain at point X, that is, calculate vx /vs .(Numerical answer
expected).
(3f) (4 points) What is the output resistance of the amplifier? (Numerical answer expected).

(3g) (4 points) What are the minimum and maximum voltages that the output can swing? (Numer-
ical answers expected).
4. (28 points) Dynamic random-access memory (DRAM) is widely used in computer applications.
This is because DRAMs are relatively fast, can be made very dense and are fairly inexpensive.
Consider a one-transistor (DRAM) cell sketched below:

Vw

bit line Vb
CB

+
Cs -
Vs

word
line

In this DRAM cell, the information is stored in the form of charge in the capacitor Cs. If the voltage
across the capacitor Vs is HI, then a ”1” is stored. If Vs is LO, a ”0” is stored.

The ”word line” is used to select cells for reading or writing, as follows:

• if the word line is at ground (Vw = 0), the cells on that line are not selected for reading or
writing;
• if the word line is at Vw = VDD , the cells on that line are selected for reading or writing.

The ”bit line” is used to write or read the bits. It has three possible states:

• if the bit line is at Vb = VDD , a ”1” is to be written

• if the bit line is at Vb = 0 V , a ”0” is to be written
• if the bit line is floating, the stored bit in the capacitor is to be read.

In this problem you will analyze the basic operation of the DRAM cell. In this DRAM cell the
transistor is characterized by the following parameters: L = 1 µm, W = 4 µm, µn Cox = 50 µA/V 2,
VT = 1 V . The storage capacitor is Cs = 50 fF . The bit line has a capacitance CB = 500 fF .
VDD = 3.3 V .
2 Consider the operation of writing a ”1” when the cell had a ”0” stored at t = 0− , that is,
Vs (t = 0− ) = 0. At t = 0, the word line and the bit line are set to VDD (Vw = Vb = VDD ).

(4a) (2 points) In what regime is the transistor operating at t = 0+ ? Explain. (Suitable explanation
expected).

(4b) (2 points) In what regime is the transistor operating at t → ∞? Explain. (Suitable explanation
expected).
(4c) (4 points) Estimate the value of Vs at t → ∞. Explain your result. (Numerical answer and
suitable explanation expected).

(4d) (4 points) Estimate the charge in Cs at t → ∞. (Numerical answer expected).

(4e) (4 points) Estimate the time that it takes for the capacitor to charge up to 80% of its final
value. (Numerical answer expected).
2 Now consider the operation of writing a ”0” when the cell stored a ”1” at t = 0− , that is,
Vs (t = 0− ) = Vs (HI) from previous part (if you didn’t solve for (4c), assume that Vs (HI) = VDD ).
At t = 0, the word line is set to VDD (Vw = VDD ) and the bit line is set to zero (Vb = 0).

(4f) (2 points) In what regime is the transistor operating at t = 0+ ? Explain. (Suitable explanation
expected).

(4g) (2 points) In what regime is the transistor operating at t → ∞? Explain. (Suitable explanation
expected).
2 Now consider the operation of reading a ”1”. In this case, again, Vs (t = 0− ) = Vs (HI) (if you
didn’t solve for (4c), assume that Vs(HI) = VDD ). At t = 0, the word line is set to VDD (Vw = VDD )
and the bit line is left floating with an initial value Vb (t = 0− ) = 0.

(4h) (2 points) In what regime is the transistor operating at t = 0+ ? Explain. (Suitable explanation
expected).

(4i) (2 points) In what regime is the transistor operating at t → ∞? Explain. (Suitable explanation
expected).
(4j) (4 points) Estimate the value of Vb(t → ∞). (Numerical answer expected).
Spring 2001 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo

May 24, 2001 - Final Exam

problem grade
Name:
1
2
Recitation: 3
4
5

total
General guidelines (please read carefully before starting):

• Make sure to write your name on the space designated above.

• Open book: you can use any material you wish.
• All answers should be given in the space provided. Please do not turn in any extra material.
If you need more space, use the back page.
• You have 180 minutes to complete your exam.
• Unless stated otherwise, assume room temperature.
• Make reasonable approximations and state them, i.e. quasi-neutrality, depletion approxima-
tion, etc.
• Partial credit will be given for setting up problems without calculations. NO credit will be
given for answers without reasons.
• Use the symbols utilized in class for the various physical parameters, i.e. µn , ID , E, etc.
• Every numerical answer must have the proper units next to it. Points will be subtracted for
answers without units or with wrong units.
• Use φ = 0 at no = po = ni as potential reference.
• Use the following fundamental constants and physical parameters for silicon and silicon dioxide
at room temperature:

ni = 1 × 1010 cm
−3
kT /q = 0.025 V

q = 1.60 × 10−19 C

s = 1.05 × 10−12 F/cm

ox = 3.45 × 10−13 F/cm

1. (15 points) The figure below shows the measured transconductance characteristics of the n-
channel MOSFET that you characterized in Device Characterization Project #2. Each of the lines
represents a different value of VDS , starting with VDS,min = 0.25 V , in steps of ∆VDS = 0.25 V .

This device has L = 1.5 µm and W = 46.5 µm.

(1a) (10 points) In the space below, carefully sketch the gm vs. VGS characteristics predicted by the
ideal MOSFET model presented in 6.012. Indicate the evolution of gm for several values of VDS .
Derive suitable equations for each of the branches that you identify.
(1b) (5 points) From the data shown in the figure above, estimate VT and µn Cox for the measured
device.
2. (15 points) Consider the two-stage BiCMOS differential amplifier below.

VCC=+5 V

RD RD RC=1K RC=1K

+
vO2
M1 M2 Q1 Q2 -
+ +
vI1 vI2
- -

I1=1 mA I2=5 mA

VEE=-5 V

M1 and M2 are identical and are biased in the saturation regime. Q1 and Q2 are also identical and
are biased in the forward active regime. Suitable parameters for these transistors are:

nMOSFET: VT = 1 V and W
L µn Cox = 0.1 mA/V 2

npn BJT: βF = 250, VBEon = 0.7 V and VCEsat = 0.2 V

The current sources I1 and I2 need at least 0.5 V across to operate properly.

(2a) (5 points) Compute the power dissipation of this amplifier.

(2b) (5 points) What constraint is imposed on RD so that the amplifier can properly handle a
maximum common-mode input of 3 V ? (Express your answer as RD > X or RD < X. Give value
of X).
(2c) (5 points) If RD = 5 kΩ, what is the maximum possible voltage swing of node VO2 with respect
to ground? Give VO2min and VO2max .
3. (25 points) Consider the two-stage bipolar current amplifier shown below. At the input of this
amplifier there is a signal source with an internal resistance RS = 2.5 kΩ; at the output, there is a
load characterized by RL = 2.5 kΩ.

VCC=+5 V

I1=1 mA I2=1 mA

iOUT

Q1 Q2
RC=2.5 KΩ

is RS IBIAS

signal source
RS=2.5 KΩ

VEE=-5 V

Both transistors in this amplifier are identical and are characterized by the following parameters:
βF = 100 and VA = 50 V . Treat all biasing current sources as ideal, that is, with infinite internal
resistance.

(3a) (10 points) Draw a two-port low-frequency small-signal equivalent-circuit model of the first
stage of this amplifier. Derive values for all elements of this two-port model.
[this page left blank intentionally]
(3b) (10 points) Draw a two-port low-frequency small-signal equivalent-circuit model of the second
stage of this amplifier. Derive values for all elements of this two-port model.
(3c) (5 points) Calculate the loaded current gain Ai = iout
is of this amplifier.
4. (15 points) The diagram below shows an unloaded common-source amplifier with a current
source supply. The adjoining table describes the relationship between device parameters and circuit
parameters for this amplifier stage.

VDD

iSUP
signal source Device ∗ Circuit Parameters
Parameters |Avo | Rin Rout ωH
RS iD +
ISU P ↑ ↓ - ↓
vOUT W ↑ ↑ - -

vs µn Cox ↑ ↑ - -

- L↑ ↑ - ↑
VGG

VSS

In this table, when changing one of the device parameters, adjustments are made to VGG , the gate
bias, so that none of the other parameters are affected.

In this problem, you have to fill the fourth column of this table that contains the 3dB bandwidth of
the amplifier. Use the same format as in the rest of the table and indicate in what direction ωH will
change when the device parameters increase one at a time. Nothing else changes, except perhaps
for VGG as explained above. In the space below, provide an explanation for your entry. If there is
no explanation, there are no points!

(4a) (3 points) If ISU P ↑, how does ωH change? Select: ↑, −, ↓. Why?

(4b) (3 points) If W ↑, how does ωH change? Select: ↑, −, ↓. Why?

(4c) (3 points) If µn Cox ↑, how does ωH change? Select: ↑, −, ↓. Why?

(4d) (3 points) If L ↑, how does ωH change? Select: ↑, −, ↓. Why?

(4e) (3 points) If we now connect the output of the amplifier to a load resistance RL  ro //roc , how
does ωH change? Select: ↑, −, ↓. Why?
5. (30 points) Consider the following CMOS amplifier:

VDD

signal source
RS

+
vs
vOUT RL
VGG
-

VSS

The devices are characterized by the following parameters:

nMOS: Ln = 1 µm, Wn = 4 µm, µn Cox = 50 µA/V 2 , VT n = 1 V , λn = 0.1 V −1 , Cgsn = 6 f F ,

Cgdn = 1 f F , Cdbn = 5 f F .
pMOS: Lp = 1 µm, Wp = 8 µm, µp Cox = 25 µA/V 2 , VT p = −1 V , λp = 0.1 V −1 , Cgsp = 12 f F ,
Cgdp = 2 f F , Cdbp = 10 f F .

Other values are: VDD = 5 V , VSS = −5 V , RS = 1 kΩ, and RL = 1 kΩ.

(5a) (5 points) Compute the value of VGG required to obtain a quiescent output voltage VOUT = 0 V .
A low-frequency small-signal equivalent circuit model for this amplifier in an unloaded configuration
at the bias point specified in part (5a) is given below:

+ +
vin Gmovin Rout vout
- -

with Gmo = 1.6 mS and Rout = 3.1 kΩ.

(5b) (5 points) Calculate the loaded voltage gain of the entire CMOS amplifier (don’t be alarmed if
it comes out a bit small, this is not a very good amplifier).
(5c) (15 points) Estimate the 3 dB bandwidth of the entire CMOS amplifier (that is, in its loaded
configuration). To do this, calculate the time constant of each capacitor at a time (six capacitors at
2 points each). Then compute the 3 dB bandwidth in Hz (3 points).
[this page left blank intentionally]
(5d) (5 points) Calculate the voltage swing of the output node of this amplifier in its loaded confi-
turation.
Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo

October 13, 2005 ­ Quiz #1

problem grade
1
Name:
2
Recitation:
3
4

total

General guidelines (please read carefully before starting):

• Make sure to write your name on the space designated above.

• Open book: you can use any material you wish.
• All answers should be given in the space provided. Please do not turn in any extra material.
If you need more space, use the back page.
• You have 120 minutes to complete your quiz.
• Make reasonable approximations and state them, i.e. quasi­neutrality, depletion approxima­
tion, etc.
• Partial credit will be given for setting up problems without calculations. NO credit will be
given for answers without reasons.
• Use the symbols utilized in class for the various physical parameters, i.e. µn , ID , E, etc.
• Every numerical answer must have the proper units next to it. Points will be subtracted for
answers without units or with wrong units.
• Use φ = 0 at no = po = ni as potential reference.
• Use the following fundamental constants and physical parameters for silicon and silicon dioxide
at room temperature:

ni = 1 × 1010 cm−3

kT /q = 0.025 V

q = 1.60 × 10−19 C

�s = 1.05 × 10−12 F/cm

�ox = 3.45 × 10−13 F/cm

1. (25 points) A bar of silicon is doped with acceptors as shown below. The doping density variers
smoothly and motononically in the x direction from NA � ni at x = 0 to NA � ni at x = L.
Na (L/2) = ni . Around x = L, the acceptor profile becomes uniform. The donor density is zero
everywhere. This is a thermal equilibrium situation.

log Na uniform�
doping
Nd=0 Na(x)
ni

0 L L x
2

On the basis of this description, answer the following questions by circling the correct answer. Write
a brief justification for your choice below.

(1a) (2 points) Where is the hole concentration the greatest?

x=0 0 < x < L/2 x = L/2 L/2 < x < L x=L uniform

(1b) (2 points) Where is the electron concentration the greatest?

x=0 0 < x < L/2 x = L/2 L/2 < x < L x=L uniform

(1c) (2 points) In which direction does the hole diffusion current flow?

−�x no current +�x

(1d) (2 points) In which direction does the hole drift current flow?

−�x no current +�x

(1e) (2 points) In which direction does the electron diffusion current flow?

−�x no current +�x

(1f) (2 points) In which direction does the electron drift current flow?

−�x no current +�x

(1g) (2 points) In which direction does the electric field point?

−�x no field +�x

(1h) (2 points) Where is the electrostatic potential the greatest?

x=0 0 < x < L/2 x = L/2 L/2 < x < L x=L uniform
(1i) (3 points) In the axis provided below, sketch the volume charge density along x.

ρ(x)

0
0 L L x
2

(1j) (3 points) In the axis provided below, sketch the electric field distribution along x.

E(x)

0
0 L x
L
2

(1k) (3 points) In the axis provided below, sketch the electrostatic potential distribution along x.
Use as reference φ = 0 at no = po = ni .

φ(x)

0
0 L L x
2
2. (10 points) Consider an MOS structure on an n­type substrate:

VGB
+­

"metal"�
(n+ polySi)

semiconductor�
oxide (n type)
contact contact

-tox 0 x

The doping level in the substrate (or body) is ND = 1017 cm−3 . The doping level in the gate is
+
ND = 1020 cm−3 .

(2a) (5 points) In the axis below, qualitatively sketch the volume charge density across this structure
at zero bias. Explain your result.

ρ(x)

0
-tox 0 L x
(2b) (5 points) Calculate the flatband voltage of this structure (numerical answer with appropriate
sign and units expected).
3. (30 points) Consider a pn junction at zero bias with an electric field distribution as sketched
below. The metallurgical junction is placed at x = 0.

E(x) [V/cm]

105

0
0 50 100 x [nm]

(3a) (10 points) Calculate the depletion capacitance at zero bias (numerical answer with appropriate
sign and units expected).

(3b) (5 points) Calculate the built­in potential (numerical answer with appropriate sign and units
expected).
(3c) (5 points) Estimate the doping type and doping level of the region between 50 < x < 100 nm
(numerical answer with appropriate sign and units expected).
(3d) (5 points) What can you say about the doping type and doping level of the region between
0 < x < 50 nm?

(3e) (5 points) What can you say about the doping type and doping level of the region defined as
x < 0?
4. (40 points) Consider a MOS structure as sketched below:

VGB
+­

"metal"�
(n+ polySi)

semiconductor�
oxide (p type)
contact contact

-tox 0 x

The oxide thickness os tox = 50 nm and the doping level in the substrate is Na = 1016 cm−3 .

This problem is about calculating the hole concentration at x = 0 (the oxide­semiconductor interface)

under the following conditions:

(4a) (10 points) At flatband (numerical answer with appropriate sign and units expected).

(4b) (10 points) At threshold (numerical answer with appropriate sign and units expected).
(4c) (10 points) At a condition in which the potential build up from the quasi­neutral body of the
semiconductor to x = 0 is 0.5 V (numerical answer with appropriate sign and units expected).
(4d) (10 points) At a condition when the capacitance per unit area of the MOS structure is
50 nF/cm2 (numerical answer with appropriate sign and units expected).
Spring 2001 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo

March 14, 2001 - Quiz #1

problem grade
1
Name:
2
Recitation:
3
4
5
6

total
General guidelines (please read carefully before starting):

• Make sure to write your name on the space designated above.

• Open book: you can use any material you wish.
• All answers should be given in the space provided. Please do not turn in any extra material.
If you need more space, use the back page.
• You have 120 minutes to complete your quiz.
• Make reasonable approximations and state them, i.e. quasi-neutrality, depletion approxima-
tion, etc.
• Partial credit will be given for setting up problems without calculations. NO credit will be
given for answers without reasons.
• Use the symbols utilized in class for the various physical parameters, i.e. µn , ID , E, etc.
• Every numerical answer must have the proper units next to it. Points will be subtracted for
answers without units or with wrong units.
• Use φ = 0 at no = po = ni as potential reference.
• Use the following fundamental constants and physical parameters for silicon and silicon dioxide
at room temperature:
ni = 1 × 1010 cm
−3
kT /q = 0.025 V

q = 1.60 × 10−19 C

s = 1.05 × 10−12 F/cm

ox = 3.45 × 10−13 F/cm

1. (10 points) Compute the equilibrium electron and hole concentrations, no and po , for silicon at
room temperature doped with:

(1a) (2 points) Boron (B) concentration = 1017 cm−3 .

(1b) (2 points) Phosphorus (P) concentration = 5 × 1016 cm−3 and Antimony (Sb) concentration =
5 × 1016 cm−3 .

(1c) (2 points) Arsenic (As) concentration = 1017 cm−3 and Boron (B) concentration = 1016 cm−3 .

(1d) (4 points) In (1a) above, what is the magnitude of the electric field that must be applied to the
sample for the magnitude of the majority carrier drift velocity to be equal to 106 cm/s?
2. (10 points) An engineer is told that a region of silicon of length 20 µm, width 5 µm and thickness
1 µm is uniformly doped with a single kind of dopant with a concentration of 1020 cm−3 . Ohmic
contacts are formed at the ends of the region and she measures the I-V characteristics given in the
table below. Is the sample n-type or p-type? Explain how you reach this conclusion. [Hint: think
about the sample resistance.]

W=5 µm

t=1 µm
voltage (V) current (A)
0 µm
0 0 L=2
1 0.025 _
2 0.05 +
V
3. (10 points) In a certain n-type region of a semiconductor in thermal equilibrium, there is a hole
concentration with the following spatial distribution:

po (x) = 103 (1 − 9 × 103 x) cm−3 for 0 ≤ x ≤ 10−4 with x in cm

Assume that in this region, the electron mobility and hole mobilities are µn = 500 cm2 /V · s and
µp = 200 cm2 /V · s, respectively.

(3a.) (5 points) Derive an expression for and sketch the hole diffusion current density in this region.
(3b.) (5 points) Derive an expression for and sketch the electric field distribution in this region.
4. (20 points) Consider an abrupt pn junction with Na = 1017 cm−3 and Nd = 1016 cm−3 , as
sketched below.

Na

Nd

0 x

4a) (6 points) Compute the value of the electrostatic potential at x = 0 in thermal equilibrium
(numerical answer expected).
4b) (4 points) Compute no and po at x = 0 in thermal equilibrium (numerical answer expected).

4c) (5 points) Compute the value of x for which no = po = ni in thermal equilibrium (numerical
answer expected).
4d) (5 points) Compute the total amount of charge per unit area on the p side of the junction when a
reverse bias voltage of 5 V is applied to the diode (numerical answer with appropriate sign expected).
5. (30 points) Consider the following MOS structure:

VGB

n+ polySi

oxide p-Si
contact (Na=6x1017 cm-3)
contact

-tox 0 x

The oxide thickness is tox = 5 nm = 5 × 10−7 cm. To save you time, for this structure:

1 �
γ= 2s qNa = 0.65 V 1/2
Cox

(5a) (5 points) Compute the threshold voltage of the structure (numerical answer with appropriate
sign expected).
(5b) (5 points) What is the value of VGB that leads to a sheet charge density in the inversion layer
of Qn = −10−6 C/cm2 ?(numerical answer expected).

(5c) (5 points) What is the magnitude of Eox (electric field across the oxide) for a condition in which
QG = −2 × 10−7 C/cm2 ? (numerical answer expected).
(5d) (5 points) What is the magnitude of Es = E(x = 0+ ) (electric field on semiconductor side of
oxide-semiconductor interface) at threshold? (numerical answer expected).

(5e) (10 points) What is the capacitance of the MOS structure at a bias point for which the total
charge in the semiconductor is equal to −2 × 10−7 C/cm2 ? (numerical answer expected).
6. (20 points) Consider a MOSFET made out of the MOS structure of problem 5. The gate length
is L = 1 µm. The gate width is W = 10 µm. The electron mobility in the channel is 200 cm2 /V · s.

The MOSFET is biased with VDS = 0.1 V , VGS = 1 V and VBS = 0 V . If you did not compute the
threshold voltage of this structure in section (5a), assume it to be 0.5 V .

(6a) (10 points) Compute the magnitude of the inversion layer charge density at the source-end of
the channel: |Qn (y = 0)| (numerical answer expected).
(6b) (10 points) Compute the magnitude of the electron velocity at the source-end of the channel:
|vy (y = 0)| (numerical answer expected).
Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo

November 16, 2005 ­ Quiz #2

problem grade
1
Name:
2
Recitation:
3
4

total

General guidelines (please read carefully before starting):

• Make sure to write your name on the space designated above.

• Open book: you can use any material you wish.
• All answers should be given in the space provided. Please do not turn in any extra material.
If you need more space, use the back of the page.
• You have 120 minutes to complete your quiz.
• Make reasonable approximations and state them, i.e. quasi­neutrality, depletion approxima­
tion, etc.
• Partial credit will be given for setting up problems without calculations. NO credit will be
given for answers without reasons.
• Use the symbols utilized in class for the various physical parameters, i.e. µn , ID , E, etc.
• Every numerical answer must have the proper units next to it. Points will be subtracted for
answers without units or with wrong units.
• Use φ = 0 at no = po = ni as potential reference.
• Use the following fundamental constants and physical parameters for silicon and silicon dioxide
at room temperature:

ni = 1 × 1010 cm−3

kT /q = 0.025 V

q = 1.60 × 10−19 C

�s = 1.05 × 10−12 F/cm

�ox = 3.45 × 10−13 F/cm

1. (30 points) Below is an n+ ­ polysilicon­gate MOSFET. The substrate doping is Na = 1017 cm−3
and the insulator thickness is 5 nm. The gate length L = 0.25 µm while the gate width is W =
2.5 µm. The inversion layer mobility for the MOSFET is µN = 250 cm2 /V · s.

A capacitance voltage curve of the n+ poly­silicon gate MOSFET was taken by connecting the
source, drain and body terminals together. A voltage was applied between the gate and the body.
With the device biased as follows: VBS = 0 V , VDS = 0.1 V , VGS = 1.11 V , answer the following
questions:

(1a) (5 points) Calculate the sheet charge density at the drain end of the device, Qn(y = L)
(numerical answer expected).
(1b) (5 points) Calculate the electron drift velocity at the drain end of the device, vn (y = L)
(numerical answer expected).

(1c) (5 points) Calculate the electron drift velocity in the middle of the channel vn(y = L/2)
(numerical answer expected).
(1d) (5 points) This device is now desired to operate at VDS = 1.8 V and VGS = 1.35 V with a
current ID = 1 mA. This requires shifting the threshold voltage VT by means of an applied body
voltage, VBS . What is VT in this situation? (Numerical answer expected).
(1e) (5 points) For the bias conditions of (1d), compute the sheet charge density at the source end
of the channel Qn(y = 0) (numerical answer expected).

(1f) (5 points) For the bias conditions of (1d), calculate the electron drift velocity at the source end
of the channel, vn (y = 0) (numerical answer expected).
2. (30 points) The circuit diagram for an NMOS inverter driving a load capacitance CL, and a
graph of its static input­output characteristics, are shown below. The graph actually shows two sets
of characteristics, the desired characteristics and the measured characteristics. The two are different
because the actual inverter was not fabricated exactly as it was designed. The point of this problem
is to determine what went wrong during fabrication.

DC Inverter Characteristic
4
V+=VDD Desired
Measured
3.5

Output Voltage [V]

2.5

VOUT 2

1.5
VIN
CL 1

0.5

0
0 0.5 1 1.5 2 2.5 3
Input Voltage [V]

The circuit parameters under suspicion are the MOSFET gate width to length ratio, W/L, the
MOSFET gate oxide thickness, tox , the MOSFET body doping level, Na , and the pull­up resistance,
R. Further, assume that one and only one of these four parameters was incorrectly fabricated.

(2a) (3 points) From the graph of the desired characteristics, estimate the desired threshold voltage
VT of the MOSFET (numerical answer expected).

(2b) (3 points) From the graph of the measured characteristics, estimate the actual threshold voltage
VT of the MOSFET (numerical answer expected).
(2c) (3 points) From the graph of the desired characteristics, estimate the product of the desired
pull­up resistance R and the desired K parameter of the MOSFET (where K = W µ C ). That is,
L n ox
estimate the desired product RK (numerical answer expected).
(2d) (3 points) From the graph of the measured characteristics, estimate the product of the actual
pull­up resistance R and the actual K parameter of the MOSFET (where K = W µ C ). That is,
L n ox
estimate the actual product RK (numerical answer expected).
In answering the following questions, remember to assume that one and only one of the four param­
eters was incorrectly fabricated.

(2e) (3 points) Could the gate width to length ratio, W/L, have been incorrectly fabricated? Why
or why not? If ”Yes”, is it too big or too small? (Appropriate explanation expected).

Circle One: Yes No

(2f) (3 points) Could the gate oxide thickness, tox , have been incorrectly fabricated? Why or why
not? If ”Yes”, is it too big or too small? (Appropriate explanation expected).

Circle One: Yes No

(2g) (3 points) Could the body doping density, Na , have been incorrectly fabricated? Why or why
not? If ”Yes” is it too big or too small? (Appropriate explanation expected).

Circle One: Yes No

(2h) (3 points) Could the pull­up resistance, R, have been incorrectly fabricated? Why or why not?
If ”Yes” is it too big or too small? (Appropriate explanation expected).

Circle One: Yes No

You observe that when the inverter is driving a known load capacitance CL , one of the propagation
delays (tP LH and tP HL ) is not as desired. In particular, the propagation delay from a rising input
to a falling output is longer than expected, while the propagation delay from a falling input to a
rising output is exactly what was expected.

(2i) (6 points) Based on all available evidence, which circuit parameter was incorrectly fabricated?
What is the ratio of the actual parameter divided by the desired parameter? (Appropriate explana­
tion expected).
3. (24 points) An pn diode at a certain forward bias point is characterized by the following values
of small­signal equivalent circuit elements:

rd = 25 Ω Cd = 40 pF

At this bias point, the depletion capacitance is negligible with respect to the diffusion capacitance.

In the following questions, you are asked to estimate how the values of these two elements change if
the diode is modified in several ways. Assume that in all cases, the diode is ideal, very asymmetric,
and that all its behavior is dominated by its lowly doped side. State any other assumptions you
need to make.

(3a) (4 points) The diode area is doubled. Nothing else is changed. The diode is biased at the same
current as in the problem statement (numerical answers expected).
(3b) (4 points) The diode area is doubled. Nothing else is changed. The diode is biased at the same
voltage as in the problem statement (numerical answers expected).
(3c) (4 points) The doping level of the lowly doped side is doubled. Nothing else is changed. The
diode is biased at the same current as in the problem statement (numerical answers expected).
(3d) (4 points) The doping level of the lowly doped side is doubled. Nothing else is changed. The
diode is biased at the same voltage as in the problem statement (numerical answers expected).
(3e) (4 points) The thickness of the lowly doped side is doubled. Nothing else is changed. The diode
is biased at the same current as in the problem statement (numerical answers expected).
(3f) (4 points) The thickness of the lowly doped side is doubled. Nothing else is changed. The diode
is biased at the same voltage as in the problem statement (numerical answers expected).
4. (16 points) Consider a CMOS logic gate driving a capacitive load CL. The inverter is made with
minimum size transistors, as sketched below:

VDD=5 V

6/1.5

VIN VOUT

3/1.5
CL=0.1 pF

In the above diagram, the two numbers next to each transistor give its gate dimensions (width/length)
in microns. In solving this problem, assume that CL is the dominant capacitance in this circuit. All
other capacitances can be neglected next to CL .

The technology is defined by the following circuit parameters plus other geometrical parameters:

Parameter Name HSPICE Symbol NMOS PMOS units

Zero bias threshold VTO 0.75 ­0.75 V
voltage
Oxide thickness TOX 1.5E­08 1.5E­08 m
Transconductance KP 100E­06 50E­06 A/V 2
parameter µCox
1.5 1.5
Channel­length LAMBDA 7E­02 L(µm) 7E­02 L(µm) V −1
modulation parameter
Zero bias planar bulk CJ 1E­04 3E­04 F/m2
depletion capacitance
Zero bias sidewall bulk CJSW 5E­10 3.5E­10 F/m
depletion capacitance
Bulk junction potential PB 0.9 0.9 V
Planar bulk junction MJ 0.5 0.5 dimensionless
grading coefficient
Sidewall bulk junction MJSW 0.33 0.33 dimensionless
grading coefficient
Diffusion length Ldif f 4.5 4.5 µm
Minimum transistor length Lmin 1.5 1.5 µm
Minimum transistor width Wmin 3 6 µm
(4a) (8 points) Estimate the energy stored in the load capacitor when the output is HI (numerical
answer expected).
(4b) (8 points) Estimate the power dissipated by this inverter when it is run at 100 MHz (numerical
answer expected).
Spring 2001 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo

April 18, 2001 - Quiz #2

problem grade
1
Name:
2
Recitation:
3
4
5

total
General guidelines (please read carefully before starting):

• Make sure to write your name on the space designated above.

• Open book: you can use any material you wish.
• All answers should be given in the space provided. Please do not turn in any extra material.
If you need more space, use the back page.
• You have 120 minutes to complete your quiz.
• Make reasonable approximations and state them, i.e. quasi-neutrality, depletion approxima-
tion, etc.
• Partial credit will be given for setting up problems without calculations. NO credit will be
given for answers without reasons.
• Use the symbols utilized in class for the various physical parameters, i.e. µn , ID , E, etc.
• Every numerical answer must have the proper units next to it. Points will be subtracted for
answers without units or with wrong units.
• Use φ = 0 at no = po = ni as potential reference.
• Use the following fundamental constants and physical parameters for silicon and silicon dioxide
at room temperature:

ni = 1 × 1010 cm
−3
kT /q = 0.025 V

q = 1.60 × 10−19 C

s = 1.05 × 10−12 F/cm

ox = 3.45 × 10−13 F/cm

1. (25 points) You are given a CMOS inverter with the following parameters:

VT n = 0.5 V tox = 10 nm µn = 400 cm2 /V · s

VT p = −1 V λn = λp = 0.1 V −1 µp = 200 cm2 /V · s
VDD = 5 V Ln = Lp = 1 µm

(1a) (5 points) Calculate the ratio Wp /Wn so that VM = 2.5 V .

(1b) (5 points) We want this inverter to have an average propagation delay tp = 1 ns when driving
a CL = 1 pF capacitive load. Calculate Wn and Wp .
(1c) (10 points) Estimate N ML and N MH for this inverter.
(1d) (5 points) Sketch and appropriately label the voltage transfer characteristics of this inverter.
2. (20 points) You are given the following I-V characteristics for a n-MOSFET with tox = 10 nm,
W = 10 µm, and L = 1 µm. The gate material is n+ -doped polysilicon. The body is tied up to the
source.

A B

In (A), gm = 1.4 × 10−4 A/V . In (B), go = 5.7 × 10−5 A/V .

(2a) (5 points) From (A), estimate the threshold voltage, VT .

(2b) (5 points) From (A), estimate the electron mobility, µn .
(2d) (5 points) Estimate the saturation voltage, VDSsat , and the saturation current, IDsat , corre-
sponding to the characteristics in (B).

(2e) (5 points) From (B), estimate the length of the channel pinch-off region, ∆L, at VDS = 4 V .

3. (20 points) An n-channel MOSFET is wired up in the form indicated below. This is an
enhancement-mode device (VT > 0). Neglect channel length modulation.

I
+

(3a) (10 points) In terms of usual MOSFET parameters, derive suitable equations for the I-V char-
acteristics of the resulting two-terminal device. Sketch the I-V characteristics in a linear scale.
(3b) (10 points) Sketch a complete high-frequency small-signal equivalent circuit model for this two-
terminal device for situations in which V > VT . Express all small-signal elements in terms of those
of the MOSFET, i.e.: as a function of gm , go , Cgs , Cgd , Csb , etc.
4. (15 points) An NMOS inverter with a resistor pull up was miswired and ended up as sketched
below.

VDD=5 V

VIN

VOUT

R=1 KΩ CL

The parameters of the transistor are: µn Cox = 50 µA/V 2 , W/L = 5, and VT = 1 V . Neglect channel
length modulation in this problem.

(4a) (5 points) For VIN = 0, in what regime is the transistor biased? How much is VOUT ? (numerical
answer expected).
(4b) (10 points) For VIN = 5 V , in what regime is the transistor biased? How much is VOUT ? (you
can leave the result in the form of an equation where VOUT is the only unknown).
5. (20 points) In a certain pn junction diode at room temperature at a particular forward bias
voltage, the current supported by hole injection into the n-side of the diode is 100 µA.

The quasi-neutral width of the n-side of the diode is wn − xn = 1 µm. The hole diffusion coefficient
is 10 cm2 /s. The pn junction area is 10 µm2 .

Make and state suitable approximations.

(5a) (5 points) Estimate the hole concentration at the space-charge region edge of the n quasi-neutral

region. (numerical answer expected).

(5b) (5 points) Estimate the velocity at which holes are injected at the edge of the n quasi-neutral
region (numerical answer expected).
(5c) (5 points) Estimate the hole flux arriving at the surface of the n quasi-neutral region. (numerical
answer expected).

(5d) (5 points) Estimate the diffusion capacitance associated with hole storage in the n quasi-neutral
region. (numerical answer expected).