2016 IEEE Computer Society Annual Symposium on VLSI

Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications

Sanjay Singh Rajput1, Ashish Singh2, Ashwani K. Chandel3, Rajeevan Chandel4

1,2,4
Electronics & Communication Engineering and 3EE Departments
National Institute of Technology Hamirpur 177 005
Himachal Pradesh, India
1
[email protected], [email protected], [email protected], [email protected]

Abstract—In the present paper, an operational amplifier (Op- Low-power and high-gain are particularly the major
Amp) topology that achieves high-gain and low-power dissipation requirements of monitoring and recording bio-potential signals
is designed and analyzed. The design uses a current mirror with (heart, brain, pulse etc.) for medical diagnosis. Modern
a class-A output stage having capacitive Miller compensation. clinical practice requires these signals to be routinely
The low power operational amplifier is the main active power
consuming block. The proposed Op-Amp operates at ±0.75V
recorded. It is usually the practice that patients are connected
supply voltage and consumes a total power of 1.83mW with the to cumbersome recording devices for the purpose of acquiring
gain  90dB. The proposed design has been implemented using signals from the body to aid diagnosis. This affects their
Tanner EDA Tools for 90nm CMOS technology node. mobility and causes general discomfort. This affects the
general diagnosis of ailments [3-6].
Keywords—bio-medical; high-gain; low-power; operational The coupling of bio-potential signals from the body into
amplifier the electronic equipment is accomplished through electrodes.
These electrodes interface ionic currents in the body with
I. INTRODUCTION electrical currents in the electronic instruments. In practice,
because the electrode comprises the first stage of the signal

R ealization of low-power high-gain system design is

always a difficult goal as both requirements almost
contradict each other. The increasing demand for portable
chain, its properties can dominate the overall noise and
performance of the acquisition system making its design and
selection crucially important. Broadly three classes of bio-
equipment and its applicability in bio-medical applications has potential electrodes are reported in the literature namely wet,
enhanced the importance of low power circuit design. The dry, and non-contact [7].
trend towards implementing systems with low supply voltages Rapid developments in medical science have led to the
has created a challenging task in the design of VLSI analog daily use of biomedical equipment. The functions of
circuits. Circuit designs with low power dissipation are biomedical equipment have become increasingly complex,
reported in literature [1]. Recently, significant efforts have along with the inbuilt electronic circuitry. It has become a
been invested in reducing power consumption of the trend to miniaturize and integrate the electronic circuits in
operational amplifiers and developing circuits that operate biomedical systems [3-6]. Depending on the types of bio-
with extremely small voltage supply [1]. However, it is potential signals that are to be monitored, these will have
envisaged that the implementation of low-power circuit design different frequency bands from sub-hertz to a few hundred
is limited by many factors [1-2]. hertz. This makes it difficult to design one system for
One of the most dominating factors in determining the monitoring different bio-potential signals [3-6].
performance of low-power system design is the gain of the Operational amplifiers, the most commonly used building
system. For achieving high-gain in a system, high supply blocks in analog circuits, are usually considered as the design
voltage is needed to ensure that no transistor goes in cutoff bottleneck in low-voltage and low-power applications,
state [1-2]. However, use of high supply voltage costs more as partially the analog to digital converters. In analog circuits,
it results in higher power dissipation in the system. Another settling behavior of the Op-Amp usually determines the
important constraint that limits the use of small supply voltage accuracy and speed of the circuit. High accuracy and fast
is signal-to-noise ratio (SNR) [1-2]. In CMOS circuits, the settling requires a high DC gain and a high unity-gain
dynamic power consumption is quadratically dependent to the frequency, respectively. Thus a high-gain high-speed
supply voltage. This results in a significant reduction in power architecture in low-voltage applications is of much interest in
consumption as the supply voltage decreases. But in analog the state-of-the-art amplifier designs.
CMOS circuits sharing the same supply voltage, results in Different techniques have been reported in literature to
increase in power dissipation in order to achieve the same increase the DC gain. Cascading multiple stages and
SNR. Thus, there exists a trade-off between supply voltage enhancing output impedance are two of the common methods.
and SNR. Consequently, the realization of low power circuits Cascading two or more stages can produce high DC gain yet
together with high speed, high SNR, high-gain and large gain- applicable for low-voltage applications. However cascading
bandwidth product demands innovative circuit design results in stability issues. Thus much more design efforts are
techniques. required in order to compensate these issues [8]. Output

978-1-4673-9039-2/16 $31.00 © 2016 IEEE 355

DOI 10.1109/ISVLSI.2016.62
impedance enhancement can be implemented using different as shown by circle with dashed line in Fig. 2. The input stage
methods, e.g. cascading, gain boosting and applying positive is simple n-channel differential amplifier with current-source
feedback [9]. Employing the cascode configuration and gain loads. This gives the widest possible input common mode
boosting requires at least stacking four transistors from top rail range, with enhancement MOSFETs without using the parallel
to bottom rail. This consumes more voltage head, which may input stage. The p-channel transistors whose source terminals
not be appropriately implemented in low-voltage circuits [9]. are connected to the output of the differential amplifier are
Thus design of low power and high gain amplifier for bio- biased so that the voltage across the source-drain terminals of
medical applications is the need. Hence, the present work is an the current-source load is V SD (sat ) . This gives the maximum
attempt in this direction. input common-mode voltage and allows the power supply to
This paper presents the design of a low-power, high-gain vary without limiting the positive input common-mode
and highly stable amplifier for bio-medical applications. Low- voltage. The differential amplifier stage facilitates in
power dissipation, high-input common mode range (ICMR), achieving high gain in the system. The inputs are given as out-
high-gain and high-phase margin are achieved. The rest of the of-phase to the common source NMOS connected in
paper is organized as follow. Section II presents the design of differential form. Owing to the differential configuration, the
low-power high-gain operational amplifier. Results and dc gain is high but at the same time this has the limitation of
discussion are presented in section III. Concluding remarks are low output swing. To make better output-swing output stage in
given in section IV. the form of common source stage is connected with
II. DESIGN OF LOW-POWER AND HIGH-GAIN OP-AMP compensation capacitor.
A two-stage amplifier is designed, with the first stage being 2) Current Mirror Circuit
a simple differential stage and the second stage is a common Design of low power Op-Amp consists of a current mirror
source stage, having a compensation capacitor. In between the circuit as shown by rectangular box with dashed line in Fig. 2.
first and the second stage a current mirror topology is used
The high gain of LPHG Op-Amp is because of the current
that works as a sink for the current. The current mirror sums mirror circuit used in between the input and output stages. The
the differential current of first stage, feeding it to the second current mirror circuit folds the differential-ended output
stage by the current mirror action. This topology provides
current of the input stage into single-ended output stage. This
highly stable system with a high gain and it also provides low is performed using transistors M6, M7 and M8, M9
power dissipation. Thus a low power high gain operational respectively in current mirror circuit. The current mirror
amplifier requires designing of sub-circuits. The various
circuit forms a cascade current sink and therefore leads to
transistors and components need to be configured to class-A operation, which boosts the overall gain. The
accomplish the required specifications. Hence a proper design maximum sinking/ sourcing current flows in the load
methodology is essential. These are detailed in this section.
capacitor. This increases the output trans-conductance. This
current is then used to bias the output stage transistor (M14) in
A. Sub-Circuits to the saturation region, such that the output stage amplifies
The main sub-circuits namely a differential stage, current the single-ended output of the first stage.
mirror, and output common source stage (also called class-A
amplifier) utilized in the present design are presented here. 3) Output Stage
Fig.1 shows a simple block diagram of designed low-power This stage is implemented using a simple common source
high-gain (LPHG) Op-Amp. amplifier which is also called as class-A amplifier. To reduce
the output resistance and increase the current driving
capability, a simple approach is to increase the bias current in
the output stage. This is effectively achieved by using a simple
Class-A at the output stage and using Miller compensation for
the second stage gain. Its schematic is shown and marked by a
Differential Output Stage circle with solid line in Fig. 2.
Input Output
Amplifier Current Mirror (Common Source
Signal Signal
Stage Amplifier) B. Low-Power High-Gain Operational Amplifier (LPHG Op-
Amp) Circuit
To design an Op-Amp, various difficulties occur with
lower power supplies of the level of 2VT [12]. The limit of low
Fig. 1. Block diagram of LPHG Op-Amp. power supply voltage is related to the desired input common
mode range. The LPHG Op-Amp is a current sink Op-Amp
1) Input Stage that provides high gain at lower supply voltage with very
The differential amplifier represents the input stage and small power dissipation.
is the main circuit block of low-power high-gain operational
amplifier. It consists of differential-input single-ended output

356
 Equations (1) to (18) present the design relationships that 2I3 (9)
VDS 3 =
are used in designing the overall proposed circuit. The dc gain k ∗ ¨ 3 ·¸
§
' W
© L3 ¹
n
of the Op-Amp AV (0) is given as
Equation (10) is used to calculate the saturation voltage
Av (0) = GMI * RI * RII * GMII (1) across M5 ( V DS 5( SAT ) ). It is given as,
where Av (0) is the dc gain of Op-Amp, G MI and G MII are the VICM ( MIN) = VDS5( SAT ) + VGS1 (10)
overall trans-conductance of the first and the second stages of where VICM (MIN) is the minimum input common-mode voltage.
Op-Amp respectively. R I and R II are the overall resistance Relationship to calculate aspect ratio of M5 is obtained as,
of first and second stages of Op-Amp respectively. VDS 5 =
2 I5 (11)
kn' ∗ §¨ 5 ·¸
First step involves the computation of compensation W
© L5 ¹
capacitance ( Cc ). It is derived from angle equation of the Op-
Similarly, (12) and (13) give the relationships to find the
Amp transfer function [12]. C c optimizes the phase margin of
aspect ratio of M6, M7 and M8, M9 respectively.
the system. This in turn makes system more stable. It is given
W6 W 7 2∗I
as = = ' 112 (12)
L6 L7 K P ∗ VSD
C c ≥ 0 .611C L (2)
W8 W9 2 ∗ I8
= = (13)
' 2
where C L is the load capacitor. L8 L9 K P ∗ V DSB
Next step of design flow is to compute trans-conductance of where I11 is the current through transistor M11, K P' is process
input transistors M1 and M2, in order to calculate their aspect
ratio. The input stage amplifier trans-conductance is given as, transconductance parameter of PMOS, VSD represents source-
drain voltage across transistor M6. Equation (13) is used to
G M 1 = GB ∗ C c (3) design the current mirror circuit in the proposed LPHG Op-
where G M 1 the trans-conductance of input stage transistors. GB Amp.
is unity gain bandwidth. Bias current to generate biasing Since the transistors M5, M10 and M16 are configuered in
voltage is given by current mirror circuit. The current through all these three
I Bias = C c ∗ SR (4) transistors are same. Consequently, their aspect ratios are the
where I Bias is the bias current and SR is the slew rate. same.
To compute aspect ratio of M11 and M12, (14) is used.
MOSFET current (Id) in saturation region is defined by (5). This gives the relation between current ( I 11 ) through M11,
I d = k ' ∗ (W ) ∗ (VGS − VT ) 2 (5)
L source to drain voltage across M11 (V SD11 ) and process trans-
Equation (5) is used to drive the relationship in terms of conductance of M11 which is given as,
aspect ratio and the other known parameters values. It is W11 W12 2 ∗ I 11
= = (14)
defined in (6). L11 L12 K P' ∗ V SD
2
11
2
W1 W2 g m1 (6)
= = The gate to source voltage of M8 (VGS8) is defined as
kn' §¨ 1 ·¸
L1 L2 I
© 2¹ VGS 8 = V DD − 2VON (15)
where g m1 is the trans-conductance of M1 and is the k n' where, VON is the saturation voltage, which drive the
process trans-conductance parameter of NMOS transistor. transistors into the saturation region. This voltage is used to
Using aspect ratio from (6), gate to source voltage ( VGS 1 ) of calculate the gate to source (VGS8) voltage of transistor M8 that
helps in calculating the size of transistor M8.
transistor M1 is computed and given by (7). The aspect ratio of M13 is computed using current through
2 I1 M13 ( I 13 ) , M12 ( I12 ) and aspect ratio of M12. It is given as,
VGS 1 = (7)
k ∗ ¨ 1 ·¸
§
' W
n
© L1 ¹ W13 § I13 · § W12 ·
= ¨ ¸∗¨ ¸ (16)
For transistor M3 to be in saturation region of operation, the L13 © I12 ¹ © L12 ¹
source to drain saturation voltage of M3 ( VSD3( SAT ) ) is The relationship between trans-conductance of transistors M1
computed using (8). and M14 is defined in (17). Using (17), aspect ratio of M14 is
VICM( MAX ) = VDD − VSD3( SAT ) + VTN (8) computed. These are given as,
where VICM (MAX ) is the maximum input common-mode g m14 = 10 g m1 (17)
voltage, V DD is supply voltage and VTN represents threshold W gm
= (18)
voltage of NMOS transistor. L k n' ∗ V DS ( sat )
Subsequently, (9) is used to determine the aspect ratio of M3
and M4 transistors as The advantage of the topology used in the present work is
that it can be used at various low supply voltages with
negligible variation in power consumption and gain.

357
 Fig. 3. Frequency response of LPHG Op-Amp.

Fig. 2. Schematic of LPHG Op-Amp.

Owing to the higher gain and lower power consumption,

this type of Op-Amp topology is at-most suited for bio-
medical applications and is analyzed in the present paper. The
proposed schematic of low-power high-gain operational
amplifier is presented in Fig. 2

III. RESULTS AND DISCUSSION

Tanner EDA tool is used for the performance evaluation of
the proposed LPHG Op-Amp at 90nm CMOS technology
node [12]. The aspect ratios (W/L) of the transistors of LPHG
Op-Amp are computed using the formulations presented in (1)
to (18). The aspect ratios and the dimensions computed for
various transistors in the LPHG Op-Amp design are specified
in Table I.
The aspect ratios of the M13 and M14 transistors are kept
large in order to achieve high gain. This also facilitates in
achieving high unity gain bandwidth (UGB). This is Fig. 4. Transient output swing with sine input of LPHG Op-Amp.
particularly important for bio-medical applications where high
gain amplifiers are required to achieve high quality output This high gain enables this circuit to perform efficiently in
signals. Also the reason of large aspect ratios is the high unity the close loop system. It is further seen from the figure that
gain bandwidth (UGB) required for the design. To fulfill these phase margin of the system is 70°. This makes the system
conditions aspect ratios need to increase as attained from eq. highly stable. Higher phase margin implies that the close loop
(4), gives the relation between UGB and the trans-conductance poles are located far away from origin which makes the
( g m1 ) of first stage. Fig. 3 shows the frequency response of system less oscillatory. The unity gain bandwidth is attained at
the LPHG Op-Amp. It is used to determine the gain of the 11 MHz, which does not satisfied the specification used for
system. From the figure, it is investigated that the gain is designing LPHG Op-Amp but this much of unity gain
93dB. bandwidth is sufficient for a system to operate at high speed,
as there is always conflict between the gain and the bandwidth
TABLE I. DESIGN SPECIFICATIONS OF THE TRANSISTORS IN THE LPHG OP- achievement with the low power dissipation. From the above
AMP
discussions it is studied that the proposed Op-Amp attains
W (m)
S.No. Transistors (W/L)
& L=90nm high-gain and high-phase margin with low-power dissipation.
1 M 1, M 2 20 1.8μ Fig. 4 shows the output transient response of the LPHG Op-
2 M 3, M 4 21 1.89μ Amp. The input swing applied to the Op-Amp is -10mV to
3 M5, M10, M16 2.5 0.225μ 10mV. From the figure, the measured output swing is -700mV
4 M6, M7, M11, M12 17 1.53μ to 750mV. Thus the amplification of nearly 70 times is
5 M 8, M 9 1 90n achieved with high accuracy using the proposed Op-Amp.
6 M13 320 28.8μ This implies that the Op-Amp discussed in the present work is
7 M14 80 7.2μ aptly suited for biomedical applications where the signal
8 M15 30 2.7μ strength is very weak and signal frequency low.

358
 The Input common mode range (ICMR) defines the linear TABLE II. SUMMARY OF PERFORMANCE OF THE DESIGNED
part of transfer curve where the slope is unity. The ICMR of LPHG OP-AMP
LPHG Op-Amp is evaluated and shown in Fig. 5. It represents Results
Parameters Specifications [18]
the transfer characteristics between the output voltage (VOut) Obtained
and current through M5 (I5) with respect to input voltage Technology 90nm 0.5μm 90nm
Gain 90dB 110dB 93dB
(VIN). It is the range of value of input VIN where VOUT get
Phase Margin 75 95 70
saturated as the maximum ICMR to the value of VIN where I5
Slew Rate 20V/μSec - 20V/μSec
get saturated as the minimum ICMR. This is an important ICMR -1V to 2V - -0.9V to 1.4V
parameter which is extracted, as it gives the range in which -1.25V
input voltage variations do not affect the analysis. 1.5V Peak to 1.45V Peak to
Output Swing to
Peak Peak
+1.35V
Supply Voltage ±0.75V ±1.5V ±0.75V
Power
<4mW 27.8μW 1.83mW
Dissipation
Gain Bandwidth
30MHz 320kHz 11MHz
(GB)
Area (mm2) 0.025 0.034 0.00459

Fig. 5. Input common mode range (ICMR) of LPHG Op-Amp.

Fig. 6, shows the transient response of the LPHG Op-Amp,

the number of ripples at the output is less and with some delay
output follows the input. Less number of ripples is because of
the high phase-margin of this Op-Amp. From this graph the
change between the output-voltage with respect to time is
determined, which gives the slew rate. A high value of the
slew rate is good. Here the slew rate is exactly the same as the
specifications for the design.

Fig. 6. Slew rate analysis of LPHG Op-Amp.

Fig. 7. Layout of LPHG Op-Amp.

The performance parameters used for the LPHG Op-Amp
are presented in Table II. The various parameters considered A comparative analysis is carried out between the desired
are gain, phase margin, slew rate input common mode range, specification of the Op-Amp, and the results obtained using
output swing, supply voltage, power dissipation and gain the designed values for the simulative analyses. It is seen that
bandwidth. both the results are in a fairly good agreement. This verifies

359
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