Digital Logic Design: Sessional Marks:40 End Exam: 3 Hours End Exam Marks:60

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Digital Logic Design

Course Code - Category: IT 124 - ES Credits: 3


L T P E O
Sessional Marks:40
3 0 0 1 6
End Exam: 3 Hours End Exam Marks:60

Course Objectives:

 To identify various number systems and work with Boolean algebra.


 To understand the concepts of Boolean Algebra various logic gates.
 To simplify the Boolean expression using K-Map and Tabulation techniques.
 To analyze various types of flip flops used for designing registers and counters.

SYLLABUS

UNIT I 8 Periods
BINARY SYSTEMS:
Digital Computers and digital systems – Binary Numbers – Number Base conversions – Octal,
Hexadecimal. Numbers Complements – . Complement Arithmetic; n’s complement and (n-1)’s
complement. Representation of signed binary numbers , Binary Codes-Decimal Codes- BCD,
NBCD, Excess-3 BCD, Error- Detection Codes, The Reflection Code, Alphanumeric Codes,
Registers, Register Transfer. Binary Logic, Truth table, logic operations- AND, OR, NOT, NAND,
NOR, Ex-OR, Ex-NOR. De Morgan’s theorem.
UNIT II 12 Periods
BOOLEAN ALGEBRA & Logic Gates: Basic Definitions, Basic Properties of Boolean algebra,
Boolean functions, Boolean Algebra – Basic Theorems and properties – Boolean Functions –
Canonical and Standard Forms, Other logical operations, Digital Logic gates.
UNIT III 10 Periods

SIMPLIFICATION OF BOOLEAN FUNCTIONS


The Map Method-Karnaugh Map Simplification – Two, Three, Four and Five Variables Maps,
Product of Sums simplification, NAND and NOR Implementation , Don’t Care Conditions, The
Tabulation Method, Determination of prim- implicants, Selection of Prime implicants.
UNIT IV 10 Periods
COMBINATIONAL LOGIC CIRCUITS
Combinational Circuits – Adder - Subtractor – Design and Analysis procedures – Binary Parallel
Adder – Decimal Adder – Encoder – Decoder – Multiplexer – Demultiplexer – Magnitude
comparators – Read Only Memory (ROM)

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UNIT V 10 Periods
SEQUENTIAL LOGIC CIRCUITS
Sequential circuits – Latches – Flip-flops – Triggering of Flip-Flops – Analysis of clocked sequential
circuits – State reduction and state assignment – Design procedure of clocked sequential circuits –
Design of counters – Registers – Shift registers – Ripple counter and Synchronous counter.

Text Books:

1. Morris Mano M., “Digital Logic and Computer Design”, [ UNIT 1 - Chapter 1 , UNIT 2 –
Chapter 2 , UNIT 3 – Chapter 3, UNIT 4 – Chapter 4 & 5, UNIT 4 – Chapter 6& 7] Pearson
Education, 1/e, 2010.

Reference Books:
1. Raj Kamal “Digital Systems Principles and Design” First Edition, Pearson Education, 2007.
2. Charles H.Roth, Jr. and Larry L. Kinney, “Fundamentals of Logic Design”, Seventh
Edition, CL Engineering, 2013.

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