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    A VHDL REview basedON) Tutorial June 30 To Students

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    dd sasdsd
    This document provides instructions for a self-check VHDL laboratory exercise. Students are asked to design a 4-bit and 16-bit adder using components, including additional circuits to output flags. They are also tasked with using behavioral modeling to create designs for examples from Section 8 in ModelSim. The work is to be done on June 30th and July 1st from 3:30-5:50pm, with screenshots and captions due by 5:50pm on July 1st. The instructor is Professor Izidor Gertner.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    A VHDL REview basedON) Tutorial June 30 To Students

    Uploaded by

    dd sasdsd
    29 views2 pages
    This document provides instructions for a self-check VHDL laboratory exercise. Students are asked to design a 4-bit and 16-bit adder using components, including additional circuits to output flags. They are also tasked with using behavioral modeling to create designs for examples from Section 8 in ModelSim. The work is to be done on June 30th and July 1st from 3:30-5:50pm, with screenshots and captions due by 5:50pm on July 1st. The instructor is Professor Izidor Gertner.

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    A_VHDL_REview_basedON)Tutorial__June_30_To_Students

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    This document provides instructions for a self-check VHDL laboratory exercise. Students are asked to design a 4-bit and 16-bit adder using components, including additional circuits to output flags. They are also tasked with using behavioral modeling to create designs for examples from Section 8 in ModelSim. The work is to be done on June 30th and July 1st from 3:30-5:50pm, with screenshots and captions due by 5:50pm on July 1st. The instructor is Professor Izidor Gertner.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views2 pages

    A VHDL REview basedON) Tutorial June 30 To Students

    Uploaded by

    dd sasdsd
    This document provides instructions for a self-check VHDL laboratory exercise. Students are asked to design a 4-bit and 16-bit adder using components, including additional circuits to output flags. They are also tasked with using behavioral modeling to create designs for examples from Section 8 in ModelSim. The work is to be done on June 30th and July 1st from 3:30-5:50pm, with screenshots and captions due by 5:50pm on July 1st. The instructor is Professor Izidor Gertner.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    CSC 343 Summer 2021

    Self-Check (Review) Laboratory Exercise Part A


    Vhdl REVIEWVerify correctness using waveforms in Model-Sim
    Use LPM (Library Parameterized Modules) to create 3-8 decoder, 1-8 demultiplexer
    Work on June 30. And July 1, 2021 Time 3:30-5:50 Pm
    Submit report by 5:50 PM ,July 1, 2021
    Instructor: Professor Izidor Gertner

    What to Submit:
    Please post on direct private channel to Instructor just Figures with SCREENSHOTS of
    waveforms. Figure Captions should state IN ONE SENTENCE why the design is correct.
    The file name has to have your last name and title, signals have to have your last name as a
    prefix.
    Report is required , video is not required to submit. QAR file is required with
    Last_name_READMYFIRST file is required.
    Grade will be given for this Self-Check lab.
    A Check Mark will be assigned. The criteria used for Check Mark (✔) A check
    mark, checkmark or tick (✓) is a mark used to indicate the concept "yes" (e.g.
    "yes; this has been verified", "yes; that is the correct answer", "yes; this has been
    completed".

    Please use VHDL tutorial as a guide.


    https://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html
    What to read for review:
    • Section 2 Levels of representation and abstraction
    • Section 3. Basic Structure of a VHDL file
    • Section 5. Data Objects: Signals, Variables and Constants ( pay attention to
    ARRAYS and MATRIXES) you will need it later.
    • Section 8. Behavioral Modeling: Sequential Statements (VERY
    IMPORTANT! To MASTER)
    • Section 9. Dataflow Modeling – Concurrent Statements
    •
    What to Do:
    Task A1
    1. Design an N bit adder ( for N=4, and N=16)as shown in Figure 4 using
    components, (pay attention to master port map concept; using
    components your design)
    2. Task A2. Design additional circuit to the adder to output
    N= negative FLAG ( Signal N =1 if the result is negative
    Z= ZERO FLAG ( Signal Z =1 if the result is ZERO
    O= overflow FLAG ( Signal O =1 if the result produces overflow
    result.

    3. Create you project in Model SIM only, Write a testbech file to verify
    N=16 bit design.

    Task A2
    CSC 343 Summer 2021
    Self-Check (Review) Laboratory Exercise Part A
    Vhdl REVIEWVerify correctness using waveforms in Model-Sim
    Use LPM (Library Parameterized Modules) to create 3-8 decoder, 1-8 demultiplexer
    Work on June 30. And July 1, 2021 Time 3:30-5:50 Pm
    Submit report by 5:50 PM ,July 1, 2021
    Instructor: Professor Izidor Gertner

    Use Behavioral model as described in section 8. Create designes for all


    examples described in section 8 inModel SIM.

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