1

1.0 INTRODUCTION
1.1 Background of the Study
Counters

Counters, as the name suggests, are for counting a sequence of values. According to
Menkiti, A.I (2011), a counter is any circuit that has the characteristic of storing the number
of times an event occur (often using a clock signal) is referred to as a counter. However,
there are many different types of counters depending on the total number of count values,
the sequence of values that it outputs, whether it counts up or down, and so on. The simplest
is a modulo-n counter that counts the decimal sequence 0, 1, 2 … up to n-1 and back to 0.
Some typical counters are described next. Counting circuits are of two types namely; Batch
counting circuits and Measurement counting circuits (Bozie, S.M.,1979).

Counters of all kinds are used in a variety of digital circuits. The kinds of counters used
include binary counters, Gray code counters, ring counters, and up-down counters. Most
of these counters cycle through a number of states, each state representing a natural
number. Because of this cyclic behavior, the next state can be determined from the present.

Givart ,S and Halmos, p.(2009) revealed that computer information is expressed in binary
(bit) because of the convenience of handling two clearly defined states; each of the bit
containing a “1” (HIGH) or a “0” (LOW). Some typical counters are described next.

Modulo-n counter: Counts from decimal 0 to n – 1 and back to 0. For example, a modulo-
5 counter sequence in decimal is 0, 1, 2, 3, and 4.

Binary coded decimal (BCD) counter: Just like a modulo-n counter, except that n is fixed
at 10. Thus, the sequence is always from 0 to 9.

n- bit binary counter: Similar to modulo-n counter, but the range is from 0 to 2n – 1 and
back to 0, where n is the number of bits used in the counter. For example, a 3-bit binary
counter sequence in decimal is 0, 1, 2, 3, 4, 5, 6, and 7.
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Gray-code counter: The sequence is coded so that any two consecutive values must differ
in only one bit. For example, one possible 3-bit gray-code counter sequence is 000, 001,
011, 010, 110, 111, 101, and 100.

Ring counter: The sequence starts with a string of 0 bits followed by one 1 bit, as in 0001.
This counter simply rotates the bits to the left on each count. For example, a 4-bit ring
counter sequence is 0001, 0010, 0100, 1000, and back to 0001.

An up-down counter behaves differently. It counts up or down, depending on the input

received.

For many counters, the value of the counter, or its count, can be read by the environment.
Sometimes, however, there is no need to be able to read the value of the counter. In the
case of a modulo-N counter, for example, it can be sufficient to detect when the count
modulo N is equal to zero. In the case of an up-down counter with a counting range from
zero through N, it can be sufficient to detect when the counter’s value is one of the
boundary values. In [DNS92], for example, an up-down counter is used to find out whether
a FIFO-queue is empty, full, or neither empty nor full. In [EG93a] the use of an up-down
counter is proposed for a similar purpose.

In this report we specify and design up-down counters that count in the range from zero
through 31. We call such counters up-down 5- bit counters. Being able to detect whether a
counter’s value is zero is called empty detection. Detecting whether the counter’s value is
N is called full detection.

We want to investigate whether or not it is possible to design N-counters with empty and
full detection of which emptiness and fullness can be detected within an amount of time
independent of N after an input has been sent to the counter. If only empty and full detection
are required in a specific application, such a counter could have a faster response time than
a readable counter for which the detection of boundary values is implemented a posteriori.
A readable up-down N counter requires a number of “memory cells” that is at least
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logarithmic in N. It is hard to imagine that in such a counter the new value can be read after
an amount of time independent of N, if no broadcasting of signals is allowed.

In the design of counters we can distinguish between synchronous and asynchronous

counters. In this report we devote our attention to asynchronous counters, i.e., counters that
do not use a global clock signal. Before giving some advantages of asynchronous circuits,
we briefly discuss synchronous counter implementations.

Selection of Counter design:

The chosen design for the 4-bit counter is a simple 4-bit synchronous counter with
synchronous set and reset option and input and output carry option. The reasons behind
choosing this design are

i. Synchronous counter is the most used and reliable counter design

ii. Synchronous design ensures that all the output bits change simultaneously at the
edge of a clock signal and holds that output until the next clock signal
iii. Low propagation delay than asynchronous counter
iv. The set reset options become effective with clock edge signal, so the outputs do
not change suddenly in mid-clock-period.
v. Set/ reset options allows to clear the count data to start new counting session.
vi. Carry in and carry out allows 8-bit or higher bits counters by cascading.

Selection of Flip-flop:

The basic building block of a counter is flip-flop. The choice of flip-flop depends on the
logic function of the circuit. The logic function of the counter suggests a T flip flop as most
appropriate for the design, but we chose to use a J K Flip flop for the following reasons

i. J K flip flop allows to include both set and reset feature in it which can also be
synchronous with the clock.
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ii. A T flip flop can be easily produced from a J K flip flop by applying the same input to
both J and K pin.

Application:

Counter is used widely in number of digital and analog circuit. There are vast application
of counter in the field of electronics. Some of them are listed below

i. A counter can be used as frequency divider. This 4-bit counter can be efficiently
used to get four different frequencies up to one sixteenth times of the original clock
frequency. Since it is triggered only at negative edge of the clock, the first cycle
gives output at half the frequency of that of the clock.
ii. Counter can be used on building entrances to keep track of number of people
entering or leaving.
iii. Counter can be used in digital logic deigns to perform certain operation at certain
steps.
iv. Counters are also applicable in timer circuit to turn on/ off a device after.

1.2 Statement of Problem

Keeping record in our contemporary time has over the years been an alarming challenge to
man, as every event that occur is very important and needs to be kept record of so that
decisions will be made due to the experience of the previous events to enable man have
control over his environment. For example, in a big organization where everyone is at his
or her duty post record may be needed of the number of people who enter into the
organization through the public gate every day. A well could be designed specifically to
perform this task.

Since record keeping is very important and paramount in the contemporary time to enable
wise and accurate decisions, well designed counters will provide a remedy for the
prevailing problems (related to record keeping and data reservation) with the proper
implementation of engineering design on this perspective.
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1.3 Aim and Objectives

1.3.1 Aim

The main aim of this project is to design and build a 5Bits synchronous up/down
(even/odd) counter using JK flip flop and to have the requisite and basic knowledge on
how to design counters

1.3.2 Objectives

i. To design a 5bit up and down counter using JK flip flop

ii. To design a BCD (binary coded decimal) to display the output on the 7-segment
display
iii. To design a counter that count up even numbers and count down odd numbers
iv. To simulate the design on Proteus environment
v. To show the output using LEDs

1.4 Significance of the Study

The 5bits up and down (even end odd) counter is very useful in getting the basic knowledge
for designing of different counters most especially young under graduates who are intending
to go into electronics and logic as their area of specialization. This study will give the
students the requite knowledge to becoming practical engineers who will provide solutions
to the prevailing problems in the aspect of data keeping thereby controlling the environment
as so desired (i.e. making accurate and proper decisions and predictions)

1.4.1 Importance/benefits

i. A counter can be used as frequency divider. This 5-bit counter can be efficiently
used to get four different frequencies up to one-thirty second times of the original
clock frequency. Since it is triggered only at negative edge of the clock, the first
cycle gives output at half the frequency of that of the clock.
ii. Counter can be used for building entrances to keep track of number of people
entering or leaving.
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iii. Counter can be used in digital logic deigns to perform certain operation at certain
steps.
iv. Counters are also applicable in timer circuit to turn on/ off a device after.
1.5 Scope of the Study
The basic building block for counters is the flip flop. There are many types of flip flops
which includes; T flip flop, D flip flop, SR flip flop and the JK flip flop but the choice of
using any of them is dependent on the problem your design is to solve. Thus this study is
limited to 5bits up/down (even/odd) counter using JK flip flop to count up even numbers
and to count down odd numbers.
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2.0 LITERATURE REVIEW

2.1 Theoretical Framework

In digital logic, counters are devices which are often used in relationship with a clock signal
to store the number of times an event or process occur (Rajat, K.D and Pattathurani, L.,
20117). Counters are widely used as the essential building block for variety of circuit
operations (Raja, R.G and Deepak, K., 2016). Counters may be classified into two as
synchronous and asynchronous counters.

Synchronous counters: A synchronous counter usually consist of two parts; the memory
element and the combinational element. The memory element is implemented using the
flip flops and the combinational element can be implemented in a number of ways; using
the logic gates is the traditional method of implementing combinational circuits which has
been for decades. Since this method often results in a minimum component cost for many
combinational systems, it is still a popular approach. However, there are other methods of
implementing combinational logic circuit that offers other advantages. They includes; the
use of multiplexers (MUX), Read Only Memory (ROM), programmable logic array.

Asynchronous counters: These are also called ripple counters. They are mot clocked by a
common pulse and hence every flip flop in the counter changes at different times. The flip
flop in an asynchronous counter is usually clocked by the output pulse of the preceding flip
flop. The first flip flop is clocked by the external event.

The comparison between synchronous and asynchronous counters is shown below

Table 1: Comparison Between Synchronous and Asynchronous Counters

Asynchronous counters Synchronous counters

1. Slow in counting They are fast

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2. Requires less circuitry Their circuits are larger

3. Requires no logic gate They require logic gates
4. It is resurgent because of low Consumes more power
power consumption
5. All the flip flops are not connected All the flip flops are connected to the same
to the same pulse clock signal

Binary up/down counter: the similarity between the implementation of a binary up counter
and a binary down counter leads to the possibility of having a binary up/down counter.
These counters have the ability to count both up and down a sequence of numbers based
on how it is designed. This project makes use of this type of counter.

2.2 Conceptual Framework

We have developed, in the course of this project, the idea of selecting the most preferred
state device for this project to be JK flip flop. It can store a logic state of either a “0” (LOW)
or a “1” (HIGH) and wait until a changing signal from the digital clock is applied. With
our sequence of counting 0 – 30 for up (even) counting and 31 – 1 for down (odd) counting,
we were able to select, with our knowledge of the timing diagram, the appropriate and
constant frequency for the clock signal and we connected all the flip flops such that the
same clock signal is supplied to them. We have selected the JK flip flop as the preferred
state device for the following reasons;

i. J K flip flop allows to include both set and reset feature in it which can also be
synchronous with the clock.
ii. A T flip flop can be easily produced from a J K flip flop by applying the same input to
both J and K pin.

2.2.1 Development of block diagram

To make the design analysis of this counter easier, the whole circuit design was split into
individual block or unit each of which formed a crucial part of the design analysis such that
the absence of any may render the design incomplete. Thus, each block was designed
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individually as a single circuit and afterwards combined together to have the desired
counter circuit. The block diagram (design algorithm) is shown below

Combinational JK Flip Flops 5Bits to BCD LED status

circuit decoder Indicator

power circuit Clock circuit Seven segment display

Figure 1: Block Diagram for 5Bits SynchronousUup/Down Counter

2.3 Review of Related Empirical Studies

To design a modified, appreciable, functional and more stable counter and also to acquire
the basic knowledge of digital logic, we made efforts to study many journals and related to
this topic to acquire our design some of these paper and works are summarized as follows;

Rajat, K.D. and Pattatherani, L. (2017) designed a synchronous counter using a SRAM
which was basically the modification of the an existed counter which used D flip flop and
CMOS where the transistors were connected in series and the power supplied to the
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transistors was used by all the succeeding transistors. This design was less of hardware
complexity, low cost for fabrication mechanical flexibility, strong optical and efficient
emission.

Harish Naik,K.P., et al (2014) proposed a reversible T Latch with which they designed a
4Bits synchronous counter

Tejaswini, M. and Raji, C. (2016) proposed and designed an optimized up/down

synchronous counter using reversible logic gates. They used the proposed T flip flop to
design a 4Bit synchronous up/down counter achieving optimization in terms of cost metrix
of reversed quantum cost, delay, number of garbage output and number of constant inputs.

Ramya, A. et al (2013) an asynchronous up/ down counter using a proposed 9T flip flop.
They made a comparison between the designed counter and a latch and the existing counter
and discovered that their design had reduced power consumption and reduced area
compared to the existing ones.

Sandhya, V. et al (2014) designed a 4Bit up and down counter using node pulse hybrid flip
flop which used clock gating technology and a dual mode logic. The clock gating was used
to disable the clock signal when the input data does not change the stored data. This design
was used to modify the performance improvement of the designs to which the dual mode
logic was introduced. They used the dual mode logic to achieve low power and high power
requirements.

Calvignac,et al. (2012).Having designed and simulated a 4-stage binary counter by CMOS
techniques on 65 nm technology using Microwind and DSCH 3.1 Software. They cascade
four D register to make 4- stage counter. Each D register was formed by connecting two D
flip flop and a NOT gate.

Sandeep Thakur,etal.(2016).Designed and simulated 4-bit ring counter using 45 nm

technologies. They designed a master slave D flip flop using NAND gate and an inverter
and four D flip flop were cascade to form counter. Flip flop were provided with same clock
pulse because of synchronous nature of the ring counter. They design the counter using
cadence EDA tool. They simulated the designed ring counter for 200ns and analyze
disusing 45 nm technologies at 1 voltage rating in cadence tool. The delay & power
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dissipation of the proposed design was compared with that of conventional design. The
transistor count, delay and power dissipation were found to be respectively 106, 120.125ns
and 313.43pw for conventional ring counter and 58, 5.216ns and 219.85 pw for proposed
ring counter.

Mubarak (2016) designed a 3Bit counter using JK flip flop and he used Proteus
professional to simulate the output with the aid of a BCD decoder connected to the seven
segment display.

2.4 Summary of Literature Review

As many journals and articles were read in the course of designing and implementation of
the up/down synchronous 5Bits counter, we discovered that most of the work done and
papers written were basically on Ripple counters, Decade counter, 4Bits, 3Bits and 2Bits
up and down counters using different types of the state devices (flip flop). Most of these
designs were achieved with the use of micro controller. However, little or less work has
been done on 5Bits up and down counter and such, this study or project has proven an
effort towards solving contemporary problems in this aspect. Therefore, this project is so
much useful.
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3.0 CIRCJIT ANALYSIS AND DESIGN

3.1 Introduction

This is a 5bit synchronous up and down counter that is designed to count up even numbers
from 0 to 30 using the sequence 0, 2 4, 6 . . . 30 and to count down odd numbers from 31
to 1 in the sequence 31, 29,27 . . .1. This counter count consecutively for both the even and
the odd numbers once the power switch is turned ON and does not require any signal to
reset it to count even nor odd numbers. The figure below shows the block diagram for the
counter design

In the course of designing this design, we made some research which made us design the
counter by designing in units (as reflected in the block diagram above individually using
electrical and electronics components), based on the laid down principles and laws, taking
into cognizance, the operating limitations of the components such as the minimum and
maximum currents and voltage supply, power rating, temperature requirement and their
tolerances.

3.2 Circuit Analysis

3.2.1 Analysis of the power supply circuit

All electronics components requires a power supply and as such this design is not an
exception. We have chosen a dc source that supplies 5V to the clock circuit. This was
achieved by using a voltage regulator called 78L05. This component is used to regulate a
range of 9V – 15V to give an output voltage of 5V which falls within a range of voltage
(4.5 – 15V) required for the clock impulse circuit.

Thus a 9V microphone battery is used as the dc source and the voltage regulator (78L05)
regulate it to give an output voltage of 5V. The diagram is shown below

Pin 1 is the voltage output (Vo)

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Pin 3 is the voltage input (Vi)

Pin 2 is the zero potential (ground)

3.2.2 Analysis of the clock circuit

For the counter to perform its designed function effectively, there must be a clock signal
that will trigger the state of the flip flops to store the bits and continue counting. The clock
circuit was designed using the 555 timer specifically called NE555 timer. NE555 timer has
different modes of operation which includes;

i. Mono-stable mode: this is used for producing a single pulse when triggered and can be
used for timing.
ii. Bi-stable mode: this is used in single with two states; it is applicable when designing
storage devices
iii. Buffer mode: It is used as an inverting buffer (NOT gate)
iv. A-stable mode: This mode of operation is used driving counters making of sound and for
flashing of LEDs.

The a-stable mode was chosen for this design because it is the most appropriate mode of 555
timer operation for this work. The design requires continuous pulse with the exact and constant
based on the value of the two resistors and capacitors of which the A-stable mode produces.
The figure below shows the schematic representation of the clock circuit using the NE5555
timer in A-stable mode.

The preferred time, T for this clock signal was chosen to be 1 second for this design and this
1
meant that a frequency, F = 𝑇

1
Therefore F= 1 = 1Hz

This implies that the time taken to activate the clock circuit (turn ON), ton =0.5second also the
time to deactivate (turn OFF) the clock toff = 0.5second

1.4
But Frequency F = (𝑅1+2𝑅2)𝐶1
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For A-stable mode, the preferred value for C2 = 10nF

To have delayed time pulses, high values are selected for the resistor and the capacitor i.e. R1
and C1. For this design, R1 and C1 are respectively chosen to be 100K and 1uF and R2 is
1.4
calculated using the frequency formula F= 1 = (100000+2𝑅2) 1x 10^−6 Therefore R2 = 680K

C2 is the decoupling capacitor; both the capacitor and the resistor discharges when the clock
is high

3.2.3 Analysis of the flip flop circuit

Since this design involves 5bits, 5 flip flops are required and they are cascaded
together. This counter could be made to perform two functions (I. e. up counting for the
even numbers and down counting for the odd numbers) separately with a reset signal after
the first function but this design has combined these two functions to be performed the
function consecutively with no reset signal required. This counter will count from 0 – 31
following the sequence 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 31, 29, 27,
25, 23, 21, 19, 17, 15. 13, 11, 9, 7, 5, 3, 1. The BCD (Binary Coded Decimal) equivalence
for this sequence and the next state is shown in the table below

Table 2: Truth Table for a 5-Bit Counter

Present State Qn Next State Qn+1

S/N A B C D E A+ B+ C+ D+ E+
0 0 0 0 0 0 0 0 0 1 0
2 0 0 0 1 0 0 0 1 0 0
4 0 0 1 0 0 0 0 1 1 0
6 0 0 1 1 0 0 1 0 0 0
8 0 1 0 0 0 0 1 0 1 1
10 0 1 0 1 1 0 1 1 0 0
12 0 1 1 0 0 0 1 1 1 0
14 0 1 1 1 0 1 0 0 0 0
16 1 0 0 0 0 1 0 0 1 0
18 1 0 0 1 0 1 0 1 0 0
20 1 0 1 0 0 1 0 1 1 0
22 1 0 1 1 0 1 1 0 0 0
24 1 1 0 0 0 1 1 0 1 0
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26 1 1 0 1 0 1 1 1 0 0
28 1 1 1 0 0 1 1 1 1 0
30 1 1 1 1 0 1 1 1 1 1
31 1 1 1 1 1 1 1 1 0 1
29 1 1 1 0 1 1 1 0 1 1
27 1 1 0 1 1 1 1 0 0 1
25 1 1 0 0 1 1 0 1 1 1
23 1 0 1 1 1 1 0 1 0 1
21 1 0 1 0 1 1 0 0 1 1
19 1 0 0 1 1 1 0 0 0 1
17 1 0 0 0 1 0 1 1 1 1
15 0 1 1 1 1 0 1 1 0 1
13 0 1 1 0 1 0 1 0 1 1
11 0 1 0 1 1 0 1 0 0 1
9 0 1 0 0 1 0 0 1 1 1
7 0 0 1 1 1 0 0 1 0 1
5 0 0 1 0 1 0 0 0 1 1
3 0 0 0 1 1 0 0 0 0 1
1 0 0 0 0 1 0 0 0 0 0

The characteristic table for JK flip flop is obtained from the characteristic equation Qn =
JQ̄+K̄Q and is given in the table below

Table 3: The Characteristic Table for JK Flip Flop

Serial J K Q Qn Q̄n
Number

0 0 0 0 0 1

1 0 0 1 1 0

2 0 1 0 0 1

3 0 1 1 0 1
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4 1 0 0 1 0

5 1 0 1 1 0

6 1 1 0 1 0

7 1 1 1 0 1

Table 4: Excitation Table for JK Flip Flop

Serial Number Present State Next State

Qn Qn+1 J K

0 0 0 0 X

1 0 1 1 X

2 1 0 X 1

3 1 1 X 0

The excitation table for this 5bits up and down synchronous counter is obtained using the
JK flip flop excitation table and it is presented in the table below.
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Table 5: Excitation table of 5Bits using JK Flip Flop

Present State Qn Next State Qn+1 JA KA JB KB JC KC JD KD JE KE

S/N A B C D E A+ B+ C+ D+ E+
0 0 0 0 0 0 0 0 0 1 0 0 0 0 X 0 X 1 X 0 X
2 0 0 0 1 0 0 0 1 0 0 0 0 0 X 1 X X 1 0 X
4 0 0 1 0 0 0 0 1 1 0 0 0 0 X X 0 1 X 0 X
6 0 0 1 1 0 0 1 0 0 0 0 1 1 X X 1 X 1 0 X
8 0 1 0 0 0 0 1 0 1 1 0 X X 0 0 X 1 X 0 X
10 0 1 0 1 1 0 1 1 0 0 0 X X 0 1 X X 1 0 X
12 0 1 1 0 0 0 1 1 1 0 0 X X 0 X 0 1 X 0 X
14 0 1 1 1 0 1 0 0 0 0 1 X X 1 X 1 X 1 0 X
16 1 0 0 0 0 1 0 0 1 0 X 0 0 X 0 X 1 X 0 X
18 1 0 0 1 0 1 0 1 0 0 X 0 0 X 1 X X 1 0 X
20 1 0 1 0 0 1 0 1 1 0 X 0 0 X X 0 1 X 0 X
22 1 0 1 1 0 1 1 0 0 0 X 0 1 X X 1 X 1 0 X
24 1 1 0 0 0 1 1 0 1 0 X 0 X 0 0 X 1 X 0 X
26 1 1 0 1 0 1 1 1 0 0 X 0 X 0 1 X X 1 0 X
28 1 1 1 0 0 1 1 1 1 0 X 0 X 0 X 0 1 X 0 X
30 1 1 1 1 0 1 1 1 1 1 X 0 X 0 X 0 X 0 1 X
31 1 1 1 1 1 1 1 1 0 1 X 0 X 0 X 0 X1 1 X 0
29 1 1 1 0 1 1 1 0 1 1 X 0 X 0 X 1 X X X 0
27 1 1 0 1 1 1 1 0 0 1 X 0 X 0 0 X 1 1 X 0
25 1 1 0 0 1 1 0 1 1 1 X 0 X 1 1 X X X X 0
23 1 0 1 1 1 1 0 1 0 1 X 0 0 X X 0 1 1 X 0
21 1 0 1 0 1 1 0 0 1 1 X 0 0 X X 1 X X X 0
19 1 0 0 1 1 1 0 0 0 1 X 0 0 X 0 X 1 1 X 0
17 1 0 0 0 1 0 1 1 1 1 X 1 1 X 1 X X X X 0
15 0 1 1 1 1 0 1 1 0 1 0 X X 0 X 0 1 1 X 0
13 0 1 1 0 1 0 1 0 1 1 0 X X 0 X 1 X X X 0
11 0 1 0 1 1 0 1 0 0 1 0 X X 0 0 X 1 1 X 0
9 0 1 0 0 1 0 0 1 1 1 0 X X 1 1 X X X X 0
7 0 0 1 1 1 0 0 1 0 1 0 X 0 X X 0 1 1 X 0
5 0 0 1 0 1 0 0 0 1 1 0 X 0 X X 1 X X X 0
3 0 0 0 1 1 0 0 0 0 1 0 X 0 X 0 X 1 1 X 0
1 0 0 0 0 1 0 0 0 0 0 0 X 0 X 0 X X X X 1
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The Karnaugh map representation of the 5bits up/down counter are shown below

Table 6: karnaugh Map JA

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00 X X X X

1 5 13 9 17 21 29 25
01 X X X X

3 7 15 11 19 23 31 27
11 X X X X

2 6 14 12 28 22 30 27
10 1 X X X X

JA=BCDĒ

Table 7: Karnaugh Map for KA

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00 X X X X

01 X 1 X 5 X 13 X 9 1 17 21 29 25

11 X 3 X 7 X 15 X 11 19 23 31 27

10 X 2 X 6 X 14 X 12 28 22 30 27

KA = B̄C̄D̄E
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Table 8: Karnaugh Map for JB

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00 X X X X

1 5 13 9 17 21 29 25
01 X X 1 X X

3 7 15 11 19 23 31 27
11 X X X X

2 6 14 12 28 22 30 27
10 1 X X 1 X X

JB = AB̄C̄D̄E + CDĒ

Table 9: Karnaugh Map for KB

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00 X X X X

1 5 13 9 17 21 29 25
01 X X 1 X X 1

7 15 11 19 23 31 27
11 X 3 X X X

2 6 14 12 28 22 30 27
10 X X 1 X X

KB = BC̄D̄E + ĀCDĒ
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Table 10: Karnaugh Map for JC

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00 X X X X

1 5 13 9 17 21 29 25
01 X X 1 1 X X 1

3 7 15 11 19 23 31 27
11 X X X X

2 6 14 12 28 22 30 27
10 1 X X 1 1 X X 1

JC = DĒ + AD̄E + BD̄E

Table 11: Karnaugh Map for KC

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00

1 5 13 9 17 21 29 25
01

3 7 15 11 19 23 31 27
11

2 6 14 12 28 22 30 27
10

KC = D̄E + ĀDĒ + B̄DĒ

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Table 12: Karnaugh Map for JD

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00 1 1 1 1 1 1 1 1

1 5 13 9 17 21 29 25
01 1 1 1 1 1 1

3 7 15 11 19 23 31 27
11 X X X X X X X X

2 6 14 12 28 22 30 27
10 X X X X X X X X

JD = A + ĀD̄ Ē + ĀB + ĀC

Table 13: Karnaugh Map for KD

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00 X X X X X X X X

1 5 13 9 17 21 29 25
01 X X X X X X X X

3 7 15 11 19 23 31 27
11 1 1 1 1 1 1 1 1

2 6 14 12 28 22 30 27
10 1 1 1 1 1 1 1

KD = Ā + BC̄ + AE + AB̄
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Table 14: Karnaugh Map JE

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 4 12 8 16 20 28 24
00

1 5 13 9 17 21 29 25
01 X X X X X X X X

3 7 15 11 19 23 31 27
11 X X X X X X X X

2 6 14 12 28 22 30 27
10 1

JE = ABCD

Table 15: Karnaugh for KE

A=0 A=1
BC
00 01 11 10 00 01 11 10
DE
0 12 8 16 20 28 24
00 X X X X X X X X
4

1 5 13 9 17 21 29 25
01 1

3 7 15 11 19 23 31 27
11

2 6 14 12 28 22 30 27
10 X X X X X X X X

KE = ĀB̄C̄D̄
 23

3.2.4 Binary status LED indicator

Before designing the BCD to the 7-segment display decoder, this design was tested using
LED indicators to know if the circuit was working well as expected before going ahead
with the design. The binary status LED indicators were used to show the counter’s present
state or count at any particular clock signal. 5 LEDs were used each representing a bit and
having a corresponding decimal value attached to it such that the blinking of the LED(s) at
any particular time represented a single number between 0 – 31. The decimal value for the
LEDs and their corresponding bit is shown below

Table 16: LEDs for the Bits and Their Corresponding Decimal Value

Bits/Inputs LEDs Decimal Equivalent

A L1 24 = 16

B L2 23 = 8

C L3 22 = 4

D L4 21 = 2

E L5 20 = 1

For instance when the counter count 22, LEDs L4 L2 and L1will turn ON which implies
that 22 = 16+4+2 and when the counter count 24 then, L4 and L3 will turn ON which
implies that 24 =16+8 and the trend continues for any other number which could be
counted. The following table, shows the LED display for the sequence
 24

Table 17: LED Display for the Sequence

Sequence LED Display Sequence LED Display

0 − 31 L1, L2, L3, L4, L5

2 L4 29 L1, L2, L3, L5

4 L3 27 L1, L2, L4, L5

6 L3, L4 25 L1, L2, L5

8 L2 23 L1, L3, L4, L5

10 L2, L4 21 L1, L3, L5

12 L2, L3 19 L1, L4, L5

14 L2, L3, L4 17 L1, L5

16 L1 15 L2, L3, L4, L5

18 L1, L4 13 L2, L3, L5

20 L1, L3 11 L2, L4, L5

22 L1, L3, L4 9 L2, L5

24 L1, L2 7 L3, L4, L5

26 L1, L2, L4 5 L3, L5

28 L1, L2, L3 3 L4, L5

30 L1, L2, L3, L4 1 L5

 25

3.2.5 BCD to 7-segment decoder

This design involves 2 7-segment display; the first to count the digits 0, 1, 2, 3, 4, 5, 6, 7,8,
and the second 7-segment to count 9 0, 1, 2, 3 for the units and tens respectively. The truth
table for the two digits BCD to 7-segment decoder and the resulting karnaugh map
representation is shown below.

Table 18: Table for the Conversion Circuit

𝑫𝟐 𝑫𝟏
(0-3) (0-9)
S/N B A D C B A
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1 1
2 0 0 0 2 0 0 1 0 2
3 0 0 0 3 0 0 1 1 3
4 0 0 0 4 0 1 0 0 4
5 0 0 0 5 0 1 0 1 5
6 0 0 0 6 0 1 1 0 6
7 0 0 0 7 0 1 1 1 7
8 0 0 0 8 1 0 0 0 8
9 0 0 0 9 1 0 0 1 9
10 1 0 1 0 0 0 0 0 0
11 1 0 1 1 0 0 0 1 1
12 1 0 1 2 0 0 1 0 2
 26

13 1 0 1 3 0 0 1 1 3
14 1 0 1 4 0 1 0 0 4
15 1 0 1 5 0 1 0 1 5
16 1 0 1 6 0 1 1 0 6
17 1 0 1 7 0 1 1 1 7
18 1 0 1 8 1 0 0 0 8
19 1 0 1 9 1 0 0 1 9
20 2 1 0 0 0 0 0 0 0
21 2 1 0 1 0 0 0 1 1
22 2 1 0 2 0 0 1 0 2
23 2 1 0 3 0 0 1 1 3
24 2 1 0 4 0 1 0 0 4
25 2 1 0 5 0 1 0 1 5
26 2 1 0 6 0 1 1 0 6
27 2 1 0 7 0 1 1 1 7
28 2 1 0 8 1 0 0 0 8
29 2 1 0 9 1 0 0 1 9
30 3 1 1 0 0 0 0 0 0
31 3 1 1 1 0 0 0 1 1
 27

KANAUGH MAP FOR BCD DOCODER

FOR D1:

Table 19: Karnaugh Map for DA

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

DA = E
Table :20 Karnaugh Map for DB

1 1
G3

1 1 G4

1 1 1 1

1 1 1 1
G5

- - - - - --- -
DB = ABD + BCD + ABCD + ABCD + ABCD
 28

Table :21 Karnaugh Map for DC

1 1 1

1 1 1
G3 G3

1 1 1

1 1 1
G4

-- - -- -
DC = ABC + ACD + ACD + ABC

Table 22: Kanaugh Map for DD

1 1

1 1
G3

- -- - - -
DD = ABCD + ABCD + ABCD
 29

FOR D2

Table 23: Karanugh Map for DA

1 1

1 1

1 1 1
1
1 1 1
G4
1 G3

- - --
DA = ABD + ABC + BCD + ABC

Table 24: Karnaugh Map for DB

1 1 1

1 1 1

1 1 1 1

1 1 1 1

DB = AC + AB
 30

3.2.6 The 7-segment display

The 7-segment display was not designed but was used as a component; the 4 pin 7-segment
was chosen for this the first to display the unit numbers (0, 1, 2, 3, . . . , 9) and the second
to display the tens (0, 1, 2, 3) to effectively display the output this design. The schematic
of the 7-segment display is shown below

3.3 Simulation Model

Figure 2: Simulation of the Circuit with LED display Showing a Count of 29

 31

Figure 3: Simulation of the Circuit with 7-Segment Display Showing 20.

 32

3.4 Circuit Diagrams

Figure 4: Power Supply Circuit

 33

Table 5: Digital Clock Circuit

 34

Figure 6: JK Flip Flop Circuit

 35

Figure 7: Circuit Diagram for BCD to 7-Segment Decoder

 36

Figure 8: Combined Circuit Diagram for 5Bits Up/Down (Even/Odd) Synchronous Counter
Using JK Flip flop.
 37

4.0 CONSTRUCTION, TESTING, RESULTS AND DESIGN

4.1 Construction

In most of the ICs, two or more gates are embedded on it same is with the flip flops and as
such identifying the pins for each gate on the ICs was quite challenging. Apart from that,
not all the ICs were readily available on the market such that one could have no option than
to order the components on-line and start waiting for their arrival. Due to the points
mentioned above, the construction of this counter was not so easy. The circuit was first
implemented and built on a bread board to ensure its workability and after confirming its
proper functionality it was transferred to the Vero board for the final prototype.

The materials used for this project are listed below

i. Resistors (100K, 1K, 680K, 0.33K X14)

ii. Capacitors (10nF, 1uF)
iii. NE555 timer
iv. 9V battery
v. 78L05 (voltage regulator)
vi. Bread boards
vii. Vero board
viii. Driver (IC 7447)
ix. Logic gates

4.1.1 Construction on the bread board

We ensured that all the components were well placed and mounted firmly on the bread
board and ensured proper and firm fixing of the wires on the breadboard but we avoided
short circuits. We also ensured a well and proper cascading of the bread board to obtain
pour design.

4.1.2 Construction on the Vero board

 38

When the circuit worked fine on the bread board we transferred it to the Vero board placing
the components gently and at their appropriate positions after which we carefully soldered
the components on the Vero board avoiding short circuit.

4.2 Testing

At the inputs and outputs of the basic units of this design, the currents and voltages were
measured appropriately using a multimeter in the right measuring mode to ensure that we
have the expected inputs and outputs in order to maintain a constant frequency of 1Hz and
a constant time delay from the digital clock and also to ensure that all the components have
up to the rated currents and voltages of the components for the effective functioning of our
design. All these tests were done on the bread board to ensure the design’s workability
before transferring it to the Vero board.

4.3 Result

In the course of testing some of the parameters at various stages of the circuit, the following
results were obtained;

For the clock circuit;

Frequency, F=1Hz

Voltage input, Vi =5V

Voltage output, Vo =5V

The voltage output of the power circuit, Vcc =5V

4.4 Discussion

Due to the results obtained from the testing and measurement of the parameters during the
implementation and building of the design on the bread board, it indicates the usefulness
of a good design (selection of the parameters) in relation to the working principles and
operations of discrete components and state devices and as such the basic knowledge of
the variation of these components.
 39

of course, there are some little constraints in the implementation of this project especially
in the value of the output current which is due to the fact that the wires used in
implementing this circuit on the bread board and Vero board have their internal resistances
which have had more or less effect on the design whereas the wires used on implementing
the circuit on the software (proteus) have on internal resistances.

The implementation of this design has helped us to understand the basic working principles
of counters and how they can be designed to perform different counts. The 9V battery was
chosen because the design could be used even where there is no ac supply. However, the
dc supply is not sustainable its supply voltage often drops with time but one simply needs
to change the battery and then takes it anywhere to use of which is more cost effective.
 40

5.0 CONCLUSION AND RECOMMENDATION

5.1 Conclusion

A 5Bits Up/Down (even/odd) synchronous counter was successfully designed using JK flip
flop (the basic building block for counters), was implemented and run successfully on
proteus 8.6 version (a software for engineering design). It was implemented and tested on
the bread board and a first prototype was successfully obtained using the Vero board.

Thus much knowledge was acquired on how a counter is designed using discrete
components and its working operations understood in the course of this project.

5.2 Recommendations

This project is quite an interesting one as much knowledge is acquired. It was not actually
meant to solve any particular problem per say because of the nature of the sequence of
counting. However, it gave the basic knowledge and understanding on the design of
counters. However, modifications can be done on this project in terms of selecting a
sequence that can solve many problems e.g. The traffic light.

Some other factors such as the availability of components and short time frame among
others also rendered a hindrance to the quick completion of this project.

The following are recommended if modifications or further studies is to be done on this to

improve it.

i. Students should be given adequate access to the equipment and also the opportunity
to borrow and use such components in the course of their studies and development
of their projects
ii. The laboratories should properly be set such that students can go and implement
their designs
iii. A good counting sequence that will solve a particular problem should be selected
by students or supervisors to encourage students to study hard and develop their
project well knowing that their project will solve a problem.
iv. More printed circuit boards should be made and taught to students
 41

v. A feasibility study should be made adequately by students or the supervisor on the

availability of the components for a particular project before choosing a topic for
miniproject.
 42

REFERENCES

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Calvignac, Y.andCambonie, P. (2012). 4-State Binary Counter, Retrieved

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Givant, S. and Halmos, P. (2009). Introduction to Boolean Algebra. Undergraduate Text in

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Harish, N.K.P. et al. (2014). Design and Implementation of Reversible Sequential Circuits.
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Menkiti, A.I. (2011). Computer Logic and Architecture. University of calabar Press, calabar,
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Mubarak, R. (2016). Designing a 3Bit Counter using JK flip flop. Retrieved from
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Ramya, A. et al. (2013). Design of Asynchronous up-down Counter using a Power Efficient D-
Flip. flop. International Journal for Advanced Research in Engineering and Technology, 1
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Raja, G. and Deeper, K. (2016). Design and Analysis of Digital Counters for VLSI Application.
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Rajat, K.D. and Pattaturani, L. (2017). Design of Counter using SRAM. IOSR Journal of.
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Sandeep, T. and Rajesh, M. (2016). Optimized Design and Simulation of Ring counter using
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Hybrid Dual Mode Dynamic Flip Flop. American journal of Engineering Research
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