This set of Computer Fundamentals Multiple Choice Questions & Answers (MCQs)

focuses on “Main Memory Organisation”.

1. Any electronic holding place where data can be stored and retrieved later whenever
required is ____________
a) memory
b) drive
c) disk
d) circuit

Answer: a
Explanation: Memory is the place where data can be stored and later retrieved. Memory
can be of classified into register, cache, main memory, etc.

2. Cache memory is the onboard storage.

a) True
b) False

Answer: a
Explanation: Cache Memory is the memory closest to the CPU. Registers, Cache and the
main memory are the means of onboard storage in the computer system.

3. Which of the following is the fastest means of memory access for CPU?
a) Registers
b) Cache
c) Main memory
d) Virtual Memory

Answer a
Explanation: Registers are the fastest means of access for CPU. Registers are the small
memory locations which are present closest to the CPU.

4. The memory implemented using the semiconductor chips is _________

a) Cache
b) Main
c) Secondary
d) Registers
 Answer: b
Explanation: The main memory is implemented using semiconductor chips. Main
memory is located on the motherboard. It mainly consists of RAM and small amount of
ROM.

5. Size of the ________ memory mainly depends on the size of the address bus.
a) Main
b) Virtual
c) Secondary
d) Cache

Answer: a
Explanation: The size of the main memory depends on the size of the address bus of the
CPU. The main memory mainly consists of RAM and ROM, where RAM contains the
current data and programs and ROM contains permanent programs like BIOS.

6. Which of the following is independent of the address bus?

a) Secondary memory
b) Main memory
c) Onboard memory
d) Cache memory

Answer: a
Explanation: The secondary memory is independent of the address bus. It increases the
storage space. It is implemented in the form of magnetic storage devices.

7. ____________ storage is a system where a robotic arm will connect or disconnect off-line
mass storage media according to the computer operating system demands.
a) Secondary
b) Virtual
c) Tertiary
d) Magnetic

Answer: c
Explanation: The tertiary storage is the correct option. It is used in the realms of
enterprise storage and scientific computing on large computer systems and business
computer networks and is something a typical personal computer never sees firsthand.
8. What is the location of the internal registers of CPU?
a) Internal
b) On-chip
c) External
d) Motherboard

Answer: b
Explanation: The internal registers are present on-chip. They are therefore present inside
the CPU. L1 cache is also present on-chip inside the CPU.

9. MAR stands for ___________

a) Memory address register
b) Main address register
c) Main accessible register
d) Memory accessible register

Answer: a
Explanation: The MAR stands for memory address register. It holds the address of the
active memory location.

10. If M denotes the number of memory locations and N denotes the word size, then an
expression that denotes the storage capacity is ______________
a) M*N
b) M+N
c) 2M+N
d) 2M-N

Answer: a
Explanation: Storage capacity is the product of a number of memory locations that is the
number of words and the word size or the number of bits stored per location. Storage
capacity should be as large as possible.
This set of Computer Fundamentals Multiple Choice Questions & Answers (MCQs)
focuses on “Cache Memory”.

1. What is the high speed memory between the main memory and the CPU called?
a) Register Memory
b) Cache Memory
c) Storage Memory
d) Virtual Memory

Answer: b
Explanation: It is called the Cache Memory. The cache memory is the high speed memory
between the main memory and the CPU.

2. Cache Memory is implemented using the DRAM chips.

a) True
b) False

Answer: b
Explanation: The Cache memory is implemented using the SRAM chips and not the DRAM
chips. SRAM stands for Static RAM. It is faster and is expensive.

3. Whenever the data is found in the cache memory it is called as _________

a) HIT
b) MISS
c) FOUND
d) ERROR

Answer: a
Explanation: Whenever the data is found in the cache memory, it is called as Cache HIT.
CPU first checks in the cache memory since it is closest to the CPU.

4. LRU stands for ___________

a) Low Rate Usage
b) Least Rate Usage
c) Least Recently Used
d) Low Required Usage
 Answer: c
Explanation: LRU stands for Least Recently Used. LRU is a type of replacement policy used
by the cache memory.

5. When the data at a location in cache is different from the data located in the main
memory, the cache is called _____________
a) Unique
b) Inconsistent
c) Variable
d) Fault

Answer: b
Explanation: The cache is said to be inconsistent. Inconsistency must be avoided as it
leads to serious data bugs.

6. Which of the following is not a write policy to avoid Cache Coherence?

a) Write through
b) Write within
c) Write back
d) Buffered write

Answer: b
Explanation: There is no policy which is called as the write within policy. The other three
options are the write policies which are used to avoid cache coherence.

7. Which of the following is an efficient method of cache updating?

a) Snoopy writes
b) Write through
c) Write within
d) Buffered write

Answer: a
Explanation: Snoopy writes is the efficient method for updating the cache. In this case,
the cache controller snoops or monitors the operations of other bus masters.
8. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
a) Associative
b) Direct
c) Set Associative
d) Indirect

Answer: a
Explanation: This happens in the associative mapping. In this case, a block of data from
the main memory can be mapped anywhere in the cache memory.

9. The number of sign bits in a 32-bit IEEE format is ____

a) 1
b) 11
c) 9
d) 23

Answer: a
Explanation: There is only 1 sign bit in all the standards. In a 32-bit format, there is 1 sign
bit, 8 bits for the exponent and 23 bits for the mantissa.

10. The transfer between CPU and Cache is ______________

a) Block transfer
b) Word transfer
c) Set transfer
d) Associative transfer

Answer: b
Explanation: The transfer is a word transfer. In the memory subsystem, word is
transferred over the memory data bus and it typically has a width of a word or half-word.
This set of Computer Organization and Architecture Multiple Choice Questions & Answers
(MCQs) focuses on “Mapping Functions”.

1. The memory blocks are mapped on to the cache with the help of ______
a) Hash functions
b) Vectors
c) Mapping functions
d) None of the mentioned
Answer: c
Explanation: The mapping functions are used to map the memory blocks on to their
corresponding cache block.

2. During a write operation if the required block is not present in the cache then ______
occurs.
a) Write latency
b) Write hit
c) Write delay
d) Write miss
Answer: d
Explanation: This indicates that the operation has missed and it brings the required block
into the cache.

3. In ________ protocol the information is directly written into the main memory.
a) Write through
b) Write back
c) Write first
d) None of the mentioned
Answer: a
Explanation: In case of the miss, then the data gets written directly in main memory.

4. The only draw back of using the early start protocol is _______
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
Answer: b
Explanation: In this protocol, the required block is read and directly sent to the processor.
5. The method of mapping the consecutive memory blocks to consecutive cache blocks is
called ______
a) Set associative
b) Associative
c) Direct
d) Indirect
Answer: c
Explanation: This method is most simple to implement as it involves direct mapping of
memory blocks.

6. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are
used for ________
a) Tag
b) Block
c) Word
d) Id
Answer: a
Explanation: The tag is used to identify the block mapped onto one particular cache
block.

7. In direct mapping the presence of the block in memory is checked with the help of block
field.
a) True
b) False
Answer: b
Explanation: The tag field is used to check the presence of a mem block.

8. In associative mapping, in a 16 bit system the tag field has ______ bits.
a) 12
b) 8
c) 9
d) 10
Answer: a
Explanation: The Tag field is used as an id for the different memory blocks mapped to the
cache.
9. The associative mapping is costlier than direct mapping.
a) True
b) False
Answer: a
Explanation: In associative mapping, all the tags have to be searched to find the block.

10. The technique of searching for a block by going through all the tags is ______
a) Linear search
b) Binary search
c) Associative search
d) None of the mentioned
Answer: c
Explanation: None.

11. The set-associative map technique is a combination of the direct and associative
technique.
a) True
b) False
Answer: a
Explanation: The combination of the efficiency of the associative method and the
cheapness of the direct mapping, we get the set-associative mapping.

12. In set-associative technique, the blocks are grouped into ______ sets.
a) 4
b) 8
c) 12
d) 6
Answer: d
Explanation: The set-associative technique groups the blocks into different sets.

13. A control bit called _________ has to be provided to each block in set-associative.
a) Idol bit
b) Valid bit
c) Reference bit
d) All of the mentioned
Answer: b
Explanation: The valid bit is used to indicate that the block holds valid information.
14. The bit used to indicate whether the block was recently used or not is _______
a) Idol bit
b) Control bit
c) Reference bit
d) Dirty bit
Answer: d
Explanation: The dirty bit is used to show that the block was recently modified and for a
replacement algorithm.

15. Data which is not up-to date is called as _______

a) Spoilt data
b) Stale data
c) Dirty data
d) None of the mentioned
Answer: b
Explanation: None.
This set of Computer Organization and Architecture Multiple Choice Questions & Answers
(MCQs) focuses on “Cache Miss and Hit”.

1. The main memory is structured into modules each with its own address register called
______
a) ABR
b) TLB
c) PC
d) IR
Answer: a
Explanation: ABR stands for Address Buffer Register.

2. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
Answer: a
Explanation: In a modular approach to memory structuring only one module can be
accessed at a time.

3. In memory interleaving, the lower order bits of the address is used to _____________
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the mentioned
Answer: b
Explanation: To implement parallelism in data access we use interleaving.

4. The number successful accesses to memory stated as a fraction is called as _____

a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
Answer: a
Explanation: The hit rate is an important factor in performance measurement.
5. The number failed attempts to access memory, stated in the form of a fraction is called as
_________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
Answer: b
Explanation: The miss rate is a key factor in deciding the type of replacement algorithm.

6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the
others are incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the
cache.

7. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are
incremented by one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
Answer: a
Explanation: If the referenced block is present in the memory it is called as hit.

8. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
Answer: b
Explanation: It has to be above 0.9 for speedy computers.
9. The extra time needed to bring the data into memory in case of a miss is called as
__________
a) Delay
b) Propagation time
c) Miss penalty
d) None of the mentioned
Answer: c
Explanation: None.

10. The miss penalty can be reduced by improving the mechanisms for data transfer
between the different levels of hierarchy.
a) True
b) False
Answer: a
Explanation: The extra time needed to bring the data into memory in case of a miss is
called as miss penalty.
This set of Computer Organization and Architecture Multiple Choice Questions & Answers
(MCQs) focuses on “Replacement Algorithms”.

1. The directly mapped cache no replacement algorithm is required.

a) True
b) False
Answer: a
Explanation: The position of each block is pre-determined in the direct mapped cache,
hence no need for replacement.

2. The surroundings of the recently accessed block is called as ______

a) Neighborhood
b) Neighbour
c) Locality of reference
d) None of the mentioned
Answer: c
Explanation: The locality of reference is a key factor in many of the replacement
algorithms.

3. In set associative and associative mapping there exists less flexibility.

a) True
b) False
Answer: b
Explanation: The above two methods of mapping the decision of which block to be
removed rests with the cache controller.

4. The algorithm which replaces the block which has not been referenced for a while is
called _____
a) LRU
b) ORF
c) Direct
d) Both LRU and ORF
Answer: a
Explanation: LRU stands for Least Recently Used first.

5. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the
others are incremented by one when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the
cache.

6. The LRU provides very bad performance when it comes to _________

a) Blocks being accessed is sequential
b) When the blocks are randomised
c) When the consecutive blocks accessed are in the extremes
d) None of the mentioned
Answer: a
Explanation: The LRU in case of the sequential blocks as to waste its one cycle just
incrementing the counters.

7. The algorithm which removes the recently used page first is ________
a) LRU
b) MRU
c) OFM
d) None of the mentioned
Answer: b
Explanation: In MRU it is assumed that the page accessed now is less likely to be accessed
again.

8. The LRU can be improved by providing a little randomness in the access.

a) True
b) False
Answer: a
Explanation: None.

9. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are
incremented by one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
 Answer: a
Explanation: If the referenced block is present in the memory it is called as a hit.

10. The counter that keeps track of how many times a block is most likely used is _______
a) Count
b) Reference counter
c) Use counter
d) Probable counter
Answer: b
Explanation: None.
This set of Computer Organization and Architecture Multiple Choice Questions & Answers
(MCQs) focuses on “Hardwired Control”.

1. ________ are the different type/s of generating control signals.

a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired
Answer: d
Explanation: The above is used to generate control signals in different types of system
architectures.

2. The type of control signal is generated based on ________

a) contents of the step counter
b) Contents of IR
c) Contents of condition flags
d) All of the mentioned
Answer: d
Explanation: Based on the information above the type of control signal is decided.

3. What does the hardwired control generator consist of?

a) Decoder/encoder
b) Condition codes
c) Control step counter
d) All of the mentioned
Answer: d
Explanation: The CU uses the above blocks and IR to produce the necessary signal.

4. What does the end instruction do?

a) It ends the generation of a signal
b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor
Answer: c
Explanation: It is basically used to start the generation of a new signal.
5. The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…
a) True
b) False
Answer: a
Explanation: The signal is generated using the logic of the formula above.

6. What does the RUN signal do?

a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one
Answer: d
Explanation: The RUN signal increments the step counter by one for each clock cycle.

7. The name hardwired came because the sequence of operations carried out is determined
by the wiring.
a) True
b) False
Answer: a
Explanation: In other words hardwired is another name for Hardware Control signal
generator.

8. The benefit of using this approach is ________

a) It is cost effective
b) It is highly efficient
c) It is very reliable
d) It increases the speed of operation
Answer: d
Explanation: None.

9. The disadvantage/s of the hardwired approach is ________

a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) less flexible & cannot be used for complex instructions
Answer: d
Explanation: The more complex the instruction set less applicable to a hardwired
approach.
10. The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False
Answer: a
Explanation: None.

This set of Computer Organization Problems focuses on “Microprogrammed Control”.

1. In micro-programmed approach, the signals are generated by ______

a) Machine instructions
b) System programs
c) Utility tools
d) None of the mentioned
Answer: a
Explanation: The machine instructions generate the signals.

2. A word whose individual bits represent a control signal is ______

a) Command word
b) Control word
c) Co-ordination word
d) Generation word
Answer: b
Explanation: The control word is used to get the different types of control signals
required.

3. A sequence of control words corresponding to a control sequence is called _______

a) Micro routine
b) Micro function
c) Micro procedure
d) None of the mentioned
Answer: a
Explanation: The micro routines are used to perform a particular task.
4. Individual control words of the micro routine are called as ______
a) Micro task
b) Micro operation
c) Micro instruction
d) Micro command
Answer: c
Explanation: The each instruction which put together performs the task.

5. The special memory used to store the micro routines of a computer is ________
a) Control table
b) Control store
c) Control mart
d) Control shop
Answer: b
Explanation: The control store is used as a reference to get the required control routine.

6. To read the control words sequentially _________ is used.

a) PC
b) IR
c) UPC
d) None of the mentioned
Answer: c
Explanation: The UPC stands for Micro program counter.

7. Every time a new instruction is loaded into IR the output of ________ is loaded into UPC.
a) Starting address generator
b) Loader
c) Linker
d) Clock
Answer: a
Explanation: The starting address generator is used to load the address of the next micro
instruction.

8. The case/s where micro-programmed can perform well _______________

a) When it requires to check the condition codes
b) When it has to choose between the two alternatives
c) When it is triggered by an interrupt
d) None of the mentioned
 Answer: d
Explanation: None.

9. The signals are grouped such that mutually exclusive signals are put together.
a) True
b) False
Answer: a
Explanation: This is done to improve the efficiency of the controller.

10. Highly encoded schemes that use compact codes to specify a small number of functions
in each micro instruction is ________
a) Horizontal organisation
b) Vertical organisation
c) Diagonal organisation
d) None of the mentioned
Answer: b
Explanation: None.