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    By: Charles G. Juarizo

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    Bardagol
    The document discusses bus design requirements and considerations. A bus is used to transport data between a transmitter and receiver. Key requirements are that a logic 0 transmitted must be received as a logic 0, and a logic 1 transmitted must be received as a logic 1. Bus design considerations include noise immunity, ensuring voltage thresholds are met between components, and accounting for current requirements to prevent overloading receivers. Compatibility between different component standards like TTL, LSTTL, and CMOS must also be evaluated.

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    By: Charles G. Juarizo

    Uploaded by

    Bardagol
    55 views12 pages
    The document discusses bus design requirements and considerations. A bus is used to transport data between a transmitter and receiver. Key requirements are that a logic 0 transmitted must be received as a logic 0, and a logic 1 transmitted must be received as a logic 1. Bus design considerations include noise immunity, ensuring voltage thresholds are met between components, and accounting for current requirements to prevent overloading receivers. Compatibility between different component standards like TTL, LSTTL, and CMOS must also be evaluated.

    Original Title

    Microprocessor –lecture 9

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    The document discusses bus design requirements and considerations. A bus is used to transport data between a transmitter and receiver. Key requirements are that a logic 0 transmitted must be received as a logic 0, and a logic 1 transmitted must be received as a logic 1. Bus design considerations include noise immunity, ensuring voltage thresholds are met between components, and accounting for current requirements to prevent overloading receivers. Compatibility between different component standards like TTL, LSTTL, and CMOS must also be evaluated.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    55 views12 pages

    By: Charles G. Juarizo

    Uploaded by

    Bardagol
    The document discusses bus design requirements and considerations. A bus is used to transport data between a transmitter and receiver. Key requirements are that a logic 0 transmitted must be received as a logic 0, and a logic 1 transmitted must be received as a logic 1. Bus design considerations include noise immunity, ensuring voltage thresholds are met between components, and accounting for current requirements to prevent overloading receivers. Compatibility between different component standards like TTL, LSTTL, and CMOS must also be evaluated.

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    BUS

    BY: CHARLES G. JUARIZO


    BUS
     A set of lines used to transport data between a
    transmitter and a receiver
     Lines are grouped together according to the signals they
    carry.
    e.g. address bus, control bus, data bus

    BUS DESIGN REQUIREMENT:


    1. A logic ‘0’ transmitted should be a logic ‘0’ received.
    2. A logic ‘1” transmitted should be a logic ‘1’ received.
    BUS DESIGN CONSIDERATION
    1. Noise Immunity
     Considers the voltage compatibility of the transmitter and the
    receiver.
     Considers also the amount of noise voltage that can be tolerated.

    VOH VIH(min)
    Xmtr Rcvr
    (TTL) (TTL)

    Requirement:

    VOH > VIH

    NI = VOH - VIH
    Example
     TTL – TTL
    VOH = 2.4 V VIH = 2V NI = 0.4V

     TTL – LSTTL
    VOH = 2.4 V VIH = 2V NI = 0.4V

     TTL – CMOS
    VOH = 2.4 V VIH = 3.5V NI = -1.1V (not compatible)

     CMOS - TTL
    VOH = 4.6V VIH = 2V NI = 2.6V
    LOGIC 0

    VOL VIL(max)
    Xmtr Rcvr
    (TTL) (TTL)

    Requirement:

    VOL < VIL


    NI = VIL - VOL
    EXAMPLE
     TTL – TTL
    VOL = 0.4V VIL = 0.8V NI = 0.4V

     TTL – LSTTL
    VOL = 0.4V VIL = 0.8V NI = 0.4V

     CMOS – TTL
    VOL = 0.4V VIL = 0.8V NI = 0.4V
    BUS DESIGN CONSIDERATION
    2. DC Loading
    - considers the current requirements

    LOGIC 1:

    IOH(CAP) IIH
    Xmtr Rcvr
    (TTL) (TTL)
    400𝜇𝐴 40𝜇𝐴

    Requirement:

    IOH > IIH


    BUS DESIGN CONSIDERATION
    Multiple Receivers
    - considers the current requirements

    LOGIC 1:

    IOH IIH
    𝐼𝐼𝐻
    Xmtr Rcvr
    (TTL) (TTL)

    Requirement:
    IIH
    𝐼𝑂𝐻 ≥ 𝐼𝐼𝐻
    Example
     TTL – TTL
    - 10 TTL receivers to 1 TTL transmitter

     TTL – LSTTL
    IOH = 400𝜇𝐴 IIH = 20𝜇𝐴
    - 20 LSTTL receivers to 1 TTL transmitter

     CMOS – TTL
    IOH = 360𝜇𝐴 IIH = 40𝜇𝐴
    - 9 TTL receivers to 1 CMOS transmitter
    LOGIC O
    IOL(CAP) IIL
    Xmtr Rcvr
    (TTL) (TTL)

    Requirement:

    IOL > IIL


    Example
     TTL – TTL
    IOL = 16mA IIL = 1.6mA
    10 TTL receivers to 1TTL transmitter

     TTL – LSTTL
    IOL = 16mA IIL = 0.4mA
    40 LSTTL to 1 TTL transmitter
    (only 20 rcvrs) can be connected

     CMOS – TTL
    IOL = 0.36mA IIL = 1.6 mA
    (not compatible) CMOS input circuit will be destroyed due to overcurrent
    Example
     CMOS – CMOS

    IOL = 360𝜇A IIL = 1𝜇A


    360 CMOS receivers to 1 CMOS transmitter

    IOH = 360𝜇A IIH = 1𝜇A


    360 CMOS receivers to 1 CMOS transmitter

    VOH = 4.6V IIH = 3.5V NI = 1.1V


    VOL = 0.4V VIL = 1.5V NI = 1.1V

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