EE434

ASIC & Digital Systems

Automatic Layout Generation

(Cadence Innovus)

Spring 2020
Dae Hyun Kim
[email protected]
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 Preparation for Lab2

• Download the following file into your working directory.

– wget http://eecs.wsu.edu/~ee434/Labs/lab2.tar.gz

• Unzip it.
– tar xvfz lab2.tar.gz

• Before you run Innovus, you should source the following files:
– source ictools_generic.sh
– source cadence_innovus17.sh

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 Benchmark

• VQS64_4 (four-input 64-bit pipelined quick sort)

– input [63:0] mX1, mX2, mX3, mX4
– input mCLK
– output [63:0] mY1, mY2, mY3, mY4

rC1
mX1 mY1

rC2
mX2 mY2

mX3 mY3
rC3

mX4 mY4
rC4
Registers Comparators
Level 0 Level 1 Level 2
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 What We Are Going To Do

1. Chip outlining
2. P/G network design
3. Placement
4. Pre-CTS optimization
5. CTS
6. Post-CTS optimization
7. Routing
8. Post-routing optimization
9. Fill insertion

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 1. Chip Outlining

• Run Innovus.
– innovus
• See the terminal.

• You can use

– GUI
– Text commands

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 1. Chip Outlining

• Click “File” → “Import Design…”.

• In the “Design Import” window, click “Load…” and choose
“VQS64_4_m.globals”. This will automatically fill up the settings.
Then, click “OK”.

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 1. Chip Outlining

• See the terminal for Innovus messages. There might be some

Error or Warning messages. You can ignore them.
• In the Innovus main window, press “f” to see the outline of the
layout.
• Innovus automatically computes and prepares the layout area.
• Let’s modify the layout area.
• In the main window, click “Floorplan” → “Specify Floorplan…”.
• Set the core utilization to 0.6.
• Set the core-to-left, core-to-top, core-to-right, and core-to-bottom
to 5.0.
• Then, click OK.

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1. Chip Outlining

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 1. Chip Outlining

• Now, you will see the following window.

Power/Ground rings will

be laid out in this area.

Std. cells will be

placed in this core area.

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 Save

• Let’s save the current design.

• In the terminal, run the following command to save the current
design into “test_01_floorplan.enc”.
innovus #> saveDesign test_01_floorplan.enc

• Later on, you can load the design as follows.

– Run Innovus, click File → Restore Design → Data Type:
Innovus → select the .enc file.

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 2. P/G Network Design

• Click “Power” → “Power Planning” → “Add Rings…”.

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 2. P/G Network Design

• Fill in the input boxes as shown in the previous page and click
OK. Now you can see the power and ground rings.

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 2. P/G Network Design

• Zoom in the top-left corner (Mouse right click – hold – drag –

release). As shown below, the outer ring is VSS and the inner
ring is VDD. Blue: Metal 1. Red: Metal 2. Zoom in the via arrays.

Zoom in

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 2. P/G Network Design

• The “X” squares are vias connecting the M1 and M2 wires.

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 2. P/G Network Design

• Press “f” to zoom out to the full design.

• Now, we will draw power/ground stripes to connect the P/G

rings to standard cells.

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 2. P/G Network Design

• Click “Route” → “Special Route…”.

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 2. P/G Network Design

• P/G network

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 2. P/G Network Design

• saveDesign test_02_pg.enc

• Zoom in the following area.

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 2. P/G Network Design

• As you see, the P/G stripes are alternating between VDD and
VSS. See the vias.

Via array Ground stripe

Std. cell row

Power stripe

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 3. Placement

• Let’s place the instances (cells).

• In the main window, click “Place” → “Place Standard Cell”.
• In the “Place” window, click “Mode”.

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 3. Placement

• Turn on “Place IO Pins”. Set the “Specify Maximum Routing

Layer” to 6. We will use only six metal layers. Click OK. In the
“Place” window, click OK.

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 3. Placement

• It shows placement and trialRoute results. trialRoute is just a

quick routing for an estimation of some design metrics.
• See the terminal. It shows some more information.Click this button
if you can’t see the layout.
– Total wire length: 32,540.21um

• Save it.
– saveDesign test_03_pl.enc

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 3. Placement

• Let’s zoom in.

Cell orientation

Flipped (Top: VSS,

Bottom: VDD)

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 3. Placement

• Click a wire and press ‘q’. You will see a property window.

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 Visibility

• Let’s see the placement result only.

• Turn off the following check-box to turn off the visibility of the
wires.

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 Timing Analysis

• Run the following command to turn off SI-awareness.

– innovus #> setDelayCalMode –siAware false

• Then, run the following command to analyze setup time.

– innovus #> timeDesign –preCTS
– preCTS means “before Clock-Tree-Synthesis”. A clock tree
is designed after placement.

• It will show the following summary:

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 Timing Analysis

in2out

reg2out
Primary inputs Primary outputs
in2reg reg2reg Reg

Setup time analysis

Negative WNS

Design Rule
Violations

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Layout density
 Timing Analysis

• Run the following command to check the longest path.

– innovus #> report_timing
– The clock frequency is 1GHz.

F/F setup time (90ps)

Clock period
RT
AT
Slack (=RT – AT)

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 4. Pre-CTS Optimization

• Now, since the design violates the timing constraints, let’s

optimize it. (Notice that we can still try to optimize it to reduce
power even if it satisfies the timing constraints.)

• Run the following command to optimize the design before CTS.

– innovus #> optDesign –preCTS

• (This will take some time, up to several minutes depending on

the machine you are working with).

• After Pre-CTS optimization is done, you will see the following

result:

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 4. Pre-CTS Optimization

• Pre-CTS optimization

Positive WNS!!!

The density increased from 57% to 61%.

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 4. Pre-CTS Optimization

• saveDesign test_04_prectsopt.enc

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 5. Clock Tree Synthesis (CTS)

• Run the following command to run CTS.

– innovus #> create_ccopt_clock_tree_spec
– innovus #> get_ccopt_clock_trees *
• myCLK (You will see this.)
– innovus #> set_ccopt_property target_max_trans 0.05
• Max. transition time at a clock pin is 50ps.
– innovus #> set_ccopt_property target_skew 0.02
• Clock skew is 20ps.
– innovus #> ccopt_design

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 5. Clock Tree Synthesis (CTS)

• saveDesign test_05_cts.enc

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 Timing Analysis

• Run the following command to check timing.

– timeDesign –postCTS

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Before CTS After CTS
 6. Post-CTS Optimization

• Although we already satisfied the timing without any further

optimization after CTS, we will run post-CTS optimization.
– innovus #> optDesign –postCTS

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 6. Post-CTS Optimization

• saveDesign test_06_postctsopt.enc

• So far, we have done

– Placement
– CTS

• Now we will route the nets.

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 7. Routing

• Click “Route” → “NanoRoute” → “Route…”.

• Make sure that the top layer is “6”. If not, set it to 6.
• Click OK.

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 7. Routing

• Routing result.
• See the log.
– WL: 35,172um

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 7. Routing

• saveDesign test_07_route.enc

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 Timing Analysis

• Run the following command to check timing.

– timeDesign –postRoute

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 8. Post-Routing Optimization

• Although we’ve already satisfied the timing without any further

optimization after routing, we will run post-routing optimization.
– innovus #> optDesign –postRoute

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Before postRoute opt. After postRoute opt.
 Power Analysis

• innovus #> report_power

Power consumed inside std. cells when switching

Power consumed to drive nets
Total power
(9.7 mW)

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 8. Post-Routing Optimization

• saveDesign test_08_postrouteopt.enc

• Done.

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9. Verification

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 9. Verification

• In the main menu, Verify → Very Geometry. Click OK.

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 9. Verification

• In the main menu, Verify → Very Connectivity. Click OK.

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 10. Conclusion

• Although there were six geometry violations, we will stop at this

point.

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