Sahakar Maharshi Shankarao Mohite Patil

Institute Of Technology & Research, Akluj

(Approved by A.I.C.T.E, New Delhi, and Govt. Of Maharashtra and Affiliated to
Solapur University, Solapur) Post – Yeshwantnagar, P.O.Box.No. 5, Pin –
413118, Tal – Malshiras, Dist – Solapur (Maharashtra)

ACADEMIC YEAR 2020 - 2021 SEMESTER ODD

NAME OF STUDENT

CLASS/ SEM./BATCH

ROLL NUMBER CSE -

Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj
INSTITUTE MISSION
“Sustainable rural development through technology
transformation”

Department of Computer Science &

Engineering

VISION
To enable & transform computer technology for rural
society

MISSION
• To realize the full potential of the internet universal accesses to
research & education.
• To create technology content those educate, inform & inspire
industry.
• To work towards an integrated technology that reaches across
all disciplines & age levels.
• To apply innovative technology to promote the highest levels of
technology support.
 PROGRAM EDUCATIONAL OBJECTIVES (PEO)

• Graduate will exhibit strong fundamental knowledge and technical skills

in the field of Computer Science & Engineering to pursue successful
professional career, higher studies and research.

• Graduate will exhibit capabilities to understand and resolve various

societal issues through their problem solving skills.

• 3.Graduate will be sensitive to ethical, societal and environmental issues

as a software engineering professional and be committed to life-long
learning.
 Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj
Department of Computer Science &
Engineering

LAB MANUAL

COURSE CLUSTER

COURSE CODE CS214

PRN. NO.

EXAM. NO.

MOBILE NO. (student) +91-

NAME OF FACULTY Prof. Bhise P. A.

 Sahakar Maharshi Shankarao Mohite Patil Institute
Of Technology & Research, Akluj

Department of Computer Science &

Engineering

INDEX
As. Pg. Submission
Name of Topic/Sub-topic Given Date Marks Sign.
No. No. Date

a) Verification of truth table of

basic and universal logic gates

1 b) Implementation of Boolean 20 20
functions using Basic and
Universal Gates.

Implementation of reduced
Boolean functions (K – map 20 20
technique) from Assignment No
2 1 using basic and universal
gates.

Implementation of half adder 20 20

and full adder using logic Gates
3

a) Design and Implement a 4:1

multiplexer using 74153 IC. 20 20
b) Design and Implement a 8:1
4
multiplexer using 74151 IC.

Implementation of flip flops 20 20

5 using NAND/NOR gates: S-R
Flip flop, D flip flop.
 Implementation of Mod 10
(Decade) Counter using IC 20 20
6 7490.

a) Write Verilog code to realize

all the logic gates, Simulate and 20 20
verify it’s working.
b) Design the Half subtractor
7 and full Subtractor using
Verilog Code, Simulate and
verify its working.

a) Design a 4:1 & 8:1

multiplexer circuit using Verilog 20 20
8 Code, Simulate and verify it’s
working.

Average Assignment Marks ( out of 6)

Attainment Level (U/D/S/E)

U=Unsatisfactory (> 6) D= Developing (6-7) S= Satisfactory (7-8) E= Exemplary (< 8)

 Sahakar Maharshi Shankarao Mohite Patil Institute
Of Technology & Research, Akluj

Department of Computer Science & Engineering

NAME OF SUBJECT Digital Technique

ROLL NO.

EXPERIMENT NO.01 a) Verification of truth table of basic and universal

logic gates

b) Implementation of Boolean functions using Basic

and Universal Gates.

GIVEN DATE

SUBMISSION DATE

SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS
 EXPERIMENT NO.01
TITLE: BASIC AND UNIVERSAL GATES
AIM:
a) Verification of truth table of basic and universal logic gates.
b) Implementation of Boolean functions using Basic and Universal Gates

OBJECTIVES:

a) To verify basic gates by using truth table.

b) To verify universal gates by using truth table.
c) To implement Boolean function using Basic and Universal Gates

APPARATUS:

IC Trainer Kit, patch chords, power supply, AND(IC 7408), OR (IC7432), NOT
(IC7404), NOR (IC7402), NAND (IC7400).

THEORY:

a) Verification of truth table of basic and universal logic gates.

A logic gate is just a simple Boolean function, in the sense that it has only
either of two outputs. Either 1 or 0, high or low, true or false, whatever you call
it. It is the most elementary tool in building a circuit. A logic gate performs a
logical operation on an input and gives the appropriate output for it. There are 3
basic logic gates. Those are AND gate, OR gate and NOT gate. There are 2
universal gates NAND gate and NOR gate. Given below are the different logic
gates, their symbols, descriptions and truth tables.

2-Input AND Gate IC 7408

The AND gate is a digital logic gate with ‘n’ i/ps one o/p, which perform
logical conjunction based on the combinations of its inputs. The output of this
gate is true only when all the inputs are true. When one or more inputs of the
AND gate’s i/ps are false, then only the output of the AND gate is false. The
symbol and truth table of an AND gate with two inputs is shown below.
 Truth Table of AND Gate
A B Y=A.B

0 0 0

0 1 0

1 0 0

1 1 1

Fig 1.1: Pin Configuration of AND gate

2-Input OR Gate IC 7432

The OR gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs
a logical conjunction based on the combinations of its inputs. The output of the
OR gate is true only when one or more inputs are true. If all i/ps of the gate
are false, then only the output of the OR gate is false. The symbol and truth table
of an OR gate with two inputs is shown below.

Truth Table of OR Gate

A B O/P

0 0 0

Fig 1.2: Pin Configuration of OR gate 0 1 1

1 0 1

1 1 1
 Inverter Gate (NOT Gate) IC7404

The NOT gate is a digital logic gate with one input and one output that
operates an inverter operation of the input. The output of the NOT gate is the
reverse of the input. When the input of the NOT gate is true then the output will
be false and vice versa. The symbol and truth table of a NOT gate with one input
is shown below.

Truth Table of NOT Gate

A B O/P

0 0 1

0 1 0

1 0 0

Fig 1.3: Pin Configuration of NOT gate 1 1 0

2-Input NAND Gate IC 7400LS

The NAND gate is a digital logic gate with ‘n’ i/ps and one o/p, that
performs the operation of the AND gate followed by the operation of the NOT
gate. NAND gate is designed by combining the AND and NOT gates. If the input
of the NAND gate high, then the output of the gate will be low. The symbol and
truth table of the NAND gate with two inputs is shown below. Truth Table of
NAND Gate

A O/P

0 1

1 0

Fig 1.4: Pin Configuration of NAND gate

2-Input NOR Gate IC 7402

 The NOR gate is a digital logic gate with n inputs and one output, that
performs the operation of the OR gate followed by the NOT gate. NOR gate is
designed by combining the OR and NOT gate. When any one of the i/ps of the
NOR gate is true, then the output of the NOR gate will be false. The symbol and
truth table of the NOR gate with truth table is shown below.

Fig 1.5: Pin Configuration of NOR gate

b) Implementation of Boolean functions using Basic and Universal Gates

A sum-of-products expression contains the sum of different terms, with

each term being either a single literal or a product of more than one literal. It
can be obtained from the truth table directly by considering those input
combinations that produce logic ‘1’ at the output. Each such input combination
produces a term. Different terms are given by the product of the corresponding
literals. The sum of all terms gives the expression. For example, the truth table
in Table 1.1 can be represented by the Boolean expression

Y=AB+AC (1.1)

Considering the fifth term, the output is ‘1’ when A =1, B =0 and C =0. Other
terms can be explained similarly.
 Table 1.1 truth table of Boolean expression of equation 1.1

A B C Y1 Y2 Y

0 0 0 0 0 0

0 0 1 0 0 0

0 1 0 0 0 0

0 1 1 0 0 0

1 0 0 0 1 1

1 0 1 0 0 0

1 1 0 1 1 1

1 1 1 1 0 0

Representation of Boolean expression by using the basic gates:

The representation of Equation (1.1) is known as Sum-Of-Product form.

This can be realized using AND-OR gates shown in fig. (1.2) .This is also a two
level realization. The first level consist of the AND gates and second level consist
of OR gate.

Fig 1.6: Logical Diagram of equation 1.1 by using basic gates

Representation of Boolean expression by using the universal gates:

Equation (1.1) can be realized by using NAND gates only. The realization is given
in figure (1.3) .This is also a two level realization and in this only NAND gates are
used. Therefore, if we express the eqn. in the SOP form we can always design the
circuit using only the one type of gates (NAND).

Fig 1.7: Logical Diagram of equation 1.1 by using universal gates

Procedure: -

1. Place the IC on IC Trainer Kit.

2. Connect VCC and ground to respective pins of IC Trainer Kit.
3. Connect the inputs to the input switches provided in the IC Trainer
Kit.
4. Connect the outputs to the switches of O/P LEDs,
5. Apply various combinations of inputs according to the truth table
and observe condition of LEDs.
6. Verify the truth table of various gates.
7. Apply various combinations of inputs according to the truth table
and observe conditions of LEDs.
8. Verify the truth table for each input-output combination.

Conclusion:

Questions

1. Write and explain all the gates with truth table and Symbols.
2. Explain uses of different Gates in various Fields.
Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj

Department of Computer Science &

Engineering
 Implementation of reduced Boolean functions (K
EXPERIMENT NO. 02 – map technique) from Assignment No 1 using
basic and universal gates.

GIVEN DATE

SUBMISSION DATE

SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL

MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS

EXPERIMENT NO. 2
TITLE: REDUCED BOOLEAN FUNCTIONS
AIM:
Implementation of reduced Boolean functions (K – map technique) from
Assignment No 1 using basic and universal gates

OBJECTIVES:

a) To implement reduced Boolean functions using basic gates.

b) To implement reduced Boolean functions using universal gates.

Apparatus:

IC Trainer Kit, patch chords, power supply, AND(IC 7408), OR(IC7432),

NOT(IC7404), NAND(IC 7400)

Theory:

Karnaugh maps are the most extensively used tool for simplification of
Boolean functions. It is mostly used for functions having up to six variables
beyond which it becomes very cumbersome. In an n-variable K-map there are 2ⁿ
cells. Each cell corresponds to one of the combination of n variable, since there
are 2ⁿ combinations of n variables. Gray code has been used for the identification
of cells. The following function is to be reduced by using K-Map.

Y=ABC+A’BC+AB’C+ABC’……….1

The given function is in SOP form. In SOP form Normal terms are represented
by 1 and negation terms are represented by 0.So, the equation will become as
in binary form as below,

Y=111+011+101+110…………2

Y=∑m (3, 5, 6, 7)…………3

This can be represented in truth table as follows,

Table No.2.1: Truth Table For Equation 1

INPUTS OUTPUT

A B C Y

0 0 0 0
 0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 1

Here, 3 Variable K-Map is required

After solving the K-map, we will get the following equation

Y=AB+BC+AC……………4

The logical diagram for above equation can be as follows,

Fig 2.1: logical diagram for equation 4

Procedure:

1. With given equation in SOP/POS forms first of all draw a K-map.

2. Enter the values of the O/P variable in each cell corresponding to its
Min/Max term.

3. Make group of adjacent ones.

4. From group write the minimized equation.

5. Design the circuit of minimized equation & verify the truth table.

Conclusion:

Questions

1. Explain K map Reduction techniques using SOP and POS form.

2. Solve 2 examples of K map reduction for SOP and POS form.

3. Explain Don’t Care Condition with Example

Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj

Department of Computer Science &

Engineering

EXPERIMENT NO. 03 Implementation of half adder and full adder using

Basic Gates.

GIVEN DATE

SUBMISSION DATE
SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL

MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS

EXPERIMENT NO. 03
Half Adder and Full Adder
AIM:

Implementation of half adder and full adder using logic Gates

OBJECTIVES:

c) To implement half adder by using logic gates

d) To implement full adder by using logic gates

Apparatus:

IC Trainer Kit, patch chords, power supply, AND(IC 7408), OR(IC7432),

NOT(IC7404).
Theory:

Half Adder:

A half adder can add two bits at a time. Its outputs are SUM and
CARRY. For two bit addition- SUM will be 1, if only one input is 1(X-OR
operation). CARRY will be one, when both inputs are 1 (AND operation).
So, by using one AND gate and one X-OR gate, a half adder circuit can be
constructed.

Table 3.1: Truth table of an half-adder.

Inputs Outputs

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

From the truth table, we obtain the logical expressions for S and C outputs as:

SUM = AB’ + A’B (3.1)

SUM=A + B

CARRY = AB (3.2)

The realization of an half adder using the gates is shown in Fig.3.1

 Fig3.1: realization of an half adder using the basic gates

Full adder:

An half adder has only two inputs and there is no Provision to add a carry
coming from lower order bits when multi bit is performed.

For this purpose ,a third input terminal is added and this circuit is used
to add An , Bn and Cn-1,where An and Bn are nth order bits of the numbers A
and B respectively and Cn- is the carry generated from the addition of (n-1)th
order bits. This circuit is referred to as full-adder and its truth table is given in
Table 3.2

Table 3.2: Truth table of a full-adder

Inputs Outputs

An Bn Cn-1 Sn Cn

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1
 The K-map for the outputs Sn and Cn are given below and the minimized
expressions are given below,

K-map for Sum

00 01 11 10

K-map for Carry

00 01 11 10

0 0 1 0

0 1 1 1

Sn=AnBnCn-1 + AnBnCn-1 + AnBnCn-1 + AnBnCn-1.

=

0 1 0 1

1 0 1 0
 Fig3.2: realization of a full adder using the basic gates

Procedure:

1. Connect the trainer kit to ac power supply.

2. Connect logic sources to the inputs of the adder.
3. Connect output from SUM and CARRY to logic indicators.
4. Apply various input combinations to the adder.
5. Observe the SUM and CARRY outputs, verify the truth table for each
input/ output combination.
6. Switch off the ac power supply.

Conclusion:
Questions

1. Explain Half Adder and Full adder with truth Table and Diagram.

2. Explain Half Sub-tractor and Full Sub-tractor with truth Table and
Diagram.
Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj
 Department of Computer Science &
Engineering

EXPERIMENT NO. 04 Sequential Logic Circuit

GIVEN DATE

SUBMISSION DATE

SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL

MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS

EXPERIMENT NO. 04
IMPLIMENTATION OF MULTIPLEXER
 Aim:

a) Design and Implement a 4:1 multiplexer using 74153 IC.

b) Design and Implement a 8:1 multiplexer using 74151 IC.

Objectives:

a) To Design and Implement a 4:1 multiplexer using 74153 IC.

b) To Design and Implement a 8:1 multiplexer using 74151 IC.

Apparatus:

IC Trainer Kit, patch chords, power supply, 74153 IC, 74151 IC

Theory:

Multiplexer:-

Multiplexer is the special type of combinational circuit. It quite often

happens, in the design of large-scale digital systems, that a single line is required
to carry two or more different digital signals. Of course, only one signal at a time
can be placed on the one line. What is required is a device that will allow us to
select, at different instants, the signal we wish to place on this common line.
Such a circuit is referred to as a Multiplexer.

A multiplexer performs the function of selecting the input on any one

of 'n' input lines and feeding this input to one output line. Multiplexers are used
as one method of reducing the number of integrated circuit packages required
by a particular circuit design. This in turn reduces the cost of the system.

Block diagram of multiplexer:-

 Fig4.1 Block diagram of multiplexer

4:1 multiplexer

IC Description:

74153 is a 4 line-to-1 line multiplexer. It has the schematic representation

shown in Fig 4.2. Selection lines S1 and S0 select the particular input to be
multiplexed and applied to the output. Strobe S acts as an enable signal. If strobe
=1, the chip 74153 is the chip disabled and output y = 0. If strobe = 0 then the
chip 74153 is enabled and functions as a multiplexer. Table 4.1 shows the
multiplex function of 74153 in terms of select lines. IC 74LS153 is used as 4x1
multiplexer IC & pinout for IC 74153 is as below:

Fig.4.2.Pin diagram of MULTIPLEXER IC74LS153

Table 4.1:Truth Table for 4:1 MUX

Strobe Select Lines Output

G S1 S0 Y

1 X X 0

0 0 0 D0
 0 0 1 D1

0 1 0 D2

0 1 1 D3

8:1 multiplexer

IC Description:

74151 is a 8 line-to-1 line multiplexer. It has the schematic representation

shown in Fig 5.2. Selection lines S2, S1 and S0 select the particular input to be
multiplexed and applied to the output. Strobe S acts as an enable signal. If strobe
=1, the chip 74151 is disabled and output y = 0. If strobe = 0 then the chip 74151
is enabled and functions as a multiplexer. Table 1 shows the multiplex function
of 74151 in terms of select lines. IC 74LS151 is used as 8x1 multiplexer IC &
pinout for IC 74151 is as below:

Fig.4.3.Pin diagram of MULTIPLEXER IC74LS151

 Fig.4.4 IC type 74151 Multiplexer 8×1

Table 5.1

Table 4.2:Truth Table for 4:1 MUX

Strobe Select Lines Output

S S2 S1 S0 Y

1 X X X 0

0 0 0 0 D0

0 0 0 1 D1

0 0 1 0 D2

0 0 1 1 D3

0 1 0 0 D4

0 1 0 1 D5

0 1 1 0 D6

0 1 1 1 D7
Procedure: -

1. Make the connections as per the circuit diagram.

2. Switch on Vcc.

3. Applying i/p and Check for the outputs.

4. Verify the truth table.

Conclusion:

Questions

1. Expain Multiplexer and Demultiplexer

2. Explain Mux And Demux Tree with an example.

Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj

Department of Computer Science &

Engineering
EXPERIMENT NO. 05 Implementation of flip flops using NAND/NOR
gates: S-R Flip flop, D flip flop.

GIVEN DATE

SUBMISSION DATE

SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL

MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS

EXPERIMENT NO. 05
Flip Flops Using NAND/NOR Gates

Aim: Implementation of flip flops using NAND/NOR gates: S-R Flip flop, D
flips flop.
Objectives:

a) To implement S-R Flip flop by using NAND/NOR gates

b) To implement D Flip flop by using NAND/NOR gates

Apparatus: IC Trainer Kit, patch chords, power supply IC 7400,

Theory:
Logic circuits that incorporate memory cells are called sequential logic
circuits their output depends not only upon the present value of the input but
also upon the previous values. Sequential logic circuits often require a timing
generator (a clock) for their operation. The latch (flip-flop) is a basic bi-stable
memory element widely used in sequential logic circuits. Usually there are two
outputs, Q and its complementary value.

S-R FLIP FLOP:

A simple memory flip-flop is the RS FF (SR FF). This device has two inputs
- S for setting and R for resetting the flip-flop (hence its name). The RS flip-flop
preserves its states as long as the inputs S and R are 0. If it receives a set signal,
it turns to 1, regardless of its former state. A reset signal enforces a 0 state.

Fig 5.1: Circuit diagram of SR Flip Flop.

The truth table of SR Flip Flop is as below,

Inputs Output

Sn Rn Qn+1

0 0 Qn

0 1 0
 1 0 1

1 1 ?

J-K Flip Flop:

The RS FF presented in the previous section has a serious disadvantage. For an

RS FF one input combination is not allowed. The JK FF is a modified RS FF (J
corresponds to the set and K to the reset input), which inverts its state when the
input J = 1 and K = 1 occurs. Since it has no forbidden input combinations, the
JK FF can be easily used to generate other types of flip flops.

Fig 7.3(a) Symbol of JK flip flop (b) Circuit diagram of JK Flip Flop.

The truth table of JK Flip Flop is as below,

Inputs Output

Sn Rn Qn+1

0 0 Qn

0 1 0

1 0 1
 1 1 Qn

Delay (D) Flip-flop

As the name implies the purpose of a D FF is to temporary store (or delay) a

single bit. A signal of 0 or 1 present at the input D is transferred to the output
Q whenever the clock CLK is set to 1. Fig. shows the gate symbol of a D flip-
flop. If we look closely at the truth table again we will see that it is quite simple
to construct a D FF out of a JK FF. A delay flip-flop uses only the situations
where the J and K inputs are different. This would make a D FF truth table only
2 lines. So how can we get rid of the other two lines in a JK FF truth table? We
make sure they do not occur by connecting a NOT gate between the inputs J and
K, as shown in Fig.

Fig 5.5(a) Symbol of D flip flop (b) Circuit diagram of D Flip Flop.

The truth table of D Flip Flop is as below,

Inputs Output

0 0

1 1

Procedure:
1 Draw block diagram, truth table and pin diagram for respective IC.

2 According to pin assignment, connect the circuit as shown in fig. by using

connecting wires.

3 Switch ‘ON’ the power supply.

4 Apply the corresponding inputs and verify the truth table.

Conclusion:

Questions

1. Explain all 4 flip flops with diagram and Truth table.

2. What is excitation Table explain in Brief.

Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj

Department of Computer Science &

Engineering
EXPERIMENT NO. 06 Implementation of Mod 10 (Decade) Counter &
Mod 5 counters using IC 7490.

GIVEN DATE

SUBMISSION DATE

SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL

MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS

EXPERIMENT NO. 06
Implementation of Mod 10 (Decade) Counter using IC 7490

Aim: Implementation of Mod 10 (Decade) Counter using IC 7490.

Apparatus: Digital IC trainer kit, IC 7490, patch chords, power supply,
Digital IC trainer kit.

Theory :
7490 4-Bit Ripple Counter:

The 7490, like the 7493, is another 4-bit ripple counter. However, its flip-
flops are internally connected to provide MOD-2 (count-to-2) and MOD-5 (count-
to-5) counter sections. Again, each section uses a separate clock: Cp0 for MOD-
2 and Cp1 for MOD-5. By connecting Q0 to Cp1 and using Cp0 as the single
clock input, a MOD-10 counter (decade or BCD counter) can be created. When
master reset inputs MR1 and MR2 are set high, the counter’s outputs are reset
to 0—provided that master set inputs MS1 and MS2 are not both high (the MS
inputs override the MR inputs).

Fig: Pin configuration of IC7490 (Decade Counter)

When MS1 and MS2 are high, the outputs are set to Q0 = 1, Q1 = 0, Q2 =
0, and Q3 = 1. In the MOD-10 configuration, this means that the counter is set
to 9 (binary 1001). This master set feature comes in handy if you wish to start a
count at 0000 after the first clock transition occurs (with master reset, the count
starts out at 0001).

Truth table of decade counters as follows,

 Clock Signal QA QB QC QD

1st 0 0 0 0

2nd 0 0 0 1

3rd 0 0 1 0

4th 0 0 1 1

5th 0 1 0 0

6th 0 1 0 1

7th 0 1 1 0

8th 0 1 1 1

9th 1 0 0 0

10th 1 0 0 1

It is a simple counter which can count from 0 – 9. As it is a 4 bit binary decade

counter, it has 4 output ports QA, QB, QC and QD. When the count reaches 10,
the binary output is reset to 0 (0000), every time and another pulse starts at pin
number 9. The Mod of the IC 7490 is set by changing the RESET pins R1, R2,
R3, R4.

If any one of R1 & R2 is at high or R3 & R4 are at ground, the counter will reset
all the outputs QA, QB, QC and QD to 0. If the pins R3 & R4 are high, then the
count on QA, QB, QC and QD is 1001.

As we studied earlier, we can increase the counting capability of a Decade

number by connecting more ICs n series; we can count 99 with two 7490 ICs
connected in series. This 7490 IC has inbuilt Divide by 2 and Divide by 5
counters in it.

It can also be used as divide by 10 counter by connecting by connecting clock

input 2 and QA and connecting all rest pins to ground and giving pulse input to
1. It is used as divide by 6 counter by supplying pulse at input 1 and grounding
reset pins R3 and R4 and connecting QA with input 2.

7490 IC can work like bi –quinary counter, which is used to store decimal digits
in the form of 4 bit binary numbers.
Procedure:

1) Make the connection as per circuit diagram for IC7490.

2) Apply the clock

3) Connect the outputs to the switches of O/P LEDs and observe conditions of
LEDs.

4) Note the readings from QA, QB, QC, QD and make the observation table.

Conclusion:

Questions

1. Explain Synchronous and asynchronous counter with example.

2. What is UP Down Counter expain with example.

Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj

Department of Computer Science &

Engineering
a) Write Verilog code to realize all the logic gates,
EXPERIMENT NO. 07 Simulate and verify it‘s working.
b) Design the Half subtractor and full subtractor
using Verilog Code, Simulate and verify its
working..
 GIVEN DATE

SUBMISSION DATE

SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL

MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS

EXPERIMENT NO. 07
Verilog code implementation

Aim: a) Write Verilog code to realize all the logic gates, Simulate and verify it’s
working.
b) Design the Half subtractor and full Subtractor using Verilog Code,
Simulate and verify it’s working.
Software Used: Xlinx

Theory :
Verilog is a Hardware Description Language; a textual format for describing
electronic circuits and systems. Applied to electronic design, Verilog is intended
to be used for verification through simulation, for timing analysis, for test
analysis (testability analysis and fault grading) and for logic synthesis.

The Verilog HDL is an IEEE standard - number 1364. The first version of the
IEEE standard for Verilog was published in 1995. A revised version was
published in 2001; this is the version used by most Verilog users. The IEEE
Verilog standard document is known as the Language Reference Manual, or
LRM. This is the complete authoritative definition of the Verilog HDL.

A logic gate performs a logical operation on one or more logic inputs and
produces a single logic output. The logic is normally performed as Boolean logic
and is most commonly found in digital circuits.

In verilog, one circuit is represented by set of "modules". We can consider

a module as a black box. With this assumption, if you draw a block diagram of
the circuit with a set of signals connection each other, that is called top level
design. Then go on writing modules for each black box, then design that black
box with in the same way. This is how we are designing a circuit. You will
understand this concept after studying some examples. A module may be one
gate, one flip-flop, one register, one ALU one controller or one SOC. Go back to
the example. Here, module is keyword, andgate is the name given to the module
in this examples and a, b and y are the ports or connections to the module. Every
modules and with the keyword endmodule.

In the beginning of a module, we have to declare all ports as input output

or inout. By default, ports will have one pin or one bit.

The different types of logic gates are:

i. AND gate
The AND gate is an electronic circuit that gives a high output (1) only
if all its inputs are high. A dot (.) is used to show the AND operation
i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

ii. OR gate
The OR gate is an electronic circuit that gives a high output (1) if one
or more of its inputs are high. A plus (+) is used to show the OR
operation.
 iii. NOT gate
The NOT gate is an electronic circuit that produces an inverted
version of the input at its output. It is also known as an inverter. If
the input variable is A, the inverted output is known as NOT A. This is
also shown as A', or A with a bar over the top, as shown at the
outputs.

iv. NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a
NOT gate. The outputs of all NAND gates are high if any of the inputs
are low. The symbol is an AND gate with a small circle on the output.
The small circle represents inversion.

v. NOR gate
This is a NOT-OR gate which is equal to an OR gate followed by a NOT
gate. The outputs of all NOR gates are low if any of the inputs are
high.

The symbol is an OR gate with a small circle on the output. The small
circle represents inversion.

vi. EXOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if
either, but not both, of its two inputs are high. An encircled plus sign
() is used to show the EOR operation.

vii. EXNOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It
will give a low output if either, but not both, of its two inputs are high.
The symbol is an EXOR gate with a small circle on the output. The
small circle represents inversion.

Program:

The half substractor schematic is mentioned below. The boolean

expressions are:
 Fig: Logical Diagram for half substractor

Program:

module hs ( a, b, d, br)
input a, b;
output d, br;
assign d= a ^ b;
assign br= ~a & b;
endmodule

The full substractor schematic (fig-2) is mentioned below. The boolean

expressions are:

Fig: Logical Diagram for full substractor

Program:
module fs ( a, b, bin, d, br)
input a, b, bin;
output d, br;
assign d= a ^ b^bin;
assign br= (~a & b)l(b & bin)l(~a & bin);
endmodule

Conclusion:

Questions

1. What is verilog HDL ?

2. List HDL implementation model and explain any two.

3. Write VHDL code for full subtractor and draw output waveforms.
Sahakar Maharshi Shankarao Mohite Patil Institute Of
Technology & Research, Akluj

Department of Computer Science &

Engineering

a) Design a 4:1 & 8:1 multiplexer circuit using

EXPERIMENT NO. 08 Verilog Code, Simulate and verify its working.
b) Design a 1:8 Demultiplexer circuit using
Verilog Code, Simulate and verify it‘s working.

GIVEN DATE
 SUBMISSION DATE

SIGN. OF STUDENT

ATTENDANCE PRESENTATION UNDERSTANDING TOTAL

MARKS

02 02 06 10

SIGN. OF FACULTY

REMARKS

EXPERIMENT NO. 08
TITLE:MULTIPLEXER USING VERILOG CODE

Aim: Design a 4:1 & 8:1 multiplexer circuit using Verilog Code, Simulate and
verify it’s working.

Software Used: Xlinx

Theory:

Multiplexer:-

Multiplexer is the special type of combinational circuit. It quite often

happens, in the design of large-scale digital systems, that a single line is required
to carry two or more different digital signals. Of course, only one signal at a time
can be placed on the one line. What is required is a device that will allow us to
select, at different instants, the signal we wish to place on this common line.
Such a circuit is referred to as a Multiplexer.

A multiplexer performs the function of selecting the input on any one

of 'n' input lines and feeding this input to one output line. Multiplexers are used
as one method of reducing the number of integrated circuit packages required
by a particular circuit design. This in turn reduces the cost of the system.

Block diagram of multiplexer:-

Fig4.1 Block diagram of multiplexer

4:1 multiplexer
Fig: Block Diagram of 4:1 MUX

Fig: Logical diagram of 4:1 MUX

Table: Truth Table for 4:1 MUX

Select Lines Output

S1 S0 Y

X X 0

0 0 D0

0 1 D1

1 0 D2

1 1 D3
 8:1 multiplexer

Fig: Block Diagram of 8:1 MUX

Fig: Logical diagram of 8:1 MUX
 Table: Truth Table for 8:1 MUX

Select Lines Output

S2 S1 S0 Y

X X X 0

0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3

1 0 0 D4

1 0 1 D5

1 1 0 D6

1 1 1 D7

Program:

4:1 multiplexer

module mux4to1(S0, S1, DO, D1, D2, D3, Y);

input S0, S1, DO, D1, D2, D3;

output Y;

reg Y;

always@ (S0 or S1 or DO or D1 or D2 or D3)

begin

case ({S0, S1})

0: Y=D0;

1:Y=D1;

2:Y=D2;
3:Y=D3;

endcase

end

endmodule

8:1 multiplexer

module mux8to1(S0, S1, S2, DO, D1, D2, D3,D4, D5, D6, D7, Y);

input S0, S1, DO, D1, D2, D3;

output Y;

reg Y;

always@ (S0 or S1 or DO or D1 or D2 or D3 or D4 or D5 or D6 or D7)

begin

case ({S2, S1,S0})

0: Y=D0;

1:Y=D1;

2:Y=D2;

3:Y=D3;

4:Y=D4;

5:Y=D5;

6:Y=D6;

7:Y=D7;

endcase

end

endmodule

Conclusion:
Questions

1. Write a HDL code for 4 : 1 multiplexer.

2. What is BUS representation in HDL

3. Write a Verilog code for 3 line to 8 line decoder using behavioral modeling
Sahakar Maharshi Shankarao Mohite Patil Institute of
Technology & Research, Akluj
Department of Computer Science &
Engineering
PROGRAM OUTCOMES (PO)
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