TRENDS AND CHALLENGES IN SOC DESIGN

A SEMINAR REPORT

Submitted by
NAGA VARDHAN .I
NITHEESH KUMAR .K

SAI HEMANDRA .B

in partial fulfillment for the award of the degree

of

BACHELOR OF TECHNOLOGY

in

ELECTRONICS & COMMUNICATION ENGINEERING

JANUARY 2021
 BONAFIDE CERTIFICATE

Certified that this seminar report entitled “TRENDS AND CHALLENGES IN SOC
DESIGN” is the bonafide work of “ NAGA VARDHAN.I (Reg. No.18UEEC0158),
NITHEESH KUMAR.K (Reg. No.18UEEC0193) and SAI HEMENDRA .B.V (Reg.
No.18UEEC0057)”.

HEAD OF THE DEPARTMENT

Dr.R.S.VALARMATHI
Professor
Department of ECE

Submitted for Evaluation of Seminar held on: 17-01-2021

INTERNAL EXAMINER EXTERNAL EXAMINER

 ACKNOWLEDGEMENT

We express our deepest gratitude to our respected Founder President and Chancellor COL. PROF. VEL.
Dr. R. RANGARAJAN, Foundress President Dr. SAGUNTHALA RANGARAJAN, Chairperson Managing
Trustee and Vice President. We are very thankful to our beloved Chancellor COL. PROF. VEL. Dr. R.
RANGARAJAN for providing us with an environment to complete the work successfully.

We would like to express our gratitude towards our Vice Chancellor PROF. Dr. S. SALIVAHANAN for
his kind cooperation and encouragement.

We obligated t o our beloved Registrar Dr. E. KANNAN, for providing i m m e n s e support in all our
endeavors.

We thankful to our esteemed Director Academics Dr. A. T. RAVICHANDRAN, for providing immense
support in all our endeavours.

We extremely thankful and pay our gratitude to our Dean Dr. V. JAYASANKAR for enormous care and
encouragement towards us throughout the seminar.

It is a great pleasure for us to acknowledge the care of our Head of the Department Dr. R. S. VALARMATHI
for her valuable suggestions which helped us in completing the work in time and we thank her for being
instrumental in the completion of the seminar with her encouragement and unwavering support. We thank
our department faculty, supporting staffs for their help and guidance to complete this seminar.

NAGA VARDHAN.I

NITHEESH KUMAR.K

SAI HEMENDRA .B.V

 TABLE OF CONTENTS

ABSTRACT

1. INTRODUCTION

2. PREVAILING SYSTEM DESIGN APPROACH

2.1. programmable processor

2.2. hardware-software co-design
2.3. ip reuse
2.4. cross-disciplinary vertical integration

3. EMERGING DESIGN ISSUES

3.1. Power Consumption

3.2. Memory Bandwidth and Latency
3.3. Transistor Variability

4.MODERN SYSTEM DESIGN TRENDS

4.1. Power Efficiency

4.2. Multi-Processor Socs
4.3. Reconfigurable Logic
4.4. Design For Verification And For Testing

5. FUTURE SYSTEM DESIGN CHALLENGES

5.1. Scalable or Reusable Architecture

5.2. IP Integration
5.3. Network-on-Chip
5.4. Embedded Memory
5.5. Reliability

6. VERIFICATION TRENDS

1. Simulation technologies

2. Analog and mixed signal verification

3. Power aware verification

 4. Functional safety verification

7. CONCLUSION

8. REFERENCES
 ABSTRACT

The success of system-on-a-chip (SoC) hinges upon a well-concerted integrated

approach from multiple disciplines, such as device, design, and application. From the
device perspective, rapidly improving VLSI technology allows the integration of billions
of transistors on a single chip, thus permitting a wide range of functions to be combined
on one chip. From the application perspective, numerous killer applications have been
identified, which can make full use of the aforementioned functionalities provided by a
single chip. From the design perspective, however, with greater device integration,
system designs become more complex and are increasingly challenging to design.
Moving forward, novel approaches will be needed to meet these challenges. This paper
explores several new design strategies, which represent the current design trends to deal
with the emerging issues. For example, recognizing the stringent requirements on power
consumption, memory bandwidth/ latency, and transistor variability, novel
power/thermal management, multi-processor SoC, reconfigurable logic, and design for
verification and testing have now been incorporated into modern system design. In
addition, we look into some plausible solutions. For example, further innovations on
scalable, reusable, and reliable system architectures, IP deployment and integration, on-
chip interconnects, and memory hierarchies are all anticipated in the near future.

Hardware verification today is a relatively mature topic, both in research and in

industrial practice. Verification research dates back to at least three decades, with a rich
body of literature . In industrial practice, verification is now firmly established as an
integral component of the system development flow. Unfortunately, in spite of these
advancements, there remains a significant gap between the state of the art in the
technology today and the verification needs for modern industrial designs. The situation
is exacerbated by the rapidly changing design ecosystem as we move rapidly and
inevitably to the era of automated vehicles, smart cities, and Internet of Things. In
particular, this new era has ushered in an environment where an electronic device
collects, analyzes ,and communicates some of our most intimate personal information,
such as location, health, fitness, and sleep patterns, communicates such information
through a network of billions of other computing devices, and must operate without
pause or halt even when that environment may include millions of potentially malicious
or otherwise compromised devices. As system design and architecture get transformed
to adapt themselves to this new ecosystem, verification must adjust aswell .
 In this paper, we discuss several challenges in SOC design and challenges
involved in its verification in this new era. Some of the challenges are classical problems
in verification and design of Soc.

INTRODUCTION

The technology revolution has had a profound impact on our daily life. For example,
personal communication will never be the same. About 80 years ago, Bell Laboratories
demonstrated the first mobile phone prototype which had to be mounted on a car. About
30 years ago, the first hand-held mobile phone became commercially available. Today,
the standard cellular phone is compact, user friendly, and packed with functionality.
Moreover, many optional features are available, such as personal digital assistants and
global positioning systems. In fact, more and more new applications are ready to harness
the technology revolution. Prominent examples include third-generation wireless
communication and a wide range of popular lifestyle consumer electronics (such as,
digital cameras, video camcorders, digital televisions, and set-top boxes). According to
In-Stat/ MDR, the market for smart appliances in digital home experienced a 70%
compound annual growth rate from 2001 to 2006. Moving forward, Gartner Market
Report predicted that $500 millions market for SoC in 2005 will grow over 80% by 2010
. The annual growth rate is about 2 faster than general-purpose microprocessors . Such a
change is largely due to the advances in device technology, which enable us to put billions
of transistors on a chip for almost unlimited processing capability.
Figure 1 shows that in the past 40 years,
we have been able to put about a million times more transistors onto a chip (keeping pace
with Moore_s Law The first microprocessor had a couple of thousand transistors with
functionalities limited to basic logic/arithmetic processing. In contrast, a modern SoC can
have billions of transistors, supporting a wide range of functions (processors/ controllers,
application-specific modules, data storage, and mixed-signal circuits). Thanks to ever
increasing large-scale integration, SoC is able to meet the increasing computational
demand by new applications. We face many formidable challenges, however. System
integration means more than simply squeezing components onto a chip. There is a huge
gap between what can be theoretically designed and what can be practically implemented.
New requirements on performance, power consumption, and rapid design cycles
necessitate we revisit some fundamental design principles. For instance, one of the
persistent challenges is how to deploy in concert an ever increasing number of transistors
with acceptable power consumption. Another challenge is that in order to meet the
increasingly demanding requirements in multimedia applications, SoC must provide
functional flexibility as well as processing capability. There are many other deeper issues
related to SoC research. In this paper, we address the driving force behind SoC designs,
the design flow, current trends, and future challenges— from an architect_s perspective
Figure 2 serves as an outline of this paper. 1. The top level shows the basic driving forces
behind SoC designs, including (1) integrating more transistors within (2) a short period of
time to provide (3) high performance and (4) flexibility, as mentioned earlier. 2. The
second level shows a divide-and-conquer strategy which was adopted to create flexible
SoC products with short design cycles. To elaborate on this strategy, Section 2 in this
paper lists the typical approaches, including hardware-software partitioning/co-design,
programmable core, IP design and reuse, and vertical integration. 3. The third level
displays emerging issues, including power consumption, memory bandwidth/ latency, and
transistor variability, which have a major impact on system designs. These are addressed
in Section 3. 4. Recognizing these emerging issues, the fourth level shows how modern
system design has incorporated novel power/thermal management, multi-processor SoC,
reconfigurable logic, and design for verification and testing. These are covered in Section
4. 5. As depicted in the fifth level, we anticipate further innovations on scalable, reusable,
and reliable system architectures, IP deployment and integration, on-chip interconnects,
and memory hierarchies in the near future. These are addressed in Section 5.
 CHAPTER 2

PREVAILING SYSTEM DESIGN APPROACH

A wealth of knowledge has been accumulated in the VLSI and application-specific

system design community in the past two decades. Many such design strategies remain
valid and are indeed very effective for SoC systems. Therefore, we first review these
prevailing approaches to the design of large-scale systems. To design complex systems,
it is natural to use a divide-and-conquer strategy as shown in Fig. 3. Given the intended
applications, the system is first divided into the analog domain and the digital domain.
The analog domain, such as radio frequency (RF) circuits, can be accomplished via
analog circuit designs. In the digital domain, the implementation of the algorithms can
be further divided into software codes on programmable processors and hardware
accelerators. In the next level, hardware accelerators comprise pre-defined intellectual
property (IP) blocks and fully custom designed circuits. All these circuits must be
integrated onto a chip in concert. Below are the major design components of this divide-
and-conquer strategy.

2.1. PROGRAMMABLE PROCESSOR

With the rapid development cycles in today_s multimedia algorithm research, there
are a number of approaches to take to meet the diverse computing requirements while
achieving high computational and energy efficiencies. A predominant approach is to
incorporate programmable cores—90% of the SoC products in 130 nm technology
have one programmable core. With programmable cores, several different algorithms
can be executed on the same hardware, and the functionality of a specific system can
be easily upgraded by a change in software. This will create a versatile platform that
can follow new generations of applications and standards. Some popular
programmable core implementations use RISC and/or DSP cores [5, 16, 32–34, 47];
or some even extend existing programmable processor cores with multimedia
enhancements
2.2. HARDWARE-SOFTWARE CO-DESIGN

Many applications can be divided into two portions: (1) complex data-dependent and
decision-making procedures, and (2) computationally intensive and regular tasks.
While using a programmable controller to implement control-intensive tasks, we can
employ fast dedicated hardware modules to perform regular computation-intensive
tasks. Therefore, for almost all multimedia SoC designs, there is a common codesign
methodology, as shown in Fig. 4. The methodology includes (1) software and
hardware partitioning, (2) software and hardware synchronization, (3) algorithm
optimization, (4) software optimization, and (5) dedicated hardware design. The
methodology is applicable to video decoders, audio decoders, and other future
multimedia applications.
2.3. IP REUSE

In order to deploy successful SoC products in a timely manner, we must build new
SoCs from circuit blocks that have been designed for previous ones. By using existing
and high-performance IP, SoC designers not only can save time and resources, but
also can create a mind-blowing solution that users want. Additionally, IP does not
just refer to hardwired logic or hardware design. Software development starts to be
on the critical path in time-to-market for SoC. Therefore, it will be great to be able to
quickly assemble new software stacks (e.g., OS, compiler, libraries) from reusable
software .As a matter of fact, while most semiconductor companies have mature
hardware reuse methodologies, the majority of them have not yet reused software
components. Embedded software design can easily take more resources than
hardware design. Furthermore, to sell silicon in today_s business environment,
semiconductor companies must minimize risk and shorten time-to-market for their
customers. There is another development: IP libraries must include behavioral model
descriptions (e.g., SystemC) so that the entire hardware/software codesign can be
simulated and verified at the early design stage.

2.4. CROSS-DISCIPLINARY VERTICAL INTEGRATION

In order to vertically integrate hardware, software, algorithms, applications, and their

interfaces, architecting a SoC design requires cross-disciplinary knowledge. We often
use the divide-and-conquer approach at the very beginning of the system design.
While it is easy get the best performance for each individual component, to get the
best overall performance for the whole system depends heavily on the initial design
of the architecture. The ability to partition the hardware and software and combine
cost-effective silicon with high-performance soft ware stacks is the key differentiator
of a successful SoC design. This requires tight interaction between
algorithm/software design and hardware design. For example, a thorough
understanding of the applications becomes critical, including analyzing the algorithm
based on the performance specification, and exploiting optimization techniques to
reduce the bottlenecks in memory capacity, data bus bandwidth, power dissipation,
and so forth.
 CHAPTER 3

EMERGING DESIGN ISSUES

There are many emerging steering factors behind the modern design trend.
Among them, the ones that have significantly influenced SoC designs are listed
below:

3.1. POWER CONSUMPTION

As more transistors are integrated into a single chip, the chip consumes
more power. However, it is getting harder to deliver more power to a
single chip. Thus, it is important not only to build a system with the
highest performance, but also to deliver the performance with the lowest
power consumption. Low-power design is critical both to battery-powered
devices (because we want our handheld or portable devices to operate
longer) and to line-powered equipment (because power dissipation
strongly influences the packaging/cooling cost and the reliability of the
chip). In addition to high performance, power consumption is a key design
concern. There are two causes of increasing power consumption. First,
because the power dissipation per transistor is not falling at the rate that
gate density is increasing, the power density of future SoCs is set to
increase. Thus, we must reduce overall system power consumption by
using system architecture design rather than relying on process technology
alone. Second, architects used to increase frequency (burn more power) in
order to achieve better performance. For example, as shown in Fig. 5,
from the 1980s to the late 1990s, the power consumption of Intel_s
microprocessors closely follows the trend of Moore_s Law, doubling
every 2 or 3 years. Nonetheless, as power consumption approached the
limits of sustainability, architects were forced to take a different direction.
As a result, the latest Intel\ Corei 2 Duo processors have lower thermal
design power than Intel\ Pentium\ 4 processors. Similarly, SoC architects
have to pay more attention to design choices
3.2. MEMORY BANDWIDTH AND LATENCY

Although computational speeds can improve at a rate of 50% per year, time to
access off-chip memory is not improving at the same rate. DRAM latencies and
bandwidths improve at only 7 and 20%, respectively, as shown in Fig. 6. This
increasing gap between processor and memory speeds is a wellknown problem,
named the memory wall. In order to feed the computational engine, SoC architects
have to take action, such as, integrating embedded memory into the same chip (e.g.,
Section 5.4), or exploiting data access localities at the algorithm or software level.

5.6. TRANSISTOR VARIABILITY

As future transistor sizes decrease to 20 nm and below, we are likely to see

increasing variability in the behavior of transistors, as shown in Fig. 7. This is
because random dopant fluctuations cause variability in transistor threshold
voltages; subwavelength lithography causes line edge roughness and thus
variability in transistors. In addition to static variability in VLSI process
technology, the environment, energy, thermal resources, and even applications can
also yield dynamic variability in circuit operation. These will inevitably lead to
inherent unreliability in components, posing serious design and test challenges. To
make reliable products in the presence of the unreliability of components, SoC
architects start pondering reliability from the perspective of multiple disciplines,
e.g., fabrication, circuit design, logic design, and software.
 CHAPTER 4

MODERN SYSTEM DESIGN TRENDS

In response to the emerging issues behind the design of SoCs discussed in Section
3, several new design strategies (discussed below) have arisen as the most
prominent and promising solutions: these characterize the new paradigm of
modern SoC systems.

4.1. POWER EFFICIENCY

As mentioned earlier, power dissipation is one of the primary design

considerations. In particular, transistor power dissipation is not falling at the same
rate as the gate density is increasing. Rather than relying on processor technology,
modern designs start addressing the problem at the circuit level and the
architecture level. For example, some power management techniques are proposed
to take advantage of idle cycles .One can reduce system-level power dissipation by
shutting off parts of the system that are not used and turning those parts back on
when requests have to be serviced (or reduce and increase the voltage and
frequency). In the past, heuristics were often used to predict workloads and turn
modules on and off. For better efficiency, modern designs further utilize the
knowledge from the applications. Another important technique to reduce power
consumption is to reduce power consumption of clock distribution. Synchronous
designs are widely used, easy to implement, and well supported by logic synthesis
tools. However, there are many drawbacks in global synchronization, especially,
power consumption for clock distribution. In recent years, mesochronous designs
have been proposed to overcome these drawbacks. Mesochronous designs use a
single clock frequency, but different blocks may be at different phases, i.e., the
clock edges may not align. Although there is a latency penalty for transferring data
between blocks, this kind of designs have an advantage of the low power
consumption of the global clock distribution. Thus, it has a potential to become
more popular for complex system designs. Additionally, with power density and
cooling costs rising exponentially, temperature-aware design has become a
necessity. First, chip reliability and performance are increasingly impacted by the
operating temperature. It is shown in that temperature variations and hotspots
account for over 50% of electronic failures. Thermal variations can also lead to
significant timing uncertainty, prompting wider timing margins, and poorer
performance. Hence, how to design and place the Bhot^ and Bcool^ components
together becomes another important aspect in the architecture design. Second, the
traditional cooling system design, which is based on worst-case analysis, will
over-provision the real requirement and thus will not be economical. Modern
designs start incorporating techniques that control or reduce heat dissipation, in
particular, runtime techniques that can regulate operating temperature when the
package_s capacity is exceeded. Note that the emerging 3D stacking technology
introduces more freedom and also places more constraints on future designs .
4.2. MULTI-PROCESSOR SOCS

Programmable cores are widely used in modern design. To further increase

performance without substantially increasing power consumption parallel
processing can be used at the instruction level (e.g., VLIW [27]) and at the data
level .Furthermore, multi-processor SoCs (MPSoCs) start becoming popular. As
multi-processing is a very power-efficient way to increase processing capabilities
we expect there will be more and more processing units in the future. Multiple
processors on the same chip do not have to be the same. A very powerful means to
accelerate multimedia processing is to adapt programmable processors to specific
algorithms via specialized instructions for frequently occurring and high-
complexity operations. A design can integrate multiple programmable cores,
which are individually optimized to a particular characteristic of different
application fields in order to deliver high performance, and complement each
other with flexibility at reduced system cost. These designs are often referred to as
heterogeneous MPSoCs. Because multi-core processors become more prevalent in
vendors_ solutions, application developers must change the algorithms to explore
the full potential of multi-core processors. There will be an essential need for
parallel algorithms and programming, and even in the future for standards
development. Without a properly parallelized program, future multi-core
processors will not deliver their best performance2 . As in the feeling of de´ja` vu,
we will begin to see existing parallel processing challenges in future designs.

4.3. RECONFIGURABLE LOGIC

Designers have used field-programmable gate arrays (FPGA) in board-level

designs for a long while. To create high-performance, versatile platforms, some
architectures start incorporating logic operations and interconnects that can be
reconfigured during run time. Adding reconfigurable logic to the SoC provides
flexibility for changing functionality after fabrication . Compared to
programmable processors, these architectures offer the potential to achieve higher
performance and power-efficiency with greater flexibility. To boost the impact of
reconfigurable SoCs, some research work has been done to extract the parallelism
from the applications/ algorithms and map the parallelism into reconfigurable
architecture efficiently.
4.4. DESIGN FOR VERIFICATION AND FOR TESTING

Traditionally, 70% of time and energy in chip design cycles is spent on verification
Typically, when Trend and Challenge on System-on-a-Chip Designs 223 there is a small
change in a component, we need to re-verify timing for the entire chip design. One way
to avoid that is to create clear boundaries and routing channels between the components.
In this case, changes in one block do not affect the timing of others. For example,
mesochronous clocking is a way to separate different logic blocks from one. As we
integrate a billion transistors onto a single chip, it takes much more time to test the chip
as a whole (verify all the state machines and logic blocks in a design). Furthermore, as
we are likely to see increasing variability in the behavior of the transistors statically and
dynamically, built-in self-tests in each logic block become essential. Additionally, if the
IPs integrated onto a chip come from more than one source, IP providers and SoC
integrators must work closely together to define effective test strategies. Each IP block
must have a wrapper so that it can be isolated from other parts of the system while it is
being tested.
 CHAPTER 5

FUTURE SYSTEM DESIGN CHALLENGES

In the future, the new generation of SoC architecture must meet more open and
challenging design issues, as exemplified below:

5.1. SCALABLE OR REUSABLE ARCHITECTURE

As multimedia applications grow in complexity, we need more and more computational

capability. For example, video coding standards have been evolved from MPEG-2 to
H.264 and the picture resolutions have been increased from DVD (720480) to HDTV
(1,280720 or 1,9201,080). To ensure fast design turnaround time without completely
redesigning the whole system, a scalable architecture is highly desired. Just as we
shifted our IC design paradigm from full custom design to standard cells, even to IP
reuse, the next-generation system design paradigm shift should be the reuse of
architecture. That is, to cope with the growing complexity of SoCs, IP reuse may not be
enough. Reuse must happen at a much higher level than it used to, e.g., architecture
reuse. However, creating a design that can be efficiently reused requires a great deal of
effort.

5.2. IP INTEGRATION

Integration requires more than simply placing components spatially together on a single
chip. A few issues, for example, are outlined below: & How to integrate analog IP
safely; in particular, how to deal with noise from the analog domain to the digital
domain or vice versa. & How to deal with black-box IP. & How to handle its I/O
requests in a timely manner without over-provisioning resources for it. & How to
migrate IPs from one process technology to the next one as quickly as possible. Is
synthesizable soft IP better than customized hard IP even though customized hard IP
may be more efficient? & How to effectively test and verify the whole system when the
IPs come from different sources. These are the challenges beyond simply placing
components together. We need good strategies for the integration of hardware and
software IP components .
5.3. NETWORK-ON-CHIP

The performance of next-generation SoCs will be limited by the ability to efficiently

connect the functional blocks together, and to accommodate their communication
requirements. As applications require more computational power in the next few years,
it is clear that we need multiple processors, processing elements, and function units.
Hence, communication becomes the critical path in the system. The need for synergy of
processing elements and interconnect architectures becomes critical as we face tighter
power budgets in the pursuit of performance targets. First, the delay and energy of
communication wires do not scale down linearly as the transistor size shrinks in the
future; the interconnect will consume a significant amount of chip energy. Second,
because processor and interconnect architectures share a common power and thermal
budget, optimizing the power consumption of each in isolation can have a significant
impact on the other_s power and performance . Furthermore, the unreliability of deep
submicron on-chip wire communication stimulates more challenges. While many
communication architectures make use of buses or crossbars, there are some recent
proposals on network-on-chip (NoC) architectures. One approach is to employ a packet-
switched interconnect. The concept is similar to traditional large-scale wide-area
networks, but in this case, onchip router-based networks are used. Programmable cores
access the network via packet-switched interfaces and have their packets forwarded to
their destinations through a multiple-hop routing path. Nevertheless, the on-die
communication architectures cannot just mimic the off-die communication. This is
because the cost tradeoff of on-chip communication is quite different from that of
onchip communication. We need different designs. For example, while compression of
contents in saved power consumption for off-die bus communication, compression may
need more power for on-die and short-distance communication. Yet another example is
shown in. Because of communication localities and the latencies, circuit-switched NoC
is sometimes more attractive than the traditional packet-switched NoC. An architect
must examine all these factors to determine the best one for the design.

5.4. EMBEDDED MEMORY

As external memory bandwidth becomes a major bottleneck in the future, more on-die
high-speed memory, such as cache or local buffer, will be deployed. Sometimes,
embedded memory (SRAM, DRAM, flash, ROM) will be integrated onto the chip. The
amount of memory integrated into an ASIC-type SoC design has increased from 20% in
1999 to 70% in 2005. Challenges arise when trying to balance efficiency and power.
SRAM provides high performance, while flash memory is the best solution in terms of
power consumption. The amount and the placement of each kind of memory in the SoC
will greatly affect access efficiency and power. Additionally, cache may introduce
indeterminate delay, cache coherence, and memory consistency challenges. Therefore,
the unpredictable latencies associated with caches must be carefully accounted for. An
alternative solution is to use a softwarecontrol local buffer instead of cache. A famous
commercial example of this is the Cell architecture developed by Sony, Toshiba, and
IBM . A software-control local buffer reduces the uncertainty when it comes to latency,
but of its use makes the software more complex. Furthermore, because digital, mixed-
signal, RF, and memory blocks are tightly integrated4 , the power and substrate noise
may cause sensitive blocks to suffer from functional failures. Because of the unique
characteristics of the memory circuit and layout, the power and substrate noise may
cause functional failures. Making embedded memories noise-tolerant will be vital to a
successful SoC design. 3D stacking memory is an alternative exciting technology to
increase bandwidth substantially. However, despite its promising advantages, the
thermal issue of multiple dies stacking together is of serious concern. In short, a high-
performance and low-power SoC architecture must balance the tradeoffs from various
memory options.

5.5. RELIABILITY

Reliability is likely to be a major focus of research as we approach the end of the

decade. As future transistor sizes become smaller than 20 nm, we are likely to see
increasing variability in the behavior of the transistors. Smaller feature sizes lead to
more failures over time from electrostatic overstressing and electro-migration. While
transistors might fail, the entire system cannot fault. We must explore mechanisms to
compensate for this underlying variability in transistor behavior. To address these
challenges, research is being carried out from fabrication to software. Some of the basic
fault tolerance principals that we used in the era of mainframe computers can potentially
be applied to today_s designs. For example, we can detect when a circuit fails and shift
the work to another circuit through hardware-/firmware-based self-management. Yet
another possible solution is to use statistical computing techniques, which use
probabilistic models to derive reliable results from unreliable components. Nonetheless,
none of these techniques is a clear answer on how to efficiently address reliability
issues. The bottom line is that there needs to be an architectural solution.
 CHAPTER 6

VERIFICATION TRENDS

Over the last few years, Foster led several industry studies to identify broad trends in
verification . One can make the following critical observations from these studies:
Verification represents bulk of the effort in the system design, incurring on an average the
cost of about 57% of the total project time. There has been a discernible increase in the
number of projects where verification incurred the cost of over 80% of the project time.
Most designs show an increase in the use of emulation and FPGA models, with more
usage of these technolo- gies the more complex the design. This is consistent withthe need
for a fast prototyping environment particularly for complex SoCs, and also perhaps
emphasizes the role of software in modern systems (which require emulation/FPGA
Prototyping for validation).
1) Most successful designs are productized after an average of two silicon spins.
Note that for a hardware/software system this translates to one spin for
catching all hardware problems and another for all the software interaction
issues. This underlines the critical role of pre-silicon verification to ensure that
there are no critical gating issues during post-silicon validation.
2) There has been a significant increase in the use of both simulation-based
verification and targeted formal verification activities.
The last point above deserves qualification. In particular, recall that both
simulation and formal verification techniques are falling short of the scalability
requirements of modern computing devices. How then are they being having
increasing adoption.
The answer lies in transformative changes that have been occurring in these technologies
in the recent years. Rather than focusing on full functional coverage, they are getting
targeted towards critical design features. Current research trends include verification of
specific emerging application domains such as automotive and security and using data
analytics to improve verification efficiency. In the remainder of this section, we dive a
little deeper into how these technologies have been changing to adapt themselves to the
increasing demand as well as to address the scalability gap.

6.1Simulation Technologies:

Simulation is the mainstay for verifying complex SOCs

thanks to its scalability to large industrial designs. State-of- the-art simulation-based
verification methodologies include a highly automated process that includes test
generation, checking, and coverage collection, combined with islands of manual labor .
In the beginning, a verification plan is defined to capture all the features required to be
verified. Then stimuli (tests) are either manually crafted by verification engineers or
automatically generated by a test generator. The stimuli are applied to the simulation
environment and the behavior of the design is monitored and checked against expectation.
To measure the completeness of verification, coverage metrics are defined in terms of
which area of the design and which design functionality are exercised in simulation.
Metric (coverage) driven verification has been adopted as an industrial paradigm where
coverage is used to monitor and control the verification process. A sufficient coverage
level is required for verification sign-off.
Simulation and test generation are the two core technologies in simulation-based
verification that have been continuously pushed forward over the years. We highlight the
recent technological trends and advances of simulation technologies in this subsection and
that of test generation in the following one Simulator is the backbone of simulation-based
verification environment and all major EDA vendors have their offerings.

6.2 Analog and Mixed Signal Verification:

Depending on the portion of analog and mixed signal circuits on chip, the
testbench architecture for AMS simulation can be divided into two categories: ”analog
on top” (top-level models are analog with digital modules inside) or ”digital on top” (top-
level models are digital with analog modules inside). The latter is more commonly used
and the proper modeling of analog behavior is critical to ”digital on top” mixed signal
chip verification. Analog models of different abstraction levels are used through the
project life cycle, with consideration of the trade-off between simulation speed and
accuracy. For example, Verilog-AMS provides four abstraction levels to model analog
behaviors. To support AMS verification, the simulator must have the performance and
capacity to simulate a mixture of models at different abstraction levels for today’s
increasingly large designs in a reasonable amount of time, while maintaining an
acceptable level of accuracy. It is not uncommon that there are nested digital and analog
blocks in complex SOC designs, which should also be supported by the simulator. In
addition, the co-existence of models at various abstraction levels creates complexity in
verification planning as the models can be mixed and matched for achieving different
verification goals.

6.3 Power-Aware Verification:

 While clock gating is usually implemented in RTL code, power gating
is implemented by capturing the power intent in a standard format and instru- menting the
necessary circuitry during synthesis . The power intent file is also used in simulation with
RTL code to find out design flaws of the low-power SoCs at an early design stage. Power-
aware simulators generally support simulating the behavior resulted from the power
gating circuitry specified in power intent file, such as power switches, isolation cells, and
retention registers.

6.4 Functional Safety Verification:

Fault simulation is the main vehicle for evaluating the robustness of a

product’s safety mechanism against unexpected errors. Faults are injected into the design
components to emulate the unexpected hardware errors. A safety module usually has a
functional unit and a checker unit. When a fault is injected, the simulator outputs whether
the fault can propagate to the functional output and the checker output. If a single fault
can propagate to the functional output and cannot be detected by the checker, it means
that the fault can propagate to the system without recovery, which is a Single Point of
Failure. Single Point of Failure is not tolerable for safety critical SoCs. Currently, most
fault simulators support fault models including stuck-at faults, Single-Event-Upset and
Single-Event-Transient faults.
To build practical data mining applications for functional test content optimization, one
needs to formulate the target problem as one that can be solved by data mining and
machine learning algorithms. Figure 4 illustrates a typical data set seen by a machine
learning algorithm. When ˜y is present, i.e., there is a label for every sample, it is called
supervised learning. In supervised learning, if each yi is a categorized value, it is a
classification problem. If each yi is a continuous value, it becomes a regression problem.
When ˜y is not present and only X is present, it is called unsupervised learning. When
some (usually much fewer) samples are with labels and others have no label, the learning
is then called semi- supervised . Interested readers can refer to for a more detailed
discussion.

Fig. 4. Typical dataset in a machine learning problem [40]

To formulate a learning problem in functional verification, the first set of important

questions concern the definition of a sample. For example, a sample could be an
assembly test program. Alternatively, a sample could also be several consecutive
instructions and an assembly program can be broken into several samples. Each sample is
encoded with n features f1, ..., fn. Hence, the characteristics of each sample
 CHAPTER 7

CONCLUSION

Nowadays, with greater device integration, SoC designs can implement high-
performance and inexpensive systems for many killer applications. However, system
designs have also become more Trend and Challenge on System-on-a-Chip Designs
complex. This paper surveyed the emerging issues, modern design trends, and future
system design challenges for SoC research and design. It goes without saying that more
research efforts are still required to create innovative solutions. The SoC architecture
must consider overall system performance, flexibility, and scalability, power/thermal
management, system partition (among digital, analog, on-chip, or off-chip), architecture
partition (between hardware and software), algorithm developments for emerging
applications, and so on. Moreover, the coverage in this article is far from
comprehensive. Some important topics, such as the integration of electro-optical
devices, and the integration of nanoscale physical, chemical, or biological sensors, are
regretfully omitted. Fortunately, there is much discussion on many of these subjects in
the literature-the remaining portions of this special issue are a good place to start.
 CHAPTER 8

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