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    Lab 5

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    SHAHZAIB AHMAD QURESHI
    The document is a lab report for a digital system design course. It contains 3 tasks: 1) Implement a 2-4 line decoder using Verilog and test it on FPGA. 2) Implement a 2-input 1-output multiplexer using Verilog and test it on FPGA. 3) Implement a 2-bit by 2-bit binary multiplier using Verilog and test it on FPGA. It also contains 2 design problems: 1) Design a 4-1 multiplexer using three 2-1 multiplexers. 2) Design a circuit to implement a Boolean function using muxes and logic gates.

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    © All Rights Reserved
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    Lab 5

    Uploaded by

    SHAHZAIB AHMAD QURESHI
    33 views13 pages
    The document is a lab report for a digital system design course. It contains 3 tasks: 1) Implement a 2-4 line decoder using Verilog and test it on FPGA. 2) Implement a 2-input 1-output multiplexer using Verilog and test it on FPGA. 3) Implement a 2-bit by 2-bit binary multiplier using Verilog and test it on FPGA. It also contains 2 design problems: 1) Design a 4-1 multiplexer using three 2-1 multiplexers. 2) Design a circuit to implement a Boolean function using muxes and logic gates.

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    The document is a lab report for a digital system design course. It contains 3 tasks: 1) Implement a 2-4 line decoder using Verilog and test it on FPGA. 2) Implement a 2-input 1-output multiplexer using Verilog and test it on FPGA. 3) Implement a 2-bit by 2-bit binary multiplier using Verilog and test it on FPGA. It also contains 2 design problems: 1) Design a 4-1 multiplexer using three 2-1 multiplexers. 2) Design a circuit to implement a Boolean function using muxes and logic gates.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    33 views13 pages

    Lab 5

    Uploaded by

    SHAHZAIB AHMAD QURESHI
    The document is a lab report for a digital system design course. It contains 3 tasks: 1) Implement a 2-4 line decoder using Verilog and test it on FPGA. 2) Implement a 2-input 1-output multiplexer using Verilog and test it on FPGA. 3) Implement a 2-bit by 2-bit binary multiplier using Verilog and test it on FPGA. It also contains 2 design problems: 1) Design a 4-1 multiplexer using three 2-1 multiplexers. 2) Design a circuit to implement a Boolean function using muxes and logic gates.

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    © All Rights Reserved
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    Digital System Design LAB 5

    Spring 2021
    Lab Report 5
    DESIGN AND IMPLEMENTATION USING GATE-LEVEL
    MODELING.

    Course: Digital System Design (EE 320L)

    Resource Persons: Sir Awais Saeed

    Prepared By:
    Shahzaib Ahmad Qureshi: F2016019065
    Digital System Design LAB 5

    Objectives:

    On successful completion of this lab, students will be able to:

     Design and Implement the digital circuits using gate level modeling.
     Implement and create scalar and wide combinatorial circuits using gate-level molding such as
    Multiplexers, Decoders. Encoders on FPGA.
     Implement the combinational circuits using Multiplexers on FPGA.

    Task 1:
    Write the Verilog code from the given circuit diagram of two to four line decoder and verify its truth
    table by implementing it on FPGA.

    Verilog File:
    module Task1(D, A, B, enable);
    output [0: 3] D;
    input A, B;
    input enable;
    wire A_not,B_not, enable_not;
    not N1 (A_not, A);
    not N2 (B_not, B);
    not N3 (enable_not, enable);
    nand N4 (D[0], A_not, B_not, enable_not);
    nand N5 (D[1], A_not, B, enable_not);
    Digital System Design LAB 5

    nand N6 (D[2], A, B_not, enable_not);


    nand N7 (D[3], A, B, enable_not);

    endmodule

    Test-Bench File:
    module Task1_tb;

    // Inputs
    reg A;
    reg B;
    reg enable;

    // Outputs
    wire [0:3] D;

    // Instantiate the Unit Under Test (UUT)


    Task1 uut (
    .D(D),
    .A(A),
    .B(B),
    .enable(enable)
    );

    initial begin
    // Initialize Inputs
    A = 0; B = 0; enable = 1; #100;
    A = 0; B = 0; enable = 0; #100;
    A = 1; B = 0; enable = 0; #100;
    A = 0; B = 1; enable = 0; #100;
    A = 1; B = 1; enable = 0; #100;

    // Add stimulus here

    end

    endmodule
    Digital System Design LAB 5

    OUTPUT:

    Task 2:
    Write the Verilog code for given two to one line multiplexer and implement on FPGA
    Digital System Design LAB 5

    Verilog Code:

    module Task2(m_out, A, B, select);


    output m_out;
    input A, B, select;
    reg m_out;
    always @(A or B or select)
    if (select == 0) m_out = A;
    else m_out = B;

    endmodule

    Test-bench File:

    module Task2_tb;

    // Inputs
    reg A;
    reg B;
    reg select;

    // Outputs
    wire m_out;
    Task2 uut (
    .m_out(m_out),
    .A(A), .B(B), .select(select)
    );
    initial begin
    A = 0; B = 1; select = 0; #100;
    A = 1; B = 1; select = 0; #100;
    A = 0; B = 1; select = 0; #100;
    A = 1; B = 0; select = 1; #100;
    A = 0; B = 1; select = 1; #100;
    A = 1; B = 0; select = 1; #100;
    Digital System Design LAB 5

    end

    endmodule

    OUTPUT:

    Task 3:
    Implement the given circuit of two bit by two bit binary multiplier on FPGA.
    Digital System Design LAB 5

    Verilog Code:

    module Task3(C,A,B );
    output [3:0] C;
    input [1:0] A,B;
    wire w1,w2,w3,w4;
    and A1(C[0],A[0],B[0]);
    and A2(w1,A[0],B[1]);
    and A3(w2,A[1],B[0]);
    and A4(w3,A[1],B[1]);
    half_Adder H1(C[1],w4,w1,w2);
    half_Adder H2(C[2],C[3],w4,w3);
    endmodule

    TestBench File:

    module Task3_tb;

    // Inputs
    reg [1:0] A;
    reg [1:0] B;

    // Outputs
    wire [3:0] C;

    // Instantiate the Unit Under Test (UUT)


    Task3 uut (
    .C(C),
    .A(A),
    .B(B)
    );

    initial begin
    Digital System Design LAB 5

    // Initialize Inputs

    A = 00; B = 00; #100;


    A = 00; B = 01; #100;
    A = 01; B = 01; #100;
    A = 11; B = 10; #100;
    A = 11; B = 11; #100;

    // Add stimulus here

    end

    endmodule

    OUTPUT:
    Digital System Design LAB 5

    Design Problem 1:

    Design and implement 4X1 multiplexer using three 2X1 multiplexers developed in task2.

    Verilog Code:
    module mux_4x1(m_out, A, B, C, D, S0, S1);
    output m_out;
    input A, B, C, D, S0, S1;
    wire w1,w2;
    mux_2x1 M1(w1,A,B,S0);
    mux_2x1 M2(w2,C,D,S0);
    mux_2x1 M3(m_out,w1,w2,S1);
    endmodule

    Test-bench file:
    module mux_4x1_tb;
    reg A; reg B; reg C; reg D; reg S0; reg S1;
    wire m_out;
    mux_4x1 uut ( .m_out(m_out), .A(A), .B(B), .C(C), .D(D), .S0(S0), .S1(S1) );
    initial begin
    A = 1; B = 0; C = 0; D = 0; S0 = 0; S1 = 0; #100;
    A = 0; B = 1; C = 0; D = 0; S0 = 1; S1 = 0; #100;
    A = 0; B = 0; C = 1; D = 0; S0 = 0; S1 = 1; #100;
    A = 0; B = 0; C = 0; D = 1; S0 = 1; S1 = 1; #100;
    A = 0; B = 1; C = 1; D = 1; S0 = 0; S1 = 0; #100;
    end
    endmodule
    Digital System Design LAB 5

    OUTPUT:

    Design Problem 2:
    Design and implement digital circuit which executes the Boolean function formed by from following min
    terms using Mux and Logic gates.

    X A B C D F F= A’B’C’D + A’B’CD + A’BC’D’ + AB’CD + ABC’D’


    0 0 0 0 0 0 + ABC’D + ABCD’ + ABCD
    1 0 0 0 1 1 A’B’C’D F (Simplified using k-map)
    2 0 0 1 0 0
    3 0 0 1 1 1 A’B’CD 00 01 11 10
    4 0 1 0 0 1 A’BC’D’
    5 0 1 0 1 0 00 1 1
    6 0 1 1 0 0 01 1
    7 0 1 1 1 0
    11 1 1 1 1
    8 1 0 0 0 0
    9 1 0 0 1 0 10 1
    10 1 0 1 0 0
    11 1 0 1 1 1 AB’CD
    F = AB + A'B'D + B'CD + BC'D'
    12 1 1 0 0 1 ABC’D’
    13 1 1 0 1 1 ABC’D
    14 1 1 1 0 1 ABCD’
    15 1 1 1 1 1 ABCD
    Digital System Design LAB 5

    Circuit Diagram:
    Digital System Design LAB 5

    Verilog Module Code:


    module Funtion_Mux(F,A,B,C,D);
    output F;
    input A,B,C,D;
    wire w1,w2,w3;
    and A1(w1,~C,~D);
    and A2(w2,C,D);
    or O1(w3,A,~A);
    mux_4x1 M1(F,D,w1,w2,w3,A,B);
    endmodule

    Test-bench File:
    module Funtion_Mux_tb;
    // Inputs
    reg A;
    reg B;
    reg C;
    reg D;
    // Outputs
    wire F;
    // Instantiate the Unit Under Test (UUT)
    Funtion_Mux uut (.F(F), .A(A), .B(B), .C(C), .D(D) );
    initial begin
    // Initialize Inputs
    A = 0; B = 0; C = 0; D = 0; #100;
    A = 0; B = 0; C = 0; D = 1; #100;
    A = 0; B = 0; C = 1; D = 0; #100;
    A = 0; B = 0; C = 1; D = 1; #100;
    A = 0; B = 1; C = 0; D = 0; #100;
    A = 0; B = 1; C = 0; D = 1; #100;
    A = 0; B = 1; C = 1; D = 0; #100;
    A = 0; B = 1; C = 1; D = 1; #100;
    A = 1; B = 0; C = 0; D = 0; #100;
    A = 1; B = 0; C = 0; D = 1; #100;
    A = 1; B = 0; C = 1; D = 0; #100;
    A = 1; B = 0; C = 1; D = 1; #100;
    A = 1; B = 1; C = 0; D = 0; #100;
    A = 1; B = 1; C = 0; D = 1; #100;
    A = 1; B = 1; C = 1; D = 0; #100;
    A = 1; B = 1; C = 1; D = 1; #100;
    // Add stimulus here
    end
    Digital System Design LAB 5

    endmodule

    OUTPUT:

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