JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.

4, DECEMBER, 2005 249

A System-on-a-Chip Design for Digital TV

Seung Hyeon Rhee, Hun-Cheol Lee, Sanghoon Kim, Byung Tae Choi,
Seok Soo Lee, and Seung Jong Choi

Abstract––This paper presents a system-on-a-chip (SOC) very important. Furthermore, the trend is that the basic
design for digital TV. The single LSI incorporates function of DTV is no more the only interest of customers
almost all essential parts such as CPU, ISO/IEC and many new features are introduced especially from the
11172/13818 system/audio/video decoders, a video post- PC area. It seems that even features such as internet
processor, a graphics/OSD processor and a display connection, USB devices handling, etc will be
processor. It has analog IP’s inside such as video implemented in DTV in the near future. This means the
DACs, an audio PLL, and a system PLL to reduce the complexity of DTV SOC are getting higher and thus a
system-level implementation cost. Descramblers and stable, well organized, architecture as a base platform is
Smart Card interface are included to support widely essential for the further development to be successful and
used conditional access systems. The video decoder can effective.
decode two video streams simultaneously. The DSP- The rule of thumb is that the more features an SOC
based audio decoder can process various audio coding supports, the higher the SOC can be appraised in the sense
specifications. The functional blocks for video quality of usability. Extensive integration makes the effort and
enhancement also form outstanding features of this extra cost for PCB design to be small but the cost of the
SoC. The SoC supports world-wide major DTV LSI itself remains still as a problem. As a consequence, the
services including ATSC, ARIB, DVB, and DIRECTV. decision of what to integrate and what to leave outside is
the most important thing for the planning of SOC
Index Terms––SOC, digital TV, audio decoder, video development. Considering the current status of the market
decoder, video post-processor, ATSC. and the technology, we estimated the effort and effect of
integrating each functional block into a single LSI, and
finally reached the specification of the SOC.
I. Introduction The outline of this paper is as follows. In section 2, the
overall picture of the SOC is briefly reviewed. Information
on CPU and peripherals, also including bus and memory
The DTV market is still on its early stage and many system is presented in section 3. System decoder, audio
manufacturers of DTV sets and set-top boxes as well as decoder, and video decoder together form the base part of
component suppliers are competing to increase their the SOC and appear in section 4. Functions for video
market shares. The price competition has already started quality enhancement are described in section 5 in detail as
and the pressure on material cost will get heavy as the another important feature of the SOC. Finally, conclusions
market grows. To reduce the material cost for mass are reached in section 6.
production, the cost performance for core components is

Manuscript received October 20, 2005; revised December 3, 2005.

DTV Lab. LG Electronics Seoul, Korea
E-mail : [email protected]
250 SEUNG HYEON RHEE et al : A SYSTEM-ON-A-CHIP DESIGN FOR DIGITAL TV

II. Overall Picture (Advanced High-performance Bus) interface, and

EmbeddedICE-RT logic for JTAG-based debug.
The cache organization is specialized to provide
The SOC integrates a high-performance CPU core, flexible methods for improving the overall performance.
ISO/IEC 11172/13818-1 system decoder, ISO/IEC 32KB level 1 cache consists of 16KB instruction cache
11172/13818-3 and Dolby AC-3 audio decoder, ISO/IEC and 16KB data cache. To minimize conflict cache misses,
11172/13818-2 video decoder, display processor, analog each cache is 64-way associativity. In addition to high
composite video decoder, graphics/OSD processor, and degree of associativity, it is possible to select cache
several peripherals including UART, ISO/IEC 7816-3 operation scheme either of write-through and write-back
Smart Card interface, GPIO and I2Cs[1][2][3][4]. Analog per-region basis for the data cache. Cache replacement
IPs (two video DACs, audio PLL and x12 PLL) are also scheme is also programmable either of pseudo-random or
integrated to lower the overall system cost, as shown in round-robin to reduce the number of cache misses.
Figure 1. Various indispensable features are integrated to Regarding power consumption, caches implement not
reduce the total cost and number of chip components only low-power CAM (Content-Addressable Memory) but
required for digital TV and DTV tuner applications for also cache power-down capability.
ATSC, DVB, ARIB, DIRECTV, etc[5][6][7][8].
2. Bus & Memory System

The nature of digital TV always devours memory

bandwidth. Besides real time characteristic inherited from
its ancestors, there is a solid demand for sacrificing
memory bandwidth to achieve the merit of digital era. The
SOC has several features on bus and memory system to
exploit all feasible memory bandwidth.
The bus system is a composition of four different bus
systems: AHB (Advanced High-performance Bus), APB
(Advanced Peripheral Bus), host bus, and unified memory
Fig. 1. Block diagram.
bus. From the viewpoint of the CPU, AHB has the highest
position is the bus hierarchy and others bus are connected
with it though bridges. Memory Bridge connects AHB to
III. CPU and Peripherals memory controller. CPU Bridge connects AHB to host bus
by which CPU controls the video/audio processing blocks.
Slow peripherals like smart card are grouped into APB bus
1. CPU and are connected to AHB as single bus slave.
In point of the memory, the video/audio processing
To meet performance requirements for covering full units and the CPU are at the same distance from the
spectrum of digital TV applications, such as data memory. Moreover, video/audio processing unit can
broadcasting, PVR (Personal Video Recorder), and so on, access the memory without CPU’s assistance. With this
the SOC integrates ARM1022E which incorporates structure, since the CPU does not position between
ARM10ETM processor core by implementing ARMv5TE video/audio processing units and the memory, the SOC is
architecture. ARM1022E is a 32-bit RISC processor core able to do seamless switching from operations that utilize
which is compatible with ARM and Thumb instruction the CPU to others that don’t. The memory contention due
sets. Its main components include integer core, MMU to intensive memory accesses is resolved by priority based
(Memory Management Unit), instruction cache, data arbitrations with a starvation preventing algorithm.
cache, branch predictor, prefetch unit, 64-bit AHB AHB bus has a multiple-layered 5x8 bus matrix
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, DECEMBER, 2005 251

structure which can accommodate up to five bus masters The system decoder can process two streams
with individual bus transactions at the same time. For simultaneously with 32 PID filters and 32 section filters
example, it is possible that the CPU accesses smart card per channel. It extracts PCR from the input TS and this can
while DMA controller, simultaneously, performs a block be used for system time clock recovery as specified in
move on the memory. DMA controller has eight channels. ISO/IEC 13818-1[1]. Descramblers such as DES-ECB,
Each can operate independently. Together with the AHB MULTI2, CS, and CSS are included for DIRECTV, ARIB,
bus matrix, DMA controller can execute concurrent DMA DVB, DVD, respectively. Furthermore, DIRECTV’s
transactions. For instance, it is capable to handle a Advanced Security Feature is also supported [12]. The
transaction from an external peripheral to memory stick integrated high-performance DSP handles decoding of
and another from OSD to the memory. commonly used audio standards including AC-3, MPEG,
Regarding memory system, DDR SDRAM controller, PCM, DTS, AAC and MP3[3][11]. Digital PCM outputs
instead of normal SDRAM, is integrated to increase for 6-channel and down-mixed 2-channel may be
memory bandwidth. Several DDR configurations are connected with external audio DACs. The dedicated H/W
supported including 128M bit x1, x2, x4, 256M bit x1, x2, video decoder can decode two HD video sequences
and x4 with choice of 32/64-bit, and 148.5/162MHz. simultaneously. The digital video bitstreams compliant
with MPEG-1 and MPEG-2 MP@HL are decoded and
3. Peripherals converted into a suitable HD/SD display format. Using a
memory compression algorithm, it can use only a half or a
The SOC integrates some on-chip peripherals. It has 32 quarter of the full memory requirement.
programmable GPIO pins, two UART channels with
modem/IrDA, and a PWM output pin. Total of three I2C
interfaces are supported. Two of them are master interfaces V. Video Display Processor
and the other one can be a master or slave. It supports a
watchdog timer and dual input timers, too. To support
various conditional access systems, the SOC has a smart The video display processor supports various functions
card interface so that it can be directly connected with related with format conversion, image enhancement and
Philips TDA8004T without any glue logics. It also satisfies display control.
NDS extension to meet DIRECTV’s requirements [9].
In addition to on-chip peripherals, the SOC supplies an 1. Input Interface
external peripheral bus interfaces categorized into four
interfaces: external master bus interface, static memory DTV video bitstreams are decoded in the internal video
controller interface, external DMA interface, and external decoder block, and transferred to display processor
bus arbitration unit. Using the external master bus through external memory. In addition to DTV video, the
interface, an external CPU, such as Pentium, can control SOC can receive widely used video signals such as
the SOC while accessing its DDR memory through the composite video, PC input(up to XGA) and component
external DMA controller. For this case, the SOC acts just signals(up to 1920x1080, 30i) in the digitized
like a coprocessor. format(D1/YC4:2:2/YC4:4:4/RGB4:4:4). The main
functions of input interface include automatic format
detection, 3D comb filtering, VBI slicing, D1 decoding
IV. System, Audio, Video Decoder and color-space conversion.

2. Format Converter
Input streams are accepted in the form of ISO/IEC
13818-1 TS (transport stream), PES (packetized The format converter supports spatial/temporal video
elementary stream) and DVD PS (program stream) [1][10]. format conversion including scanning-type, aspect ratio,
252 SEUNG HYEON RHEE et al : A SYSTEM-ON-A-CHIP DESIGN FOR DIGITAL TV

and chrominance sub-sampling conversions. The SOC has contrast enhancement depending on the luminance
internally two format converters: one for main display and distribution of the video signals. The CDF computation
auxiliary one for PIP or VCR output. The auxiliary format block computes the CDF of the input luminance. The CDF
converter can be used for simultaneous VCR output for control block restricts allowable range of control points by
recoding or it is in charge of the sub-window such as two lines because the histogram equalization may enhance
PIP/Split-Screen/POP. When operating for VCR output, it contrast too much in low-contrast images. Then, the
converts the high-definition display of the main screen into histogram information is temporally filtered by IIR filter in
a 480i/576i composite video through composite video order to avoid flickering artifacts. Finally, the input
encoder, which produces CVBS and S-video together with luminance is transformed by the computed CDF.
CGMS and Macrovision functionality for copy protection.
Through such conversion, DTV images can be stored in Sharpness enhancement
the analog VCR. In addition, auxiliary format converter Both 1x9 FIR filter and 3x3 FIR filter are
can display contents that are independent of the main implemented. Depending on the filter coefficients used,
display content. the 1x9 filter may be used as a band-peaking or band-bass
Various display modes are provided such as zoom-in/- filter. If used as a band pass filter, it realized more
out, PIP(Picture In Picture), POP(Picture Out of Picture), enhanced sharpness control by reducing the filtering error
Split-screen and multi-PIP. They can be categorized into through coring and clipping operation, which reduces low
single window, two windows and multiple windows level noise of the filtered signal and suppresses the high
depending on the number of display windows. Arbitrary level component of filtered signals, respectively.
scaling and positioning of each window is supported for
any case. For two-window mode such as PIP/Split-screen, 4. Graphics/OSD
typical combinations of two input video sources include
DTV/NTSC, DTV/PC, DTV/component, NTSC/NTSC, The graphics/OSD block is composed of 2-D graphics
NTSC/PC and NTSC/component. Also, DTV/DTV mode engine and OSD (on-screen display) controller. The graphic
is supported for dual DTV channels. POP/multi-PIP is engine supports the primitives such as line/point drawing,
quite useful for channel scanning. rectangle filling, text manipulation and bitblt functions. It
also performs color, Boolean and arithmetic operations.
De-interlacing Both RGB and YCbCr color space are supported.
Format converter includes the motion-adaptive 3-D de-
interlacing functions for up-conversion of interlaced SD to
HD-resolution. It interpolates the image data using not
only spatial but also temporal information as follows.
First, it detects the motions using information between
four adjacent fields. If there is no motion, temporal
interpolation is performed using the pixel data at the same
position in the previous/next fields. If there is large
motion, spatial interpolation is accomplished using the
adjacent pixels in the current field. In the actual
implementation, both spatial/temporal interpolation results
are averaged depending on the amount of motion.

3. Video signal enhancement

Contrast enhancement
The histogram equalization is implemented for dynamic Fig. 2. Package top view.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, DECEMBER, 2005 253

There are seven planes for Graphics and OSD, which information, “Generic coding of moving pictures and
consists of one H/W cursor (32x32), two pseudo/true-color associated audio information: Video,” Technical
planes, video plane, one 1-bit switching plane, one still Corrigendum 1, Mar. 2002.
picture plane, and one background color plane. A pixel can [3] ISO/IEC JTC1 Information technology SC29 Coding
be expressed in the form of pseudo-color (256 colors by of audio, picture, multimedia and hypermedia
look-up table) as well as true-color (16/24/32 bits/pixel) information, “Generic coding of moving pictures and
with full-screen drawing capability. Two look-up tables associated audio information-Part 3: Audio,” 2nd
having the size of 256x32 are prepared for supporting Edition, Apr. 1998.
pseudo-color representation. Alpha blending is also [4] ISO/IEC 7816-3 Information Technology-Identification
supported up to 256-level. Anti-flickering feature is cards-Integrated circuit(s) cards with contacts-Part 3:
equipped for the interlaced display. Electronic signals and transmission protocols, 2nd
Edition, Dec. 1997.
[5] ATSC Standard A/53C with Amendment No. 1 and
VI. Conclusions Corrigendum No. 1: Digital Television Standard,
Revision C, published by Advanced Television
Systems Committee, May 2003.
In this paper, we have presented a highly integrated [6] Video Broadcasting(DVB); Implementation Guidelines
SOC design. The fundamental functional blocks including for the Use of MPEG-2 Systems, Video and Audio in
CPU, system/audio/video decoders, video display Satellite, Cable and Terrestrial Broadcasting
processor, and graphics/OSD processor are included to Applications, Rev. 6, published by DVB Project
lower the system cost. For pre-silicon verification, the Office, May 2000.
overall design was partitioned into 6 separate FPGAs [7] Receiver for Digital Broadcasting, Version 3.0,
placed on 24-layer PCB. Some modules such as system published by Association of Radio Industries and
decoder and video processor had their own FPGA Businesses (Japanese), May 2001.
emulation environment. RTL and gate level simulation of [8] IRD Specification: DIRECTV Transport Protocol
the top design also were included in the verification Specification for the IRD, Version 2.2, published by
procedures. DIRECTV, Apr. 2001.
0.13 um 1P 6M logic low-voltage process was used for [9] Smart Card Interface Supplements to ISO 7816-3 for
ASIC implementation. The core and I/O voltages are 1.2 V Protocol Type T=0, Rel. B, published by NDS, Mar.
and 3.3 V, respectively. The package is 600-ball TEBGA 1999.
and its top view is presented in Figure 2. The next version [10] DVD Specifications for Read-Only Disc: Part 3
SOC is under development and it will support USB, PCI to VIDEO SPECIFICATIONS, Version 1.13, March
reinforce connectivity, with improved video quality. 2002.
[11] ATSC Standard A/52A: Digital Audio Compression
(AC-3) Standard, Rev. A, published by Advanced
References Television Systems Committee, August 2001.
[12] Specification for Advanced Security Features within
DIRECTV Transport Chips for Hard Disk equipped
[1] ISO/IEC JTC1 Information technology SC29 Coding IRDs, Version 4.1, published by DIRECTV, Jan.
of audio, picture, multimedia and hypermedia 2002.
information, “Generic coding of moving pictures and
associated audio information: Systems,” Technical
Corrigendum 2, Dec. 2002.
[2] ISO/IEC JTC1 Information technology SC29 Coding
of audio, picture, multimedia and hypermedia
254 SEUNG HYEON RHEE et al : A SYSTEM-ON-A-CHIP DESIGN FOR DIGITAL TV

Seung Hyeon Rhee He is a research Seok Soo Lee He is a research

engineer in the Digital TV Laboratory engineer in the System IC Division of
of LG Electronics in Korea. His current LG Electronics in Korea. His research
research interests include design and interests include Digital TV A/V SoC
verification of SoC for multimedia and design methodology for ASIC. He
applications such as digital TV. Before received B.S. and M.S. degrees in
he joined Digital TV Lab. in 1999, he studied image electronics engineering from Kyungpook National
coding, image restoration, and video resolution University.
enhancement. He received B.S., M.S., and Ph.D. degrees
in electronics engineering from Yonsei University, Seoul,
Korea in 1993, 1995, and 1998, respectively.

Hun-Cheol Lee He is a research

engineer in the Digital TV laboratory
of LG Electronics in Korea. He
received B.S., M.S. and Ph.D. degrees
in electrical engineering from Korea
Advanced Institute of Science and
Technology(KAIST) in 1995, 1997 and 2002, respectively.
His research interests include image/video processing,
DTV SOC design, and picture quality enhancement for flat
panel display.

Sanghoon Kim He is a research

engineer in the Digital TV laboratory
of LG Electronics in Korea. His
research interests include computer
architectures, operating systems, and
bus systems. He received B.S. degree
in Electrical Engineering form Korea University and M.S.
degree from University of Wisconsin at Madison.

Byung Tae Choi He is a research

engineer in the Digital TV laboratory
of LG Electronics in Korea. His
research interests are focused on the
picture quality improvement techniques
implemented in digital TV SoC. He
received B.S., M.S., and Ph. D. degrees in electronics
engineering from Korea University.