Hi3520D V400 H.

265 Codec Processor

Brief Data Sheet

Issue 01

Date 2018-04-27
Copyright © HiSilicon Technologies Co., Ltd. 2018. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without prior
written consent of HiSilicon Technologies Co., Ltd.

Trademarks and Permissions

, , and other HiSilicon icons are trademarks of HiSilicon Technologies Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.

Notice
The purchased products, services and features are stipulated by the contract made between HiSilicon and
the customer. All or part of the products, services and features described in this document may not be
within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements,
information, and recommendations in this document are provided "AS IS" without warranties, guarantees
or representations of any kind, either express or implied.
The information in this document is subject to change without notice. Every effort has been made in the
preparation of this document to ensure accuracy of the contents, but all statements, information, and
recommendations in this document do not constitute a warranty of any kind, express or implied.

HiSilicon Technologies Co., Ltd.

Address: New R&D Center, Wuhe Road,
Bantian, Longgang District,
Shenzhen 518129 P. R. China

Website: http://www.hisilicon.com

Email: [email protected]
 Hi3520D V400
Hi3520D V400 H.265 Codec Processor
Key Specifications bit interface (8xD1/8x960H real-time video inputs in
total)
Processor Core − 144 MHz/148.5 MHz 2x720p TDM inputs for each 8-
 ARM Cortex A7 dual-core@maximum 1.3 GHz bit interface (4x720p@30 fps real-time video inputs in
− 32 KB L1 I-cache, 32 KB L1 D-cache total)
− 256 KB L2 cache − 4x720p TDM inputs through 148.5 MHz dual-edge
− NEON and FPU sampling or 297 MHz single-edge sampling for each 8-
Video Encoding/Decoding Protocols bit interface (8x720p@30 fps real-time video inputs in
total)
 H.265 Main Profile, Level 4.1 encoding
− 148.5 MHz BT.1120 inputs in Y/C interleaved mode for
 H.265 Main Profile, Level 4.1 decoding
each 8-bit interface (2x1080p@30 fps real-time video
 H.264 Baseline/Main/High Profile, Level 4.2 encoding
inputs in total)
 H.264 Baseline/Main/High Profile, Level 4.2 decoding
− 2x1080p TDM inputs through 148.5 MHz dual-edge
 MPEG-4 SP, L0–L3/ASP L0–L5 decoding
sampling or 297 MHz single-edge sampling for each 8-
 MJPEG/JPEG baseline
bit interface (4x1080p@30 fps real-time video inputs in
Video Encoding/Decoding total)
 H.265/H.264/JPEG encoding and decoding of multiple − 148.5 MHz BT.1120 standard mode for the 16-bit
streams interface (1x1080p@60 fps real-time video inputs in
− 4x1080p@15fps H.265/H.264 encoding+4xD1@15fps total)
H.265/H.264 encoding+4x1080p@15fps H.265/H.264  VO interfaces
decoding+4x1080p@2fps JPEG encoding − One HDMI 1.4b output interface with the maximum
− 4x720p@30fps H.265/H.264 encoding+4xD1@30fps output of 3840 x 2160@30 fps
H.265/H.264 encoding+4x720p@30fps H.265/H.264 − One VGA HD output interface with the maximum
decoding+4x720p@2fps JPEG encoding output of 1080p@60 fps
 Constant bit rate (CBR) mode, variable bit rate (VBR) − Two independent HD output channels (DHD0 and
mode, FIXQP mode, adaptive variable bit rate (AVBR) DHD1), output over any HD interface (HDMI or VGA)
mode, and QpMap mode − 16-picture output for DHD0, maximum output of 3840
 Maximum 40 Mbit/s output bit rate x 2160@30 fps
 ROI encoding − 16-picture output for DHD1, maximum output of
 Color-to-gray encoding 1080p@60 fps
Intelligent Video Analysis − One CVBS SD output interface
 Integrated IVE, supporting various intelligent analysis − Three full-screen GUI graphics layers in ARGB1555 or
applications such as motion detection, perimeter defense, ARGB8888 format for two HD channels and one SD
and video diagnosis channel
− Two hardware cursor layers in ARGB1555 or
Video and Graphics Processing
ARGB8888 format (configurable) with the maximum
 Deinterlacing, sharpening, 3D denoising, dynamic contrast resolution of 256 x 256
improvement, and demosaic
 Anti-flicker for output videos and graphics
Audio Interfaces
 1/15x to 16x video scaling  Three unidirectional I2S/PCM interfaces
 1/2x to 2x graphics scaling − Two input interfaces, supporting 16 multiplexed inputs
 Four Cover regions − One output, supporting dual-channel output
 OSD overlaying of eight regions − 16-bit audio inputs and outputs

Audio Encoding/Decoding Ethernet Ports

 ADPCM, G.711, and G.726 hardware audio encoding  One gigabit Ethernet port
 Software audio encoding and decoding complying with − RGMII, RMII, and MII modes
multiple protocols − 10/100 Mbit/s half-duplex or full-duplex
− 1000 Mbit/s full-duplex
Security Engine
− TSO for reducing the CPU usage
 AES, DES, and 3DES algorithms implemented by
hardware
Peripheral Interfaces
 Two SATA 3.0 interfaces
Video Interfaces
− PM
 VI interfaces − eSATA
− Two 8-bit interfaces or one 16-bit interface
 Two USB 2.0 host ports, supporting the hub
− 108 MHz/144 MHz 4xD1/960H TDM inputs for each 8-

HiSilicon Proprietary and Confidential

Issue 01 (2018-04-27) 3
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3520D V400
Hi3520D V400 H.265 Codec Processor
 Three UART interfaces, one of which supporting four Configurable Boot Modes
wires  Booting from the BOOTROM
 One SPI, supporting two CSs  Booting from the SPI NOR flash
 One IR interface  Booting from the SPI NAND flash
 One I2C interface
SDK
 Multiple GPIO interfaces
 Linux 3.18-based SDK
Memory Interfaces  Audio encoding and decoding libraries complying with
 One 16-bit DDR3 SDRAM interface various protocols
− Maximum frequency of 800 MHz  High-performance H.265/H.264 PC decoding library
− ODT
Physical Specifications
− Maximum capacity of 1 GB
 Power consumption
− Automatic power consumption control
− Typical power consumption of 2.0 W
 SPI NOR/NAND flash interface
− Multi-level power consumption control
− 1-/2-/4-wire SPI NOR/NAND flash
 Operating voltages
− Two CSs, connected to different types of flash
− 0.9 V core voltage
memories
− 1.0 V CPU voltage
− Maximum capacity of 64 MB for each CS (for the SPI
− 3.3 V I/O voltage
NOR flash)
− 1.5 V DDR3 SDRAM interface voltage
− Maximum capacity of 512 MB for each CS (for the
 Package
SPI NAND flash)
− RoHS, TFBGA
− 2 KB/4 KB page size (for the SPI NAND flash)
− Lead pitch of 0.65 mm (0.03 in.)
− 8-bit/1 KB or 24-bit/1 KB ECC (for the SPI NAND
− Body size of 15 mm x 15 mm (0.59 in. x 0.59 in.)
flash)
 Operating temperature ranging from 0°C (32°F) to 70°C
 Embedded 4 KB BOOTROM and 16 KB SRAM
(158°F)
RTC with an Independent Power Supply
 Independent battery for supplying power to the RTC

HiSilicon Proprietary and Confidential

Issue 01 (2018-04-27) 4
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3520D V400
Hi3520D V400 H.265 Codec Processor

Functional Block Diagram

ARM Subsystem Image Subsystem

16bit VPSS/VGS HDMI/

DDRC VGA/
DDR3
A7 dual [email protected] GHz CVBS
32KB/32KB L1 Cache TDE
256KB L2 Cache BT.656/
SATA Hard
SATA3.0 x2 NEON/FPU BT.1120
disk
IVE input

SPI
NOR/NAND FMC
Flash AMBA3.0 BUS

RTC
Video AD SSP
Video Codec
I2C
H.265/H.264/
GMAC MJPEG/JPEG SRAM
GE PHY
(TSO)
BootROM

USB 2.0 AES/DES/ IR

USB PORT VOIE
Host x2 3DES
UARTx3

DMAC PMC
Audio Codec I2S
GPIOs
Hi3520DV400

The Hi3520D V400 is a professional SoC targeted for the multi-channel HD (1080p/720p) or SD (D1/960H) DVR. The Hi3520D
V400 provides an ARM A7 dual-core processor, a high-performance H.265/H.264 video encoding/decoding engine, a high-
performance video/graphics processing engine with various complicated graphics processing algorithms, HDMI/VGA HD outputs,
and various peripheral interfaces. These features enable the Hi3520D V400 to provide high-performance, high-picture-quality, and
low-cost analog HD/SDI solutions for customers' products while reducing the eBOM cost.

DVRs (Each with a Hi3520D V400)

4x1080p Non-Real-Time DVR
 4x1080p@15 fps H.265 encoding+4xD1@15 fps H.265 encoding+4x1080p@15 fps H.265 decoding+4x1080p@2 fps JPEG
encoding
 HDMI+VGA 1080p@60 fps outputs from the same source+CVBS outputs
4x720p DVR
 4x720p@30 fps H.265 encoding+4xD1@30 fps H.265 encoding+4x720p@30 fps H.265 decoding+4x720p@2 fps JPEG
encoding
 HDMI+VGA 1080p@60 fps outputs from the same source+CVBS outputs

HiSilicon Proprietary and Confidential

Issue 01 (2018-04-27) 5
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3520D V400
Hi3520D V400 H.265 Codec Processor

SATA SATA SATA

HDD HDD HDD

SATA SATA
Port Multiplier Port Multiplier

HDMI VGA CVBS SATA SATA

(1080p) (1080p)

Flash FMC

USB2.0 Host

DDR3 DDR Ctrl

GE PHY GMAC
GMAC VI0
VI0 VI1 I2S0 I2S1 I2S2

LAN/WAN
2x4M or 4x1080p or 8x720p CHs. A/V Dec.

HiSilicon Proprietary and Confidential

Issue 01 (2018-04-27) 6
Copyright © HiSilicon Technologies Co., Ltd.
 Hi3520D V400
Hi3520D V400 H.265 Codec Processor

Acronyms and Abbreviations

3DES triple data encryption standard
ADPCM adaptive differential pulse code modulation
AES advanced encryption standard
CBR constant bit rate
CS chip select
CVBS composite video broadcast signal
DCI dynamic contrast improvement
DDR double data rate
DES data encryption standard
DVR digital video recorder
eBOM engineering bill of materials
ECC error correcting code
eSATA external serial advanced technology attachment
GPIO general-purpose input/output
HD high definition
HDMI high definition multimedia interface
I 2C inter-integrated circuit
I 2S inter-IC sound
IR infrared
IVE intelligent video engine
MII media independent interface
ODT on-die termination
OSD on-screen display
PCM pulse code modulation
PM port multiplexer
QP quantization parameter
RGMII reduced gigabit media independent interface
RMII reduced media independent interface
RoHS Restriction of Hazardous Substances
ROI region of interest
RTC real-time clock
SATA serial advanced technology attachment
SD standard definition
SDI serial digital interface
SDK software development kit
SDRAM synchronous dynamic random access memory
SoC system-on-chip
SPI serial peripheral interface
SRAM static random access memory
TDM time division multiplexing
TSO TCP segmentation offload
UART universal asynchronous receiver transmitter
VBR variable bit rate
VGA video graphics array
VI video input
VO video output

HiSilicon Proprietary and Confidential

Issue 01 (2018-04-27) 7
Copyright © HiSilicon Technologies Co., Ltd.