Unit-V Memory And Programmable

DIGITAL PRINICPLES AND SYSTEM DESIGN Logic

PART-A
1. List basic types of programmable logic devices.
 Read only memory
 Programmable logic Array
 Programmable Array Logic.
2. Explain ROM.
A read only memory (ROM) is a device that includes both the decoder and the OR gates within a single IC package. It
consists of n input lines and m output lines. Each bit combination of the input variables is called an address. Each bit
combination that comes out of the output lines is called a word. The number of distinct addresses possible with n input
n
variables is 2 .
3. Define address and word.
In a ROM, each bit combination of the input variable is called on address. Each bit combination that comes out of the
output lines is called a word.
4. State the types of ROM. MAY-2011
 Masked ROM
 Programmable Read only Memory
 Erasable Programmable Read only memory.
 Electrically Erasable Programmable Read only Memory.
5. What is programmable logic array? How it differs from ROM? (MAY-2009)
In some cases the number of don’t care conditions is excessive, it is more economical to use a second type of LSI
component called a PLA. A PLA is similar to a ROM in concept; however it does not provide full decoding of the
variables and does not generates all the min-terms as in the ROM.
6. Explain PROM.
PROM (Programmable Read Only Memory):
It allows user to store data or program. PROMs use the fuses with material like nichrome and polycrystalline. The user
can blow these fuses by passing around 20 to 50 mA of current for the period 5 to 20µs.The blowing of fuses is called
programming of ROM. The PROMs are one time programmable. Once programmed, the information is stored
permanent.
7. Explain EPROM.
EPROM (Erasable Programmable Read Only Memory):
EPROM use MOS circuitry. They store 1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase
the stored data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20 minutes. It is
not possible to erase selective information. The chip can be reprogrammed.
8. Explain EEPROM.
EEPROM (Electrically Erasable Programmable Read Only Memory):
EEPROM also use MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating
gate in the device. EEPROM allows selective erasing at the register level rather than erasing all the information since
the information can be changed by using electrical signals.

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Unit-V Memory And Programmable
DIGITAL PRINICPLES AND SYSTEM DESIGN Logic
9. What is RAM?
RAM-Random Access Memory.
Read and write operations can be carried out.
10. Mention few applications of PLA and PAL.
Applications of PLA and PAL are: (i) They are used to implement combinational circuits.
(ii)They can be programmed to use as code converters.
(iii) Register PALs can be used to implement sequential circuits.
11. What is mask - programmable?
With a mask programmable PLA, the user must submit a PLA program table to the manufacturer.
12. What is field programmable logic array? (Nov/Dec 2009)
The second type of PLA is called a field programmable logic array. The word field refers to the ability of the gate arrays
to be programmed for a specific function by the end user. The word array indicates a series of columns and rows of
gates that can be programmed by the end user. The user by means of certain recommended procedures can program
the EPLA.
13. List the major differences between PLA and PAL? DEC- 2009
PLA:
 Both AND and OR arrays are programmable and Complex
 Costlier than PAL
PAL:
 AND arrays are programmable OR arrays are fixed
 Cheaper and Simpler
14. Define PLD.
Programmable Logic Devices consist of a large array of AND gates and OR gates that can be programmed to achieve
specific logic functions.
15. How is individual location in a EEPROM programmed or erased? (MAY 2006)
Since it is electrically erasable memory, by activating particular row and column it is possible that can be programmed or
erased.
16. Define PROM.
PROM is Programmable Read Only Memory. It consists of a set of fixed AND gates connected to a decoder and a
programmable OR array.
17. Define PLA.
PLA is Programmable Logic Array (PLA). The PLA is a PLD that consists of a programmable AND array and a
programmable OR array.
18. Define PAL.
PAL is Programmable Array Logic. PAL consists of a programmable AND array and a fixed OR array with output logic.

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Unit-V Memory And Programmable

DIGITAL PRINICPLES AND SYSTEM DESIGN Logic
19. Why was PAL developed?
It is a PLD that was developed to overcome certain disadvantages of PLA, such as longer delays due to additional fusible
links that result from using two programmable arrays and more circuit complexity.
20. Why the input variables to a PAL are buffered?
The input variables to a PAL are buffered to prevent loading by the large number of AND gate inputs to which available or
its complement can be connected.
21. What does PAL 10L8 specify?
PAL - Programmable Logic Array
10 - Ten inputs
L - Active LOW Output
8 - Eight Outputs
22. Give the comparison between PROM and PLA. (MAY 2010)
PROM PLA
(i) And array is fixed and OR (i) Both AND and OR arrays are array
Is programmable.
(ii) Cheaper and simple to use. (ii) Costliest and complex than PROMS.
23. Define ROM.
Read only memory is a device that includes both the decoder and the OR gates within a single IC package.
24. Mention the two types of erasable PROM. (DEC 2006)
 Erasable Programmable Read Only Memory
 Electrically Erasable Programmable Read Only Memory
25. Define a memory cell. Give an example. (DEC 2004, 2006 MAY 2007)
Memories are made up of registers. Each register consists of storage elements (flip-flops or capacitors in semiconductor
memories and magnetic domain in magnetic storage), each of which stories one bit of data. Such a storage element is
called a memory cell.
26. Define a memory location. (MAY 2006)
Memories are made up of registers. Each register in the memory is one storage location also called memory location. Each
memory location is identified by an address.
27. What is a volatile memory? Give example. (DEC 2007)
The memory which cannot hold data when power is turned off is known as volatile memory. The Static Ram is a volatile
memory.
28. List the configurable elements in the FPGA architecture.
The FPGA architecture consists of three types of configurable elements:
 A perimeter of input/output Blocks (IOBs)
 A core array of configurable logic Blocks (CLBs)
 Resources for interconnection

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Unit-V Memory And Programmable
DIGITAL PRINICPLES AND SYSTEM DESIGN Logic

29. What is memory expansion? Mention its limit. (MAY 2010)

  The memory expansion can be achieved in two ways: By expanding word size and by expanding memory
capacity.
 It is possible to expand word size of memory by connecting two or more ICs together.
 The memory capacity can be increased by connecting two or more memory ICs in parallel.
 The memory devices are interfaced with processors and are accessed using address, data and control bus provide
by the processor. Each processor has defined number of address lines and data lines.
30. How many locations are addresses using 18 address bits? (DEC 2008)
18
The number of locations addressed= 2 = 262144.
31. How many address bits are needed to operate a 2K x 8 ROM?
2K memory locations= 2048 locations.
11
Since 2 =2048, we need 11 address lines.
32. Define Static RAM. (DEC 2009)
Memories that consist of circuits capable of retaining their state as long as power is applied are known as static memories.
These are random access memory and hence combine called static RAM memories.
33. Write the application of FPGA.
 They are used to build random logic, integrating multiple SPLDs, devices controllers, communication encoding and
filtering, small to medium sized systems with SRAM blocks, and many more.
 They are used to build higher level embedded functions such as adders and multiplers.
34. What is meant by input buffer?
Input buffers are provided in the PLA to limit loading of the sources that drive the inputs. They also provide inverted and
non-inverted form of inputs at its output.
35. What is meant by output buffer?
The driving capacity of PLA is increased by providing buffers at the output. The output buffer may provide totem pole, open
collector or tri-state output.
36. What is a cross point in ROM?
In ROM, the programmable intersection between two lines is called a cross point. It is logically equivalent to a switch that
can be altered to either be closed or open.
37. How is the internal operation of a ROM interpreted?
The internal operation of a ROM is interpreted in two ways:
 Interpreting the memory unit that contains a fixed pattern of stored words.
 The second interpretation is of a unit that implements a combinational circuit.
38. What is access time? (DEC 2010)
The access time of a memory is the time required to select a word and read it.
39. What is cycle time? (DEC 2010)
The cycle time of a memory is the time required to complete a write operation.

40. Define capacity.

Capacity of memory is defined as how many bits can be stored in a particular capacity.

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Unit-V Memory And Programmable
DIGITAL PRINICPLES AND SYSTEM DESIGN Logic

41. What is Non-volatile memory?

The content of memory is not lost even when the power is removed from the memory. These types of memory are called
Non-volatile memory.
42. Define read operation.
The binary data word reads the content in a specific memory location during the read operation.
43. Define write operation.
A binary word is placed in a specific memory location during the write operation. It is also referred to as a store operation.
44. Define read write memory.
A memory in which it is possible to read from or written into a specified location is called read write memory.
45. Define Dynamic RAM.
The dynamic RAM stores the binary information in the form of electric charges on capacitors. The capacitors are provided
inside the chip by MOS transistor. The stored charge on the capacitors tends to discharge with time and the capacitors
must be periodically recharged by refreshing the dynamic memory.
46. Define coincident decoding.
The total number of gates and the number of inputs per gate can be reduced by employing two decoders in a two
dimensional selection scheme, which is known as coincident decoding.
47. Define RAM Cell.
The smallest storage unit a RAM, capable of storing one bit.
48. What is the procedure followed to store a new word in memory?
 Apply the binary address of the desired word to the address lines.
 Apply the data bits that must be stored in memory to the data input lines.
 Activate the write input: The memory unit will then take the bits from the input data lines and store them in the word
specified by the address line.
49. What is the procedure followed to take a word out of memory?
 Apply the binary address of the desired word to the address lines.
 Activate the read input: The memory unit will then strike the bits from the word that has been selected by the
address and apply them to the output data lines.
50. What is the term that determines the size of a PLA?
The size of a PLA is specified by the:
 Number of inputs
 Number of product terms and
 Number of outputs

51. What is memory enable?

Memory enable is a control input, which is used enable the particular memory chip in a multi chip implementation of a
large memory. When the memory enable is inactive, the memory chip is not selected and no operation is performed. When
the memory enable input is active, the read write input determines the operation to be performed.

52.What is PLA? How it differs from ROM? (May/June 2010)

PLA is a device with a programmable AND array and programmable OR array.
i. Cheaper and simple in use than PLA.
ii. All minterms are decoded
iii. AND array is fixed and OR array is programmable.

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 Unit-V Memory And Programmable
DIGITAL PRINICPLES AND SYSTEM DESIGN Logic
PART – B
1. i. Write notes on PLA and PAL.
ii.Write notes on RAM, its operations and its types. (Nov/Dec 2012)
2. With suitable timing diagram explain how Read operation is performed in RAM. (Nov/Dec 2011)
3. Explain the different types of ROM. (Nov/Dec 2007)
4. Explain the operation of DRAM with suitable diagram. Also explain how Read /Write operation is performed
in DRAM with timing diagram. (May/June2009)
5. i. Write short notes on semiconductor materials.
ii. What are the advantages of PLA over ROM? Explain the internal construction of ROM. (May/June2007)
6. What is micro programmed control unit? Explain the different types of ROM. (Nov/Dec 2006)
7. Implement the given function using PROM and PAL. (May/June2007)

F 1=  m(0,1,3,5,7,9, ) F 2=  m(1,2,4,7,8,10,11, )
8. Implement the given function using PAL and PLA . (May/June2007)

F 1=  m(0,1,2,4,6,7) F 2=  m(1,3,5,7) F 3=  m(0,2,3,6)

9. Write notes on semiconductor memories and methods of memory decoding. (Nov/Dec 2005)
10. i. Draw the CMOS RAM cell and explain the Read and Write operation performed in this cell.
ii. Compare the features of PROM, EPROM and EEPROM. (Nov/Dec 2005)
11. i. Describe the RAM organization.
ii. A bipolar RAM chip is arranged as 16 words. How many bits are stored in the chip? (Nov/Dec 2005)
12. What are the classifications of PLD’s? Explain with example. (May/June2005)
13. Explain the structure and characteristics of the following memories: (May/June2005)
i. PROM II.EPROM III. EEPROM

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 DIGITAL PRINICPLES AND SYSTEM DESIGN Unit-I Boolean Algebra & Logic Gates

PART – A
1. What are prime implicants? (Dec 05,08, May 12)
All the implicants of a function determined using a karnaugh map are called prime implicants.
2. Define binary logic.
Binary logic consists of binary variables and logical operations. The variables are designated by the
alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0.
There are three basic logic operations: AND, OR, and NOT.
3. Convert (634)8 to binary.
6 3 4
110 011 100
Ans = 110011100
4. Convert (9B2 - 1A)H to its decimal equivalent
N = 9 x 162 + B x 161 + 2 x 160 + 1 x 16-1 + A (10) x 16-2
= 2304 + 176 + 2 + 0.0625 + 0.039
= 2482.110
5. Convert 0.640625 decimal numbers to its octal equivalent.
0.640625 x 8 = 5.125
0.125 x 8 = 1.0
(0.640625)10 = (0.51)8.
6. Convert 0.1289062 decimal numbers to its hex equivalent.
0.1289062 x 16 = 2.0625
0.0625 x 16 = 1.0
= (0.21)16.
7. State the steps involved in Gray to binary conversion.
The MSB of the binary number is the same as the MSB of the gray code number. So write it down. To
obtain the next binary digit, perform an exclusive OR operation between the bit just written down and
the next gray code bit. Write down the result.

8. Find 2’S complement of (1 0 1 0 0 0 1 1 0)2.

0 1 0 1 1 1 0 0 1 - 1’s Complement
+ 1
0 1 0 1 1 1 0 1 0 - 2’s complement.
9. What are the basic digital logic gates?
The three basic logic gates are
 AND gate
 OR gate
 NOT gate.
10. What is a Logic gate?
Logic gates are the basic elements that make up a digital system. The electronic gate is a circuit that
is able to operate on a number of binary inputs in order to perform a particular logical function.
11. Which gates are called as the universal gates? What are its advantages?
The NAND and NOR gates are called as the universal gates. These gates are used to perform any
type of logic application.
12. State the properties of Boolean algebra.
 Commutative properties
 Associative properties
 Distributive properties
 Identity properties
 Null properties
 Negation properties.
13. Simplify the following using De Morgan's theorem [((AB)'C)'' D]'.
[((AB)'C)'' D]' = ((AB)'C)'' + D' [(AB)' = A' + B']
= (AB)' C + D'
= (A' + B’) C + D'.
14. Reduce A (A + B)
A (A + B) = AA + AB
= A (1 + B) [1 + B = 1]
= A.
15. Reduce A'B'C' + A'BC' + A'BC
A'B'C' + A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B].
16. Reduce AB + (AC)' + AB’C (AB + C)
AB + (AC)' + AB’C (AB + C) = AB + (AC)' + AAB'BC + AB'CC
= AB + (AC)' + AB'CC [A.A' = 0]
= AB + (AC)' + AB'C [A.A = 1]
= AB + A' + C' =AB'C [(AB)' = A' + B']
= A' + B + C' + AB'C [A + AB' = A + B]
= A' + B'C + B + C' [A + A'B = A + B]
= A' + B + C' + B'C
=A' + B + C' + B'
=A' + C' + 1= 1 [A + 1 =1].
17. Show that (X + Y' + XY) (X + Y') (X'Y) = 0
(X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X) (X + Y’) (X' + Y) [A + A'B = A + B]
= (X + Y’) (X + Y’) (X'Y) [A + A = 1]
= (X + Y’) (X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0].
18. Prove that ABC + ABC' + AB'C + A'BC = AB + AC + BC
ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C + A'BC
=AB + AB'C + A'BC
=A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
19. Convert the given expression in canonical SOP form Y = AC + AB + BC.
Y = AC + AB + BC
=AC (B + B’) + AB (C + C’) + (A + A') BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
20. Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz).
By applying De-Morgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z') F2' = [x (y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
= x' + (y + z) (y' + z').
21. What are the methods adopted to reduce Boolean function?
 Karnaugh map
 Tabular method or Quine Mc-Cluskey method
 Variable entered map technique.
22. Find the minterms of the logical expression Y = A'B'C' + A'B'C + A'BC + ABC'?
Y = A'B'C' + A'B'C + A'BC + ABC'
= m0 + m1 +m3 +m6
= m (0, 1, 3, 6).
23. Write the maxterms corresponding to the logical expression
Y = (A + B + C’) (A + B' + C')(A' + B' + C)
= (A + B + C’) (A + B' + C')(A' + B' + C)
= M1.M3.M6
= M (1, 3, 6).
24. State the associative property of Boolean algebra. (May 2008)
The associative property of Boolean algebra states that the OR ing of several variables results in the
same regardless of the grouping of the variables. The associative property is stated as follows:
A+ (B+C) = (A+B) +C.
25. State the commutative property of Boolean algebra.
The commutative property states that the order in which the variables are OR ed makes no difference.
The commutative property is: A+B=B+A.
26. State the distributive property of Boolean algebra.
The distributive property states that AND ing several variables and OR ing the result with a single
variable is equivalent to OR ing the single variable with each of the several variables and then AND
ing the sums. The distributive property is: A+BC= (A+B) (A+C).
27. What is meant by principle of duality? (May 2003, 2004, 2005, 2008, 2010, Dec 2003, 2005, 2007,
2011)
The principle of Duality theorem says that, starting with a Boolean relation, you can derive another
Boolean relation by
1. Changing each OR sign to an AND sign.
2. Changing each AND sign to an OR sign.
3. Complementing any 0 or 1 appearing in the expression.
28. What are universal gates? Give examples. (May 2005, 2009, Dec 2006)
The NAND and NOR gates are known as universal gates, since any logic function can be
implemented using NAND or NOR gates.
29. Name the two canonical forms for Boolean algebra. (May 2007)
Standard SOP and standard POS forms.
30. What do you meant by literal?
In Boolean function, the total number of variables in complemented or uncomplemented form is called
literals.
31. State two absorption properties of Boolean algebra. (Dec 04)
(1) A+AB = A (2) A (A + B) = A
32. State the consensus theorem in Boolean algebra.
In simplification of Boolean expression, the redundant term in an expression can be eliminated to
form the equivalent expression. The theorem used for this simplification is called consensus theorem.
33. How many inputs are required for W = AB’D + ACD’+EF? (DEC 04)
Six inputs.
34. Express F = BC’ + AC in a canonical SOP form.(DEC 03)
F = BC’ + AC
= (A+A’)BC’ + AC(B+B’)
= ABC’+A’BC’+ABC+AB’C
35. What is variable mapping? (May 07)
Representing the minterms of the sum of product expression in the Karnaugh map of appropriate
variables is known as variable mapping.
36. State two significant features of tabular method of minimization of Boolean function.(Dec 04)
1) It is an exact method to simplify the Boolean expression..
2) It can be used to simplify expression with 7,8 or even variables.
37. Give an application for XOR function.
XOR function can be used as an inverter by connecting one input to logic 0. It can also be used as a
modulo 2 adder.
38. Simplify the following Boolean function: ab’c’ + ab’c + abc.
ab’c’ + ab’c + abc = ab’c’ + ac (b + b’ )
= ab’c’ + ac
= a (b’c’ + c)
= a( b’ + c )
= ab’ + ac.
39. Simplify (X+Y) (X+Y’).
(X+Y) (X+Y’) = XX + XY’ + XY + 0
= X + X(Y’+Y)
= X+X
= X
40. What are don’t care condition and incompletely specified term function?
Sometime, while designing a digital circuits, certain condition of input are of no use. Consider an
example of BCD input for a seven segment display. In this case, input from 0 through 9 valid inputs.
Thus, rest of the inputs from 10 through 15 do not signify anything at the output side .The outputs for
which inputs are not specified are called don’t care outputs. The Boolean function in which don’t
care outputs exists is called incomplete Boolean function or incompletely specified functions.
41. What is meant by weighted coding?
In weighted codes, each digit position of the number represents a specified weight. For example, in
decimal code, if number is 567 then weight of 5 is 100, weight of 6 is 10 and weight of 7 is 1. In
weighted binary codes each digit has a weight 8,4,2, or 1. The codes 8421,2421, and 5211 are all
weighted codes.
42. What is meant by Non - weighted coding?
Non – weighted codes are not assigned with any weight ta each digit position, i.e., each position
within the number is not assigned fixed value. Excess- 3 and gray codes are the non-weighted codes.
43. What is meant by error detecting and correcting coding?
The data along with extra bit/bits forms the code. Codes which allow only error detection are called
error detecting codes and codes which allow error detection and correction are called error detecting
and correcting codes.
44. What is meant by sum of product (SOP) ?
A product term is any group of literals that are ANDed together. For example, ABC, XY and so on. A
sum term is any group of literals that are ORed together such as A+B+C, X+Y and so. A SOP is a
group of product term ORed together. Example: ABC + AB’C’+A’B’C’.
45. What is meant by product of sum (POS) ?
A sum term is any group of literals that are ORed together. For example, A+B+C, X+Y and so on. A
product term is any group of literals that are ANDed together such as ABC, XY and so. A POS is a
group of sum term ANDed together. Example: (A+B+C) (A+B’+C’) (A’+B’+C’).
46. What is meant by minterm?
Each individual term in standard SOP form is called minterm.
47. What is meant by maxterm?
Each individual term in standard POS form is called minterm.
48. What is meant by positive logic system?
The system in which the higher of the two voltage levels represent a 1 and the lower voltage
represents a 0 is called a positive logic system.
Positive Logic: HIGH = 1
LOW = 0.
49. What is meant by negative logic system?
The system in which the lower of the two voltage levels represent a 1 and the higher of the voltage
represents a 0 is called a positive logic system.

Negative Logic: HIGH = 0

LOW = 1.
50. Which gates are called as the universal gates?
The NAND and NOR gates are called as the universal gates.
51.What are the limitations of Karnaugh map? (May/June 2013)
The size can be limited to 6 variables and also can be used for simplifying Boolean expressions.
52.Write the applications of Gray code? (May/June 2012)
Gray code are used in applications where the normal sequence of binary numbers may produce an error
or ambiguity during transition from one number to the next. Gray code in used in telegraphy, for more
robust communication and in error detection and correction.
53.Represent the decimal numbers -200 and 200 using 2’s complement binary form. (April/May 11)
2’s complement of +200 = 11001000
2’s complement of -200 = 100111000

PART – B
1. (i) State and prove Demorgan’s theorem. (Dec 2003)
(ii) Compare the performance of any five logic families, based on any five suitable parameters.
(May 2005)
2. Draw the symbol, truth table and the equation of the three basics gates and two universal gates
and realize all the five gates using either of the universal gates. (Dec 2011)
3. (ii) Explain the basics laws of Boolean algebra. (May 2007, Dec 2006)
(iii)Realize XOR function using four NAND gates only. (Dec 2007)
4. Simplify using Tabulation method
(i) F (W , X , Y , Z )   m(1,4,6,7,8,9,10,11,15) (Dec 2004)
(ii) F ( A, B, C , D, E )   M (0,1,4,5,9,11,13,15,16,19,25,27,28,29,31)   d ( 20,21,22,30) (Dec 2006)
(iii) F ( A, B, C , D, E , F , G )   m( 20,28,38,39,52,60,102,103,127) (Dec 2003)
(iv) F (V , W , X , Y , Z )   m( 4,5,6,7,9,10,14,19,26,30,31) ( Dec 2007)
(v) F ( A, B, C , D )   m(0,2,3,6,8,12,15)   d (1,5) (May 2008)

(vi) F ( A, B, C , D )   m(1,2,4,8,10,11,12,13,15) (Sep 2009)

(vii) F ( A, B, C , D )   m(1,2,3,7,8,9,10,11,14,15) (Dec 2008)
 (viii) F ( A, B, C , D )   m(1,2,4,5,6,8,9,12)   d (3,10,13,15)
(ix) F (W , X , Y , Z )   m(3,4,5,7,9,13,14,15) (Dec 2009)
(x) F ( A, B, C , D )   m(1,3,4,5,7,9,10,11)    (6,8) (May 2010)
(xi) F ( A, B, C , D )   m(0,2,3,6,7,8,10,12,13) (Dec 2011)
(xii)Prove that (X1 +X2) (X1’X3’ +X3 ) (X1X3 +X2’)’ = X1’X2 (Dec 2003, 2005)

5. Simplify the following function using K-map.

(i) F ( E , D, C , B, A)   m(3,5,6,8,9,12,13,14,19,22,24,25,30)
(ii) Find a minimal sum of products representation for
F ( A, B, C , D, E )   M (2,4,7,9,26,28,29,31) using K-map method. Draw the circuit of the minimal
expression using only NOR Gates. (Dec 2006)
(iii) Find a minimal sum of products representation for
F ( A, B, C , D, E )   m(1,4,6,10,20,22,24,26)   d (0,11,16,27) using K-map method. Draw the
circuit of the minimal expression using only NAND Gates. (Dec 2003, 2005)
(i) F ( A, B, C , D )   m(0,2,3,4,8,10,12,13,14) (Dec 2007)
(ii) F ( A, B, C , D )   m(0,1,2,5,8,9,10) (Dec 2008)
(iii) F ( w, x, y , z )  (1,3,4,5,6,7,8,9,12,13) (Dec 2008)

(iv) F ( A, B, C , D, E )   m(0,2,3,6,7)   d (8,10,11,15). Also implement them using

universal gates. (Sep 2009)
(v) F ( A, B, C , D )   M (0,1,4,5,6,8,9,12,13,14) (May2010)
(vi) F ( A, B, C , D, E )  m(0,3,5,6,7,12,14,15,18,21,25,26,27,29,31) (Dec 2011)
(vii) F ( A, B, C , D, E )  m(0,1,4,5,16,17,21,25,29) (Dec 2011)
6. Simplify using K-map to obtain a minimum POS expression (Dec 2009)

Y  ( A  B  C  D )( A  B +C+D) (A+B+ C +D) (A+B+ C+ D ) ( A +B+ C+ D ) (A+B+ C + D )

7. (i) Find the minterms of the given expression and reduce it using K-Map.

A B + BC + CD + AD + BCD + ABC D
(ii) Prove the following expression algebraically A+BC = (A+C)(A+B)
8. Implement the following Boolean function with NAND-NAND Logic.
(i) Y  AC  ABC  ABC  AB  D
(ii) F  ABC ' A' B ' C  ABC  AB ' C (Dec 2011)
(iii) Y  AC  AB  BD (Dec 2007)

9. Implement the following Boolean function with NOR-NOR logic. (Dec 2010)

(i) F ( A, B, C )   M (0,2,4,5,6) (ii) F  ( A B + AB ) ( C + D )

(iii) Prove the following using Demorgan’s theorem. (Dec 2008)

AB+CD = ((AB)’. (CD)’)’ & (A+B)(C+D) = ((A+B)’+(C+D)’)’

10. (i)Simplify the following function and draw the logic diagram for the same. (Dec 2008)
f 1  F ( A, B, C )   m(2,3,7) f 2  F ( A, B, C )   m(0,1,3)
(ii) Realize the following function as f  B( A  CD )  A C (May 2010)
a) Multilevel NAND-NAND gate network
b) Multilevel NOR-NOR gate network
 DIGITAL PRINICPLES AND SYSTEM DESIGN Unit-II Combinational Circuits

PART – A
1. Define combinational circuits. (May/June 2009)
When logic gates are connected together to produce a specified output for certain specified combinations
of input variables, with no storage involved, the resulting circuit is called combinational logic.
2. Define Half adder.
The logic circuit which perform the arithmetic sum of two bits is called a half adder.
3. What do you mean by comparator?
A comparator is a special combinational circuit designed primarily to compare the relative magnitude of
two binary numbers.
4. Define half subtractor.
Half subtractor: (i) Half subtractor is the combinational circuit which is used to perform subtractions
Of two bits.
(ii) It has two inputs (minuend, subtrahend) and two outputs D(difference), B(borrow).
5. What are code convertors?
Code convertor is a logic circuit that changes data presented in one type of binary code to another type of
binary code. Eg. BCD to excess-3-code.
6. What is BCD adder?
 BCD adder is used to add two BCD digit and produces a sum in BCD digit.
 BCD number means 0 to 9 (10 digit) are represented in binary form 0000 to 1001.
 BCD number cannot be greater than 9 and 10 is represented in BCD as 0001 0000.
7. Explain the design procedure for combinational circuits?
 The problem definition
 Determine the number of available input variables & required O/P variables.
 Assigning letter symbols to I/O variables
 Obtain simplified Boolean expression for each O/P.
 Obtain the logic diagram.
8. Which gate is equal to AND-invert Gate?
NAND gate.
9. Which gate is equal to OR-invert Gate?
NOR gate.
10. Bubbled OR gate is equal to--------------
NAND gate
11. Bubbled AND gate is equal to--------------
NOR gate
12. Implement the Boolean Expression for EX – OR gate using NAND Gates.

13. What do you mean by carry propagation delay?

In parallel adders, sum and carry outputs of any stage cannot be produced until the input carry occurs.
This time delay in the addition process is called carry propagation delay. This delay increases with
increase in the number of bits to be added in an adder circuit.
14. Suggest a solution to overcome the limitation on the speed of an adder.
It is possible to increase speed of adder by eliminating inter-stage carry delay. This method utilizes logic
gates to look at the lower order bits of the augends and added to see if a higher order carry is to be
generated.
15. What is serial adder?
 Serial adder uses shift registers
 The serial adder requires only one full adder circuit
 The serial adder is a sequential circuit
 Time required for addition depends on the number of bits
 It is slower
16. What is parallel adder?
 Parallel adder uses registers with parallel load capacity
 It is faster
 Time required for addition does not depend on number of bits
 Excluding the registers, the parallel adder is a purely combinational circuit
17. What is meant by restoring division method?
 Needs restoring of registers A if the result of subtraction is negative
 In each cycle content of register A is first shifted left and then divisor is subtracted from it.
 Does not need restoring of remainder
 Slower algorithm
18. What is meant by Non-restoring division method?
 Does not need restoring
  In each cycle content of register A is first shifted left and then divisor is added or subtracted from
with the content of register A depending on the sign of A.
 Needs restoring of remainder if remainder is negative.
 Faster algorithm

19. What are the limitations of half adder?

In multidigit addition, we have to add two bits along with the carry of previous digit addition. Effectively
such addition requires addition of three bits. This is not possible with half adder.
20. What are the limitations of half subtractor?
In multidigit subtraction, we have to add two bits along with the borrow of previous digit subtraction.
Effectively such subtraction requires subtraction of three bits. This is not possible with half subtractor.
21. Draw the block diagram of a 2’s complement adder/subtractor.

22. Draw the block diagram of full adder and logic diagram.
Block Diagram: Logic diagram:
23. Draw the block diagram of 4-bit binary parallel adder and subtractor.

24. What is binary multiplier?

 Multiplication of binary numbers is performed in the same way as in decimal numbers –
partial product: the multiplicand is multiplied by each bit of the multiplier starting from the
least significant bit.
 Multiplication process involves multiplication (product) of 2-bit number and addition of 2-bit
number.
25. What is meant by array multiplier?
The combination logic circuit implemented to perform such multiplication is called multiplier or array
multiplier.
26. Draw the block diagram of 2-bit by 2-bit binary multiplier.
Performance: Logic Diagram:
27. Write down the truth table of a half subtractor. (Nov/Dec 2005)

X Y BORROW DIFFERENCE

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

28. Write down the truth table of a half adder.

X Y CARRY SUM

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

29. Define parity generator.

A parity bit is used for the purpose of detecting errors during transmission of binary information. A
parity bit is an extra bit included with a binary message to make the number of 1’s either odd or
even.The message, including the parity bit is transmitted and then checked at the receiving end for
errors.

30. What is meant by logic optimization?

The logic expressions produced by the synthesis tools are not likely to be in an optimal form. It is the
task of the synthesis tool to manipulate the user’s design to produce an equivalent but better circuit
automatically. This step of synthesis process is called logic synthesis or logic optimization.
31. What are the types of parity generator?
There are two types of parity generator i) Even parity generator ii) Odd parity generator
 32. Define parity checker.

The circuit that checks the parity in the receiver is called a partiy checker.

33. Define even parity.

In even parity the added parity bit will make the total number of 1’s an even amount.

34. Define odd parity.

In odd parity the added parity bit will make the total number of 1’s an odd amount.

35. Define Full subtractor.

Full subtractor accepts three inputs-minuend, subtrahend, borrow from previous stage
And generates differences output & borrow output.
36. Define Full adder.
The circuit that performs the addition of three bits is a full adder.
37. What is meant by look ahead carry addition?
A method of speeding up this process by eliminating inter stage carry delay is called look ahead carry
addition.
38. Mention any two uses of HDL. (May/June 2006)
* HDL is used to describe hardware for the purpose of simulation, modeling, testing design and
documentation.
* The HDL makes it easy to exchange the ideas between the designers.
39. What is meant by array multiplier?
The combinational logic circuits implemented to perform such multiplication is called array multiplier
or combinational multiplier.
40. Draw the block diagram of 4-bit by 3-bit binary multiplier.Logic diagram:

41. Draw the block diagram of serial subtractor.

42. Define full adder. (May/June 2007)
The logic circuit which perform the arithmetic sum of three bits is called a full adder.
43. Define Half subtractor.
It is a combinational circuit that subtracts two bits and produces their difference and borrows.
44. Define Full subtractor.
It is a combinational circuit that performs a subtraction between two bits. It also takes into account
borrow of the lower significant stage.
45. List some procedure to design code converters.
* Write the truth table showing the relationship between input code and output code.
* For each output code bit determine the simplified Boolean expression using K- map.
* Realize the code converter using the logic gates.
46. What are the basic steps are involved in HDL process?
*Specify the desired behavior of the circuit.
* Synthesize the circuit.
* Implement the circuit.
* Test the circuit to check whether the desired specifications meet.

47. What is meant by combinational multiplier?

The combinational logic circuit implemented to perform such multiplication is called combinational
multiplier.
48. What is meant by logic synthesis? (Nov/Dec 2006)
The logic expressions produced by the synthesis tools are not likely to be in an optimal form. It is the
task of the synthesis tool to manipulate the user’s design to produce an equivalent but better circuit
automatically. This step of synthesis process is called logic synthesis or logic optimization.
49. What do you meant by HDL? (April/May 2010)
The Computer Aided Design (CAD) tools are used in the design of such systems. One such a tool is
a Hardware Description Language (HDL). HDL describes the hardware of digital system. This description
is an textual form. The Boolean expressions, logic diagrams and digital circuits (simple and complex) can
be represented using HDL.
50.How to overcome the limitation on the speed of an adder?
It is possible to increase speed of adder by eliminating inter-stage carry delay. This method utilizes logic
gates to look at the lower order bits of the augends and added to see if a higher order carry is to be
generated.
51.List the important features of HDL. (Nov/Dec 2006)
i.HDL can be used to represent logic diagrams, Boolean expressions and other complex digital circuits.
ii.As documentation language, HDL: is used to rpresent and document digital systems in a form that can
be read by both humans and computers and is suitable as an exchange between designers.
52. What are the modeling technique available to build HDL module. (May/June 2007)
i. Gate level modeling using instantiation of primitive gates and user defined modules
ii. Data flow modeling using continuous assignment statements with keyword ‘assign’.
iii. Behavioral modeling, using procedural assignment statements with keyword ’always’.
53.What are the drawback of k-map method? (Nov/Dec 2007)
The k-map method of simplification is convenient as long as the number of variables does not exceed five
or six, as the number of variable increases it is difficult to make judgements about which combinations
from the minimum expressions.
54.What is logic synthesis in HDL? (Nov/Dec 2007)
Logic synthesis is the process of deriving the list of components and their interconnections (called a net list)
From the model of a digital system described in HDL.
55.What is the difference between Behavioral modeling and Data flow modeling? (Nov/Dec 2008)
Behavioral modeling represent digital circuits at a functional and algorithmic level. It is used mostly to
describe sequential circuits, but can be used also to describe combinational circuits.
Data flow modeling uses a number of operators that act on operands to produce desired results.
56. What is the need for code conversion? Give two commonly used codes. (May/June 2009)
The availability of a large variety of codes for the same discrete elements of information results in the
use of different codes by different logic systems. It is sometimes necessary to use the output of one
system as the input to another. A conversion circuit must be inserted between the two systems if each
uses different codes for the same information. Two codes commonly used are 1.Binary code 2.Binary
coded decimal 3.Gray code.
57. What is priority encoder? (April/May 2007, 08)
A priority encoder is an encoder circuit that includes the priority function. In priority encoder, if two or
more inputs are equal to 1 at the same time, the input having the highest priority will taken precedence.
Inputs Outputs

DDDD
58.What is the function of encoder? (Nov/Dec 2006)
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2 n
lines (or fewer). The output line generate the binary code corresponding to the input value.

59.What is the function of decoder? (Nov/Dec 2006)

A decoder is a combinational circuit that converts binary information from n input lines to a maximum
of 2n unique output lines. If the n-bit coded information has unused combinations, the decoder may have
fewer than 2n outputs.
60. What is a multiplexer? (Nov/Dec 2006)
A multiplexer is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. The selection of a particular input is controlled by a set of selection lines.
61.Mention any two applications of Multiplexer. (May/June 2007)
I .Multiplexer can be used to realize a Boolean function.
ii. It can also be used in communication systems.
62. What is a Demultiplexer? (Nov/Dec 2008)
A demultiplexer is a circuit that receives information from a single line an directs if it one of 2 n possible
output lines. The selection of specific output is controlled by the bit combination of n selection lines.
63. Define simulation. (May/June 2012)
Simulation is the representation of the structure and behaviour of a digital logic system through the use
of a computer.
64. Define Tristate gates. (May/June 2012)
Tristate means a state of logic other than ‘1’ and ‘0’ in which there is a high impedance state and there is
no isource and isink at the output stage transistor. A gate capable of being in ‘1’ , ’0’ and tristate is known as
tristate gate.

PART – B
1. Explain in detail the working Principle of fast adder. (or) Explain in detail the look ahead carry
generator. (Dec 2010)
2. Draw a logic diagram of a 4-bit parallel adder/subtractor using full adder and explain. (or)
Design a 4-bit ripple carry adder. (Dec 2007,May 2003)
3. Design a 4-bit binary subtractor circuit. (May 2003)
4. Design a combinational circuit that performs the arithmetic sum of three inputs and produces a
sum and carry output. (or) Explain half adder and full adder with neat circuit diagram. (May
2006)
5. Explain half subtractor and full subtractor with neat circuit diagram. (May 2010,2003,2011)
6. Implement full adder using two half adder. (Dec 2007,May 2011)
7. Implement full subtractor using two half subtractor. (May 2010)
8. Draw the circuit of BCD adder and Explain. (Dec 2011)
9. Design a BCD to excess-3 code using binary parallel adder. (Dec 2007)
10. Draw and explain the circuit for 4-bit by 4-bit binary multiplier. (or) Design a combinational
system that produces the product of 2 binary number A= (A1,A2) X B =(B2,B1,B0). (Dec
2010)
11. Draw and explain the circuit for 4-bit by 3-bit binary multiplier. (Dec 2011)
12. Explain the restoring division algorithm and non-restoring division algorithm with the help of
suitable example. (Dec 2003,May 2007,2009)
13. Explain even & odd Parity generator and checker. (Dec 2008,May 2010)
14. Design a 4-bit binary to BCD converter.
15. Design a 4-bit binary to Gray code converter. (May2010, 2009)
16. Design a 4-bit binary to excess-3 code converter.
17. Design a 4-bit BCD to excess-3 code converter. (Dec 2003,May 2010)
18. Design a 4-bit BCD to gray code converter. (Dec 2003)
19. Design a 4-bit excess-3 code to BCD converter.
20. Design a 4-bit Gray code to BCD converter. (May 2005)

21. Design a 4-bit Gray code to Binary converter. (Dec 2009)

22. Design (i) 2-bit comparator using gates. (ii) 1-bit comparator using gates. (May 2011)
(iii) 4-bit comparator using gates. (May2005).(May 2008)
23. (ii)Perform 11002 ÷ 1012 using restoring division algorithm. (Dec 2008)
24. Explain the various data types supported in Verilog HDL.
 Unit-III Synchronous sequential
DIGITAL PRINICPLES AND SYSTEM DESIGN logic
PART – A
1. What is the classification of sequential circuits?
The sequential circuits are classified on the basis of timing of their signals into two types. They are:
 Synchronous sequential circuit.
 Asynchronous sequential circuit.
2. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop maintains its output state either at 1 or 0 until directed by an
input signal to change its state.
3. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned below they are:
 RS flip-flop
 SR flip-flop
 D flip-flop
 JK flip-flop
 T flip-flop
4. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if D=1, the output Q is set and if D=0, the output is reset.
5. What is the operation of JK flip-flop?
 When K input is low and J input is high the Q output of flip-flop is set.
 When K input is high and J input is low the Q output of flip-flop isreset.
 When both the inputs K and J are low the output does not change
 When both the inputs K and J are high it is possible to set or reset the flip-flop (ie) the output
toggle on the next positive clock edge.
6. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.
 When T=0 there is no change in the output.
 When T=1 the output switch to the complement state (ie) the output toggles.
7. Define race around condition. (Nov/Dec 2009)
In JK flip-flop output is fed back to the input. Therefore change in the output results change in the input. Due to
this in the positive half of the clock pulse if both J and K are high then output toggles continuously. This
condition is called ‘race around condition’.
8. What is edge-triggered flip-flop?
The problem of race around condition can solved by edge triggering flip flop. The term edge triggering means
that the flip-flop changes state either at the positive edge or negative edge of the clock pulse and it is sensitive
to its inputs only at this transition of the clock.
9. What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.

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 Unit-III Synchronous sequential
DIGITAL PRINICPLES AND SYSTEM DESIGN logic

10. Define rise time.

The time required to change the voltage level from 10% to 90% is known as rise time (tr).
11. Define fall time.
The time required to change the voltage level from 90% to 10% is known as fall time (tf).
12. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is referred to as skew and the time delay between
the two clock pulses is called clock skew.
13. Define setup time.
The setup time is the minimum time required to maintain a constant voltage levels at the excitation inputs of
the flip-flop device prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked
into the flip flop. It is denoted as tsetup.
14. Define hold time.
The hold time is the minimum time for which the voltage levels at the excitation inputs must remain constant
after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip flop. It is
denoted as thold .
15. Define Propagation Delay.
A propagation delay is the time required to change the output after the application of the input.
16. Define registers.
A register is a group of flip-flops flip-flop can store one bit information. So an n-bit register has a group of n flip-
flops and is capable of storing any binary information/number containing n-bits.
17. Define shift registers. (May/June 2009)
The binary information in a register can be moved from stage to stage within the register or into or out of the
register upon application of clock pulses. This type of bit movement or shifting is essential for certain arithmetic
and logic operations used in microprocessors. This gives rise to group of registers called shift registers.
18. What are the different types of shift registers? (May/June 2009)
There are five types. They are:
 Serial In Serial Out Shift Register
 Serial In Parallel Out Shift Register
 Parallel In Serial Out Shift Register
 Parallel In Parallel Out Shift Register
 Bidirectional Shift Register.
19. Explain the flip-flop excitation tables for RS FF.
RS Flip-Flop:
In RS flip-flop there are four possible transitions from the present state to the next state. They are:
 0->0 transition: This can happen either when R=S=0 or when R=1 and S=0.
 0->1 transition: This can happen only when S=1 and R=0.
  1->0 transition: This can happen only when S=0 and R=1.
 1->1 transition: This can happen either when S=1 and R=0 or S=0 and R=0.

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Unit-III Synchronous sequential
DIGITAL PRINICPLES AND SYSTEM DESIGN logic

20. Define sequential circuit?

In sequential circuits the output variables dependent not only on the present input variables but they also
depend up on the past history of these input variables.
21. What do you mean by present state?
The information stored in the memory elements at any given time.
22. Give the comparison between combinational circuits and sequential circuits.(Nov/Dec 2007,2009)
Combinational circuits Sequential circuits
1. Memory unit is not required 1. Memory unity is required
2. Parallel adder is a combinational
circuit 2. Serial adder is a sequential circuit
23. What do you mean by next state?
The present state and the external inputs determine the outputs and the next state of the sequential circuit.
24. Write brief notes on state assignment problem. (May 2010)
The state assignment procedure is based on the methods which assign binary values to the states in such way
that it reduces the cost of the combinational circuits that drives the flip-flops. The completing of the
combinational circuits obtained depends on the binary state assignment chosen
25. Define synchronous sequential circuit.
In synchronous sequential circuits, signals can affect the memory elements only at discrete instant of time.
26. What are the different types of triggering?
There are two types of triggering. They are:
 Level triggering
 Edge triggering
27. What is a counter?
A register that goes through a prescribed sequence of states, upon the application of input clock pulses is
called a counter.
28. What is a ripple counter?
Ripple counter is a simple binary counter, where the changing state of the LSB flip-flop trigger, the clock input
of the next flip-flop and so on and time delay results from the rippling of the count from LSB to MSB.
29. What is modulus of a counter?
The modulus of a counter is the number of different states; the counter must go through, to complete its
counting cycle.
30. What is binary count-down counter?
A binary counter with a reverse count is called as a binary count-down counter. In this counter, the binary
count is decremented by 1 with every input count pulse.
31. What are the uses of counters?
Counters are bused a frequency dividers in digital time pieces, such as electric digital clocks, automobile digital
clock and wristwatches, frequency counters, oscilloscope and television receivers.
32. Define up-down counter.
 It has an up control input and a down control input.

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Unit-III Synchronous sequential

DIGITAL PRINICPLES AND SYSTEM DESIGN logic

 When the up input is 1, the circuit counts up.

 When the down input is 0 and the up input is 1, the circuit counts down.
 This ensures that only one operation is performed at any given time.
33. Give some basic flip-flop applications.
 Parallel data storage
 Data transfer
 Frequency division and
 counting
34. Draw the graphical symbol of edge-triggered D flip-flop.
The bubble outside the block adjacent to the dynamic indicator designates a negative edge for triggering
circuit. The absence of bubble designates a positive – edge response.
35. Give some applications of D flip-flop.
 It is used as temporary memory devices.
 D flip-flops are wired together to form shift registers and storage registers, which are commonly used
in digital systems.
36. Define unidirectional shift register.
A register capable of shifting in one direction is called as a unidirectional shift register.
37. Define Bidirectional Shift register.
A register capable of shifting in both directions are called as a bidirectional shift register.
38. Define universal shift register.
A register which has both shifts and parallel load capabilities is referred to as a universal shift register.
39. What are the applications of shift register? (Nov/Dec 2010)
 Time delay
 Serial to parallel converter
 Parallel to serial converter
 Shift register used for counters
40. How will be converted ring counter to Johnson counter?
To obtain the Johnson counter, the complement output of last flip flop is given to the input of first flip flop.
41. Which shift register is used for serial to parallel converter?
The serial in parallel out shift register is used for serial to parallel converter in the digital systems.
42. Define serial modes of operation.
Information is transferred one bit at a time, while the registers are shifted in the same direction during one
clock pulse.
43. Define parallel modes of operation.
Information is available from all bits of a register and all bits can be transferred simultaneously.

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Unit-III Synchronous sequential

DIGITAL PRINICPLES AND SYSTEM DESIGN logic

44. What is meant by storage capacity of a register?

The storage capacity of a register is the number of bits of digital data, it can retain. Each stage of a shift
register represents one bit of storage capacity and therefore the number of stages in a register determines its
total storage capacity.
45. What are the characteristics of a clocked R-S flip-flop?
 It operates synchronously i.e. it operates in step with the clock.
 Once the flip-flop is set or reset, it stays stable even if some inputs are changed.
46. Give some applications of clocked RS flip-flop.
 Clocked R-S flip-flops are used in calculators and computers.
 It is widely used in modern electronic products.
47. What is meant by excitation tables?
A table showing the required input conditions for every possible transition of a flip-flop output.
48. Define synchronous counter.
When counter is clocked such that each flip-flop in the counter is triggered at the same time, the counter is
called synchronous counter.
49. Define asynchronous counter.
The counter in which the output of the current Flip-flop drives the clock input of the next higher-order flip-flop is
called asynchronous counter.
50. What is a master-slave flip-flop?
A master slave flip-flop consists of two flip-flops where one circuit serves as a master and the other as a slave.
The output of the master flip-flop is fed as an input to the slave flip-flop. The master flip-flop is triggered at the
positive edge of the clock and slave flip-flop is triggered at the negative edge of the clock.
51.What is a binary counter? (Nov/Dec 2006)
A counter that follows the binary sequence is called a binary counter. An n-bit binary counter consists of n flip-
flop and can count in binary from 0 to 2-1.
52.What are the models used to represent clocked sequential circuits? (or) (Nov/Dec 2006)
 Differentiate Moore and Mealy circuit model. (Nov/Dec 2010)

The synchronous or clocked sequential circuits(networks) are represented by two models

Moore model : The output depends only on the present state of the flip-flops.
Mealy model : The output depends on both the present state of the flip-flop and on the input.
53.What is gate level modeling? (Nov/Dec 2007)
Gat level modeling describes the circuit by specifying the gates and how they are connected with each other.
In this type of representation, a circuit is specified by its logic gates and their interconnection.
54. What is the maximum range of memory that can be accessed using ten address lines?
(May/June 2008)
Maximum memory = 1024 bytes.
55. What is modulo-N counter? (May/June 2008)
A counter is a circuit used to count a repeated set of values for a variable like clock pulses. Modulo-N counter
decides the number of bits in the output sequence like N=2n, where ‘n’ is the number of bits (Number of flip-
flops used to design the counter).
56. Differentiate flip-flop from latches. (April/May 2010)
Flip-flops is a sequential device that normally samples its inputs and changes its outputs only at times
determined by clocking signal.
Latch is a sequential circuit that clocks all of its inputs continuously and changes its output accordingly at any
time independent of a clocking signal.
57. What is a ring counter? (Nov/Dec 2012)
A ring counter is basically a circulating shift register in which the output of the most significant stage is fed back
to the input of the least significant stage.
58. List any two mechanisms to achieve edge triggering of flip-flops (May 2012)
The mechanisms are classified as either edge triggered(ET) or Master Slave(MS).
59. What is Mealy Circuit? (May/June 2013)
When the output of the sequential circuit depends on both the present state of the flip-flops and on the inputs,
the sequential circuit is referred to as Mealy circuit.

PART – B
1. Realize a SR flip-flop using NAND gates and explain its operation. Derive the characteristics
equation. (Dec 2003,2005)
2. Explain the working of a master-slave JK flip-flop. (Dec 2005)
3. Realize a SR flip-flop using NOR gates and explain its operation. Derive the characteristics
equation. (Dec2005)
4. Realize a JK flip-flop using NOR gates and explain its operation. Derive the characteristics
equation. (Dec 2003)
5. Draw the logic diagram of a D-FF using NAND gates and explain. (Dec 2008)
6. Draw the clocked RS flip-flop and explain with truth table. (May 2007)
7. Explain the T-flip-flop.
8. (i) Convert JK flip-flop to D flip-flop. (May 2003,2005)
(ii) Convert D flip-flop to T flip-flop. (May 2011)
(iii) Convert SR flip-flop to D flip-flop. (Dec 2008)
(iv) Convert D flip-flop to JK flip-flop. (Dec 2009, 2011)
(v) Convert SR flip-flop to JK flip-flop.
(vi) Convert SR flip-flop to T flip-flop.
(vii) Convert JK flip-flop to T flip-flop.
(viii) Convert JK flip-flop to SR flip-flop.
9. Explain in detail the operation of a 4-bit binary ripple counter (or) Design and explain the
working of an up/down counter. (May 2003)
10. (i) Design BCD ripple counter using JK flip-flop. (Dec 2004,May 2006)

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Unit-III Synchronous sequential
DIGITAL PRINICPLES AND SYSTEM DESIGN logic

(ii ) Design a 3-bit asynchronous BCD ripple counter using T flip-flop. (May 2009)
(iii) Design a three bit binary counter using T flip-flop. (Dec 2011, 2009)
(iv) Design and explain the working of a synchronous mod-3 counter. (May 2003)
(v) Design and explain the working of Mod-7, Mod-15 and Mod-11 counter. (Dec 2003)
(vii) Design a synchronous counter with states 0, 1, 2, 3, 0, 1,…using JK FFs. (May 2004)
(viii)Design a 3-bit binary counter using T flip-flop that has a repeated sequence of six states.
000-001-010-100-101-110. Give the state table, state diagram and logic diagram. (Dec 2007)
11. Draw a 4-bit SISO, PISO, SIPO and PIPO Shift register. (Dec 2006,May 2006)
12. Explain the operation of universal shift register with neat block diagram. (Dec 2010,May 2009)
13. Draw a six-stage ring counter and explain its operation. (Dec 2005)
14. Draw the 4-bit Johnson counter and explain the operation. (or) Design Johnson Counter and
state its advantages and disadvantages. (Dec 2011,May 2007)
15. Explain in detail about sequence generator and detector.
16. Design a synchronous sequential circuit using JK flip-flop to generate the
following sequence and repeat. 0, 1, 2, 4, 5, 6 (16)
17. What is the aim of state reduction? Reduce the given state diagram and
prove that the both state diagrams are equal. (16)
18.Using D flip-flops design a synchronous counter which counts in the sequence
000,001,010,01,10,101,110,111,000 (April/May 2013)
19. Design a 3-bit binary counter. (Nov/Dec 2012)
20. Write the HDL description of T flip-flop and JK flip-flop from D flip-flop and gates. (Nov/Dec 2012)
III Semester ECE– Page 6
 DIGITAL PRINICPLES AND SYSTEM DESIGN Unit-IV Asynchronous sequential Logic

PART – A
1. Define Asynchronous sequential circuit.
In asynchronous sequential circuits change in input signals can affect memory element at any instant of time.
2. Give the comparison between synchronous & Asynchronous sequential circuits?

Synchronous sequential circuits Asynchronous sequential circuits.

(i)Memory elements are clocked flip-flops (i) Memory elements are either unlocked flip -
flops or time delay elements.

(ii)Easier to design (ii)More difficult to design

3. What is race around condition?
In the JK latch, the output is feedback to the input, and therefore changes in the output results change in the
input. Due to this in the positive half of the clock pulse if J and K are both high then output toggles continuously.
This condition is known as race around condition.
4. The tpd for each flip-flop is 50 ns. Determine the maximum operating frequency for MOD - 32
ripple counter
f max (ripple) = 5 x 50 ns = 4 MHZ
5. What are secondary variables?
Secondary variables are the present state variables in asynchronous sequential circuits.
6. What are excitation variables?
Excitation variables are the next state variables in asynchronous sequential circuits.
7. What is fundamental mode sequential circuit? (or) (April/may 2008)
What are the assumptions that must be made for fundamental mode sequential circuit?
 Input variables changes if the circuit is stable
 Inputs are levels, not pulses
 Only one input can change at a given time.
8. What are pulse mode circuits? (or) (Nov/Dec 2006.2007 May/June 2007)
What are the assumptions that must be made for pulse mode sequential circuit?
 Inputs are pulses instead of levels
 Width of pulses are long for circuit to respond to the input
 Pulse width must not be so long that it is still present after the new state is reached
9. What is the significance of state assignment?
 In synchronous circuits-state assignments are made with the objective of circuit reduction
 Asynchronous circuits-its objective is to avoid critical races
10. When does race condition occur?
The race condition occurs at two or more binary state variables change their value in response to the change in
input variable.
11. What is non critical race? (May/June 2006)
Non critical race final stable state does not depend on the order in which the state variable changes -race
condition is not harmful.
12. What is critical race? (Nov/Dec 2005,2010)
The critical race final stable state depends on the order in which the state variable changes -race condition is
harmful.

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DIGITAL PRINICPLES AND SYSTEM DESIGN Unit-IV Asynchronous sequential Logic

13. When does a cycle occur?

The cycle occurs asynchronous circuit makes a transition through a series of unstable state.
14. What are the different techniques used in state assignment?
 Shared row state assignment
 One hot state assignment
15. Define state assignment.
The state assignment is an one step in the design of sequential circuits which assigns binary values to the states
in such a way that it reduces the cost of the combinational circuit that drives the flip-flops.
16. What is hazard? (May/June 2007, April/May 2008,2009)
A hazard is a condition where is a single variable change produces a momentary output change when no output
change should occur.
The unwanted switching transients that may appear at the output of a circuit are called hazards, which may
cause the circuit to malfunction.
17. What is static 1 hazard? (May/June 2013)
Static 1 hazard -output goes momentarily 0 when it should remain at 1.
18. What are static 0 hazards? (May/June 2013)
Static 0 hazard -output goes momentarily 1 when it should remain at 0
19. What is dynamic hazard? (April/May 2011)
Dynamic hazard occurs when the output of a network is to change between its two logic states
19. What is the cause for essential hazards? (May/June 2012)
The cause for essential hazards is unequal delays along 2 or more path from same input. An excessive delay
through an inverter circuit in comparison to the delay associated with the feedback path may cause such a
hazard
20. Define state table.
For the design of sequential counters we have to relate present states and next states. The table, which
represents the relationship between present states and next states, is called state table.
21. What is flow table?
Flow table is the state table of an synchronous sequential network.
22. Define total state.
The combination of level signals that appear at the inputs and the outputs of the delays define what is called the
total state of the circuit.
23. What are the steps for the design of asynchronous sequential circuit? (Nov/Dec 2009)
 Construction of a primitive flow table from the problem statement.
 Primitive flow table is reduced by eliminating redundant states using the state reduction
 State assignment is made
  The primitive flow table is realized using appropriate logic elements.
24. Define primitive flow table.
It is defined as a flow table which has exactly one stable state for each row in the table. The design process
begins with the construction of primitive flow table.
25. What are the types of asynchronous circuits? (May/June 2006)
 Fundamental mode circuits
 Pulse mode circuits.

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DIGITAL PRINICPLES AND SYSTEM DESIGN Unit-IV Asynchronous sequential Logic

26. Give the comparison between state Assignment Synchronous circuit and state assignment
asynchronous circuit.
In synchronous circuit, the state assignments are made with the objective of circuit reduction. In asynchronous
circuits, the objective of state assignment is to avoid critical races.
27. What is essential hazard?
An essential hazard is caused by unequal delays along two or more paths that originate from the same input.
Such hazards can be eliminated by adjusting the amount of delays in the affected path.
28. What are races?
When two or more binary state variables change their value in response to a change in an input variable, race
condition occurs in an asynchronous sequential circuit. in case of unequal delays, a race condition may cause
the state variables to change in an unpredictable manner.
29. What is a state diagram?
A state diagram is graphical representation of the information available in a state table. In the diagram, a state is
represented by a circle and the transitions between states are indicated by directed lines connecting the circles.
30. What are input and output equations?
The part of the circuit that generates the inputs to flip-flops is described algebraically by a set of Boolean
functions called input equations.
31. What are called clocked sequential circuits?
Synchronous sequential circuits that use clock pulses in the inputs of storage elements are called clocked
sequential circuits.
32. How can we describe the structure of a sequential circuit?
The sequential circuit is made up of flip-flops and gates and so its structure can be described by a combination of
data flow and behavioral statements.
33. Define Moore model.
 The output of this machine is the function of the present state only.
 Input changes do not affect output.
 It requires more number of states for implementing same function.
34. Define Mealy model.
 Its output is function of present input as well as present state.
  Input changes may affect the output of the circuit.
 It requires less number of states for implementing same function.
35. What is a sensitivity list?
A sensitivity list specifies the events that must occur to initiate the execution of the procedural statements in the
always block. Statements within the block execute sequentially and the execution suspends after the last
statement has been executed.
36. How can the hazards in combinational circuits be removed?
Hazards in the combinational circuits can be removed by covering any two minterms that may produce

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DIGITAL PRINICPLES AND SYSTEM DESIGN Unit-IV Asynchronous sequential Logic

hazard with a product term common to both. the removal of hazards requires the addition of redundant gates to
the circuit.
37. How do the essential hazards differ from static and dynamic hazards?
 They exist only in sequential circuits with two or more feedbacks.
 If they exist, they result from a combination of both delay and the design specifications.
38. How can we overcome the problems due to essentials hazards?
 The problems can be corrected by adjusting the amount of delay in the affected path.
 To avoid the hazards, each feedback loop must be handled with individual care, to ensure that the delay
in the feedback path is long enough compared to delays of other signals that originate from the input
terminals.
39. What is meant by procedural assignment?
A procedural assignment is an assignment within an initial or always statement. The initial behavior executes
once at time O. The always behavior executes repeatedly and re-executes until the simulation terminates.
40. Define merger graph.
The merger graph is defined as follows. it contains the same number of vertices as the state table contains state.
A line drawn between the two state vertices indicates each compatible state pair. it two states are incompatible
no connecting line is drawn. it is used as a tool in state reduction process.
41. What is lockout? How it is avoided? (Nov/Dec 2009)
 In a counter, if the next state of some unused state is again some unused state, it may happen that the
counter remains in unused states never to arrive at a used state. Such a condition is called a lockout
condition.
 To avoid lockout, the counter should be provided with an additional logic circuitry which will force the
counter from an unused state to the next state as initial state.
42. What is a self starting counter?
In a counter, if the next state of some unused state is again an unused state and if by chance the counter is said
to be in the lockout conditions. The counter which never goes in lockout condition is called self starting counter.
43. What are the basic building blocks of an algorithmic state machine chart?
 State box
 Decision Box
  Conditional box
44. Under what circumstances asynchronous circuits are preferred?
Asynchronous circuits can operate faster than synchronous circuits and hence they are preferred when speed is
an important criterion.
45. Define Algorithms state machine (ASM) chart.
A special flowchart that has been developed specifically to define digital hardware algorithms is called an ASM
Chart.

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DIGITAL PRINICPLES AND SYSTEM DESIGN Unit-IV Asynchronous sequential Logic

46. Define datapath.

The data processing path, commonly known as a data path, manipulates data in registers according to systems
requirements.
47. Define sequence detector.
The specified input sequence can be detected using a sequential machine called sequence detector.
48. Define sequence generator.
A sequential circuit which generates a prescribed sequence of bits, in synchronism with a clock, is referred to as
a sequence generator.
49. Why is state reduction necessary?
The state reduction is a technique that reduces the number of states in the sequential circuit by keeping
Only on one state for two or more redundant/equivalent states. This reduces the number of required flip-flops and
logic gates, reducing the cost of the final circuit.
50. What are the modeling techniques available in VHDL?
 Structural modeling/Gate-level modeling
 Dataflow modeling
 Behavioral modeling
51. What are the various types of operators in VHDL?
 Boolean logical
 Bitwise logical
 Relational
 Binary arithmetic
 Unary arithmetic
52. With 16-bit shift registers, how many timing signals can be generated? (Nov/Dec 2008)
16(sixteen) timing signals can be generated.
53.What is the advantage of debounce circuit? (Nov/Dec 2008)
A debounce circuit is one that removes the series of pulses that result from a contact bounce and produces a
single smooth transition of the binary signal from 0 to 1 or from 1 to 0.
54.What are the types of hazards? (Nov/dec 2010)
1. Static 1 hazard
2. Static 0 hazard
3. Dynamic hazard
4. Essential hazard.
55.Distinguish between a conventional flow chart and an ASM chart. (Nov/Dec 2012)
A conventional flow chart is a convenient way to specify the sequence of procedural steps and decision paths for
an algorithm.
Algorithmic state machine (ASM) chart is a flow chart that has been developed specifically to define digital
hardware algorithmic.
56.What is primitive flow table? (May/June 2013)
A primitive flow table is a flow table with only one stable total state in each row.
57.Mention any one advantage and disadvantage of asynchronous sequential circuits. (Nov/Dec 05)
Advantage: Because of absence of clock, asynchronous circuits are faster than synchronous circuits.
Disadvantage: Asynchronous circuits are more difficult to design.
58.Express the next state characteristics of D and SR flip-flops. (April/May 2011)
Characteristic equation of D flip-flop: Qt+1 = D

Characteristic equation of SR flip-flop: Qt+1 = S+ R Qt

59.What is Race condition? (April/May 2010)
A race condition occurs in an asynchronous circuit when two or more state variables change in response to a
change in the value of a circuit input.

PART – B
1. Explain the steps for the design of asynchronous sequential circuits. (May/June2013)
2. Write detailed notes on hazards in combinational circuits and sequential circuits (Nov/Dec 2012)
3. Explain race-free state assignment with an example. (Nov/Dec 2012)
4. With suitable design example explain ASM chart. (Nov/Dec 2011)
5. i. Write short notes on races and cycles that occur in fundamental mode circuits.
ii. What is essential hazard? Explain with example. (May/June2007)
6. What is meant by hazard? Differentiate between static, dynamic and essential hazard. (Nov/Dec 2003)
7. Show that no static 0(static 1) hazard can happen in a two level AND-OR (OR-AND) realization of a
switching function F. (May/June2003)
8. Implement the switching function x1x’2y1‘+ x1x2y2 by a static hazard free two level AN D-OR gate
network. (May/June2004)
9. What is race-around condition in latches? How is it overcome? Explain. (Nov/Dec 2004)
10. Explain races, Hazards, cycles, Stable state and unstable state with example. (May/June2005)
11. Draw the schematic diagram of master-slave JK flip-flop and input and output waveforms. Discuss
how it prevents race around condition. (May/June2005)
12. Explain the principle of pulse mode asynchronous sequential logic circuits. What are the restrictions to
be laid on the input signal of a pulse mode asynchronous sequential circuit? (Nov/Dec 2005)
13.Implement a scalar with a period of 24 by technique of asynchronous coupling and explain the
procedure. (Nov/Dec 2005)