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    Electrical and Computer Engineering Computer Organization and Architecture CSE 332 Credits - 3 Prerequisites: CSE 231 Digital Logic Design

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    Syed Latiful Akhter Ankon
    This document discusses computer organization and architecture, specifically datapath and control for various MIPS instruction types. It contains 3 key points: 1. It describes the datapath for load and store (LW and SW) memory instructions, showing how the base register and offset are used to calculate the memory address and load from or store to data memory. 2. It shows the datapath for branch instructions like BEQ, which compares two registers and branches to a target address if they are equal, using the ALU zero flag and offset to calculate the new PC value. 3. It explains that in a 5-stage pipeline processor, instructions can execute back-to-back in different stages with a clock cycle of 1,

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    Electrical and Computer Engineering Computer Organization and Architecture CSE 332 Credits - 3 Prerequisites: CSE 231 Digital Logic Design

    Uploaded by

    Syed Latiful Akhter Ankon
    29 views39 pages
    This document discusses computer organization and architecture, specifically datapath and control for various MIPS instruction types. It contains 3 key points: 1. It describes the datapath for load and store (LW and SW) memory instructions, showing how the base register and offset are used to calculate the memory address and load from or store to data memory. 2. It shows the datapath for branch instructions like BEQ, which compares two registers and branches to a target address if they are equal, using the ALU zero flag and offset to calculate the new PC value. 3. It explains that in a 5-stage pipeline processor, instructions can execute back-to-back in different stages with a clock cycle of 1,

    Original Title

    CSE 332 L6 & L7 - 19 & 24 Dec 2020

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    This document discusses computer organization and architecture, specifically datapath and control for various MIPS instruction types. It contains 3 key points: 1. It describes the datapath for load and store (LW and SW) memory instructions, showing how the base register and offset are used to calculate the memory address and load from or store to data memory. 2. It shows the datapath for branch instructions like BEQ, which compares two registers and branches to a target address if they are equal, using the ALU zero flag and offset to calculate the new PC value. 3. It explains that in a 5-stage pipeline processor, instructions can execute back-to-back in different stages with a clock cycle of 1,

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    29 views39 pages

    Electrical and Computer Engineering Computer Organization and Architecture CSE 332 Credits - 3 Prerequisites: CSE 231 Digital Logic Design

    Uploaded by

    Syed Latiful Akhter Ankon
    This document discusses computer organization and architecture, specifically datapath and control for various MIPS instruction types. It contains 3 key points: 1. It describes the datapath for load and store (LW and SW) memory instructions, showing how the base register and offset are used to calculate the memory address and load from or store to data memory. 2. It shows the datapath for branch instructions like BEQ, which compares two registers and branches to a target address if they are equal, using the ALU zero flag and offset to calculate the new PC value. 3. It explains that in a 5-stage pipeline processor, instructions can execute back-to-back in different stages with a clock cycle of 1,

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 39

    Electrical and Computer Engineering

    Computer Organization and Architecture


    CSE 332
    Credits – 3

    Prerequisites : CSE 231 Digital Logic


    Design

    1
    LESSON 7
    Datapath & Control.

    Source:
    https://sites.google.com/site/neuro11school/lect
    2
    3
    4
    5
    MIPS Program 1000
    Add $t0,…
    Inst. Addr. instruction
    1000 Add $t0,…
    1004 Lw $t1, …
    …. ….

    Instruction Memory is a part of Main Memory.

    6
    1004 1000
    PC is a 32 bit Register

    1004 1000

    7
    1000

    1004

    0004

    1004 1000

    8
    Inst. Addr. instruction
    1000 Add $t0,…
    1004 Lw $t1, …
    …. ….

    Draw
    Draw & Explain
    Develop or complete

    Into CPU
    for
    execution

    9
    10
    -add, and

    lw, sw

    Bne, J

    11
    [$t3]

    [$t2]

    [$t1]

    12
    [$t3]
    [$t3]

    [$t1]
    [$t2]
    [$t2]

    13
    010

    [$t3]

    Add result
    [$t2]

    14
    [$t1] Add result

    [result]

    15
    [$t1]
    [result]
    Add result

    =1

    16
    16 bits Offset
    Base
    Lw $t1, 0($t2)

    16 bits Offset
    Base
    Sw $t1, 0($t2)

    17
    16 bits Offset
    Base
    Lw $t1, 0($t2)

    16 bits Offset
    Base
    Sw $t1, 0($t2)

    If [$t2] = 0000 0008H then;


    Base [$t2] + 32 bits Offset
    =00000008 + 00000000 H
    =00000008H

    18
    16 bits Offset
    Base Write to register $t1
    Lw $t1, 0($t2)
    =0
    Base [$t2] + 32 bits Offset
    00000008H data
    32 bits Offset

    =1

    19
    16 bits Offset
    Base
    Sw $t1, 0($t2) =1

    Base [$t2] + 32 bits Offset


    00000008H
    32 bits Offset

    Update mem with [$t1]


    =0

    20
    Base
    Lw $t1, 0($t2)

    Base
    Sw $t1, 0($t2)

    Complete the
    datapath for
    Load & Store
    instructions.

    21
    The datapath for Load & Store instructions with fetch:
    Lw $t1, 0($t2)
    Sw $t1, 0($t2)

    Base 010
    =1 for sw
    [$t2]
    [$t2]

    [$t1]

    =1
    Sw $t1, 0($t2)

    16 bits Offset (0) 32 bits Offset (0) =1 for lw

    Lw $t1, 0($t2) 22
    LESSON 7 (S2)
    Datapath & Control.

    Source:
    https://sites.google.com/site/neuro11school/lect
    23
    Lw $t1, 0($t2) Sw $t1, 0($t2)

    24
    From Reg mem
    0

    Sign ext
    1
    Control o or 1

    At the lower input of ALU

    0
    m
    u
    x
    1

    25
    Lw/Sw & Add

    From Data mem


    0

    ALU
    1
    Control o or 1

    At the input of write data of reg mem

    0
    m
    u
    x
    1

    26
    MIPS Program
    Inst. Addr. instruction
    1000 Add $t0,…
    1004 Lw $t1, …
    1008 Sw $t1, …

    27
    We have developed
    MIPS Program datapath and controls
    Inst. Addr. instruction for R type/ Memory
    1000 Add $t0,… Data transfer
    1004 Lw $t1, … instructions in last class.
    1008 Sw $t1, …

    Today we will
    look into Branch
    Inst. Addr. instruction
    instructions
    1000 Add $t0,…
    1004 Lw $t1, …
    1008 Sw $t1, …
    ….
    1012 Beq $t1, $t2, 0

    28
    # If [$t1] = [$t2] then branch out

    29
    beq $t1, $t2, 16 bits offset # If [$t1] = [$t2] the branch to a Target location in memory based on
    given offset.

    $t1, $t2

    If [$t1] = [$t2] then sub result =0


    Hence ALU zero output =1

    beq $t1, $t2, 1


    Say, 16 bits Offset = 0001H
    32 bits Offset = 0000 0001H

    32 bits Offset = 0000 0100H

    Target address = 0000 0000 0000 1000H

    30
    beq $t1, $t2, 1
    bne $t1, $t2, 1
    J1
    Word 0000 1000H
    displacement

    0000 0100H

    110 (sub) 12
    √8
    [$t1] [$t1] 4
    0 PC
    [$t2]
    =1 when equal (beq)
    [$t2] =0 when not equal (bne)
    0001H
    If [$t1] = [$t2] then sub result =0
    Hence ALU zero output =1
    0000 0001H

    31
    32
    33
    beq $t1, $t2, 1 ; Branch
    PC+4
    add $t1, $t2, $t3 ; R type

    Plus branch

    0
    x
    x x
    x

    34
    beq $t1, $t2, 1 ; 1 cycle
    add $t1, $t2, $t3 ; 1 cycle
    addi $t1, $t2, 1 ; 1 cycle
    lw $t1, 16($t3) ; 1 cycle

    CPI=1
    1 cycle for 1 inst.

    Executing one instruction at a time within one 35

    cycle. CPI=1
    36
    37
    38
    END OF LESSON 7

    39

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