INTEGRATED CIRCUITS

DATA SHEET

TDA1517ATW
8 W BTL or 2 × 4 W SE power
amplifier
Product specification 2001 Apr 17
Supersedes data of 2001 Feb 14
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

FEATURES • Electrostatic discharge protection

• Requires very few external components • Thermal protection
• Flexibility in use: mono Bridge-Tied Load (BTL) and • Reverse polarity safe
stereo Single-Ended (SE); it should be noted that in • Capable of handling high energy on outputs (VP = 0 V)
stereo applications the outputs of both amplifiers are in
• No switch-on/switch-off plop
opposite phase
• Low thermal resistance.
• High output power
• Low offset voltage at output (important for BTL)
GENERAL DESCRIPTION
• Fixed gain
The TDA1517ATW is an integrated class-AB output
• Good ripple rejection
amplifier contained in a plastic heatsink thin shrink small
• Mode select switch (operating, mute and standby) outline package (HTSSOP20). The device is primarily
• AC and DC short-circuit safe to ground and VP developed for multimedia applications.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VP supply voltage 6 12 18 V
IORM repetitive peak output current − − 2.5 A
Iq(tot) total quiescent current − 40 80 mA
Istb standby current − 0.1 100 μA
SE application
Po output power THD = 10%; RL = 4 Ω − 4 − W
SVRR supply voltage ripple rejection RS = 0 Ω 46 − − dB
αcs channel separation RS = 10 kΩ 40 55 − dB
Vn(o) noise output voltage RS = 0 Ω − 50 − μV
⎪Zi⎪ input impedance 50 − − kΩ
BTL application
Po output power THD = 10%; RL = 8 Ω − 8 − W
SVRR supply voltage ripple rejection RS = 0 Ω 50 − − dB
⎪ΔVOO⎪ output offset voltage − − 150 mV
Vn(o)(offset) noise output offset voltage RS = 0 Ω − 70 − μV
⎪Zi⎪ input impedance 25 − − kΩ

ORDERING INFORMATION

TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
TDA1517ATW HTSSOP20 plastic thermal enhanced thin shrink small outline package; SOT527-1
20 leads; body width 4.4 mm; exposed die pad

2001 Apr 17 2
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

BLOCK DIAGRAM

handbook, full pagewidth VP1 VP2

15 16

non-inverting 3 mute switch Cm

input 1 +
60 8
kΩ − OUT1a

VA
+ 9
2 OUT1b
kΩ −

18 kΩ power stage

VP
TDA1517ATW
17
standby MODE
switch 1
2
VA 6
mute 7 not
switch 14 connected
15 kΩ 19
20
x1 +
+ standby
5 −
SVRR 15 kΩ reference
voltage
mute
reference
voltage

18 kΩ

2 −
12
kΩ OUT2a
+
VA
inverting 18
input 2 13
− OUT2b
60
kΩ +
Cm
mute switch
input power stage
reference
voltage

4 10 11 MGU303

SGND PGND1 PGND2

Fig.1 Block diagram.

2001 Apr 17 3
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

PINNING

SYMBOL PIN DESCRIPTION

n.c. 1 not connected
n.c. 2 not connected
handbook, halfpage
IN1+ 3 non-inverting input 1 n.c. 1 20 n.c.
SGND 4 signal ground
n.c. 2 19 n.c.
SVRR 5 supply voltage ripple rejection
IN1+ 3 18 IN2−
n.c. 6 not connected
SGND 4 17 MODE
n.c. 7 not connected
OUT1a 8 output 1a SVRR 5 16 VP2
TDA1517ATW
OUT1b 9 output 1b n.c. 6 15 VP1

PGND1 10 power ground 1 n.c. 7 14 n.c.

PGND2 11 power ground 2 OUT1a 8 13 OUT2b
OUT2a 12 output 2a
OUT1b 9 12 OUT2a
OUT2b 13 output 2b
PGND1 10 11 PGND2
n.c. 14 not connected
MGU302
VP1 15 supply voltage 1
VP2 16 supply voltage 2
MODE 17 mode select switch
IN2− 18 inverting input 2
n.c. 19 not connected Fig.2 Pin configuration.
n.c. 20 not connected

FUNCTIONAL DESCRIPTION
The TDA1517ATW contains two identical amplifiers with differential input stages. This device can be used for Bridge-Tied
Load (BTL) or Single-Ended (SE) applications. The gain of each amplifier is fixed at 20 dB. A special feature of this
device is the mode select switch. Since this pin has a very low input current (<40 μA), a low cost supply switch can be
used. With this switch the TDA1517ATW can be switched into three modes:
• Standby: low supply current
• Mute: input signal suppressed
• Operating: normal on condition.

2001 Apr 17 4
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT.
VP supply voltage − 18 V
VPSC AC and DC short-circuit-safe voltage − 18 V
Vrp reverse polarity voltage − 6 V
ERGo energy handling capability at outputs VP = 0 V − 200 mJ
IOSM non-repetitive peak output current − 4 A
IORM repetitive peak output current − 2.5 A
Ptot total power dissipation − 5 W
Tvj virtual junction temperature − 150 °C
Tstg storage temperature −55 +150 °C
Tamb ambient temperature −40 +85 °C

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

tbf − −

DC CHARACTERISTICS
VP = 12 V; Tamb = 25 °C; measured in Fig.3; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply
VP supply voltage note 1 6.0 12 18 V
Iq quiescent current RL = ∞ − 40 80 mA
Operating condition
VMODE(oper) mode switch voltage level 8.5 − VP V
IMODE(oper) mode switch current VMODE = 12 V − 15 40 μA
VO DC output voltage − 5.7 − V
⎪ΔVOO⎪ DC output offset voltage − − 150 mV
Mute condition
VMODE(mute) mode switch voltage level 3.3 − 6.4 V
VO DC output voltage − 5.7 − V
⎪ΔVOO⎪ DC output offset voltage − − 150 mV
Standby condition
VMODE(stb) mode switch voltage level 0 − 2 V
Istb standby current − 0.1 100 μA

Note
1. The circuit is DC adjusted at VP = 6 to 18 V and AC operating at VP = 8.5 to 18 V.

2001 Apr 17 5
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

AC CHARACTERISTICS
VP = 12 V; f = 1 kHz; Tamb = 25 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

SE application; note 1
Po output power note 2
THD = 1% 2.5 3.3 − W
THD = 10% 3 4 − W
THD total harmonic distortion Po = 1 W − 0.1 − %
fro(L) low frequency roll-off −1 dB; note 3 − 25 − Hz
fro(H) high frequency roll off −1 dB 20 − − kHz
GV voltage gain 19 20 21 dB
⎪ΔGV⎪ channel balance − − 1 dB
SVRR supply voltage ripple rejection note 4
on 46 − − dB
mute 46 − − dB
standby 80 − − dB
⎪Zi⎪ input impedance 50 60 75 kΩ
Vn(o)(rms) noise output voltage (RMS value) note 5
on; RS = 0 Ω − 50 − μV
on; RS = 10 kΩ − 70 100 μV
mute; note 6 − 50 − μV
αcs channel separation RS = 10 kΩ 40 55 − dB
Vo(mote) output voltage in mute note 7 − − 2 mV
BTL application; note 8
PO output power note 2
THD = 1% 5 6.6 − W
THD = 10% 6.5 8.0 − W
THD total harmonic distortion Po = 1 W − 0.03 − %
fro(L) low frequency roll-off −1 dB; note 3 − 25 − Hz
fro(H) high frequency roll off −1 dB 20 − − kHz
GV voltage gain 25 26 27 dB
SVRR supply voltage ripple rejection note 4
on 50 − − dB
mute 50 − − dB
standby 80 − − dB
⎪Zi⎪ input impedance 25 30 38 kΩ
Vn(o)(rms) noise output voltage (RMS value) note 5
on; RS = 0 Ω − 70 − μV
on; RS = 10 kΩ − 100 200 μV
mute; note 6 − 60 − μV
Vo(mute) output voltage in mute note 7 − − 2 mV

2001 Apr 17 6
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

Notes to the characteristics

1. RL = 4 Ω, measured in Fig.4.
2. Output power is measured directly at the output pins of the IC.
3. Frequency response externally fixed.
4. Vripple = Vripple(max) = 2 V (p-p); RS = 0 Ω.
5. Noise voltage measured in a bandwidth of 20 Hz to 20 kHz.
6. Noise output voltage independent of RS.
7. Vi = Vi(max) = 1 V (RMS).
8. RL = 8 Ω, measured in Fig.3.

APPLICATION INFORMATION

handbook, full pagewidth VCC

100 1000
nF μF
15 16
TDA1517ATW
3
8
Ri +OUT
A
60 kΩ 9

470 nF
RL
+IN1
8Ω
12
VCC Ri −OUT
B
60 kΩ 13
18
10 kΩ
MODE 17 STANDBY/
MUTE LOGIC
VCC
SHORT CIRCUIT
8.2 15 kΩ AND
μc1 kΩ 5 TEMPERATURE
MICRO- PROTECTION
CONTROLLER
input
μc2 15 kΩ reference
voltage
μc1 μc2
On 0 0 4 10 11
Mute 0 1
Standby 1 0
MGU304
SGND PGND

Fig.3 BTL application block diagram.

2001 Apr 17 7
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

handbook, full pagewidth VCC

100 1000
nF μF
15 16
TDA1517ATW
3
220 nF 8 1000 μF
IN1+ Ri
A
60 kΩ 9 +OUT RL
4Ω
220 nF
18
IN2−
12 1000 μF
VCC Ri
B
60 kΩ 13 −OUT RL
10 kΩ 4Ω
MODE 17 STANDBY/
MUTE LOGIC
VCC
SHORT CIRCUIT
8.2 15 kΩ AND
μc1 kΩ 5 TEMPERATURE
MICRO- PROTECTION
CONTROLLER
100 input
μc2 15 kΩ
μF reference
voltage
μc1 μc2
On 0 0 4 10 11
Mute 0 1
Standby 1 0
MGU305
SGND PGND

Fig.4 SE application block diagram.

Test conditions Proper supply bypassing is critical for low noise

performance and high power supply rejection. The
Tamb = 25 °C; unless otherwise specified: VP = 12 V, BTL
respective capacitor locations should be as close as
application, f = 1 kHz, RL = 8 Ω, fixed gain = 26 dB, audio
possible to the device and grounded to the power ground.
band-pass: 22 Hz to 22 kHz. In the figures as a function of
Decoupling the power supply also prevents unwanted
frequency a band-pass of 10 Hz to 80 kHz was applied.
oscillations. For suppressing higher frequency transients
The BTL application block diagram is shown in Fig.3. The (spikes) on the supply line a capacitor with low ESR
PCB layout [which accommodates both the mono (BTL) (typical 0.1 μF) has to be placed as close as possible to the
and stereo (single-ended) application] is shown in Fig.6. device. For suppressing lower frequency noise and ripple
signals, a large electrolytic capacitor (e.g. 1000 μF or
Printed-Circuit Board (PCB) layout and grounding greater) must be placed close to the IC.
For high system performance levels certain grounding In single-ended (stereo) application a bypass capacitor
techniques are imperative. The input reference grounds connected to pin SVR reduces the noise and ripple on the
have to be tied to their respective source grounds and midrail voltage. For good THD and noise performance a
must have separate traces from the power ground traces; low ESR capacitor is recommended.
this will separate the large (output) signal currents from
interfering with the small AC input signals. The small signal Input configuration
ground traces should be located physically as far as
It should be noted that the DC level of the input pins is
possible from the power ground traces. Supply and output
approximately 2.1 V; a coupling capacitor is therefore
traces should be as wide as possible for delivering
necessary.
maximum output power.

2001 Apr 17 8
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

The formula for the cut-off frequency at the input is as Average listening level without any distortion yields:
1 P tot 5
follows: f IC = ------------------------------ P ALL = ----------------
- = --------------- = 315 mW
2 × π × Ri Ci factor 15.85

1 The power dissipation can be derived from Fig.11 for 0 dB

thus f IC = ------------------------------------------------------------------------------ = 11 Hz
–3 –9 and 12 dB headroom.
2 × π × 30 × 10 × 470 × 10

As can be seen it is not necessary to use high capacitor Table 1 Power rating
values for the input; so the delay during switch-on, which
POWER
is necessary for charging the input capacitors, can be RATING HEADROOM
DISSIPATION
minimized. This results in a good low frequency response
and good switch-on behaviour. Po = 5 W 0 dB 3.5 W
(THD = 0.1%) 12 dB 2.0 W
In stereo applications (single-ended) coupling capacitors
on both input and output are necessary. It should be noted
that the outputs of both amplifiers are in opposite phase. Thus for the average listening level (music power) a power
dissipation of 2.0 W can be used for the thermal PCB
Built-in protection circuits calculation; see Section “Thermal behaviour (PCB design
considerations)”.
The IC contains two types of protection circuits:
• Short-circuits the outputs to ground, the supply to Mode pin
ground and across the load: short-circuit is detected and
For the 3 functional modes: standby, mute and operate,
controlled by a SOAR protection circuit
the MODE pin can be driven by a 3-state logic output
• Thermal shut-down protection: the junction temperature stage, e.g. a microcontroller with some extra components
is measured by a temperature sensor. Thermal foldback for DC-level shifting; see Fig.10 for the respective
is activated at a junction temperature of >150 °C. DC levels.
• Standby mode is activated by a low DC level between
Output power
0 and 2 V. The power consumption of the IC will be
The output power as a function of supply voltage has been reduced to <0.12 mW.
measured on the output pins and at THD = 10%. The • Mute mode is activated by a DC level between
maximum output power is limited by the maximum 3.3 and 6.4 V. The outputs of the amplifier will be muted
allowable power dissipation and the maximum available (no audio output); however the amplifier is DC biased
output current, 2.5 A repetitive peak current. and the DC level of the output pins stays at half the
supply voltage. The input coupling capacitors are
Supply voltage ripple rejection charged when in mute mode to avoid pop-noise.
The SVRR has been measured without an electrolytic • The IC will be in the operating condition when the
capacitor on pin 5 and at a bandwidth of 10 Hz to 80 kHz. voltage at pin MODE is between 8.5 V and VCC.
The curves for operating and mute condition (respectively)
were measured with Rsource = 0 Ω. Only in single-ended Switch-on/switch-off
applications is an electrolytic capacitor (e.g. 100 μF) on
pin 5 necessary to improve the SVRR behaviour. To avoid audible plops during switch-on and switch-off of
the supply voltage, the MODE pin has to be set in standby
Headroom condition (VCC level) before the voltage is applied
(switch-on) or removed (switch-off). The input and SVRR
A typical music CD requires at least 12 dB (is factor 15.85) capacitors are smoothly charged during mute mode.
dynamic headroom (compared with the average power
output) for passing the loudest portions without distortion. The turn-on and turn-off time can be influenced by an
The following calculation can be made for this application RC-circuit connected to the MODE pin. Switching the
at VP = 12 V and RL = 8 Ω: Po at THD = 0.1% is device or the MODE pin rapidly on and off may cause ‘click
and pop’ noise. This can be prevented by proper timing on
approximately 5 W (see Fig.7).
the MODE pin. Further improvement in the BTL application
can be obtained by connecting an electrolytic capacitor
(e.g. 100 μF) between the SVRR pin and signal ground.

2001 Apr 17 9
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

Thermal behaviour (PCB design considerations) The thermal vias (0.3 mm ∅) in the ‘thermal land’ should
not use web construction techniques, because those will
The typical thermal resistance [Rth(j-a)] of the IC in the
have high thermal resistance; continuous connection
HTSSOP20 package is 37 K/W if the IC is soldered on a
completely around the via-hole is recommended.
printed-circuit board with double sided 35 μm copper with
a minimum area of approximately 30 cm2. The actual For a maximum ambient temperature of 60 °C the
usable thermal resistance depends strongly on the following calculation can be made: for the application at
mounting method of the device on the printed-circuit VP = 12 V and RL = 8 Ω the (ALL-) music power
board, the soldering method and the area and thickness of dissipation approximately 2.0 W;
the copper on the printed-circuit board. Tj(max) = Tamb + P × Rth(j-a) = 60 °C + 2.0 × 37 = 134 °C.
The bottom ‘heat-spreader’ of the IC has to be soldered Note: the above calculation holds for application at
efficiently on the ‘thermal land’ of the copper area of the ‘average listening level’ music output signals. Applying (or
printed-circuit board using the re-flow solder technique. testing) with sine wave signals will produce approximately
twice the music power dissipation; at worst case condition
A number of thermal vias in the ‘thermal land’ provide a
this can activate the maximum temperature protection.
thermal path to the opposite copper site of the
printed-circuit board. The size of the surface layers should
be as large as needed to dissipate the heat.

60
handbook, full pagewidth
K/W
50 ON-BOARD-COOLING
COPPER DESIGN

40 CU-LAYER 1

L
Rth(j-a)
30 L

20
Rth(j-p) CU-LAYER 2-4

10

0
0 1 2 3 4
number of 35 μm copper layers MGU306

Rth(j-p) curve is given for practical calculation purpose.

L = 30 mm plus vias

Fig.5 Thermal resistance of the HTSSOP20 mounted on printed-circuit board.

2001 Apr 17 10
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

handbook, full pagewidth

top view top view

bottom copper layout top copper layout

+VP

TDA
1517ATW
1000 μF
25 V
100 nF
220 nF

IN2 IN1

Std By
On 100 μF/16 V

1000 μF
16 V
sept −2000
− OUT2 + OUT1
MGU312

top view
component layout

For BTL applications the two 1000 μF/16 V capacitors must be replaced by 0 Ω jumpers.

Fig.6 Printed-circuit board layout for BTL and SE application.

2001 Apr 17 11
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

Typical performance characteristics for BTL

application at VP = 12 V and RL = 8 Ω

MGU307 MGU308
10 10
handbook, halfpage handbook, halfpage
THD THD
(%) (%)

1 1

Po = 1 W
10−1 10−1

10−2 10−2
10−2 10−1 1 10 10−2 10−1 1 10 102
Po (W) f (kHz)

Fig.7 THD as a function of Po. Fig.8 THD as a function of frequency.

MGU309 MGU310
0 10
handbook, halfpage handbook, halfpage
Vo
SVRR (V)
(dB)
1
−20

10−1

−40
10−2

−60
10−3

mute

−80 10−4
10−2 10−1 1 10 102 0 2 4 6 8 10 12
f (kHz) VMODE (V)

Fig.9 SVRR as a function of frequency. Fig.10 Vo as a function of VMODE.

2001 Apr 17 12
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

MGU311 MGU323
6 12
handbook, halfpage handbook, halfpage
P Po
(W) (W)
5 10

4 VP = 12 V 8
RL = 8 Ω
RL = 4 Ω 8Ω 16 Ω
3 6

VP = 15 V
2 4
RL = 16 Ω

1 2

0 0
0 2 4 6 8 10 6 8 10 12 14 16 18
Po (W) VP (V)

Fig.11 Power dissipation as a function of Po. Fig.12 Po as a function of VP.

2001 Apr 17 13
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

PACKAGE OUTLINE
HTSSOP20: plastic thermal enhanced thin shrink small outline package; 20 leads;
body width 4.4 mm; exposed die pad SOT527-1

D E A
X

y exposed die pad side HE v M A

Z Dh

20 11

A2 (A 3)
Eh A
A1
pin 1 index

θ
Lp
L
1 10
detail X
w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D(1) Dh E(2) Eh e HE L Lp v w y Z(1) θ
max.
o
0.15 0.95 0.30 0.20 6.6 4.3 4.5 3.1 6.6 0.75 0.5 8
mm 1.1 0.25 0.65 1 0.2 0.13 0.1 o
0.05 0.80 0.19 0.09 6.4 4.1 4.3 2.9 6.2 0.50 0.2 0

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

03-04-07
SOT527-1 MO-153
05-11-02

2001 Apr 17 14
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

SOLDERING • Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a
Introduction to soldering surface mount packages
smooth laminar wave.
This text gives a very brief insight to a complex technology. • For packages with leads on two sides and a pitch (e):
A more in-depth account of soldering ICs can be found in
– larger than or equal to 1.27 mm, the footprint
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011). longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
– smaller than 1.27 mm, the footprint longitudinal axis
mount IC packages. Wave soldering can still be used for
must be parallel to the transport direction of the
certain surface mount ICs, but it is not suitable for fine pitch printed-circuit board.
SMDs. In these situations reflow soldering is
recommended. The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering • For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
Reflow soldering requires solder paste (a suspension of
printed-circuit board. The footprint must incorporate
fine solder particles, flux and binding agent) to be applied
solder thieves downstream and at the side corners.
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement. During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
Several methods exist for reflowing; for example,
applied by screen printing, pin transfer or syringe
convection or convection/infrared heating in a conveyor
dispensing. The package can be soldered after the
type oven. Throughput times (preheating, soldering and
adhesive is cured.
cooling) vary between 100 and 200 seconds depending
on heating method. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
Typical reflow peak temperatures range from
of corrosive residues in most applications.
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
Manual soldering
thick/large packages, and below 235 °C for small/thin
packages. Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
Wave soldering less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
Conventional single wave soldering is not recommended
300 °C.
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and When using a dedicated tool, all other leads can be
non-wetting can present major problems. soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:

2001 Apr 17 15
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

Suitability of surface mount IC packages for wave and reflow soldering methods

SOLDERING METHOD
PACKAGE
WAVE REFLOW(1)
BGA, HBGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS not suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable

Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2001 Apr 17 16
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

DATA SHEET STATUS

DOCUMENT PRODUCT
DEFINITION
STATUS(1) STATUS(2)
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.

Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.

DISCLAIMERS property or environmental damage. NXP Semiconductors

accepts no liability for inclusion and/or use of NXP
Limited warranty and liability ⎯ Information in this
Semiconductors products in such equipment or
document is believed to be accurate and reliable.
applications and therefore such inclusion and/or use is at
However, NXP Semiconductors does not give any
the customer’s own risk.
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and Applications ⎯ Applications that are described herein for
shall have no liability for the consequences of use of such any of these products are for illustrative purposes only.
information. NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
In no event shall NXP Semiconductors be liable for any
specified use without further testing or modification.
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost Customers are responsible for the design and operation of
savings, business interruption, costs related to the their applications and products using NXP
removal or replacement of any products or rework Semiconductors products, and NXP Semiconductors
charges) whether or not such damages are based on tort accepts no liability for any assistance with applications or
(including negligence), warranty, breach of contract or any customer product design. It is customer’s sole
other legal theory. responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
Notwithstanding any damages that customer might incur
customer’s applications and products planned, as well as
for any reason whatsoever, NXP Semiconductors’
for the planned application and use of customer’s third
aggregate and cumulative liability towards customer for
party customer(s). Customers should provide appropriate
the products described herein shall be limited in
design and operating safeguards to minimize the risks
accordance with the Terms and conditions of commercial
associated with their applications and products.
sale of NXP Semiconductors.
NXP Semiconductors does not accept any liability related
Right to make changes ⎯ NXP Semiconductors
to any default, damage, costs or problem which is based
reserves the right to make changes to information
on any weakness or default in the customer’s applications
published in this document, including without limitation
or products, or the application or use by customer’s third
specifications and product descriptions, at any time and
party customer(s). Customer is responsible for doing all
without notice. This document supersedes and replaces all
necessary testing for the customer’s applications and
information supplied prior to the publication hereof.
products using NXP Semiconductors products in order to
Suitability for use ⎯ NXP Semiconductors products are avoid a default of the applications and the products or of
not designed, authorized or warranted to be suitable for the application or use by customer’s third party
use in life support, life-critical or safety-critical systems or customer(s). NXP does not accept any liability in this
equipment, nor in applications where failure or malfunction respect.
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe

2001 Apr 17 17
NXP Semiconductors Product specification

8 W BTL or 2 × 4 W SE power amplifier TDA1517ATW

Limiting values ⎯ Stress above one or more limiting Quick reference data ⎯ The Quick reference data is an
values (as defined in the Absolute Maximum Ratings extract of the product data given in the Limiting values and
System of IEC 60134) will cause permanent damage to Characteristics sections of this document, and as such is
the device. Limiting values are stress ratings only and not complete, exhaustive or legally binding.
(proper) operation of the device at these or any other
Non-automotive qualified products ⎯ Unless this data
conditions above those given in the Recommended
sheet expressly states that this specific NXP
operating conditions section (if present) or the
Semiconductors product is automotive qualified, the
Characteristics sections of this document is not warranted.
product is not suitable for automotive use. It is neither
Constant or repeated exposure to limiting values will
qualified nor tested in accordance with automotive testing
permanently and irreversibly affect the quality and
or application requirements. NXP Semiconductors accepts
reliability of the device.
no liability for inclusion and/or use of non-automotive
Terms and conditions of commercial sale ⎯ NXP qualified products in automotive equipment or
Semiconductors products are sold subject to the general applications.
terms and conditions of commercial sale, as published at
In the event that customer uses the product for design-in
http://www.nxp.com/profile/terms, unless otherwise
and use in automotive applications to automotive
agreed in a valid written individual agreement. In case an
specifications and standards, customer (a) shall use the
individual agreement is concluded only the terms and
product without NXP Semiconductors’ warranty of the
conditions of the respective agreement shall apply. NXP
product for such automotive applications, use and
Semiconductors hereby expressly objects to applying the
specifications, and (b) whenever customer uses the
customer’s general terms and conditions with regard to the
product for automotive applications beyond NXP
purchase of NXP Semiconductors products by customer.
Semiconductors’ specifications such use shall be solely at
No offer to sell or license ⎯ Nothing in this document customer’s own risk, and (c) customer fully indemnifies
may be interpreted or construed as an offer to sell products NXP Semiconductors for any liability, damages or failed
that is open for acceptance or the grant, conveyance or product claims resulting from customer design and use of
implication of any license under any copyrights, patents or the product for automotive applications beyond NXP
other industrial or intellectual property rights. Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
Export control ⎯ This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.

2001 Apr 17 18
 NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise

Customer notification

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version. The Ordering information was modified accordingly.

Contact information

For additional information please visit: http://www.nxp.com

For sales offices addresses send e-mail to: [email protected]

© NXP B.V. 2010

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands 753503/02/pp19 Date of release: 2001 Apr 17 Document order number: 9397 750 08264