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    1973 National Linear Applications

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    antonio silva
    This document provides an index of application notes from National Semiconductor organized by numerical order. It includes a preface describing the purpose and organization of the handbook. The index lists over 75 application notes covering various integrated circuit applications.

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    © All Rights Reserved
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    1973 National Linear Applications

    Uploaded by

    antonio silva
    33 views435 pages
    This document provides an index of application notes from National Semiconductor organized by numerical order. It includes a preface describing the purpose and organization of the handbook. The index lists over 75 application notes covering various integrated circuit applications.

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    1973_National_Linear_Applications

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    This document provides an index of application notes from National Semiconductor organized by numerical order. It includes a preface describing the purpose and organization of the handbook. The index lists over 75 application notes covering various integrated circuit applications.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    33 views435 pages

    1973 National Linear Applications

    Uploaded by

    antonio silva
    This document provides an index of application notes from National Semiconductor organized by numerical order. It includes a preface describing the purpose and organization of the handbook. The index lists over 75 application notes covering various integrated circuit applications.

    Copyright:

    © All Rights Reserved
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    National

    PREFACE The purpose of this handbook is to provide a


    fully indexed and cross-referenced collection of linear in-
    tegrated circuit applications using both monolithic and
    hybrid circuits from National Semiconductor.
    Individual application notes are normally written to ex-
    plain the operation and use of one particular- device or to
    detail various methods of accomplishing a given function.
    The organization of this handbook takes advantage of this
    innate coherence by keeping each application note intact,
    arranging them in numerical order, and providing a de-
    tailed Subject Index composed of approximately 1200 ref-
    erences to the main body of the text. This Subject Index
    provides the key to efficient access to the applications ex-
    perience accumulated over the last five years by National
    Semiconductor.

    $2.50
    APPLICATION LITERATURE NUMERICAL LIST

    APPLICATION NOTES DATE

    AN-l A Versatile Monolithic Voltage Regulator . . . . . . . . . . . . . . . . . . . . . .. . 11/67


    AN-2 Designing Switching Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/69
    AN-3 Drift Compensation Techniques for Integrated DC Amplifiers .. . . . . . . . . . . 11/67
    AN-4 Monolithic Op Amp - The Universal Linear Component . . . . . . . . . . . . 4/68
    AN-5 A Fast Integrated Voltage Follower with Low Input Current . . . . . . . . . . . . 5/68
    AN-6 Tuned Circuit Design Using Monolithic RF/IF Amplifiers . . . . . . . . . . . . . . 3/68
    AN-8 New Uses for the LM100 Regulator ____ . . ........ . 6/68
    AN-l0 Low Power Operational NH0001 Amplifier . . . . . . . . . . . 12/68
    AN-13 N H0002 Current Amplifier . . . . . . . . . . . . . . . . . . .. . 9/68
    AN-15 A Complete Monolithic IF Strip for AM/AGC Applications. 8/68
    AN-20 An Appl icatians Gu ide for Op Amps . . . .. . 2/69
    AN-21 Designs for Negative Voltage Regulators . . . . . . . . . 12/68
    AN-23 The LM105 - An Improved Positive Regulator . . . . 1/69
    AI\!-24 A Simplified Test Set for Op Amp Characterization . 6/69
    AN-28 High Speed MOS Commutators . . . . . . . . 1/70
    AN-29 IC Op Amp Beats FETs on Input Current . 12169
    AN-30 Log Converters . . . . . . . . . . 11/69
    AN-31 Op Amp Circuit Collection . . . . . . . 2/70
    AN-32 FET Circuit Applications. . . . . . . . . ........ . 2/70
    AN-33 Analog-Signal Commutation . . . . . . . . . . . . . . . . . 2/70
    AN-34 How to Bias the Monolithic JFET Dual . . . . . . . . . . . . . . . . . . . . . . . 3170
    AN-38 Applications of MOS Analog Switches . . . . . . . . . . . . 5/70
    AN-41 Precision Ie Comparator Runs from +5V Logic Supply . . . . . . . . . . . . . . . . 10/70
    AN-42 Ie Provides On-Card Regulation for Logic Circuits . . . . . . . . . . . . . . . . . . 2/71
    AN-46 The Phase Locked Loop IC as a Comm. System Building Block 6/71
    AN-48 Applications for a New Ultra-High Speed Buffer. . . ...... . 8171
    AN-49 PIN Diode Drivers . . . . . . . . . . . . . . . . . . . ........ . 8/71
    AN-51 A Unique Monolithic AGCISqueich Amplifier . . . . 9171
    AN-53 High Speed Analog Switches . . . . . . . . . . . . . . 9171
    AN-54 A Complete Monolithic AM/FM/SSB I F Strip 4/72
    AN-56 1.2 Volt Reference . . . . . . . . . . . . . . . . . 12/71
    AN-63 New Design Techniques for FET Op Amps . . 3/72
    AN-64 LM381 Low Noise Dual Preamplifier . . . . . . 5172
    AN-69 LM380 Power Audio Amplifier (Note 1) . . . . 12172
    AN-70 LM381A Dual Preamplifier for Ultra-Low Noise Applications . . . . . . . . 8172
    AN-71 Micropower Circuits Using the LM4250 Programmable Op Amp . . . . . . . . . . 7/72
    AN-72 The lM3900 - A New Current-Differencing Quad of ± Input Amplifiers . . . . . . . . . . . . 9/72
    AN-74 LM1391LM239/LM339 - A Quad of Independently Functioning Comparators (Note 1) . . . . 1/73
    AN-75 Applications for a High Speed FET Input Op Amp (Note 1) . . . . . . . . . . . . . . . . . . . . 12/72

    LINEAR BRIEFS

    LB-l Instrumentation Amplifier . . . . . . . . . . . . . . . . . . 3169


    LB-2 Feedforward Compensation Speeds Op Amp . . . . . . 3169
    LB-3 Worst Case Power Dissipation in Linear Regulators 4169
    LB-4 Fast Compensation Extends Power Bandwidth .. . 4169
    LB-5 High Q Notch Filter . . . . . . . . . . . . . . . . . . . 3169
    --' LB-6 Fast Voltage Comparators with Low Input Current 5169
    LB-7 Tracking Voltage Regulators . . . . 8/69
    LB-8 Precision AC/DC Converters . . . . . . . . . . . 8/69
    .... LB-9 Universal Balancing Techniques . . . . . . . . . 8/69
    LB-l0 IC Regulators Simplify Power Supply Design. 1170
    LB-ll The LM110 - An Improved IC Voltage Follower . . . . . 3170
    LB-12 An IC Voltage Comparator for High Impedance Circuitry 1/70
    LB-13 Applications of the LM 173/LM273/LM373 . . . . . . . 11/70
    LB-14 Speed Up the LM108 Feedforward Compensation. 11/70
    LB-15 High Stability RegUlators . . . . . . . . . . 1/71
    LB-16 Easily Tuned Sine Wave Oscillators . . . . . . . 3171
    LB-17 LM118 Op Amp Slews 70Vlltsec . _ . . . . . . 9/71
    LB-18 +5 to -15 Volts DC Converter . . . . . . . . . . 7/72
    LB-19 Predicting Op Amp Slew Rate Limited Response . . . 8/72
    LB-20 A Fully Differential Input Voltage Amplifier (Note 1) 12172

    NOTE 1: Late addition which is not listed in the subject index.

    ii
    DEVICE VERSUS APPLICATION
    LITERATURE CROSS-REFERENCE

    DEVICE APPLICATION DEVICE APPLICATION


    NUMBER LITERATURE NUMBER LITERATURE

    AM1000 . . . . . . • . . . • . . . • • . . • . . . • . AN-53 LMll0 . . . . • • . . . • . • . • . . . • .. AN-31, LB-ll


    DH0035 .. • . . . • . . . . . . . . • . . • . . . . • AN-49 LMlll . . . . . • . . . • • . . • • . AN-41, LB-12, LB·16
    FETS . . • . . . . . . . . . . . . . • AN·32, AN·34, AN-63 LMl13 • . • • . . • • . • . . . . . . . . • . . . . . • AN-56
    LHOOOl (NH0001) . . . . . . . • • . . . • . . . . • AN-l0 LMllB . . . . . • • . • • . • . . . . • . . . . . . . . LB-17
    LH0002 (NH0002) . . . . . . . . . . . . . . . . . . AN-13 LM139 (Note 1) . . . . . . . . . • . . . . . . . . . AN·74
    LHOCJ14 (NH0014) . . . . • . . • . . . . . . . . . . AN-3B LM170 . . . . • . • . . • • . . . • • • . . . . . • • • AN-51
    LH0019 (NH0019) . . . . . . . . • . . . . . . . . . AN-3B LMl71 . . • . • • . . . • • . . . • • • . • • . • . •. AN-6
    LH0022 AN-63 LMl72 . • . • • . . • . . • . . • . • • • . . . . • . . AN-15
    LH0033 AN-4B LM173 . . . . . . . . • . • . • . . • . . . . • AN·54, LB-13
    LH0042 AN·63 LM174 . . . . • . . • . • • . . • . . . • • . . . • • . AN-54
    LH0052 AN·63 LM3BO (Note 1). . . . . . . . . . . . . . . . . . . • AN-69
    LH0062 (Note 1) . . . . . . . . . . . . . . . . • • AN-75 LM3Bl . • • . . • . . . . • • . . . • . • . . . . . • . AN-64
    LH10l . . . • • . . • • . . . . . . • • . • . . . . • . AN-20 LM3B1A • . . . • • • . • • • • • . • • • • • . . • • • AN-70
    LM100 . . . . • . • . . • . . • . AN·l, AN·2, AN·B, LB·3 LM565 . • . • • • • • • . . • • • . . . • . . • . • • • AN-46
    LM10l . . • . . . . • . . .• AN·3, AN·4, AN·20, AN-24 LM703 • • . . . • • • • . • • . . . . . • . . . . • . • . AN·6
    LM101A . . . • AN·30, AN·31, LB·2, LB·4, LB·B, LB-16 LM709 • • . . . • • • • . • • . . . . . • • . . . • . • AN-24
    LM102 . • . . . . . . . • AN·5, AN·31, LB·l, LB-5, LB·6 LM3900 • . • • • • • • . • • . • . . . • • • . . . . . AN-72
    LM104 • . . . • . . . • . . . . AN·21, LB·3, LB·7, LB-l0 LM3900 (Note 1) . . . . . . . . . . . . . . . . . . LB-20
    LM105 . • . . . . . . . . • • • • . . . AN·23, LB·7, LB-l0 LM4250 • . • . • • . • . . • . . . . . . . • . . . . . AN-71
    LM106 . . . . . . • . . • • . . . . . . . . . . . • • . . LB-6 MM450. • . . . • . . . . . . . . . . • . . • . . . . . AN-33
    LM107 . . • . . . • . • . • . . • . . . . . • . . . . . AN·31 MM451 . • . . . • . . • • . • • • . . . . . . . • • . . AN-33
    LM10B • . . • . • . AN-29, AN-30, AN-31, LB-14, LB-15 MM454. . . • • • . • . • • . . . • • . • •• AN·2B, AN-33
    LM109 • . . . • • . . . . • . . . . . . . .. AN-42, LB-15

    NOTE 1: Late addition which is not listed in the subject index.

    SUBJECT INDEX

    AtoO CirCUit deSCription LH0001: AN 10-1


    Converter: LB6-' Circuit description LH0002: AN13-2
    Ladder driver: AN5-7 CirCUit deSCription LH0022: ANS3-3
    ABSOLUTE VALUE AMPLIFIER: AN31·12 Circuit descnptlon LH0033: AN4S-1
    AC AMPLIFIER: ANS·9. AN31·I, AN31·18, AN48·4, AN72·6 Circuit description LH0042: AN63-3
    AC TO DC CONVERTER: AN31·12, LB8 Circuit descriptIOn LHOOS2: AN63-3
    ACTIVE FILTER (See Filter) Circuit description LM10B/LM20S/LM30B: AN29-2,AN29-1B
    AGC Circuit descnption LM11B/LM218/LM318: LB17
    AGe/squelch amplifier: AN51 Circuit deSCription LM3900: AN72-1
    AMI1F AGe: ANIS, ANS4·1 CirCUit deSCription LM4250 micropower programmable
    Circuit deSCription: LM170/ LM2701LM370: AN51·3 amp; AN71-1
    DC: AN72·7 Clamping: AN 10-2, AN31-11, LeS-1
    Element comparison: AN51-' Class A audio: AN72-38
    FET amplifier: AN34-2 Difference: AN20-3, AN29-12, AN31-1, AN31-9,
    Hints: AN51·4 AN31·10, AN63·10, AN72·9
    Methods: AN51-1, AN72·7 Differentlator: AN20-3. AN31-2. AN72-34
    RF cascade amplifier: ANS-3 FET: AN34
    Temperature compensation: AN51·11 FET Input: AN4-3, AN29-1, AN32-9, AN34-3. ANS3
    AM/FM Follower (See Voltage Follower)
    Demodulators and detectors: AN38-7, AN46-11, AN54-3. AN54-4. High current buffer: AN4-3, AN13, AN29-1S, AN31-16.
    AN54·6, ANS4·8, LB13 AN48·1, AN48·4, AN63·1 I
    AM/IF STRIP: AN15, AN54 High input Impedance AN29-14, AN31-1, AN31-11,
    AMMETER: AN71-5, AN71-6 AN31·1a, AN32·1, AN32·7, AN48·4, AN63, AN72·7,LB1·2
    AMPLIFIER
    High voltage_ AN72-37
    AC: AN5·9, AN31·1, AN31-18. AN48-4. AN72-6
    IF: AN6·S, AN1S·2, AN1S·S, ANS4, LB13
    Absolute value: AN31-12
    Input guarding. AN29-16. AN63-4, AN63-5
    Anti-log generator: AN30-3, AN31-20
    Instrumentation AN29-11, AN31-9, AN31-10,
    Audio: AN32-S, AN72-38
    AN31-11, AN63-9. AN71-7, LBl
    Battery powered_ AN71-4, AN71-5
    Bridge: AN2S-12, AN31-11 Instrumentation shield/line driver: AN48-3
    Buffered high current output: AN4-3, AN 13-3 Integrator: AN20-4. AN29-7, AN31-2, AN31-3,
    AN29·15, AN31-16, AN48·1, AN48·4 AN31-13, AN38-4, AN63-7, AN72-34
    Cascode, FET' AN32-2, AN32-S Integrator, J-FET AC coupled: AN32-1
    Cascade, RF: ANS-1, ANS-3, ANS-4, AN32-S Inverting: AN20-1. AN31-1, AN31-4, AN71-4. AN72-6.
    Charge: ANS3-S AN72·7, AN72·37, LB17·2
    Chopper stabilized: AN38-4 Level shifting: AN4-2, AN 13-4, AN32-5. AN41-3. AN48-3

    iii
    SUBJECT INDEX (cont'd)

    line driver: AN 13-4 DH0035 PIN diode driver: AN49-2


    Line receiver: AN72·S LHOOOl Low power op amp: AN10-1
    Logarithmic converter: AN29·12, AN30, AN31-18, AN31·20 LH0002 Current amplifier: AN13-2
    Low power: AN·l0 LH0022 FET input op amp: AN63-3
    Meter: AN63·11. AN71·5 LH0033 Buffer amplifier: AN48-1
    Micropower: AN71 LH0042 FET Input op amp: AN63-3
    Nano-watt: AN71-4 LH0052 FET input op amp: AN63-3
    Noise: AN63-2, AN70 LM100/LM200/LM300 Positive voltage regulator: ANl-2, AN8-l
    Non-inverting amplifier: AN20-2. AN31-1, AN31-4, LM102/LM202/LM302 Voltage follower: AN5-1
    AN63-7, AN72-6, AN72-9, AN72-37 LM104/LM204/LM304 Negative voltage regulator:
    Non-linear: AN4-4, AN31-16 AN21-1, AN21-15
    Norton: AN72-' LM 105/LM205/LM305 Positive voltage regulator:
    Output resistance: AN29-5 AN23-1, AN23-2
    Photocell: AN20-5. AN20-B LM10S/LM208/LM30S Operational amplifier: AN29-2, AN29-18
    Photodiode: AN20-5, AN29-13, AN31-3, AN31-18, LB12-2 LM109/LM209/LM309 Three terminal regulator: AN42-l
    Photoresistor bridge: AN29-12 LM110/LM210/LM310 Voltage follower: LB11
    Phototransistor: ANa-8 LM11l/LM211!LM3ll Voltage comparator: AN41-1, LB12
    Piezolectric transducer: AN29-13, AN31-17 LM113 1.2 Volt reference diode: AN56
    Power: ANS-G, AN72·9 (See Also Buffer, High Current) LM118/LM218/LM318 High slew rate op amp: LB17
    Pulse: ANS-l1, AN13-4 LM170/LM270/LM370 AGC squelch amplifier: AN5l-3
    Rejection, power supply: AN29-6 LMl72 AM-IF strip: AN15-', AN15-4
    Reset stabilized: AN20-7. AN 38-4 LM173/LM273/LM373 IF amplifier/detector: AN54-1. Le13
    RF (See RF Amplifier) LM274 AM/FM/SSB IF video amp/detector: AN54-,
    Sample and hold: AN4-3, AN5-8, AN29-S. AN3l-l2. LM381 Dual preamplifier: AN64-2
    AN32-1, AN32-6, AN32-7, AN4B-3, AN63-7, LM565 Phase locked loop: AN46-5
    AN72-34, LBll-2 LM3900 Quad amplifier: AN72-1
    Single supply: AN72 LM4250 Micropower programmable op amp: AN7l-'
    Solar cell: AN4-5 CLAMP
    Squaring: AN72-33 Operational amplifier: AN 10-2
    Squelch. AGC: AN5l Precision: AN31-1', Le8-l
    Summing: AN20-3. AN3l-1. AN31-l3 Voltage follower input: AN5-5
    Temperature probe: AN3l-17. AN5S-3 CLASS A AUDIO AMPLIFIER, AN72-38
    Transconductance: ANS3-9 CMOS LOGIC VOLTAGE REGULATOR, AN71-7
    Variable gain: AN3l-9. AN3l-l5. AN32-5. LBl-2 COMPARATOR (See Voltage Comparator)
    (See Also AGC) COMPENSATION, DRIFT (See Drift Compensation)
    Zeroing: ANS3-8 COMPENSATION, FREQUENCY (See FrequencyCompensation)
    ANALOG COMMUTATOR (See Analog Switches) COMPENSATION, TEMPERATURE (See Drift Compensation)
    ANALOG DIVIDER, AN4-5, AN30-4, AN31-19 CONVERTER
    ANALOG MULTIPLIER, AN4-5, AN20-B, AN30-4, 100 MH" AN32-3
    AN3l-l5. AN3l-17. AN3l-l9 AC to DC: AN3l-l2, LBB
    ANALOG SIGNAL, DEFINITION, ANS3-1 Analog to digital: LeG-1
    ANALOG SWITCH, ANS-B, AN2B, AN32-4, AN32-B, Current to voltage: AN20-5. AN3l-2, AN3l-1S
    AN32-9, AN32-10, AN32-12, AN33, AN38, AN53 DC to DC: LB18 (See Also Switching Regulator)
    ANALOG TO DIGITAL Digital to analog: AN48-3
    Cony-erter: LBS-l Logarithmic: AN29-12, AN30, AN3l-1S, AN31-20
    Ladder driver: AN5-7 COUNTER, PULSE, AN72-23
    AND GATE, AN72-27 CRYSTAL OSCILLATOR, AN32-2, AN32-8, AN41-4
    ANTI-LOG GENERATOR, AN30-3, AN31-20 CUBE GENERATOR, AN30-3, AN31-19
    AUDIO AMPLIFIER, AN32·5, AN72-38 CURRENT LIMITING
    AUDIO MIXER, AN64-10, AN72-35 Adjustable: AN2l-7
    AUTOMATIC GAIN CONTROL IS•• AGCI External: AN21-9, AN29-1S
    BANDPASS FILTER: AN72-15. L8l'-2 (See Also Notch Filter) Foldback (See Foldback Current Limiting)
    BANDWIDTH, EXTENDED, AN29-S, LB2, LB4, LB14, LB19 Output short circuit: AN10-3, AN72-12
    BANDWIDTH, FULL POWER, LB19-1 Sense voltage reduction: AN21-4, AN2l-7, AN3l-l6, AN32-11
    BATTERY POWERED AMPLIFIERS, AN71-4, AN71-5
    Switchback (See Foldback Current Limiting)
    BI·QUAD FILTER, AN72-17
    Switching regulator: AN2-8. ANS-4, AN2l-12
    BIAS CURRENT COMPENSATION (See Drift Compensation)
    Voltage regulator, positive: AN 1-5
    BIAS CURRENT TEST SET, AN24-2
    BIASING, FET, AN34 CURRENT MIRROR, AN72-2
    BOARD LAYOUT, AN29-16, AN63-4 CURRENT MODE MULTIPLEXING, AN53-5
    BOOTSTRAPPED SHUNT FREQUENCY COMPENSATION, CURRENT MONITOR: AN3l·16, AN32-l1 (See Also
    AN29-16 Current to Voltage Converter)
    BRIDGE AMPLIFIER, AN29-12, AN31-11 CURRENT SINK
    BUFFER HIGH CURRENT, AN4-3, AN13-3, AN29-15, Fixed: AN72-3l
    Precision: AN20-S, AN3l-8, AN32-6. AN63-9
    AN31-16, AN48-1, AN4B-4, AN63-11
    BYPASSING, SUPPLY TERMINAL: AN4-B. LB2-2, LB15-' CURRENT SOURCE
    CAPACITANCE MULTIPLIER, AN29-10, AN31-14, AN31-15 Bilateral: AN29-14, AN31-6
    CAPACITOR Floating: AN8-4
    Bypass: AN4-B. LB2-2, LB15-l Focus control current source: AN8-3
    Compensation: AN29-4 (See Also Frequency Compensation) High current: AN8-4, AN42-6
    Dielectnc polarization: AN29-7 Multiple: AN72-30
    Filter, power supply: AN23-7, LB10-2 Precision: AN20-G, AN3l-S, AN32-12
    Multiplier, capacitance: AN29-10, AN3l-14. AN3l-l5 Switching current regulator: AN8-4
    Switching regulator filter: AN2l-11 CURRENT-TO-VOLTAGE CONVERTER, AN20-5,
    Tantalum bypass: LB1S-l AN31-2, AN31-16
    CASCODE AMPLIFIER, AN6-1, AN6-3, AN6-4, AN32-6, D TO A CONVERTER, AN48-3
    AN 32-9 DC TO AC CONVERTER, LB18
    CHARGE AMPLIFIER, AN63-9 DEMODULATOR
    CHOPPER STABILIZED AMPLIFIER, AN3B-4 AM-FM, AN38-7, AN46-11, AN54-3, AN54-4, AN54-6,
    CIRCUIT DESCRIPTIONS AN54-B, LB13
    AM 1 000 Analog switch series: AN53-2 DSB, AN38-5, AN38-6

    iv
    SUBJECT INDEX (cont'd)

    Frequency shift keying: AN46·9. AN54-7 FREaUENCY COMPENSATION


    IRIG channel: AN46-8 BandWidth, extended: AN29·5, LB2, LB4. LB14, LB19
    Slope detector, FM: AN54-B Bootstrapped shunt: AN29-l6
    SSB: AN54-4, AN54-5, AN54-B, LB13-2 Capacitance, stray: AN4-B, AN31-3
    Synchronous AM detector: AN54-6 Capacitive loads: AN4-8, LB14-1
    Weather satellite picture: AN46-11 Differentiator: AN20-4
    DETECTOR (See Demodulator) Feedforward: LB2, LB14. LB17-2
    DIELECTRIC POLARIZATION, CAPACITOR: AN29-7 Ferrite bead: AN23-S
    DIFFERENCE AMPLIFIER: AN20-3, AN29-12, AN31-1, Hints: AN4-7, AN20-2, AN23·6. AN41-5, LB2, LB4
    AN31-9, AN31-10, AN63-10, AN72-9 Multivlbrator: AN4-'
    DIFFERENCE INTEGRATOR: AN72-34 Oscillation, Involuntary: AN4-B. AN20-2, AN29-5
    DIFFERENTIATOR: AN20-3, AN31-2, AN72-34 FREQUENCY DOUBLER: AN41-4
    DIGITAL SWITCHING CIRCUITS: AN72-26 FREQUENCY RESPONSE: LB191See Also
    DIGITAL TO ANALOG CONVERTER: AN48-3 Frequency Compensation)
    DIODE FREOUENCY SHIFT KEYING DEMODULATOR: AN46-9,
    Catch: AN21-11 AN54-7
    PIN driver' AN49 FULL POWER BANDWIDTH: LB19-1
    Precision: AN31-11, LBB-' GAIN TEST SET: AN24-4
    Protective: AN21·8 GATES, OR AND AND: AN72-26
    Temperature compensated zener diodes: AN54-7 GENERATOR (See Oscillator)
    Zener: ANS6 GUARD DRIVER: AN48-3, AN63-6
    Zenered transistor base-emitter junction: AN71-8 GUARDING AMPLIFIER INPUTS: AN29-16, AN63-4
    DISCRIMINATOR, MULTIPLE APERTURE WINDOW: HIGH PASS ACTIVE FILTER: AN5-10, AN31-16, AN72-14,
    AN31-3 LBll-2
    DIVIDER, ANALOG: AN4-5, AN30-4, AN31-19 IF AMPLIFIER: AN6-5, AN15-2, AN 15-5, AN54-4, LB13
    DOUBLE CONVERSION IF STRIP: AN54-6 INDUCTOR
    DOUBLE ENDED LIMIT DETECTOR: AN31-3 Core, sW1tching regulator: AN21-11
    DOUBLER, FREQUENCY: AN41-4 Ferrite bead: AN23-S
    DRIFT COMPENSATION Simulated: AN3l-15
    AGe gain: AN51-11 INSTRUMENTATION AMPLIFIER: AN29-11, AN31-9, AN31·10,
    Bias current: AN3-', AN10-3, AN20-1, AN29-B. AN31-3 AN31·1" AN63-9, AN71-7,LBl
    Board layout: AN29-16 INTEGRATOR: AN20-4, AN29-7, AN31-2, AN31-3, AN31-13,
    Chopper stabilized amplifier: AN38-4 AN32-1, AN38-4, AN63-7, AN72-34
    Gain, AGe: AN51-11 INTERNAL TIMER: AN31-17
    Gain, transistor: AN56-3 INVERTING AMPLIFIER: AN20-1, AN31-1, AN31-4, AN11-4,
    Guardmg inputs: AN29-16. AN63·5 AN72-6, AN72-7, AN72-37, LB17-2
    Integrator, low drift: AN31-13 ISOLATION, DIGITAL: AN41-3
    Non-linear amplifiers: AN4·4, AN31·16 LAMP DRIVER
    Offset voltage: AN3·3, AN20-1, AN31-4, AN63·3 Ground referenced: AN72-36
    Reset stabilized amplifier: AN20·7 Voltage comparator: AN4-2. AN72-29. LB12-2
    Sample and hold: AN4-4, AN29·7 LARGE SIGNAL RESPONSE: LB19
    Transistor gain: ANS6-3 LEVEL SHIFTING AMPLIFIER: AN4-2, AN13-4, AN32-5,
    Voltage regulator: AN1·lO, ANS·11, AN21-4, AN23·4, AN41-3, AN48-3
    AN42-6, LB15 LIGHT-INTENSITY REGULATOR: AN8-8
    DRIFT, VOLTAGE AND CURRENT: AN29-1 (See Also LIMIT DETECTOR: AN31-3
    Dnft Compensation! LIMITER (Soe Ciampi
    DRIVER (See Amplifier. High Current Buffed LINE DRIVER: AN13-4, AN48-3
    DSB MODULATION-DEMODULATION: AN38-5, AN38-6 LINE RECEIVER AMPLIFIER: AN72-8
    EMITTER COUPLED RF AMPLIFIER: AN6-1, AN6-2 LOGARITHMIC AMPLIFIER: AN29-12, AN30, AN31-18, AN31-20
    FEEDFORWARD COMPENSATION: LB2, LB14, LB17-2 LOW PASS ACTIVE FILTER: AN5-9, AN20-4, AN31-16, AN72-14
    FERRITE BEAD: AN23-6 METER AMPLIFIER: AN63-11, AN71-5
    FET MICROPHONE PREAMPLIFIER: AN51-1
    Amplifier: AN32, AN34 MICROPOWER
    Blasing: AN34 Amplifier: AN71
    Operational amplifier input: AN4-3, AN29·1, AN32·9, Circuit description LM4250 programmable op amp_ AN71-'
    AN34·3, AN63. Voltage comparator· AN71-4
    Switches: AN5-8. AN28. AN32·4. AN32·8. AN32-9. MIXER
    AN32-10, AN32-12, AN33, AN38, AN53 AudiO: AN64-10, AN72-35
    Voltage comparator: AN34-2 Low frequency: AN72-35
    Voltmeter, FET VM: AN32-2, ANS3·11 MODULATION
    FILTER Voltage regulator, switching: ANB-6
    AdJustable Q: AN31-14, L85-2 MODULATOR
    Bandpass: AN72-15, LB11·2 (See Also Filter, Notch) AM/IF: AN51-9
    BI-quad: AN72·17 DSB: AN38-5
    Full wave rectifying and averaging: AN20·8, AN31·12 Pulse width: AN31-5
    High pass active filter: AN5·10, AN3l-16, AN72·l4, SSB, high efficiency: ANS-6
    LB11-2 MDNOSTABLE MUL TlVIBRATORS: AN72-27
    Low pass active filter: AN5-9. AN20-4, AN31·16. MULTIPLEXER (See Analog Switch)
    AN72-14 MULTIPLEXING, DEFINITION: AN53-1
    Notch: AN31-14, AN48-4. LB5. LB1'-2 MULTIPLIER
    Notch, adjustable Q: AN31·14, LB5·2 Analog: AN4-5, AN20-8, AN30-4. AN3l·15. AN31-17, AN31-19
    Power supply: AN23-7, LB10·2 Capacitance: AN29·10, AN31·14. AN3l-15
    SenSitivity functions: AN72-13 Cube generator: AN30-3, AN31-t9
    Tone control: AN32-3, AN32-1', ANS4-10 Resistance: AN29·14
    FLIP-FLOP, TRIGGER: AN72-27 MULTIVIBRATOR: AN4-1, AN24-6, AN31-6, AN41-4, AN71-6,
    FOLDBACK CURRENT LIMITING AN72-19
    Negative voltage regulator: AN21-5. LB3-2 NAB TAPE PLAYBACK PREAMPLIFIER: AN64-4
    POSitive voltage regulator: AN 1-8, AN23-5. LB3·2 NAB TAPE RECORD PREAMPLIFIER: AN64-7
    Power dissipation curve: AN23-6 NEGATIVE AND POSITIVE VOLTAGE REGULATORS (Se.
    Temperature sensitivity: AN23·6 Symmetrical Voltage Regulators)

    v
    SUBJECT INDEX (cont'd)

    NEGATIVE SWITCHING VOLTAGE REGULATORS: AN2·10, POSITIVE ANO NEGATIVE VOLTAGE REGULATORS ISee
    AN21·10, AN21·11, AN21-12, AN21·13 Symmetrical Voltage Regulators)
    NEGATIVE VOLTAGE REFERENCE: AN20·6, AN31·8 POSITIVE VOLTAGE REFERENCE: AN20·6, AN31·2, AN31·8, AN56
    NEGATIVE VOLTAGE REGULATOR POSITIVE VOLTAGE REGULATOR
    Circuit description LM104/LM204, and LM304: AN21-1, AN21-15 Adjustable output LM109: AN42-5
    Drift compensation (See Drift Compensation, Voltage Regulatod Circuit description LM100/LM200/LM300. AN1·2, AN8·1
    Foldback current limiting: AN21-5, lB3-2 CirCUit deSCription LMI 05/LM205/LM305: AN23·1,23-2
    High current: AN21-3, AN21-4, AN21-5, LB1C CirCUit deSCription LM'09/LM209/LM309: AN42·1
    High voltage: AN21-9 CMOS compatible: AN71·7
    Hints: LB10-2, LB15 Current limit: AN1-5. AN72·12
    Line regulation improvement: AN21-7 Drift compensation (See Drift Compensation, Voltage Regulatod
    LM100 as a negative regulator: ANl-9 Efficiency: AN,-8
    Overvoltage protection: AN21-8 Failure mechanisms: AN23-7, LB3
    Power dissipation: AN21-3. AN21-5 Filtering, power supply: AN23·7, LB10-2
    Precision, stable: LB15-2 Fixed output: AN42·5
    Programmable: AN20-11, AN31-7 Foldback current limiting: AN l-B, AN23-5, LB3·2
    Protective diodes: AN21-8 Heat diSSIpation: AN1·S, AN23·3, AN23·6, AN23·7. LB3
    Remote sensing: AN21-4. AN21-9 High current: AN1-7, AN23·4, AN23·5, AN23·6. AN72·1',
    Ripple: AN21-2, AN21-6 LB3, LB10·l
    Shunt regulator: ANS-' High voltage: AN8·B. ANB-9, AN72·"
    Transient response: AN21-2 Hmts: AN23-7, LB3. LB10-2. LB15
    NIXIE DRIVER: AN32-6 Impedance. output: ANl-6
    NOISE, AMPLIFIER AND RESISTOR: AN63·2, AN70 Low voltage: AN56..J
    NON·INVERTING AMPLIFIER: AN20·2, AN31·1, AN31·4, Micropower quiescent power dram: AN7'·7
    AN63·7, AN 72·6, AN72·9, AN72·37 Noise reduction: AN 1-6
    NON·LlNEAR AMPLIFIER: AN4·4, AN31·16 NPN pass transistors: AN8-l0, AN72-11. LB'O·'
    NORTON AMPLIFIER: AN72·1 Power limitations: AN23-3, LB3
    NOTCH FILTER: AN31·14, AN48-4, LB5, LBll·2 PreciSion: AN42-6, LBl5
    OFFSET CURRENT TEST SET: AN24·3 Programmable low power: AN20·'l. AN31-7
    OFFSET VOLTAGE ADJUSTMENT: AN63·3, LB9 Protection: AN23-7. AN72·11
    OFFSET VOLTAGE COMPENSATION (See Drift Compensation) Regulation, load: AN 1-5
    OFFSET VOLTAGE TEST SET: AN24·3 Remote sensing: ANB· 10
    ONE·SHOT: AN72·27 Ripple induced failures: AN23·7, LB10·2
    OPERATIONAL AMPLIFIER TEST SET: AN24 Shunt regulator: ANB-1
    OPERATIONAL AMPLIFIERS: AN4, AN20, AN29, AN3l (See Shutdown: AN8-4
    Also Ampliflersl SWitching regulator (See SWitching Regulator)
    OR GATE: AN72·26 Temperature compensation: AN1-10. ANB-l1. AN42·6. LB15
    OSCILLATION. INVOLUNTARY CSee Frequency Compensation) Transient response: ANl-6
    OSCILLATOR POWER AMPLIFIER (See Buffer. High Current)
    Crystal: AN41-4 PREAMPLIFIER
    Crystal J·FET: AN32-2, AN32-B CirCUit description LM3Bl dual preamplifier: AN64·2
    Modulated RF: AN5l·9 Flatband: AN70·3
    Multivibrator: AN4-1, AN24-6. AN31-6, AN4l-4. AN71-6, Low nOIse: AN70
    AN72·19 Microphone, squelched: AN51·7
    Piezoelectric driver: AN72-37 Phono: AN32·4, AN32-l1. AN64-8
    Programmable "unijunction": AN72-39 Servo. AN4-4, AN31-16
    Pulse output: AN71-6. AN72·20 Stereo: AN64-10, AN64·1'
    Quadrature output: AN31-5. LBt6 Tape playback: AN64·4
    RF J·FET: AN32·2, AN32-8 Tape record: AN64-7
    Sawtooth: AN72·22 VOX: AN51·8
    Sine wave: AN20-9, AN2g·9. AN31·5. AN31·6. AN3'-7, PROGRAMMABLE OP AMP: AN71
    AN32·7, AN32·8, AN51·8, AN72·19, LB16 PROGRAMMABLE "UNIJUNCTION" OSCILLATOR: AN72·39
    Staircase: AN72-23 PROGRAMMABLE VOLTAGE REGULATOR: AN20·11, AN31·7
    Triangle wave: AN20-l0. AN24-6. AN31-6, AN72·21 PULSE AMPLIFIER: AN8·11, AN13·4
    Tunable frequency: ANSI-9. L816 PULSE COUNTER: AN72·23
    Wein bridge: AN20·9, AN31-6, AN31·7, AN32·7, ANS1·B PULSE GENERATOR: AN71·6, AN 72·20
    PEAK DETECTOR: AN4-4, AN31·12, AN51·5, AN51·B, AN 54·4, PULSE REGULATOR: AN8-11
    AN 72-36 PULSE WIDTH MODULATOR: AN31-6
    PHASE COMPARATOR: AN72·25 OUADRATURE OSCILLATOR: AN31·5, LB16
    PHASE LOCKEO LOOP RECEIVER IF STRIP: AN6·5, AN15·2, AN15·5, AN54, LB13
    CirCUit description, LMS65: AN46·5 RECTIFIER, FAST HALF·WAVE: AN31·11, LB8·1
    Damping: AN46·3 RECTIFIER, FULL·WAVE: AN20·8, LB8·2
    Lockmg: AN46-5 REFERENCE VOLTAGE REGULATOR: AN20·6, AN31·2, AN31-8
    Loop filter: AN46·2 RELAY DRIVER: AN72·36
    Multiampltfler: AN72·24, AN72-26 REMOTE SENSING
    NOise performance: AN46-5 High current negative regulator. AN214
    Phase comparator: AN72-25 High negative voltage: AN21·9
    Theory: AN46·1 Line resistance compensation: AN8-'O
    VCO: AN72·24 RESET STABILIZED AMPLIFIER: AN20·7, AN3B·4
    PHASE LOCKED RECEIVER: AN54·7 RESISTANCE MULTIPLICATION: AN29·14
    PHASE SHIFTER: AN32·8 RESISTOR NOISE: AN63·2, AN70·2
    PHONO PREAMPLIFIER: AN32·4, AN32·11, AN64·8 RF AMPLIFIER
    PHOTOCELL AMPLIFIER: AN20·5, AN20·B AM/IF ;trip: AN15, AN54
    PHOTODIODE Biasing: AN6-'
    Amplifier: AN20·5, AN29-13, AN3l-3, AN31-1B, LB12·2 Cascade: AN6-1 , AN6·3, AN6-4, AN32·9
    Level detector: AN41-2 Emitter coupled: AN6-1, AN6-2
    PHOTOMULTIPLIER TUBE SUPPLY: AN8·9 Forward transadmittance: AN6-3
    PHOTORESISTOR AMPLIFIER: AN29·12 Gain: AN6-2
    PHOTOTRANSISTOR AMPLIFIER: AN8·8 IF amplifier: AN6-S. AN15-2. AN1S-5, AN54. LB13
    PIN DIODE DRIVER: AN49 Input impedance: AN6·2. AN6-3
    POLARIZATION, DIELECTRIC: AN29·7 Tuned interstage circuits: AN6-4. La 13

    vi
    SUBJECT INDEX (cont'd)
    RF OSCILLATOR (See Oscillator. RFI TAPE PLAYBACK PREAMPLIFIER: AN64-4
    RIAA PHONO PREAMPLIFIER: AN64-B TAPE RECORD PREAMPLIFIER: AN64-7
    RIPPLE. POWER SUPPLY: AN21-2. AN21-6. AN23-7. LB10-2 TEMPERATURE COMPENSATED ZENER DIODE: ANS6
    RISE TIME, AMPLIFIER: LB19·2 TEMPERATURE COMPENSATION (See Drift Compensation)
    ROOT EXTRACTOR: AN4-6. AN31-1B TEMPERATURE CONTROLLER: ANB·S
    SAMPLE AND HOLD: AN4-3. ANS·B. AN29-6. AN31-12. AN32.1. TEMPERATURE PROBE AMPLIFIER: AN31-17. ANS6-3
    AN32·6. AN32·7. AN48-3, AN63-7, AN72-34, LB11·2 TEMPERATURE PROBE COMPARATOR: AN72-3B
    SAWTOOTH GENERATOR: AN72-22 TEST SET. OPERATIONAL AMPLIFIER: AN24
    SCHMITT TRIGGER: AN32-12. AN72-30 THERMOMETER. ELECTRONIC: AN31-17. ANS6-3
    SENSE VOLTAGE (See Current limiting) THRESHOLD OETECTOR: AN20-10. AN31-3
    SENSITIVITY FUNCTIONS: ANn· 13 TIME DOMAIN MULTIPLEXING: ANS3-1
    SERVO PREAMPLIFIER: AN4·4, AN31·16 TIME, INTERVAL: AN31-17
    SETTLING TIME: LB17·2 TONE CONTROL: AN32-3. AN32-1', ANS4-10
    SHUNT REGULATOR: ANS-1 TRACKING VOLTAGE REGULATOR: LB7 (See Also Symmetrical
    SINE WAVE OSCILLATOR: AN20-9. AN29-9. AN31-S. AN31-6. Voltage Regulators)
    AN31-7, AN32-7. AN32-a. AN51-B, AN72·19. L816 TRANSADMITTANCE. RF AMPLIFIER: AN6-3
    SINE WAVE RESPONSE: LB19 TRANSCONDUCTANCE AMPLIFIER: AN63-9
    SINGLE SUPPLY AMPLIFIER: AN72 TRANSFER FUNCTION TEST SET: AN24-4
    SINGLE SUPPLY OPERATION: AN31-2, AN48-4 TRIANGLE WAVE OSCILLATOR: AN20-10, AN24-6. AN31-6,
    SLEW RATE: ANS-5, LB17, La19 (See Also Frequency AN72-21
    Compensation, Feedforward) TRIGGER FLIP-FLOP: AN72-27
    SLEW RATE LIMITING: LB19 TRIGGER. SCHMITT: AN32-12. AN72-30
    SLOPE DETECTOR, FM: AN54·6 TUNED RF CIRCUITS (See Amplifiers)
    SMALL SIGNAL RESPONSE: LB19 UNITY·GAIN BUFFER: AN20-2. AN63-7
    SOLAR CELL AMPLIFIER: AN4-S VOLTAGE COMPARATOR
    SOUARE ROOT CIRCUIT: AN4-6. AN31-1B A to D converter circuit: LBG-l
    SQUARING AMPLIFIER: AN72-33 AC coupled: LB6-2
    SQUELCH AMPLIFIER. AGC: ANS1 Buffered output: AN29-15
    SQUELCH RELEASE TIMING: ANS1-12 Circuitdescflptlon LM111fLM211/LM311: AN41-1. L812
    SQUELCHED PREAMPLIFIER: ANS1-7 Comparison: LB 12-2
    SSB DTL driver: AN4-2. AN10-2, AN29-15. AN31-3. LB12-2
    Demodulator: AN54-4, AN54-5. AN54-B. LB13-2 Dual limit, high speed: AN48-3
    Modulator: ANS-6 Fast: LB-6
    STAIRCASE GENERATOR: AN72-23. AN72-24 FET: AN34-2
    STEP RESPONSE: LB19-2 High current: AN71-4
    STEREO PREAMPLIFIER: AN64-10. AN64-11 Hints: AN41-5
    SUBTRACTOR (See Difference Amplifier) Lamp driver: AN4-2, AN72-29, LB12-2
    SUMMING AMPLIFIER: AN20-3. AN31-1. AN31-13 Micropower: AN71-4
    SUPERHETERODYNE RECEIVER IF STRIP: AN1S·S MOS driver: AN 10-2, AN41-2, AN41-3, LB12-2
    SUPPLY VOLTAGE SPLITTING: AN31-2 Op amp voltage comparator: AN4-2, AN63-9, AN71-4,
    SWITCH. ANALOG: ANS-8. AN2B. AN32-4. AN32-B. AN32-9. AN72-29
    AN32-10. AN32-12. AN33. AN3B. ANS3 PreCision: AN63-9
    SWITCHBACK CURRENT LIMITING (See Foldback Current TTL driver: AN4-2, AN 10-2, AN29-15, AN31-3, AN41-2,
    Limiting) AN41-3. AN63-9. LB12-2
    Zero crossing: AN31-17, AN41-2. AN41-3, LB6-2, LB12-2
    SWITCHING AND LINEAR REGULATOR COMBINATION:
    AN2-11 VOLTAGE CONTROLLED OSCILLATOR: AN72-24
    SWITCHING CURRENT REGULATOR: ANBA VOLTAGE FOLLOWER
    SWITCHING REGULATOR A to D ladder driver: AN5-7
    Bandwidth, full power: AN5-5
    Capacitor selection: AN21-11 Bias current: AN5-3, AN20-3
    Catch diode selection: AN21-11 Buffer, voltage reference: AN5-7
    Current limiting: AN2-8, ANB-4, AN21-12 Circuit deSCription LH0033: AN48-1
    DC plus to DC minus converter: LS 18
    Circuit description LM102/LM202fLM30~: AN5·'
    DisSipation: AN21-11
    Circuit description LM110fLM210fLM310: LB11
    Driver: AN2-7, AN21-14 Clamping, input: AN5-S
    Efficiency: AN2-5, AN2-6, AN2-7, AN21-1.0 Comparison: LB 11-2
    Frequency of operation: AN2-4, AN2-5, AN2-6, AN2-7 Frequency response: AN5-3
    High negative current: AN2l-1', AN21-12, AN21-13
    Gain: AN5-5
    High positive current: AN1-l', AN2-6, AN8-2
    Hints, operating: AN5-6, AN20-2, AN63-7
    High voltage: AN2-11
    Increased output swing: AN5-5
    Hints: AN21-11 Offset adjustment: AN31-4, LB9-2
    Inductor core selection: AN21-11
    Aesistan"ce. output: AN5-5
    Lme regulation: AN2-6, AN2l-11
    Single supply: AN72-10
    Modulation: ANB-6
    Slew rate: AN5-5, AN63-7
    Negative: AN2-10, AN21-l0, AN2'-", AN21-12, AN21-13
    Source resistance effect: AN5-5
    Overload shutdown: AN8-2, AN21-13
    Transient response: AN5-7
    Overvoltage protection: AN8-3
    Voltage reference: AN20-S, AN31-2, AN31-8, AN56
    Polarity conversion: LB18
    Voltage reference buffer: AN5·7
    Ripple: AN2-4, AN21-11
    VOLTAGE REGULATOR (See Positive. Negative. Dr Switching
    Self-OSCillating: AN2-2, AN21-1O
    Voltage Regulator!
    Shutdown: AN8-2, AN21-13
    VOLTMETER: AN32-2.AN63-11.AN71-6
    Symmetrical: AN2-10
    VOX PREAMPLIFIER: ANS1-B
    Synchronous: AN2-7, AN21-14
    WEIN BRIOGE OSCILLATOR: AN 20-9. AN31-6. AN31-7.
    Theory: AN1-1'.AN2-2. AN21-10. LB18 AN32-7, AN51-8
    SYMMETRICAL SWITCHING VOLTAGE REGULATOR: AN2-10 WINDOW DISCRIMINATOR. MULTIPLE APERTURE: AN31-3
    SYMMETRICAL VOLTAGE REGULATOR ZENER DIODE
    LM100 as a symmetrical regulator: ANl-9 IC: ANS6
    Regulation: AN21-6 Transistor-base-emitter junction: AN7l-8
    Trackmg regulator: AN20-10, AN21-6. LB7 ZERO CROSSING DETECTOR: AN31-17. AN41-2. AN41-3.
    SYNCHRONOUS AM DETECTOR: ANS4-6 LB6-2. LB12-2
    TACHOMETER: AN72-32 ZEROING. AMPLIFIER: AN63-B

    vii
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    November 1967 ....
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    AN1-1
    INTRODUCTION to 250 mAo A second external power transistor
    will enable the regulator to deliver currents in
    The great majority of linear integrated circuits
    excess of 2A.
    being produced today are DC amplifiers, particu-
    larly operational amplifiers_ This has come about The regulation is better than l-percent for widely
    both because the DC operational amplifier is a varying load and line conditions. The device
    basic analog building block and because this also features 1-percent temperature stability over
    device makes good use of the well-matched char- the full military temperature range, externally
    acteristics of monolithic components, characteris- adjustable short-circuit-current limiting, fast re-
    tics which are normally expensive to duplicate sponse to both load and line transients, a small
    with discrete parts. A voltage regulator is a cir- standby power dissipation, freedom from oscilla-
    cuit which requires similar precision. As shown in tions with varying resistive and reactive loads,
    the diagram of Figure 1, a basic regulator circuit and the ability to self start with any load.
    employs an operational amplifier to compare a
    reference voltage with a fraction of the output VOLTAGE REFERENCE
    voltage and control a series-pass element to
    regulate the output. The voltage reference of a regulator is normally
    a temperature compensated avalanche diode. Com-
    mercially available diodes have a breakdown voltage
    UNRfGUUHO
    I~PUT
    temperature coefficient of O.Ol-percentfC to
    0.0005fc, depending on selection. Normal inte-

    ;\ grated circuit processing yields an avalanche diode


    with acceptable characteristics for this application.

    tt
    "'''''' The reversed-biased emitter-base junction of the
    transistors has a breakdown voltage of approxi-
    >-',,"' mately 6.5V and an unusually uniform temperature

    r-~
    coefficient of +2.3 mV tC. Hence, the positive
    temperature coefficient of the avalanche diode can
    be very nearly balanced out by a forward biased,
    diode-connected transistor to produce a tempera-
    ture compensated reference. However, exact com-
    pensation requires surface impurity concentrations
    in the transistor-base diffusion which are higher
    FIGURE 1. Basic Series-Regulator Circuit than desired to produce optimized transistors. One
    design objective of an integrated regulator is, then,
    to develop a reference element which permits
    Perhaps the reason that monolithic regulators nearly-exact compensation without requiring pro-
    have not appeared sooner is because it is diffi- cess alteration.
    cult to make one design flexible enough to
    satisfy an appreciable percentage of the market. Another design objective is also centered around
    Different systems require vastly different output the reference. In the regulator circuit of Figure 1,
    voltages and currents, as well as varying degrees the output voltage can be adjusted down to, but
    of regulation. In addition, the current handling not lower than, the reference voltage. This means
    ability of monolithic circuits is limited because that, unless additional circuitry is incorporated,
    of the large physical die size of high-current the reference restricts the use of the regulator to
    transistors. Power dissipation is also a factor, applications requiring output voltages above about
    since there are no readily available multi-lead 8V. It is therefore desirable to obtain as low as
    power packages for integrated circu its. possible a reference voltage.

    A design is presented here which is versatile A circuit which provides a simple solution to the
    enough to overcome many of these problems. It temperature compensation problem in addition
    is able to deliver regulated voltages which are to supplying a low reference voltage is shown in
    externally adjustable from 2V to 30V, operating Figure 2. In this circuit, the breakdown diode is
    as either a linear, dissipating regulator or a high supplied by a current source from the unregu-
    efficiency switching regulator. This covers the lated supply. An emitter follower, Q" buffers
    range from low-level logic circuits to the majority the output voltage of the diode. The positive
    of solid-state linear systems. Although the output temperature coefficient of this buffered output
    current ofthe integrated circuit is limited (12 mAl. is increased to approximately 7 mV tc by the
    an external transistor can be added for currents addition of the diode connected transistor, ~.

    ANl-2
    A resistor divider reduces this voltage as well as The gain of this stage is made much higher than
    the temperature coefficient to exactly compen- would normally be expected by the use of Q 3
    sate for the negative temperature coefficient of and Q 4 as collector loads. If very large PNP
    Q3, producing a temperature compensated out- current gain and good matching are assumed,
    put. With the integrated circuit process used, this the collector current of Q 4 will be equal to the
    output voltage is about 1.8V for optimum com- collector current of Q,. Therefore, the differential
    pensation_ stage will be in balance independent of the
    magnitude of the collector currents of Q, and
    Q 2 and for the complete range of output voltage
    settings and input voltage variations. Even this
    simple circuit gives a no load to full load regula-
    tion of 0.2-percent and a line regulation of 0.05-
    percent per volt.
    The complete schematic of the regulator in Figure 4
    shows several additions. First, an emitter follower,

    r -......_ _ _--1>-_--1>-_--<t-lO~R(GUlAIED

    FIGURE 2. Voltage Reference Circuitry

    One feature of this integrated reference is that


    the reverse emitter base breakdown, must have
    an extremely sharp knee (even in the 1 jlA region)
    in order for the transistors in the circuit to be
    acceptable. Therefore, the diodes can be reliably
    operated at low currents where the noise is low
    and has a nearly uniform frequency spectrum.
    At higher currents (above about 100 jlA for these FIGURE 4. Complete Schematic of the LM100
    particular devices) the noise becomes a sensitive
    function of current with low-repetition-rate pul- Q3' and a level-shifting diode, Q" have been added
    sations. At even higher currents, the noise reduces to increase the effective current gain of the PNP
    in amplitude and loses its current sensitivity but transistor, Q2' This device is a lateral PNP' which
    still retains a heavy fluctuation component. has a low current gain (0.5 to 5) but has the advan-
    tage that it can be made without adding any steps
    REGULATOR CIRCUIT or process controls to the normal NPN inte-
    grated circuit process. One collector of the PNP
    A simplified schematic of the regulator is shown
    serves as a collector load for the error·sensing
    in Figure 3. It is a single-stage differential ampli- transistor, ag. A second collector supplies current
    fier with a Darlington, emitter-follower output. for the breakdown diode, 0,. A third collector,
    which determines the output current of the other
    two, maintains a current nearly equal to the
    collector current of Q 4 by means of negative
    feedback to the PNP base through Q 3 and Q,.
    The collector current of Q 4 is established at a
    known fraction of the resistive divider current
    through R, and R2 by the second emitter on Q s .
    This emitter-base junction of Qs, which is five
    times larger than that of Q6, bypasses most of
    the divider current, at a ratio determined by the
    relative geometries, to the collector of Q s . This
    current, combined with the collector current of
    as through the other emitter of Qs, supplies
    current for the emitter of Q 3 to drive the base
    FIGURE 3. Simplified Schematic of the Regulator of Q2'

    AN1-3
    R4 and R9 serve the sole purpose of starting the 0'0, it removes base drive from 0" to prevent
    regulator. They only need to supply enough base any further increase in output current. It can be
    current to O2 to bring the breakdown diode, D" seen from Figure 4 that the voltage turning on
    up to voltage. Since it can supply many times the 0'0 is the voltage drop across the external cur·
    required current under worst·case conditions, start· rent limit resistor plus a fraction of the emitter·
    ing is ensured. base voltage of the serie$ pass transistor, 0,2.
    This arrangement was used for two reasons.
    The clamp diode, D2 , reduces the current varia· First, less voltage is dropped across the current
    tion seen by 0 3 with changes in input voltage, limit resistor, permitting the circuit to regulate
    improving line regulation. R9 is a pinch resistor 2 with lower input voltages. Second, since in cur·
    which has a sheet resistivity more than two orders rent limit 0'2 is operated at a much higher
    of magnitude higher than diffused base resistors, emitter·current density than is 0'0, it has a lower
    so it can be made quite small physically. Pinch negative temperature coefficient of emitter·base
    resistors do have the disadvantages of non·linear voltage. The negative temperature coefficient of
    voltage·current characteristic, a large temperature the emitter·base voltage of 010 along with this
    coefficient, a low breakdown voltage and rather difference in temperature coefficients causes the
    large production variations in sheet resistivity. current limit to decrease by a factor of 2 as the
    However, as shown in Reference 3, these charac· chip temperature increases from 25°C to 150°C.
    teristics can be designed around and actually put This enables the regulator to deliver maximum
    to good use, as they are here. current to room temperature but still be protected
    when the output is shorted and the dissipation
    The start·up network is connected to the regulator
    increases: the current will decrease as the chip
    output terminal, rather than ground, so that the
    heats, holding the dissipation to a safe level.
    internal power dissipation is minimized without
    requiring large resistance values. Because of this, It is interesting to note that this current limit
    the load current of the regulator cannot drop below scheme will only work when the two transistors
    the current supplied from the unregulated input are in close thermal contact, as they are in a
    through R4. If it does, the circuit will no longer monolithic integrated circuit.
    regulate. This is not usually a problem, since
    the resistive divider which sets the output voltage Since a regulator is an operational amplifier with
    will normally draw enough current. However, it a large amount of feedback, frequ.llncy compen·
    should be kept in mind in applications where the sation is required to prevent oscillations. However,
    regulator might be lightly loaded and the difference a voltage regulator has compensation problems in
    between the unregulated input voltage and the reg· addition to those encountered in an operational
    ulated output voltage is apt to be high. amplifier. For one, the compensation method must
    provide a high degree of rejection to in put voltage
    The collector of the output transistor, 0,2, is
    brought out separately to permit the addition of transients. Secondly, it must be stable with reactive
    an external PNP transistor for higher currents. loads which are far heavier than those normally en·
    An emitter·base resistor for the external PNP, Ra , countered with operational amplifiers. Thirdly, it
    is also included. This resistor is shorted out when must minimize the overshoot caused by large load
    the regu lator is used without the external tran· and line transients.
    sistor. A compensation method satisfying those require·
    The output of the voltage reference is brought ments is shown in Figure 5. The operational am·
    out so that the inherent noise of the breakdown plifier is connected as an integrator and isolated
    diode can be bypassed out. Since the low operating
    current of the diode minimizes low·frequency
    noise, adequate bypassing can be provided by a
    capacitor as small as 0.1 JlF.
    The purpose of the clamp diode, D3 , is to keep
    Og from saturating when the circuit is used as a
    switching regulator. It plays no functional role
    in linear operation.
    Output· current limiting is provided by 0'0. The
    value of current limit is determined by an external
    resistor between the current limit, and regulated
    output terminals. When the voltage drop across FIGURE 5. Simplified Schematic Showing Regulator
    this resistor becomes high enough to turn on Frequency Compensation

    ANl-4
    from the load with an emitter follower, which APPLICATIONS
    serves as a series pass transistor. If the feedback
    The basic regulator circuit for the LM100 is shown
    loop is opened at point A and the frequency
    in Figure 7. The output voltage is set by R, and
    response measured, it can be seen that the feed·
    back at high frequencies where the loop response
    must be controlled is through CF . Reactive loads
    have little effect since they are isolated from the
    high frequency feedback path by 0 5 .
    This compensation method provides excellent
    response to load transients. That part of a load
    transient which is not absorbed by the output
    capacitor, C L , sees the output impedance of 0 5
    which is quite low since it is driven by an oper·
    ational amplifier with a low AC output impedance.
    FIGURE 7. Basic Regulator Circuit
    In the actual regulator (Figure 4) the operational
    amplifier is a single stage amplifier (Og). Hence, R2, with a fine adjustment provided by the poten·
    it is stable in the integrator connection, with a tiometer, R3 . The resistance seen by the feedback
    collector base capacitor on Og, without addi· terminal should be approximately 2.2k to minimize
    tional compensation which might degrade either drift caused by the bias current on this terminal.
    the load or line transient response. The series Figure 8 is based on this and gives the optimum
    pass transistor is a compound emitter follower
    to insure isolation from reactive loads. In addi·
    tion, the stability of the circuit is not dependent
    I-- .2
    on the output impedance of the unregulated
    supply. It is also stable with no bypass capaci·
    30
    .,
    tance on the output (if external booster transis·
    tors are not used) so it is possible to obtain
    extremely rapid current limiting as might be
    i 2D

    lD R1/RZ=Z.2k!l 3
    required with sensitive transistor loads.
    A photomicrograph of the monolithic regulator • 1 610 203050
    die is shown in Figure 6. Since the design reo OUTPUT VOLTAGE (V)
    quires a minimum of resistance, substituting active
    devices where possible, the entire circuit has been FIGURE 8. Optimum Divider Resistance Values as a
    Function of Output Voltage
    constructed on a 38·mil·square die. This die size is
    comparable to that of a single silicon transistor.
    values for R, and R2 as a function of design·center
    output voltage. The potentiometer should be least
    1/4 of R2 to insure that the output can be set to
    the desired voltage.
    It is possible to operate the regulator with or
    without internal current limiting. If current limiting
    is not needed, improved load regulation can be rea·
    lized by shorting together the current limit ter·
    minals (R se = 0). Figure 9 gives the load regulation
    for this condition. Short circuit protection is
    obtained by connecting a resistor between the
    current limit terminals. The resistor value is deter·
    mined from the current limit sense voltage which
    is plotted asa function oftemperature in Figure 10,
    for low output currents which corresponds to the
    case where external booster transistors are used.
    The current limit sense voltage is the voltage
    across the current limit terminals when the regulator
    is current limiting with the output shorted. The
    regulation and current limit characteristics with a
    10n current limit resistor are given in Figures 11
    FIGURE 6. Photomicrograph of the LM100 Regulator and 12, respectively.

    ANl-5
    1.001
    11 Rsc "100
    ~
    ... 2... 1.0 TJ-~'~f-E
    ~ 1.000
    ~> r-
    i"
    TI51-
    ..'"~...
    >
    ",' "'t"RJ"-55'C

    5; .999
    ~'c l -I--
    ..~
    ;\TJ '" 125°C
    I'-.
    ...~
    0.99 \
    I"JI >
    TJ'" 150D C

    ~ ~98 ;:::

    ~91
    ITJ·Rc ~
    0.98
    10 15 20
    o 5 10 15 20 25 30 35 40
    LOAD CURRENT (mAl
    OUTPUT CURRENT (mAl

    FIGURE 9. Regulation Characteristics Without Current FIGURE 11. Regulation Characteristics with Current
    Limiting Limiting

    1.2
    Rsc '" 10n
    ~
    ...
    !;l
    ~
    ~
    ...
    '"'"
    ~
    1.0

    0.8 f - )--J Tr ,,;c -- =_55°C

    ...> 0.4
    >
    ~ !; 0.6
    ~
    !::
    ~ 0.3 f-H-+-++++-=1o.-H-I--
    ~ DA
    f- t- TJ= 125°C

    ~
    .... l - t-- TJ '" 150°C

    I ~ 0.2

    0.2 L..J-1-...L.L-L.i-L...LLl....L..J
    -80 -40 40 80 120 160 5 10 15 20 25 30 35 4D 45
    JUNCTION TEMPERATURE (DC) OUTPUT CURRENT (mAl

    FIGURE 10. Current Limit Sense Voltage as a Function FIGURE 12. Current Limiting Characteristics
    of Junction Temperature

    A bypass capacitor is not required on the regula- by the addition of a 0.1 J,lF capacitor on the refer-
    tor output in the circuit of Figure 7. This permits ence bypass terminal. This reduces the noise
    extremely fast current limiting_ The output imped- inherent in the reference diode.
    ance as a function of frequency is plotted in
    The transient response of the regulator is shown
    Figure 13 for this condition. The output impedance
    in Figures 14 and 15_ Figure 14 shows the
    at high frequencies can be reduced somewhat by
    response to a current step from 3 mA to 15 mA,
    the addition of a bypass, as shown in Figure 13.
    without any output bypass capacitor and with a
    However, it is necessary to use a low-inductance
    capacitor (such as a solid-tantalum capacitor) to
    lOn current limit resistor. The overshoot can be
    reduced both by the addition of an output bypass
    gain any real advantage. Similarly, bypassing on the
    capacitor and by the removal of the current limit
    unregulated input is not normally needed, although
    resistor since the overshoot is developed across
    it may be advisable to use a small (0.01 J,lF)
    the resistor. The response to a line voltage transient
    ceramic capacitor when the regulator is fed through
    is shown in Figure 15. Neither the line transient
    long leads which can look I ike a high-Q resonant
    response nor the load transient response is affected
    circuit. by the output voltage setting. Therefore, the over-
    shoot becomes a smaller percentage of the output
    A reduction in the output noise can be realized voltage as this voltage is increased.

    AN1-6
    ~ 0.2

    ">=
    0

    0.1
    " !7
    ~ - CL =a
    I"
    '"
    ~0 -+
    CL= l,uF
    ...
    :>
    -0.1
    Rsc -l0n
    ...'" .:W 1N =5V
    '"
    0 -0.2 VOUT '" lOV
    10k lOOk 1M 10M 10 15 20
    FREQUENCY {Hd TIME (lIS)

    FIGURE 13. Output Impedance as a Function of FIGURE 15. Line Transient Response
    Frequency

    when the device is operated under conditions of


    ~ D.'
    "
    0 0.3 I I high dissipation.
    ~ 0.2
    C,· D'/'
    L1
    CL::: l,uF
    ~ 0.1
    .:\ ... HIGH POWER REGULATORS
    '"" •• OC':": i:"" l- 11
    ~ -0.1
    II Rsc::: 10n Increased output current capability and improved
    ...:> -0.2 I FL "'20mA-
    load regulation can be obtained by the addition
    '" -0.3 INL:::3mA -
    ~ -D.' V~uT·lO~-
    of external transistors. The output currents achiev-
    able are in fact limited only by the power dissipat-
    10 15 20 ing and current handling capabilities of the external
    TIME (,us) transistors. The use of these external transistors as
    the series pass elements also reduces internal dissi-
    pation in the integrated circuits and prevents the
    temperature drift mentioned above.
    FIGURE 14. Load Transient Response

    One circuit which is capable of up to 200 mA load


    current with l-percent regulation is shown in
    Figure 16. The load characteristics are essentially
    The regulator provides a line regulation of 0.1- the same as those given in Figures 11 and 12 except
    percent per volt change in input voltage. The full- that the current scale is multiplied by a factor of 10.
    load regulation is better than 0.5-percent. The
    output voltage drift is less than l-percent for a
    temperature change from +25°C to either the
    -55°C or +125°C temperature extreme. The reg-

    ~
    ulator will operate within specifications for output ' ',. "';~~~:: ...
    voltages between 2V and 30V. for input voltages
    between B.5V and 40V. for a difference between 1.1~~!A Z LMICO 6"·' . ~I'I
    the input and output voltage between 3V and 30V J .! Rl

    and over -55°C to +125°C temperature range. This "~R!GULAT[O

    10'UT G"Ou~o
    applies whether the regulator is used alone or with
    external current-boosting transistors.
    The load and line regulation given above is for
    a constant chip temperature on the integrated
    circuit. Temperature drift effects caused by inter- FIGURE 16. Regulator Connected for 200 rnA Output
    nal heating must be taken into account separately Current

    ANl-7
    When external transistors are used, it is necessary Another high-power regulator is shown in Figure 18.
    to bypass the output terminal close to the inte- This circuit is a minor variation of that described
    grated circuit_ This is required to suppress oscil- previously and is useful when low output voltages
    lations in the minor feedback loop around the
    external transistor and the output transistor of the
    integrated circuit (0'2 in Figure 4)_ Since the
    instability is inclined to occur at high frequencies,
    a low inductance (solid tantalum) capacitor must
    be used_ Electrolytic capacitors which have a high
    equivalent series resistance at high frequencies are
    not effective.

    It is not always necessary to bypass the input of


    the regulator in Figure 16, although it would be
    advisable if the regulator were being operated from
    long supply leads or from a source with unknown FIGURE 18. Circuit for Obtaining Higher Efficiency
    output impedance characteristics. Again, if a bypass Operation with Low Output Voltages
    is used, it should be of the low-inductance variety
    and located close to the regulator. are required. Here, the series pass transistor, O2 ,
    and the regulator are operated from separate
    If output currents much greater than about 200 mA supplies. The series pass transistor is run off of a
    are required, it becomes necessary to add a second low voltage main supply which minimizes the
    external transistor to provide more current gain. input-output differential for increased efficiency.
    The method of accomplishing this is shown in The regulator, on the other hand, operates from a
    Figure 17. The PNP transistor, O2 , is used to drive low power bias supply with an output greater than
    B_5V.

    With this circuit, care must be taken that O 2 never


    saturates. Otherwise, Q, will try to supply the
    entire load current and destroy itself, unless the
    bias supply is current limited.

    ,,,",'-+--4----{il
    SWITCHBACK CURRENT LIMITING

    With high power regulators it is possible to run into


    excessive power dissipation when the output is
    shorted, even though the regulator has current
    FIGURE 17. Regulator Connected for 2A Output Current limiting. This happens, with normal current limit-
    ing, because the series pass transistor must dissi-
    pate the power generated by the full input voltage
    a NPN power transistor, 0,. With this circuit it is at a current slightly above the full load current.
    necessary to bypass both the input and output This dissipation can easily be three times the worst
    terminals of the regulator, as indicated, with low case dissipation in normal operation at full load.
    inductance capacitors to prevent oscillation in the
    minor feedback loop through O 2 , 0, and the out- This problem can be overcome by reducing the
    put transistor of the integrated circuit. In addition, short circuit current to a value substantially less
    with certain types of NPN power transistors, it may than the full load current. A circuit for doing this
    be necessary to install a ferrite bead 4 in the emitter with the LM100 is shown in Figure 19, along with
    lead of the device to suppress parasitic oscillations the current limit characteristics obtained. As can
    in the power transistor. be seen from the schematic, two components are
    added to achieve this - R4 and R 5 . These resistors
    The load characteristics of the circuit are again supply a voltage which bucks out the voltage drop
    essentially the same as those given in Figures 11 across the current limit sense resistor, R3 , thereby
    and 12 except that the current scale is multiplied increasing the maximum load current from O.5A to
    by a factor of 100. As before, the line regulation, 2.0A_ When the output is shorted, however, this
    temperature drift, etc., are all the same as for the bucking voltage is no longer generated so the short
    basic regulator. circuit current is only O.5A.

    ANl-8
    11., LIMITING CHII.RII.CTERISTl~S

    15 , - - - - - , - - - - , - - - - - ,

    10 f------j----.::;tr2.111.

    OUTPUT CURRENT {A)

    B, SCHEMATI~ DIAGRAM

    FIGURE 19. Circuit for Obtaining Switchback Current


    Limiting with the LM100 FIGURE 20. Positive and Negative Regulators using
    the LM100
    In this circuit, the voltage drop across the current·
    sense resistor at full load is 1.5V as compared to
    about 0.37V when the bucking arrangement is Figure 21 shows a somewhat simpler circuit. Split
    not used. However, this does not increase the secondaries are used on a power transformer to
    minimum input·output voltage differential since create a floating voltage source for the negative
    the output of the LM 100 does not see this increased regulator. With this floating source, the conven·
    voltage. With a 10V output and a 2A load, the tional regulator is used, except that the output is
    circuit will still work with input voltages down to grounded.
    13V, worst case.
    In addition to providing the switchback character·
    istics, R4 and R5 also give a 20 mA preload on the
    regu lator so that it can be operated without a load.
    NEGATIVE VOLTAGE REGULATORS
    A schematic diagram for using the LM100 as
    both a positive and a negative regulator is shown
    in Figure 20. With this circuit, the inputs and
    outputs of both regulators have a common
    ground.
    The positive regulator is identical to those des·
    cribed previously. For the negative regulator, the
    normal output terminal (pin 8) of the LM100 is
    grounded, and the ground terminal (pin 4) is
    connected to the regulated negative output. Hence,
    as in the usual mode of operation, it regulates the

    °
    voltage between the output and ground terminals.
    A PNP booster transistor, 2 , is connected in the
    normal manner; and it drives a NPN series·pass
    transistor, 03' The additional components (R 7 , Rs ,
    Rg , RlO and 04) are included to provide current FIGURE 21. Circuit for using the LM100 as Both a
    limiting. Positive and a Negative Regulator

    ANl-9
    TEMPERATURE COMPENSATING REGULATORS have the advantages of fast response to load
    transients as well as low noise and ripple. How·
    In the majority of applications, it is desired that the
    ever, since they must dissipate the difference
    output voltage of the regulator be constant over the
    between the unregulated supply power and the
    operating temperature range of equipment. How·
    ever, in some applications, improved performance output power, they sometimes have a low effi·
    can be realized if the output voltage of the regulator ciency. This is not always a problem with AC
    changes with temperature in such a way as to line·operated equipment because the power loss
    operate the load at its optimum voltage. is easily afforded, because the input voltage is
    already fairly well regulated, and because losses
    An example of this in integrated logic circuitry. can be minimized by adjustment of transformer
    Optimum performance can be realized by powering ratios in the power supply. In systems operating
    the devices with a voltage that decreases with from a fixed DC input voltage, the situation is
    increasing temperature. A circuit which does this often much different. It might be necessary to
    is shown in Figure 22. Silicon diodes are used in regulate a 28V input voltage down to 1OV. In
    this case the power loss can quickly become
    A CIRCUIT DIAGRAM excessive. This is true even if ef.ficiency is not
    one of the more important criteria, since the high
    power dissipation requirements will necessitate
    expensive power transistors and elaborate heat
    sinking methods.

    A CIRCUIT DIAGRAM

    u.
    "
    B. OUTPUT VOLTAGE AS A FUNCTION OF TEMPERATURE

    -
    ......
    .....r--.. II. OUTPUT VOLTAGE ASA FUNCTION OF TEMPERATURE

    ....-
    -55 +25 +125
    TEMPERATURE (OC)

    FIGURE 22. Temperatwe Compensating Voltage


    Regulator with Negative Temperature
    Coefficient ,
    ---
    -55 +25 +125
    the feedback divider to give the required negative TEMPERATURE I"CI

    temperature coefficient. The advantage of using


    FIGURE 23. Temperature Compensating Voltage
    diodes, rather than thermistors or other tempera, Regulator with Positive Temperature
    ture sensitive resistors, is that their temperature Coefficient
    coefficient is quite predictable so it is not nec-
    essary to make cut-and-try adjustments in temper- One way of overcoming this difficulty is to go to a
    ature testing. Reference 6 gives a method of pre- switching regulator. With switching regulators, eff-
    dicting the voltage change in the emitter base volt· iciencies approaching SO· percent can be realized
    age of a transistor within 5 mV over a 1OOCC temp- even though the regulated output voltage is only a
    erature change. Diodes are not quite this predict- fraction of the input voltage. By proper design,
    able, but diode connected transistors (base shorted transient response and ripple can also be made
    to collector) can be used if greater accuracy is qu ite acceptable.
    required. .
    A circuit using the LM 100 as a switching regulator
    SWITCHING REGULATORS
    is given in Figure 24. It is designed for an applica-
    tion where a 28V DC power source must supply a
    The dissipating-type regulators described already system operating at 1OV.

    AN1-l0
    As shown in Figure 24, the LM 100 is connected in A far more complete description of switching
    much the same way as a linear regulator when regulators is given in Reference 7.

    CONCLUSIONS
    A regulated power supply is required in practically
    every piece of electronic equipment. A monolithic
    integrated circuit was described here which covers
    an extremely wide voltage range and can supply
    virtually unlimited power by the addition of ex-
    ternal transistors. As indicated in Table I, its
    performance is more than adequate for the major·
    's..I.......,...
    ~~~;; :!!;'.~:;,:-:~~:~,';:
    ity of applications. It is flexible enough to be
    used as either a linear dissipating regulator or as a
    high efficiency switching regulator without sacrific·
    FIGURE 24. High Current Switching Regulator ing performance in either application. The LM100
    also has fast transient response in that overshoot
    and recovery time can be made vanishingly small
    it is used as a switching regulator. Two external in most applications. In addition, the frequency
    transistors, a NPN and a IlNP, are connected in stability is indicated by the fact that it is vinually
    cascade to handle the output current. The regu· impossible to make the regulator oscillate in a
    lated output is fed back through a resistive divider properly designed circuit.
    which determines the output voltage in the normal The suitability of the design to monolithic con-
    manner. The regulator is made to oscillate by struction is demonstrated by the fact that it is
    applying positive feedback to the reference ter· built on a 38-mil-square silicon die - a size com-
    minal through R4 (from Figure 4, the reference parable to modern silicon transistors. This small
    terminal is the non·inverting side of the input size helps to achieve high yields which are neces-
    differential amplifier). sary to realize low manufacturing costs and insure
    In operation, the switching transistors, 0, and 2 ,
    turn on when the voltage on the feedback terminal
    ° off-the-shelf availability.

    is less than that on the reference terminal. This REFERENCES


    action raises the reference voltage since current
    is fed into this point from the switch output 1. H. C. Lin, T. B. Tan, G. Y. Chang, B. Van der
    through R4 . The switching transistors remain on Leest and N. Formigoni, "Lateral Complemen-
    until the voltage on the feedback terminal in· tary Transistor Structure for the Simultaneous
    creases to the higher reference voltage. The regu· Fabrication of Functional Blocks:' Proc. IEEE,
    lator then switches off, lowering the reference Vol. 52, No. 12, pp. 1491-1495, Dec. 1964.
    Voltage. It remains off until the voltage on the 2. G. E. Moore, "Semiconductor Integrated Cir-
    feedback terminal falls to the lower reference cuits:' Chap. V, Microelectronics, Edward
    voltage. Keonjian, ed., McGraw Hill, Inc., New York,
    When the switch transistors are on, power is 1963.
    delivered from the power source to the load 3. R. J. Widlar, "Some Circuit Design Techniques
    through L,. When the transistors turn off, the for Linear Integrated Circuits:' IEEE Trans on
    inductor continues to deliver current to the load Circuit Theory, Vol. CT-12, No.4, pp. 586-
    with D, supplying a return path. Since fairly fast 590, Dec. 1965.
    rise and fall times are involved, D, cannot be an 4. Leslie Solomon, "Ferrite Beads:' Electronics
    ordinary silicon rectifier. A fast-switching diode World, pp. 42-43, October, 1966.
    must be used to prevent excessive switching tran-
    sients and large power losses. 5. R. J. Widlar, "The Operation and Use of a Fast
    Integrated Circuit Comparator:' Fairchild Semi·
    Additional details of the circuit are that Rs limits conductor APP-116, February, 1966.
    the output current of the LM100, which drives
    the base of 02' C3 causes the full output ripple 6. R. J. Widlar, "An Exact Expression for the
    to be delivered to the feedback terminal of the Thermal Variation of the Emitter Base Voltage
    regulator. The bypass capacitor, C" is used on the of Bi-Polar Transistors:' Proc. IEEE, Vol. 55,
    input line both to minimize the voltage transients No. I, pp. 96-97, Jan. 1967.
    on this line and to reduce power losses in the 7. R. J. Widlar, "Designing Switching Regulators:'
    line resistance. National Semiconductor AN-2, April, 1967.

    AN1-11
    TABLE 1. Typical Performance of the National LM100 Voltage Regulator

    PARAMETER CONDITIONS VALUE


    Input Voltage Range 8.5 -40V
    Output Voltage Range 2.0 -30V
    Output·lnput Voltage Differential 3.0 -30V
    Load Regulation Rsc ~ 0, 10 < 15 rnA 0.1%
    Line Regulation 0.05%N
    Temperature Stability -55°C:':; T A :':; + 125°C 0.3%
    Output Noise Voltage 0.005%
    Long Term Stability 0.1%
    Standby Current Drain 1 mA
    Minimum Load Current 1.5mA

    ANI-12
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    I
    March 1969 N

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    G')
    C
    r-
    ~
    0
    DESIGNING SWITCHING REGULATORS :xl
    en

    INTRODUCTION One of the disadvantages of switching regulators is


    that they are more complex than linear regulators,
    The series pass element in a conventional series but this is often a substitution of electrical com·
    regulator operates as a variable resistance which plexity for the thermal and mechanical complexity
    drops an unregulated input voltage down to a of high power linear regulators. Another disad·
    fixed outpu t voltage. This element, usually a tran· vantage is higher output ripple. However, this can
    sistor, must be able to dissipate the voltage differ- be held to a minimum (about 10 mV) and it is at a
    ence between the input and output at the load high enough frequency so that it can be easily fil·
    current. The power generated can become exces- tered out. Another limitation is that the response
    sive, particularly when the input voltage is not well to load transients is not always as fast as with
    regulated and the difference between the input linear regulators, but this can be largely overcome
    and output voltages is large. by proper design. The rejection of line transients,
    however, is every bit as good if not better than
    Switching regulators, on the other hand, are capa- linea r regulators. Lastly, switching regulators
    ble of high efficiency operation even with large throw current transients back into the unregulated
    differences between the input and output voltages. supply which are somewhat larger than the maxi·
    The efficiency is, in fact, negligibly affected by the mu m load current. These, in some cases, can be
    voltage difference since this type of regulator acts troublesome unless adequate filtering is used.
    as a continuously·variable power converter.
    This article will demonstrate the use of a mono·
    Switching regulators are, therefore, useful in lithic voltage regulator in a number of switching
    battery·powered equipment where the required regulator applications. These include both self·
    output voltage is considerably lower than the oscillating and synchronously driven regulators in
    battery voltage. An example of this is a missile the O.lA to 5A range. Circuits are shown for both
    with a 30V battery as its only power source, con· positive and negative regulators with output volt·
    taining a large number of integrated logic circuits ages in the 2V to 30V range. Methods of isolating
    which require a 5V supply. Switching regulators the integrated circuit from the input voltage are
    are also useful in space vehicles where conservation given, permitting input voltages in excess of 1OOV.
    of power is extremely important. In addition, they Further, current limiting schemes which keep peak
    are frequently the most economical solution in currents and dissipation well within safe limits for
    commercial and industrial applications where the both over·load and short·circuit conditions are pre·
    increased efficiency reduces the cost of the series· sented. Finally, component selection details pecu·
    pass transistors and simplifies heat sinking. liar to switching regulators are covered.

    AN2-1
    SWITCHING REGULATOR OPERATION

    The method by which a switching regulator pro-


    duces a voltage conversion with high efficiency can
    be explained with the aid of Figure 1. 0, is a
    switch transistor wh ich is turned on and off by a
    pulse waveform with a given duty cycle, and D, is
    a catch diode which provides a continuous path
    for the inductor current when 0, turns off. The
    voltage waveform on the collector of 0, will be as R1
    shown in the figure. The output of the LC filter
    will be the average value of the switched wave-
    form, V,. If the voltage drops across the transistor R2 D1
    and diode are neglected, the output voltage will be 11

    (1)
    L-_ _ _ _ _ _ _ _ _. ._ _ _ _ V OUT = VREF
    and it is independent of the load current. It is
    obvious from the equation that changes in input
    voltage can be compensated for by varying the
    duty cycle of the switched waveform. This is what
    is done in a switching regulator. FIGURE 2
    Self-oscillating Switching Regulator
    V'N
    In operation, when the circuit is first turned on,
    the output voltage is less than the reference volt-
    age so the switch transistor is turned on. When this
    happens, current flow through R, raises the volt-
    age on the non-inverting input of the operational
    amplifier slightly above the reference voltage. The
    circuit will remain switched on until the output
    rises to this voltage. The amplifier now goes into
    the active region, causing the switch to turn off.
    A t this point, the reference voltage seen by the
    amplifier is lowered by feedback through R" and
    the circuit will stay off until the output voltage
    drops to this lower voltage. Hence, the output
    voltage oscillates about the reference voltage. The
    t o
    amplitude of this oscillation (or the output ripple)
    is nearly equal to the voltage fed back through R,
    VI i:toN -1\ tOFF=:j to R2 and can be made quite small.

    t-
    FIGURE 1 THE LM100
    SWitching Circuit for Voltage Conversion
    The switching regulator circuits described here use
    the LM 100 integrated voltage regulator as the con-
    Figure 2 shows a self-oscillating switching regu- trol element. This device contains, on a single
    lator which produces this duty-cycle control. A silicon chip, the voltage reference, the operational
    reference voltage, Vref equal to the desired output amplifier and the circuitry for driving a PNP
    voltage, is supplied to one input of an operational switch transistor. Discrete switch transistors, catch
    amplifier, A,. The operational amplifier, in turn, diodes and reactive elements are employed since
    drives the switch transistor. The resistive divider, these components are not easily integrated.
    arranged such that R,» R 2 , provides a slight
    amount of positive feedback at high frequencies to A complete circuit description of the LM100 is
    make the circuit oscillate. At lower frequencies given in Application Note AN-1 along with a num-
    where the attenuation of the LC filter is less than ber of its applications as a linear regulator. How-
    the attenuation of the resistive divider, there is net ever, a brief description will be included here in
    negative feedback to the inverting input of the order to facilitate understanding of the regulator
    operational amplifier. circuits which follow.

    AN2-2
    Figure 3 shows a schematic diagram of the LM100. output current of 0'2 to the value required for
    The voltage reference portion of the circu it starts driving a PNP transistor connected on the booster
    with a breakdown diode, 0" which is supplied by output. This current is determined by a resistor
    a current source from the unregulated input (one placed between the current limit and regulated
    of the collectors of O2 ). The output of the refer· output terminals. The value of the drive current
    ence diode, which has a positive temperature can be determined from Figure 4 which plots the
    coefficient of 2.4 mV tc, is buffered by an emit· output current as a function of temperature for
    ter follower, 0 4 , which increases the temperature various current limit resistors.
    coefficient to +4.7 mVtC. This is further in·
    creased to 7 mVtC by the diode·connected
    40
    transistor, 0 6 , A resistor divider reduces this volt·
    age as well as the temperature coefficient to ex· ;(
    IJ I
    actly compensate for the negative temperature .§
    30
    I~
    ,
    I-
    coefficient of 0 7 , producing a temperature·com· ~
    I:
    R~'M~ ,In ~
    I:
    pensated output of 1.8V. 1'l
    I- zo
    Il'f... RUM = 10G

    ~ RL!~ 1'""
    ....
    '1'0..
    U
    r~ ~ '100..
    3in
    . - -....- - - -. . .- -. . .---+JUNREOUlATEDINPUT
    I-
    I:
    =
    ill
    10
    Ri'M 1 ~ ... ~~
    o III
    r-:J1:::=t=;---"1-t1~~ .....--!:~."
    2 BOOSTER OUTPUT
    -60 -40 40 80 'ZO '60
    JUNCTION TEMPERATURE 1°C)

    t/Io'lll6M'I-1F----+-B REGULATED OUTPUT FIGURE 4


    Switched Output Current as a Function of
    ...._ _ _ _ _ 11:0MPENSATION Temperature for Various Values of Current
    Limit Resistors

    ~~. . .~.;:r-----6FEEDBACK

    '-__i-_______ 5REfERENCE BYPASS


    As for the remaining details of the circuit, as, 0 3
    L-_ _ +-______....______ 4GRDUND and a, are part of a bias stabilization circuit for
    O2 to set its collector currents at the desired value.
    R9 , R4 and O2 serve the sole function of starting
    the regulator. Lastly, 0 3 is a clamp diode which
    keeps 0 9 from saturating when it is switching.

    REGULATED
    OUTPUT

    SWITCHING REGULATOR CIRCUITS

    Figure 5 demonstrates the use of the LM100 as a


    switching regulator. Feedback to the inverting
    input of the operational amplifier (Pin 6 of the
    LM 100) is obtained through a resistive divider
    FIGURE 3 wh ich can be used to set the output voltage any·
    Schematic and Connection Diagrams of the where in the 2-30V range. R3 determines the base
    LM100 Voltage Regulator drive for the switch transistor, 0" providing
    enough drive to saturate it with maximum load
    current. R4 works into the 1 kQ impedance at the
    reference termi nal, producing the positive feed·
    The transistor pair, as and 0 9 , form the input back. C2 serves to minimize output ripple by
    stage of the operational amplifier. The gain of the causing the full ripple to appear on the feedback
    stage is made high by the use of a current source, terminal. The remaining capacitor, C3 , removes
    one of the collectors of O2 , as a collector load. the fast·risetime transients which would otherwise
    The output of this stage drives a compound emit· be coupled into Pin 5 through the shunt capaci-
    ter follower, a" and a, 2' The output of a, 2 is tance of R4 . It must be made small enough so that
    taken across Rs to drive the PNP switch transistor. it does not seriously integrate the waveform at this
    An additional transistor, a, 0, is used to limit the point.

    AN2-3
    The circuit shown in Figure 5 is suitable for out- peak currents which are significantly larger than
    put currents as high as 500 mA_ This limit is set by the load current. The change in inductor current
    the output current available from the LM 1 00 to can be written as
    saturate the switch transistor, 0 1 _ For lower cur-
    rents, the value of R3 should be increased so that (3)
    the base of 0 1 is not driven unnecessarily hard_

    I n order for the peak current to be about 1_2 times


    R'
    2M
    the maximu m load current, it is necessary that

    L11 2_5 V OUTtoff


    ~ (4)
    1
    ===SmH
    VOUT"'5V L1 lOUT Imaxl

    :~ C2
    O.Ij..lf
    1+ Cit
    15
    35V"'
    A value for toft can be estimated from

    ®-I-~
    R2
    2.27K toft ~ f1 ( 1 - V;;;
    VOUT) , (5)
    1%

    *Basing diagram IS Top View where f is the desired switching frequency and V IN
    tS ohdtantalum is the nomi nal input voltage_
    T125 turns =22 on Arnold Englneermg
    A262123·2molybdenumpermalloycore.
    The size of the output capacitor can now be deter-
    mined from
    FIGURE 5
    Switching Regulator Using the LM100
    C1 ~ (VIN - VOUT) (VOUT)2 (6)
    2L1 t.V OUT fV IN '
    The optimum switching frequency for these regu-
    lators has been determined to be between 20 kHz
    and 100 kHz. At lower frequencies, the core where t. VOUT is the peak-to-peak output ripple
    becomes unnecessarily large; and at higher fre- and V IN is the nominal input voltage.
    quencies, switching losses in 0 1 and D1 become
    excessive. It is important, in this respect, that both It now remains to determine if the component
    0 1 and D1 be fast-switching devices to minimize values obtained above give satisfactory load·
    transient response. The overshoot of the regu lator
    switching losses.
    can be determined from
    The output ripple of the regulator at the switching
    frequency is mainly determined by R4 . It should
    (7)
    be evident from the description of circuit opera-
    tion that the peak-to-peak output ripple will be
    nearly equal to the·peak-to-peak voltage fed back for increasing loads, and
    to Pin 5 of the LM 100. Since the resistance look-
    ing into Pin 5 is approximately 1DODD, this volt-
    (8)
    age will be

    1000 V IN for decreasing loads, where t.1 L is the load-current


    t. V ,ef .... --R-4- - . (2) transient. The recovery time is

    t ~ 2L1t.IL (9)
    In practice, the ripple will be somewhat larger than , VIN-VOUT
    this. When the switch transistor shuts off, the cur-
    and
    rent in the inductor will be greater than the load
    2L1t.1 L
    current so the output voltage will continue to rise t, ~--~
    V OUT (10)
    above the value required to shut off the regulator.
    An important consideration in choosing the value
    of the inductor is that it be large enough so that for increasing and decreasing loads respectively.
    the current through it does not change drastically
    during the switching cycle. If it does, the switch In order to improve the load transient response, it
    transistor and catch diode must be able to handle is necessary to allow larger peak to average current

    AN2-4
    ratios in the switch transistor and catch diode. More exact expressions would involve a design
    Reducing the value of inductance given by Equa· procedure which is too cumbersome to be of
    tion (4) by a factor of 2 will reduce the overshoot practical value_
    by 4 times and halve the response time. This, of
    course, assumes that the output capacitance is
    doubled to maintain a constant switching fre· The variation of switching frequency with input
    quency. voltage and load current is shown in Figures 6 and
    7. The sharp rise in frequency at low output cur-
    rents happens because the output transistor of the
    The above equations outline a design procedure LM 100 (Q'2) begins to supply an appreciable
    for determining the value for R4 , L" and C" portion of the load current directly.
    given the switching frequency and the output
    ripple. These equations are not exact, but they do
    provide a starting point for designing a regulator to The efficiency of the regulator over a wide range
    fit a given application. of input voltages and output currents is given in
    Figures 8 and 9.
    As an example, this design method will be applied
    to a regulator which must deliver 15V at a maxi-
    mum current of 300 mA from a 28V supply. To
    start, a 40 kHz switching frequency will be
    selected along with an output ripple of 14 mV,
    peak-to-peak.
    100
    \
    From (2), R4 is calculated to be 2 Mil In deter-
    mining L" toff is found to be 11.6 f-ls from (5). !
    90
    80
    ....
    ~
    Inserting this into (4) gives a value of 1.45 mH for t 10
    ..........
    L,. The value of C, obtained from (6) is then 57.5 ill 60

    f-lF.
    ~ 50
    40
    In the actual circuit of Figure 5, a standard value '"z 3D
    of 47 f-lF is used for C,; and L, is adjusted to 1.7 ...~ 20
    V1N = lBV

    mH _ The switching frequency obtained experi- ~ 10


    mentally on this circuit is 60 kHz and the peak-to- o
    peak output ripple is 20 m V. The fairly-large dis- o 1DO 200 300 400 500

    agreement between the calculated and experi- OUTPUT CURRENT ImAI

    mental values is not alarming since many simplify-


    ing assumptions were made in the derivation of the FIGURE 7
    equations. They do, however, provide a convenient Switching Frequency as a Function of Output
    Current
    method of handling a large number of mutually-
    dependent variables to arrive at a working circuit.

    80
    , -.... 100
    ~ 10
    :!
    f
    90
    80
    I...L
    I -
    ~ 60 10
    I
    g It. =300 mA
    ffi
    il:
    50
    Il" 300 rnA
    g
    ;:;
    60
    50
    '"z 40 40
    ~
    t:
    $ 3D
    ~ 3D 20
    10
    20
    10 15 20 25 30 35 40 45 50 o
    INPUT VOLTAGE IVI
    o 5 10 15 20 25 3D 35 40
    INPUT VOLTAGE IVI

    FIGURE 6
    FIGURE 8
    Switching Frequency as a Function of Input
    Voltage Efficiency as a Function of Input Voltage

    AN2-5
    100
    90
    80 -~ ~
    10
    g
    ~ 60 VIN = 28V
    ill 50
    U
    40
    $ lO
    20
    10

    100 200 lOO 400 500


    OUTPUT CURRENT (mAl

    FIGURE 9
    Efficiency as a Function of Output Current

    HIGHER CURRENT REGULATORS FIGURE 11


    High Current Switching Regulator
    If output currents greater than about 500 mA are
    requ irea, it is necessary to add another switch
    transistor to obtain more current gain. This is
    illustrated in Figure 10. With the exception of the

    same as that described previously.


    °
    added NPN power switch, 2 , this circuit is the 100
    I

    -
    90
    80
    A photograph of a high·current regulator is shown 10 I I r-
    in Figure 11. It is capable of delivering output cur· g V1N "'28V
    60
    ~
    rents of 3A continuously with only a small heat
    sink. Figure 12 shows that the efficiency is better ~ 50
    40
    than 80 percent at this level. Output currents to $ lO
    5A can be obtained at reduced efficiency. How- 20
    ever, the case temperature of the power switch and 10
    catch diode approach 1000 e under this condition, o
    so continuous operation is not recommended o 1.0 2.0 l.O 4.0 5.0
    unless more heat sink is provided. OUTPUT CURRENT (AI

    FIGURE 12
    Efficiency as a Function of Output Current

    Figure 13 shows that the efficiency is not signif-


    icantly affected by input voltage. In Figure 14 it
    can be seen that the switching frequency is fairly
    constant over a wide range of input voltages. F ig-
    ure 15 shows that the switching frequency
    increases with increasing load current. The higher
    dc current through the inductor reduces the incre-
    *BaslRg dl.gram IS Top View mental inductance causing the frequency to go up.
    tSolidtlntalum The last graph, Figure 16, illustrates the line regu·
    '60 turns =20 an Arnold Engineering
    A9JD157·Z molybdenum permllloytor!
    lation of the device. this can be improved by
    putting a small capacitor (0.01 JlF) in series with
    FIGURE 10 the positive feedback resistor, R3 , to isolate the
    Switching Regulator for Higher Output reference termi nal from the dc input voltage
    Currents changes.

    AN2-6
    10.30

    10.20

    70 - _ .. - ._>--+--+-+--1 ~ I~ ",.~A
    10.10

    ~ :: I-+_t_.t-'L_"t-'_+-+_t-_ A '"<t
    ~ 10,00
    I :
    I........
    u 40 __ - _j-_+-+_+-+_
    >
    S V
    ~ 30r-~-+-t-~~-+--+--l ~
    9.90
    V
    20
    10
    ---t--I-+-·~·-t·-t-~--j

    - r--r--- 1-1-
    9.80 ,
    OL-L-~~~-L-L~-J 9.70
    o 5 10 15 20 25 30 35 40 o 5 10 15 20 25 30 35 40
    INPUT VOLTAGE (VI INPUT VOLTAGE (VI

    FIGURE 13 FIGURE 16
    Efficiency as a Function of Input Voltage Line Regulation

    At low output currents the inductor current can


    drop to zero at some time after the switch tran-
    sistor turns off. When this happens, ringing occurs
    30 on the switching waveform. This is perfectly
    norma I and causes no ill effects.
    ~ 25
    ~

    ~ 20 / I-
    ..... ~ The use of solid tantalum capacitors for C, and C3
    ffi '( is recommended when the regulator is expected to
    :::0 It. = lA

    ~ 15 perform over the full military temperature range.


    '"z 10 I The reason for using 35V capacitors on the out-
    put, even though the output voltage is only 10V, is
    ~ I
    ~ that the 40 mV peak-to-peak ripple on the output
    would, for example, exceed the ratings of a
    o 100 J.lF, l5V capacitor.
    o 5 10 15 20 25 30 35 40
    INPUT VOLTAGE (VI
    Alumi num electrolytic capacitors have been used
    successfully over a limited temperature range. And
    FIGURE 14 there is basically no reason why wet foil or wet
    Variation of Switching Frequency with slug tantalums could not be used as long as their
    I nput Voltage equivalent series resistance is low enough so that
    they behave like capacitors with the high fre-
    quency switched-current waveform. It is also
    important that manufacturer's data be consulted
    to insure that they can withstand the high fre-
    quency ripple.
    50
    45
    As was mentioned with the low current regulator,
    ~ it is necessary to use fast-switching diodes and
    ~
    40
    transistors in these circuits. Ordinary silicon recti-
    ~ V
    VIN'" Z8V
    35 fiers or low·frequency power transistors will
    ~ 30
    :::
    '"z 25
    1--' .... '" operate at drastically-reduced efficiencies and will
    quickly overheat in these circuits.
    ;:
    ~ 20
    ........ I"'"
    ill 15

    10
    i DRIVEN SWITCHING REGULATOR
    o 1.0 2.0 3.0 4.0 5.0
    OUTPUT CURRENT (AI When a number of switching regulators are used
    together in a system it is sometimes desirable to
    FIGURE 15 synchronize their operation to more uniformly
    Variation of Switching Frequency with Out~ distribute the switched current waveforms on the
    put Current input line. Synchronous operation is also wanted

    AN2-7
    when a switching regulator is operated in conjunc- about 1 kn, the integrating capacitor, Ca , should
    tion with a power converter_ have a capacitive reactance of less than lOOn at
    the drive frequency. The value of Ra is determined
    A circuit for synchronizing the switching regulator so that the amplitude of the triangular wave on
    with a square wave drive signal is shown in Fig- Pin 5 is about 40 mV. .
    ure 17_ In this circuit, positive feedback is not
    used_ Instead, the square wave drive signal is Driven regulators also have other advantages. For
    integrated; and the resulting triangular wave one, it is possible to design the LC filter indepen·
    (about 40 mV peak-to-peak) is applied to the dent of switching frequency considerations.
    reference bypass terminal of the LM100. Thistri- Hence, lower output ripple and better transient
    angular wave will cause the regulator to switch response can be realized. A second advantage is the
    since its gain is so high that the waveform over- frequency stability. In a self-oscillating regulator,
    drives it. The duty cycle of the switched waveform the switching frequency is controlled by a rela-
    is controlled by the voltage on the feedback tively large number of factors. As a resu It, it is not
    terminal, Pin 6. If this voltage goes up, the duty well determined when normal tolerances are taken
    cycle wi II decrease since it is picking off a smaller into account. With low and medium power
    portion of the triangular wave on Pin 5. By the regulators, this is not usually a problem since the
    same token, the duty cycle will decrease if the efficiency does not vary greatly with frequency.
    voltage on Pin 6 drops. However, high power regulators tend to be more
    frequency sensitive and it is desirable to operate
    them at constant frequency .

    .........- ......'iRiiii'4-....- - - _ _ . - - . . _ VOUT =5V


    01
    lN311D
    CURRENT LIMITING

    In the circuits described previously, the regulator


    is not protected from overloads or short-circuited
    output. Providing short·circuit protection is no
    simple problem, since it is necessary to keep the
    20kHz
    regulator switching when the output is shorted.
    t-:C:::-3--'lR"'311<--:~~RE Otherwise, the dissipation will become excessive
    ~D.l pF DRIVE even though the current is limited.

    ·Bning di.gr.m is Top Vitw A circuit that does this is shown in Figure 18. The
    tSolidtlntllum peak current through the switch transistor is
    t.OO turns #22 on Arnold Engineering sensed by Rs. When the voltage drop across this
    A930157·2 molybdenum permalloy core
    resistor becomes large enough to turn on Oa, the
    FIGURE 17 output voltage begins to fall since current is being
    Driven Switching Regulator supplied to the feedback terminal of the regulator
    from the collector of Oa so less has to be supplied
    from the output through R,. Furthermore, the cir-
    cuit will continue to oscillate, even with a shorted
    output, because of positive feedback through Rs
    and the relatively-long discharge time constant of
    C2 ·
    This action produces the desired regulation: if the
    output voltage starts to go up, it will raise the It is necessary to put a resistor, R7 , in series with
    voltage on Pin 6 such that a smaller portion of the the base of Oa to insure that excessive current will
    triangular wave is picked off. This reduces the not be driven into the base. In addition, a
    duty cycle, counteracting the output voltage capacitor, C4 , must be added across the input of
    increase. Oa so that it does not turn on prematurely on the
    large current spike (about twice the load current)
    In order for this circuit to work properly, the through the switch transistor caused by pulling the
    ripple voltage on Pin 6 should be less than a stored charge out of the catch diode. A zener
    quarter of the peak·to·peak amplitude of the trio diode bias supply must also be used on the output
    angular wave. If this condition is not satisfied, the of the LM100 since the current limiting will not
    regulator will try to oscillate at its own frequency. work if the voltage on this point drops below
    Further, since the resistance looking into Pin 5 is about lV.

    AN2-8
    V1N >8.5V R4 1.0
    10K

    Rl
    22
    ':'
    01
    5V

    VOUT
    = 5V
    ~
    ~

    "w
    "'"u=>
    .75

    .50 ~

    Vi
    ~---
    ~
    ~
    ,-,
    V =28V
    1N
    VI\
    \ , --

    ~ V I
    t--
    l\-
    '" .25
    V
    1--
    I

    o
    0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
    OUTPUT CURRENT IAI

    FIGURE 20
    Illustrating Drop in Input Current as Regu-
    lator Goes Into Limiting

    difficult to prove that the circuit will sustain a


    continuous short circuit under worst-case condi-
    tions. This is particularly true with high current
    *Basing diagram is Top View regulators where the required amount of over-
    tSolidtanta[um design can become qu ite expensive.
    '70 turns #20 on Arnold Engineering
    A930157-2 molybdenum permalloy core
    Figure 21 shows a circuit which is more easily
    FIGURE 18 designed for continuous short-circuit protection
    Switching Regulator with Current Limiting under worst-case conditions. In this circuit, the
    current-sensing resistor is located in series with the
    inductor. Therefore, the peak-limiting current can
    be more precisely determined since the current
    spike generated by pulling the stored charge out of
    The current limiting characteristics of this circuit the catch diode does not flow through the sense
    are shown in Figure 19. Figure 20 shows how the resistor.
    average input current actually drops off as the cir-
    cuit goes into current limiting.

    This current limiting scheme protects the switch· V'N


    ing transistors from overload or short-circuited
    output. However, the drop-out current and short-
    circuit current are not well controlled, so it is

    5.05

    5.00

    ~
    4.95

    4.90
    "' 1\
    ~ 4.0 V
    > V1N = 28V
    1
    ~
    ~
    CI
    3.0

    2.0

    1.0
    1 , ·Baslng dlaglamis Top View
    tS(llidtantalum

    tlD tUlns:t2D on Alnold Englnewng


    A93D151·2 molybdenum pelmalloy cOle

    o
    0.5 1.0 1.5 2.0 2.5 l.O l.5 4.0 4.5
    OUTPUT CURRENT IAI
    FIGURE 21
    FIGURE 19 Switching Regulator with Continous Short-
    Current Limiting Characteristics Circuit Protection

    AN2-9
    5.05 NEGATIVE REGULATORS
    5.00

    1! 4.95
    1 All circuits discussed thus far are for regulators
    ~

    ~ 4.90
    I with positive outputs. Although negative regu·
    !:;
    ,. 4.0
    I;; lators can be obtained by floating the unregulated
    supply and grounding the output, this is not
    ..." VIN = lav
    always convenient .
    =
    ~
    3.0
    2.0
    "
    1.0 1-++-+-+-++-t-1 Figure 24 shows a circuit for a negative switching
    o~~~~~~~~~
    .5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 regulator where the unregulated input and regu-
    OUTPUT CURRENT (AI
    lated output have a commo n ground. The only
    limitation of the circuit is that there must be a
    FIGURE 22 positive voltage greater than 3V available in order
    Current Limiting Characteristics to properly bias the negative regulator.

    ~
    D1 "oj:
    -:!-
    lN388 ' Rl~R4 I. C3:0UT '5V
    02
    2N3441
    66
    ~~H05A
    22
    1
    5.5. C2
    1% 0.1/4
    r .::!:;r 100.,
    35V
    lMI00.h.....~
    ~'s't to 35V --ir-+--..I>--......ID...~f!.cllr R5
    elt +
    ~~ Tl~~K
    ":'"
    47.''1' , - - - - - -_ _ _-'
    l5V .;:

    ::~ !
    o~~~~~~~--'--'
    .5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
    OUTPUT CURRENT (AI
    ~~2905A
    >=6 '"
    lMI00·.T~t-"'II\~+---'
    .m
    R6
    5.5.

    R12
    lK
    R1
    '1

    3.1K
    ~:,

    1%
    FIGURE 23 t--+---t--VaUT= -5V
    t III
    :
    Plot of Input Current as Regulator Goes
    Iota Limiting Rl0 U ~~ :r ~~~~F
    C5 t

    ~
    ~:2222MQ4 !:!:f~3880 2N3441
    Rl1

    Operation of this circuit is essentially the same as


    150
    ;:~ -=
    v,.
    the previous one in that an NPN transistor, 0 4 , -6Vto-35V C6t
    senses the overcurrent condition and turns on 0 3 # 47Jl.F
    ..LJ5V
    which 3upplies the current·limit signal to the feed·
    back tlrminal. The zener diode, D3 , is required on "Baing dllgrlm is Top View t60 turns #20 on Arnold Engineerlnl
    tSolidtantalum A9J015H molybdenum permilloy tor.
    the fE~dback terminal to guarantee that this ter·
    minco: ~annot go more than 0.5V higher than Pin 1.
    If :" does happen, the circuit can latch up and
    bUI" ·,ut. The performance of this current-limiting FIGURE 24
    scheme is illustrated in Figures 22 and 23. Positive and Negative Switching Regulators

    With this circuit it is not only possible to more


    accurately determine the limiting current, but as
    can be seen from Figures 22 and 23, the limiting In this circuit, the normal output terminal of the
    characteristic is considerably sharper. One dis- LM100 (Pin 8) is grounded and the ground ter-
    advantage of this circuit is that the load current minal (Pin 4) is connected to the regulated nega-
    flows continuously through the current sense tive output. Hence, as before, it regulates the volt-
    resistor, reducing efficiency. As an example, with a age between the output and ground terminals. The
    5V regulated output the efficiency will be reduced unregulated input terminal (Pin 3) is run from a
    by 10 percent at full load. positive voltage for proper biasing. A PNP booster

    AN2-10
    transistor, 03, is connected in the normal manner; SWITCHING AND LINEAR REGULATOR
    and it drives a Darlington-connected NPN switch_ COMBINATION
    Positive feedback is developed by the resistive
    divider, Rs and R,2' In certain applications, the output ripple and load
    transient response requirements rule out the use of
    It is necessary to use a Darlington switch even a switching regulator, yet the input-output voltage
    though the current gain is not needed. The power differential is still high. In this case, a power con-
    switch transistor, 04, cannot be operated with a verter might be used to reduce the input voltage
    fixed base drive: if the base drive is made large and this reduced voltage would be regulated by a
    enough to insure saturation at maximum load cur· linear regulator. This arrangement, however, is not
    rent, it will overstore so badly at lower currents nearly as efficient as the switching and linear regu-
    that the output ripple will increase radically. With lator combination shown in Figure 26. The
    the extra transistor, however, it is kept out of satu- switching regulator not only reduces the input
    ration at lower output currents, eliminating the voltage with high efficiency, but it also regulates
    problem. it. Therefore, the linear regulator operates with a
    fixed input-output voltage differential which holds
    dissipation to a minimum.

    HIGH VOLTAGE REGULATORS

    With switching regulators, an application can easily


    arise where the input voltage can be higher than
    the 40V maximu m rating of the LM 100, even
    though the output voltage is within the 30V maxi- C1
    mum. As shown in Figure 25, it is possible to O.lJ.1F
    isolate the LM 100 from the unregulated supply so
    that it can be used with input voltages limited only VIN " 30v...,.-t-+-~---{lL""--'(\)

    by the switch transistors and the catch diode.

    RJ
    1M

    t--'W'r--t-...",..,...,...-...,.-.,-V OUT :: 5V
    0'
    tNJ880

    + eJt
    10DpF
    lOV

    R5
    -B'Slngd'lgram IsTop View
    tSohdtantalum
    '60 turns#ZD on Afllotd Engineering
    A9J0157·2 molybdenum permalloy core
    .t---.....-I--+- VIN >40V
    elt
    ~ 47 ~F (lId
    w
    ~::::;~ad~::;;: IS Top View
    fSOturns;::2D on Arnold EnQlneermg FIGURE 26
    A9J0157-2 molybdenum permalloy core Switching and Linear Regulator Combina-
    tion for Obtaining Very Low Ripple and Fast
    Transient Response
    FIGURE 25
    Switching Regulator for High-voltage Inputs

    In this circuit, the linear regulator is biased by a


    zener pre-regulator (R g , D2 and 05) to isolate it
    In this circuit, the voltage seen by the LM100 is from noise on the unregulated supply. This
    maintained at a fixed level within ratings by the separate bias supply permits the linear pass tran-
    zener diode, D 2 . The zener voltage must be at least sistor, 03, to operate right down into saturation.
    3V greater than the output Voltage. The output of The collector of 0 3 is supplied by the output of a
    the LM 100 is level·shifted up to the input voltage switching regulator which is made enough higher
    by an additional NPN transistor, 03, which is than the linear regulator output to allow for the
    operated common base. This drives the PNP switch maximum overshoot of the switching regulator
    driver in the normal manner. plus the saturation of 3 , °

    AN2-11
    SUMMARY driving the regulator in synchronism with an
    external clock signal was given. In addition, cir-
    A number of switching regulator circuits which use cuits which provide overload protection, limiting
    a readily-available monolithic voltage regulator as both the output current as well as the power dissi-
    the voltage reference and control circu itry have pation, were presented. The performance of the
    been described. These regulators are useful over a regulator circuits was described in detail. and a
    2V to 30V range for either positive or negative design procedure was outlined. Suggestions were
    supplies. Although the discussion was limited to also made on the selection of components for
    circuits providing maximum output currents from switching regulators.
    100 mA to 5A, it is possible to obtain even higher
    output currents. The output current is, in fact, The circuits which have been described here for
    limited by the discrete components - not by the the LM100 work equally well with the LM200
    basic design or the integrated circuit. or the LM300. These devices are identical, except
    that the LM200 is specified over a -25°C to 85°C
    temperature range and the LM300 is specified from
    The majority of the circuits shown were self- oOe to 70°C instead of the -55°C to 125°C
    o sc i lIati ng regu lators; however, a method of temperature range for the LM 100.

    AN2-12
    »2
    ,
    November 1967 W

    C
    :l3

    "
    -I
    (")
    DRIFT COMPENSATION TECHNIQUES o
    FOR INTEGRATED DC AMPLIFIERS 3:
    "'tI
    m
    INTRODUCTION 2
    en
    With DC amplifiers, it is usually possible to
    substantially improve drift performance by using
    transistors tend to track well over temperature so
    that low drift is also achieved. The disadvantage ~
    additional circuitry along with some form of adjust- of the method is that a given compensation setting o
    ment_ In fact, one of the reasons that discrete- works only with fixed feedback resistors, and the 2
    component operational amplifiers have better input" compensation must be readjusted if the equivalent
    -I
    current specifications than monolithic amplifiers parallel resistance of R, and R2 is changed. m
    is that current compensation is used_ Monolithic (")
    Figure 2 shows a similar circuit for a non-inverting
    circuits cannot incorporate these techniques be- ::J:
    cause it is not possible to select components or amplifier. The offset voltage produced across the 2
    make adjustments_ These adjustments can, how- DC resistance of the source due to the input
    P
    ever, be made external to the amplifier_ This c
    article will discuss a number of compensation m
    methods which can substantially reduce the input en
    currents of monolithic amplifiers, especially in
    Iimited-temperature-range applications_ o"
    Bias current compensation reduces offset and drift :l3
    when the amplifier is operated from high source FIGURE 2. Non-Inverting Amplifier with Bias-Current
    resistances_ With low source resistances, such as a 2
    Compensation for Fixed Source Resistances.
    thermocouple, the drif.t contribution due to bias
    -I
    current is cancelled by the drop across R3 . For
    m
    current can be made quite small. In this case, the C)
    offset voltage drift becomes important_ proper adjustment range, R3 should have a max- :l3
    A technique is presented here by which offset volt-
    imum value about three times the source resistance
    and the equivalent parallel resistance of R, and R2
    »
    -I
    age drifts better than 0.5 IJ.V tc
    can be realized. should be less than one-third the input source m
    The compensation technique involves only a single resistance_ C
    room-temperature balance adjustment. Therefore,
    chopper-stabilized performance can be realized, This circuit has the same advantages as that in C
    Figure 1, however, it can only be used when the (")
    with low source resistances, in a fairly-simple amp-
    lifier without tedious cut-and-try compensation input source has a fixed DC resistance, In many
    applications, such as long-interval integrators, sam-
    »
    methods.
    ple-and-hold circuits, switched-gain amplifiers or
    3:
    "'tI
    voltage followers operating from unknown source,
    BIAS CURRENT COMPENSATION
    the source impedance is not defined. In these cases
    !:
    The simplest and most effective way of compen-
    sating for bias currents is shown in Figure 1. Here,
    other compensation schemes must be used. "m
    Figure 3 gives a compensation technique which :l3
    does not depend upon having a fixed source resis- en
    '''"'~.''-''''
    tance. A current is injected into the input terminal
    from the base of a PNP transistor. Since NPN input
    ... '" lOU,,", transistors are used on the integrated amplifier,'
    " ' the base current of the PNP balances out the base
    current of the NPN. Further, since a silicon-planar
    ." PNP transistor has approximately the same current-
    gain versus temperature characteristic as the inte-
    grated transistors, an improvement in temperature
    FIGURE 1. Summing Amplifier with Bias-Current
    Compensation for Fixed Source drift will also be realized. t However, perfect
    Resistances.

    the offset produced by the bias current on the


    *This is true for all monolithic operational amplifiers pre-
    inverting input is cancelled by the offset voltage sentlyavailable.
    produced across the variable resistor, R3 . The tlf the operational amplifier uses a Darlington input stage,
    main advantage of this scheme, besides its simpli- however, the drift compensation will not be nearly as
    city, is that the bias currents of the two input good.

    AN3-1
    ,.

    ~-
    '-~'~"~"
    ,-----

    ..
    ,
    .,
    l ,,,"I. I O"lP~r
    '."'"1
    j

    t
    L~'"
    •
    I 0"""'

    -= 's,,",,,.. ,,,.

    FIGURE 3. Summing Amplifier with Bias·Current FIGURE 5. Voltage Follower with Bias-Current
    Compensation. Compensation.

    compensation should not be expected because of compensating current does not change appreciably
    unit-to-unit variations in the temperature charac- with signal level, giving input impedances about
    teristics of both the PNP transistor and the inte- 1000 Mn. The negative temperature coefficient of
    grated circuit. the diode voltage also provides some temperature
    compensation.
    Although the circuit in Figure 3 works well for the
    summing amplifier connection, it does have limit- All the circuits discussed thus far have been tailored
    ations in other applications, It could, for example, for particular applications. Figure 6 shows a com-
    be used for the voltage follower configuration by pletely-general scheme wherein both inputs are
    connecting the base of the PNP to the non-inverting
    input. However, this would reduce the input imped-
    ance (to about 150 Mn) because the current
    supplied by the PNP will vary with the input
    voltage level.
    If this characteristic is objectionable, the more-
    complicated circuit shown in Figure 4 can be used.

    FIGURE 6. Bias-Current Compensation for


    Differential Inputs.

    current compensated over the full common mode


    range as well as against power supply and temper-
    ature variations. This circuit is suitable for use
    FIGURE 4. Bias-Current Compensation for Non-Inverting either as a summing amplifier or as a non-
    Amplifier Operated Over large Common inverting amplifier. It is not required that the DC
    Mode Range. impedance seen by both inputs be equal, although
    lower drift can be expected if they are.
    The emitter of the PNP transistor is fed from a
    As was mentioned earlier, all the bias compensa-
    current source so that the compensating current
    does not vary with input-voltage level. The design tion circuits require adjustment. With the circuits
    of the current source is such as to give it about the in Figures 1 and 2, this is merely a matter of
    same characteristics as those on the input stage of adjusting the potentiometer for zero output with
    zero input. It is not so simple with the other
    the better monolithic amplifierst to give closer com-
    circuits, however. For one, it is difficult to use
    pensation with changes in temperature and supply
    potentiometers because a very wide range of resis-
    voltage. The circuit makes use of the emitter base
    tance values are required to accommodate expected
    voltage differential between two transistors oper-
    unit-to-unit variations. Resistor selection must
    ated at different collector currents. 1 .2 Although it
    therefore be used. Test circuits for selecting bias
    is recommended in the references that these tran-
    compensation resistors are given in Figure 7.
    sistors be well matched, it is not really necessary
    since the devices are operated at much different
    collector currents.

    ~
    Figure 5 shows another compensation scheme for
    the voltage follower connection. This circuit is
    ,~, , ~
    much simpler than that shown in Figure 4, but the - ,.
    temperature compensation is not quite as good. The
    cr c.
    compensating current is obtained through a resistor -=
    ..
    II lOBo' 30"

    connected across a diode which is bootstrapped to '":' ,,


    the output. The diode acts as a regulator so that the
    FIGURE 7. Test Circuits for Selecting
    *The 709 and the LM10L Bias·Compensation Resistors.

    AN3-2
    OFFSET VOLTAGE COMPENSATION

    The highly predictable behavior of the emitter-base


    voltage of transistors has suggested a unique drift
    compensation method; it is shown in Reference 3
    that the offset voltage drift of a differential tran-
    sistor pair can be reduced by about an order of ~~'". "'
    magnitude by unbalancing the coll'ector currents 'i' ~~'
    such that the initial offset voltage is zero. The basis
    for this comes from the equation for the emitter- L" .:~
    base voltage differential of two transistors operating
    at the same temperature:

    kT IS2 kT IC2 (1)


    L).V BE = -log. - - - log. -
    q lSI q ICI FIGURE 8. Example of a DC Amplifier Using
    the Drift-Compensation Technique.

    where k is Boltzmann's constant, T is the absolute


    temperature, q is the charge of an electron, Is is, a output for zero input, unbalances the collector load
    constant which depends only on how the transistor resistors of the transistor pair such that the col-
    is made and Ic is the collector current. This lector currents are unbalanced for zero offset. This
    equation is derived in Reference 2. gives minimum drift. An interesting feature of the
    circuit is that the performance is relatively un-
    It is worthwhile noting here that these expressions affected by supply voltage variations: a 1V change
    make no assumptions about the current gain of the in either supply causes an offset voltage change of
    transistors. It is shown in Reference 5 and '6 that about 10 IlV. This happens because neither term in
    the em itter-base voltage is a function of collector Equation (1) is affected by the magnitude of the
    current not emitter current. Therefore, the balance collector currents.
    will not be upset by base current (except for
    interaction with the DC·source resistance). In order to get low drift, it is necessary that the
    The first term in Equation (1) is the offset voltage gain of the preamplifier be high enough so that the
    of the two transistors for equal collector currents. drift of the operational ampl ifier does not degrade
    It can be seen that this offset voltage is directly performance. The gain can be determined from the
    proportional to the absolute temperature - a fact expression for the transconductance of the input
    which is substantiated by experiment. 4 The second transistors:
    term is the change of offset voltage which arises
    from operating the transistors at unequal collector
    (2)
    currents. For a fixed ratio of collector currents,
    this is also proportional to absolute temperature.
    Hence, if the collector currents are unbalanced in
    a fixed ratio to give a zero emitter-base voltage The voltage gain is
    differential, the temperature drift will also be zero.
    aV OUT
    Experiment indicates that this is indeed true. Ther- Av = - - - (3)
    aV 1N
    mal drifts less than 10'0 IlV over the -55°C to
    +125°C temperature range have been realized con-
    sistently. In order to obtain these low drifts, (4)
    however, it is almost necessary to use a mono-
    lithic transistor pair, sihce a 0.05°C temperature
    differential will give a 100 IlV drift. With a mono- where RL is the average value of the two collector
    lithic pair, the physical proximity of the devices as load resistors on the input stage and Ic is the
    well as the high thermal conductivity of silicon average of the two collector currents.
    holds this differential to an absolute minimum.

    For low drift, the transistors must operate from a Substituting Equation (2), this becomes
    low enough source resistance that the voltage drop
    across the source due to base current (or base
    current differential if both bases see the same (5)
    resistance) is insignificant. Furthermore, the tran-
    sistors must be operated at a low enough collector = qV RL '
    current that the em itter-contact and base-spreading (6)
    kT
    resistances are negligible, since Equation (1) assumes
    that they are zero.
    The input referred drift is then
    A complete amplifier using this principle is shown
    in Figure 8. A monolithic transistor pair is used as
    a preamplifier for a conventional operational amp-
    lifier. A null potentiometer, which is set for zero

    AN3-3
    where 11 Vos is the offset voltage drift of the SUMMARY
    operational amplifier and I110s is its offset current
    A number of compensation circuits designed to
    drift.
    increase the DC resolution of monolithic opera·
    Using Equation (7), tional amplifiers have been presented. Both current
    compensation techniques for high impedance levels
    o:::.
    I1V 1N ;k_T-.:.(I1_V.::: s _+_R....:L:...I1:.:I.:::o::::..s) (8) as well as methods of achieving chopper·stabilized
    qV RL drift performance at low impedance levels have
    been covered.
    With the circuit shown in Figure 8, Equation (8) Fairly·simple current compensation which requires
    gives a 25 IlV input·referred drift for every 10 mV that the impedance levels be fixed have been des·
    of offset voltage drift or for every 100 nA of offset cribed along with compensation which is effective
    current drift. It is obvious from this that the offset in cases where the source impedance is not well
    current drift is most important if an operational defined. This latter category includes long·interval
    amplifier with bipolar input transistors is used. integrators, sample·and·hold circuits, switched·gain
    amplifiers or voltage followers which operate from
    Another important consideration is the matching an unknown source. The application of these
    of the collector load resistors on the preamplifier schemes is generally limited to integrated amplifiers
    stage. A O.l·percent imbalance in the load resistors since modular amplifiers almost always incorporate
    due to thermal mismatches or any other cause wi II current compensation.
    produce a 25 IlV shift in offset. This includes the
    balancing potentiometer which can introduce an The drift·reduction techniques provide stabilities
    error that will depend on how far it is set off mid· better than 0.5 IlV fc for low impedance sources,
    point if it has a different temperature coefficient such as thermocouples, current shunts or strain
    than the resistors. gauges. With a properly designed circu it, compen·
    sation depends only on a single room temperature
    The most obvious use of this type of low drift
    adjustment, so excellent performance can be ob·
    ampl ifier is with thermocouples, magnetometers,
    tained from a fairly·simple amplifier.
    current shunts, wire strain gauges or similar signal
    sources where very low drift is required and the
    source resistance is low enough that the bias REFERENCES
    currents do not cause a problelT\. The 0.5 to 1 IlV I
    °c drift' realized with this relatively simple amp· 1. R. J. Widlar, "A Unique Circuit Design for a
    lifier over a _55°C to +125°C temperature range High Performance Operational Amplifier Espec·
    compares favorably with the drift figures achieved ially Suited to Monolithic Construction," Proc.
    with chopper amplifiers: O.4IlVfC for mechanical of NEC, Vol. XXI, pp. 85·89, October, 1965.
    choppers, 0.5 IlV fc with photoelectric choppers
    2. R. J. Widlar, "Some Circuit'Design Techniques
    over a DoC to 55°C temperature range and 21lV fc
    for Linear Integrated Circuits," IEEE Trans. on
    with field·effect·transistor choppers over a _55°C
    Circuit Theory, Vol. XII, pp. 586·590, Decem·
    to +125°C temperature range. In order to give some
    ber, 1965.
    appreciation of the level of performance, it is
    interesting to note that no substantial improvement 3. A. H. Hoffait and R. D. Thorton, "Limitations
    in performance would be realized by operating the of Transistor DC Amplifiers," IEEE Proc., Vol.
    amplifier in a temperature·controlled oven. Any 52, pp. 179·184, February, 1964.
    improvement wou Id be masked by various thermo·
    electric effects not directly associated with the 4. A. Tuszynski, "Correlation Between the Base·
    amplifier unless extreme care were taken in the Emitter Voltage and Its Temperature Coeffi·
    choir.e of input lead material, the method of mak· cient," Solid State Design, pp. 32·35, July,
    ing connections and the balancing of thermal paths. 1962.
    These factors are, in fact, important when making
    5. C. T. Sah, "Effect of Surface Recombination
    oven tests to verify the drift of thp Jmplifier since
    and Channel on P·N Junction and Transistor
    thermoelectric effects can easily produce drift
    Characteristics," IRE Trans. on Electron De-
    voltages larger than those of the amplifier if they
    vices, Vol. ED·9, pp. 94·108, January, 1962.
    are not properly handled.
    6. J. E. Iwersen, A. R. Bray, and J. J. Kleimack,
    *Drifts of 0.05 IJ,Vrc over a 0-50°C temperature range "Low·Current Alpha in Silicon Transistors,"
    were reported in Reference 3 using matched discrete IRE Trans. on Electron Devices, Vol. ED·9,
    transistors in one can. pp. 474·478, November, 1962.

    AN3-4
    »
    z
    April 1968 ~

    3:
    o
    z
    o
    r-
    MONOLITHIC OPERATIONAL AMPLIFIERS- =t
    THE UNIVERSAL LINEAR COMPONENT
    :t
    n
    INTRODUCTION OPERATIONAL-AMPLI FI ER OSCI LLATOR
    o"tJ
    m
    Operational amplifiers are undoubtedly the easiest The free-running multivibrator shown in Figure 1 :J:I
    and best way of performing a wide range of linear is an excellent example of an application where one »
    -I
    functions from simple amplification to complex does not normally consider using an operational
    analog computation. The cost of monolithic am· amplifier. However, this circuit operates at low fre- o
    plifiers is now less than $2.00, in large quantities, quencies with relatively small capacitors because it Z
    which makes it attractive to design them into cir- can use a longer portion of the capacitor time con- »
    r-
    cuits where they would not otherwise be con- stant since the threshold point of the operational
    sidered. Yet low cost is not the only attraction of amplifier is well determined. In addition, it has »
    monolithic amplifiers. Since all components are a completely-symmetrical output waveform along 3:
    simultaneously fabricated on one chip, much higher with a buffered output, although the symmetry can "tJ
    circuit complexities than can be used with discrete be varied by returning R2 to some voltage other C
    amplifiers are economical. This can be used to give than ground. ."
    improved performance. Further, there are no insur-
    "
    160K
    m
    mountable technical difficulties to temperature sta- :J:I
    bilizing the amplifier chip, giving chopper-stabilized CJ)
    performance with little added cost. ~
    :t
    m
    Operational amplifiers are designed for high gain, ". C
    low offset voltage and low input current. As a re- Z
    sult, dc biasing is considerably simplified in most OO"'I R2
    9101(.
    R3
    160K
    <:m
    applications; and they can be used with fairly sim-
    ple design rules because many potential error terms - .... :J:I
    CJ)
    can be neglected. This article will give examples
    demonstrating the range of usefulness of operation-
    FIGURE 1. Free-Running Multivibrator
    »r-
    al amplifiers in linear circuit design. The examples
    are certainly not all-inclusive, and it is hoped that Another advantage of the circuit is that it will C
    they will stimulate even more ideas from others. A always self start and cannot hang up since there is Z
    few practical hints on preventing oscillations in m
    operational amplifiers will also be given since this
    more dc negative feedback than positive feedback.
    This can be a problem with many "textbook"
    »
    :J:I
    is probably the largest single problem that many multivibrators.
    engineers have with these devices. n
    Since the operational amplifier is used open loop,
    o
    the usual frequency compensation components are
    3:
    "tJ
    Although the designs presented use the LM101 op- not required since they will only slow it down. But
    even without the 30 pF capacitor, the LM101 does
    o
    erational amplifier and the LM102 voltage follower Z
    produced by National Semiconductor, most are have speed limitations which restrict the use of this m
    generally applicable to all monolithic devices if the circuit to frequencies below about 2 kHz. Z
    manufacturer's recommended frequency compen- -I
    sation is used and differences in maximum ratings
    are taken into account. A complete description of The large input voltage range of the LM101 (both
    the LM101 is given elsewhere;l but, briefly, it dif- differential and single ended) permits large voltage
    fers from most other monolithic amplifiers, such swings on the input so that several time constants
    as the LM709,2 in that it has a ±30V differential of the timing capacitor, C1, can be used. With most
    input voltage range, a +15V, -12V common mode other amplifiers, R2 must be reduced to keep from
    range with ±15V supplies and it can be compen- exceeding these ratings, which requires that C1 be
    sated with a single 30 pF capacitor. The LM102,3 increased. Nonetheless, even when large values are
    which is also used here, is designed specifically as a needed for C1, smaller polarized capacitors may be
    voltage follower and features a maximum input used by returning them to the positive supply volt-
    current of 10 nA and a 10V/p.s slew rate. age instead of ground.

    AN4-1
    LEVEL SHIFTING AMPLIFIER VOLTAGE COMPARATORS

    Frequently, in the design of linear equipment, it is The LM101 is well suited to comparator applica·
    necessary to take a voltage wh ich is referred to tions for two reasons: first, it has a large differen-
    some dc level and produce an amplified output tial input voltage range and, second, the output is
    which is referred to ground. The most straight· easily clamped to make it compatible with various
    forward way of doing this is to use a differential driver and logic circuits. It is true that it doesn't
    amplifier similar to that shown in Figure 2a. This have the speed of the LM7104 (10 Ils versus 40 ns,
    circuit, however, has the disadvantages that the under equivalent conditions); however, in many
    signal source is loaded by current from the input linear applications speed is not a problem and the
    divider, R3 and R4, and that the feedback resis· lower input currents along with higher voltage capa·
    tors must be very well matched to prevent errone- bility of the LM101 is a tremendous benefit.
    ous outputs from the common mode input signal.

    A circuit which does not have these problems is Two comparator circuits using the LM101 are
    shown in Figure 2b. Here, an F ET transistor on shown in Figure 3. The one in Figure 3a shows a
    the output of the operational amplifier produces clamping scheme which makes the output signal
    a voltage drop across the feedback resistor, R1, directly compatible with DTL or TTL integrated
    which is equal to the input voltage. The voltage circuits. An LM103 breakdown diode clamps the
    across R2 will then be equal to the input voltage output at OV or 4V in the low orhigh states, respec·
    multiplied by the ratio, R2/R1; and the common tively. This particular diode was chosen because it
    mode rejection will be as good as the basic rejec· has a sharp breakdown and low equivalent capaci-
    tion of the amplifier, independent of the resistor tance. When working as a comparator, the amplifier
    tolerances. This voltage is buffered by an LM 102 operates open loop so normally no frequency com·
    voltage follower to give a low impedance output. pensation is needed. Nonetheless, the stray capaci·
    tance between Pins 5 and 6 of the ampl ifier Should
    An advantage of the LM101 in this circuit is that be minimized to prevent low level oscillations when
    it will work with input voltages up to its positive the comparator is in the active region. If this be-
    supply voltages as long as the supplies are less than comes a problem, a 3 pF capacitor on the normal
    ±15V. compensation terminals will eliminate it.

    I o~.v. ~:~
    ____ ". __-,

    To\~ ~~~-DUTPUT OUTPUT

    C1 C1
    IDpF IOpF

    a. Standard Differential Amplifier b. LeveI·lsolation Amplifier

    FIGURE 2. Level-Shifting Amplifiers

    .28V

    OUTPtJT

    a. Comparator for Driving DTL b. Comparator and Lamp Driver


    and TTL Integrated Circuits

    FIGURE 3. Voltage Comparator Curcuits

    AN4-2
    Figure 3b shows the connection of the LM101 as a
    comparator and lamp driver. 01 switches the lamp,
    with R2 limiting the current surge resulting from
    turning on a cold lamp. R1 determines the base
    drive to 01 while D1 keeps the amplifier from put-
    ting excessive reverse bias on the emitter-base junc-
    tion of 01 when it turns off.

    MORE OUTPUT CURRENT SWING

    Because almost all monolithic amplifiers use class-B


    output stages, they have good loaded output volt-
    age swings, delivering ±10V at 5 mA with ±15V
    supplies. Demanding much more current from the
    integrated circuit would require, for one, that the FIGURE 5. FET Operational Amplifier
    output transistors be made considerably larger. In
    addition, the increased dissipation could give rise
    to troublesome thermal gradients on the chip as composite circuit has roughly the same gain as the
    well as excessive package heating in high-tempera- integrated circuit by itself and is compensated for
    ture applications. It is therefore advisable to use unity gain with a 30 pF capacitor as shown. Al-
    an external buffer when large output currents are though it works well as a summing amplifier, the
    needed. circuit leaves something to be desired in applica-
    tions requiring high common mode rejection. This
    A simple way of accomplishing this is shown in happens both because resistors are used for current
    Figure 4. A pair of complementary transistors are sources and because the FET's by themself do not
    used on the output of the LM10l to get the in- have good common mode rejection.
    creased current swing. Although this circuit does
    have a dead zone, it can be neglected at frequen- STORAGE CIRCUITS
    cies below 100Hz because of the high gain of the
    amplifier. Rl is included to eliminate parasitic oscil- A sample-and-hold circuit which combines the low
    lations from the output transistors. In addition, ade- input current of FET's with the low offset voltage
    quate bypassing should be used on the collectors of monolithic amplifiers is shown in Figure 6. The
    of the output transistors to insure that the output circuit is a unity gain ampl ifier employing an opera-
    signal is not coupled back into the amplifier. This tional amplifier and an FET source follower. In
    circuit does not have current limiting, but it can be operation, when the sample switch, 02, is turned
    added by putting 50n resistors in series with the on, it closes the feedback loop to make the output
    collectors of 01 and 02. equal to the input, differing only by the offset volt-
    age of the LM101. When the switch is opened, the
    charge stored on C2 holds the output at a level
    equal to the last value of the input voltage.
    Some care must be taken in the selection of the
    OIJTPUr
    holding capacitor. Certain types, including paper and
    mylar, exhibit a polarization phenomenon which
    causes the sampled voltage to drop off by about
    50 mV, and then stabilize, when the capacitor is
    exercised over a 5V range during the sample inter-
    val. This drop off has a time constant in the order
    of seconds. The effect, however, can be minimized
    FIGURE 4. High Current Output Buffer by using capacitors with teflon, polyethylene, glass
    or polycarbonate dielectrics.
    AN FET AMPLIFIER Although this circuit does not have a particularly
    low output resistance, fixed loads do not upset the
    For ambient temperatures less than about 70°C, accuracy since the loading is automatically com-
    junction field effect transistors can give exception- pensated for during the sample interval. However,
    ally low input currents when they are used on the if the load is expected to change after sampling, a
    input stage of an operational amplifier. However, buffer such as the LM 1 02 must be added between
    monolithic FET amplifiers are not now available the F ET and the output.
    since it is no simple matter to diffuse high quality
    FET's on the same chip as the amplifier. Nonethe- A second pole is introduced into the loop response
    less, it is possible to make a good FET amplifier of the amplifier by the switch resistance and the
    using a discrete F ET pair in conjunction with a holding capacitor, C2. This can cause problems with
    monolithic circuit. overshoot or oscillation if it is not compensated for
    by adding a resistor, R1, in series with the LM101
    Such a circuit is illustrated in Figure 5. A matched compensation capacitor such that the breakpoint
    FET pair, connected as source followers, is put in of the R 1 Cl combination is roughly equal to that
    front of an integrated operational amplifier. The of the switch and the holding capacitor.

    AN4-3
    01
    DUTPUT_....._ _ _ _ _....._ _ _-":..":..:·':-.·- V '

    INPUT el'

    CI
    30pF
    I"'" ·PolycarbanatedlllectriccaplICltor

    FIGURE 6. Low Drift Sample and Hold

    It is possible to use an MaS transistor for 01 NON-LINEAR AMPLIFIERS


    without worrying about the threshold stability.
    The threshold voltage is balanced out during every When a non-linear transfer function is needed from
    sample interval so only the short·term threshold an operational amplifier, many methods of obtain-
    stability is important. When MaS transistors are ing it present themself. However, they usually re-
    used along with mechanical switches, drift rates quire diodes and are therefore difficult to tempera-
    less than 10 mV/min can be realized. ture compensate for accurate breakpoints. One way
    of getting around this is to make the output swing
    so large that the diode threshold is negligible by
    comparison, but this is not always practical.
    Additional features of the circuit are that the am·
    plifier acts as a buffer so that the circuit does not A method of producing very sharp, temperature-
    load the input signal. Further, gain can also be pro- stable breakpoints in the transfer function of an
    vided by feeding back to the inverting input of operational amplifier is shown in Figure 8. For
    the LM101 through a resistive divider instead of small input signals, the gain is determined by R1
    directly. and R2. Both 02 and 03 are conducting to some
    degree, but they do not affect the gain because
    their current gain is high and they do not feed any
    appreciable current back into the summing mode.
    The peak detector in Figure 7 is similar in many
    When the output voltage rises to 2V (determined
    respects to the sample-and-hold circuit. A diode is
    by R3, R4 and V-), 03 draws enough current to
    used in place of the sampling switch. Connected as
    saturate, connecting R4 in parallel with R2. This
    shown, it will conduct whenever the input is greater
    cuts the gain in half. Similarly, when the output
    than the output, so the output will be equal to the
    voltage rises to 4V, 02 will saturate, again halving
    peak value of the input voltage. In this case, an
    the gain.
    LM 102 is used as a buffer for the storage capacitor,
    giving low drift along with a low output resistance. Temperature compensation is achieved in this cir-
    cuit by including 01 and 04. 04 compensates the
    emitter-base voltage of 02 and 03 to keep the
    voltage across the feedback resistors, R4 and R6,
    As with the sample and hold, the differential input very nearly equal to the output voltage while 01
    voltage range of the LM 101 permits differences be· compensates for the emitter base voltage of these
    tween the input and output voltages when the cir- transistors as they go into saturation, making the
    cuit is holding. voltage across R3 and R5 equal to the negative sup-
    ply voltage. A detrimental effect of 04 is that it
    causes the output resistance of the amplifier to in-
    crease at high output levels. It may therefore be
    necessary to use an output buffer if the circuit
    must drive an appreciable load.

    SERVO PREAMPLIFIER

    In certain servo systems, it is desirable to get the


    D1
    FD3DO
    rate signal required for loop stability from some
    sort of electrical, lead network. This can, for ex-
    ample, be accomplished with reactive elements in
    the feedback network of the servo preamplifier.

    Many saturating servo amplifiers operate over an


    extremely wide dynamic range. For example, the
    CI
    lO" maximum error signal could easily be 1000 times
    the signal required to saturate the system. Cases
    FIGURE 7. Positive Peak Detector with like this create problems with electrical rate net-
    Buffered Output works because they cannot be placed in any part

    AN4-4
    02
    R~
    187~K 2N2G05
    ~---'WIo----,
    "'
    'OK

    Q3 R4
    ......~'IM_i-_ _--;:2N2601'_ _...',..DO""_ _ -+
    V---15V
    A2
    lOOK

    RI
    la'
    INPUT_-JVVV-_ _~"

    "
    JOpf

    FIGURE 8. Nonlinear Operational Amplifier with Temperature·Compensated Breakpoints

    of the system which saturates. If the signal into the corporating the proper resistors and capacitors in
    rate network saturates, a rate signal wi" only be the feedback circuit of an amplifier. Many of these
    developed over a narrow range of system operation; circuits are described in reference 5. Multiplication
    and instability wi" result when the error becomes and division, however, are a bit more difficult.
    large. Attempts to place the rate networks in front These operations are usually performed by taking
    of the error amplifier or make the error amplifier the logarithms of the quantities, adding or subtract·
    Iinear over the enti re range of error signals fre- ing as required and then taking the antilog.
    quently gives rise to excessive dc error from signal
    attenuation. At first glance, it might appear that obtaining the
    log of a voltage is difficult; but it has been shown 6
    These problems can be largely overcome using the that the emitter·base voltage of a silicon transistor
    kind of circuit shown in Figure 9. This amplifier follows thelogof its co" ector current over as many
    operates in the linear mode until the output voltage as nine decades. Th is means that common transis·
    reaches approximately 3V with 30 /lA output cur· tors can be used to perform the log and antilog
    rent from the solar cell sensors. At th is point the operations.
    breakdown diodes in the feedback loop begin to
    conduct, drastically reducing the gain. However, a A circuit wh ich performs both multiplication and
    rate signal wi" still be developed because current is division in this fashion is shown in Figure 10. It
    being fed back into the rate network (R 1, R2 and gives an output which is proportional to the prod·
    Cl) just as it would if the amplifier had remained cut of two inputs divided by a third, and it is about
    in the linear operating region. In fact, the amplifier the same complexity as a divider alone.
    wi" not actually saturate until the error current
    reaches 6 mA, which would be the same as having The circuit consists of three log converters and an
    a linear amplifier with a ±600V output swing. antilog generator. Log converters similar to these
    have been described elsewhere,7 but a brief descrip·
    Q1
    LM103
    24V D2
    tion follows. Taking amplifier Al, a logging tran-
    sistor, 01, is inserted in the feedback loop such
    that its collector current is equal to the input volt-
    age divided by the input resistor, Rl. Hence, the
    emitter-base voltage of 01 will vary as the log of
    "
    50"F~
    the input voltage, El.

    A2 is a similar amplifier operating with logging


    OUTPUT
    transistor, 02. The emitter-base junctions of 01
    and 02 are connected in series, adding the log
    voltages. The third log converter produces the log
    of E3. This is series-connected with the antilog
    C2
    30pf transistor, 04; and the combination is hooked in
    para"el with the output of the other two log con-
    FIGURE 9. Saturating Servo Preamplifier with vertors. Therefore, the emitter-base of 04 wi" see
    Rate Feedback the log of E3 subtracted from the sum of the logs
    of El and E2. Since the collector current of a tran-
    COMPUTING CIRCUITS sistor varies as the exponent of the emitter-base
    voltage, the collector current of 04 wi" be pro-
    In analog computation it is a relatively simple portional to the product of Eland E2 divided by
    matter to perform such operations as addition, E3. This current is fed to the summing amplifier,
    subtraction, integration and differentiation by in· A4, giving the desired output.

    AN4-5
    '""

    "' 4
    6,-....',."........ eo
    6 "
    ""

    02 OJ
    lN457 lM57

    C1 C3
    JOOpF 3DOpF

    ·12N3728m.1Chedpa"5

    FIGURE 10. Analog Multiplier/Divider

    This circuit can give 1·percent accuracy for input The logging transistors provide a gain which is de-
    voltages from 500 mV to 50V. To get this precision pendent on their operating level. which complicates
    at lower input voltages. the offset of the amplifiers frequency compensation. Resistors (R3. R6 and
    handling them must be individually balanced out. R71 are put in the amplifier output to limit the
    The zener diode. D4. increases the collector-base maximum loop gain. and the compensation capaci-
    voltage across the logging transistors to improve tor is chosen to correspond with this gain. As a
    high current operation. It is not needed. and is in result. the amplifiers are not especially designed for
    fact undesirable. when these transistors are running speed. but techniques for optimizing this parameter
    at currents less than 0.3 mAo At currents above are given in reference 6.
    0.3 mAo the lead resistances of the transistors can
    become important (0.25>2 is 1-percent at 1 mAl Finally. clamp diodes D1 through D3. prevent ex-
    so the transistors should be installed with short ceeding the maximum reverse emitter-base voltage
    leads and no sockets. of the logging transistors with negative inputs.

    ROOT EXTRACTOR *

    Taking the root of a number using log converters


    is a fairly simple matter. All that is needed is to
    An important feature of this circuit is that its oper- take the log of a voltage. divide it by. say 1/2 for
    ation is independent of temperature because the the square root. and then take the antilog. A cir-
    scale factor change in the log converter with tem- cuit which accomplishes this is shown in Figure 11.
    perature is compensated by an equal change in the A 1 and 01 form the log converter for the input
    scale factor of the antilog generator. It is only re- signal. This feeds 02 which produces a level shift
    quired that 01, 02. 03 and 04 be at the same to give zero voltage into the R4. R5 divider for a
    temperature_ Dual transistors should be used and 1 V input. This divider reduces the log voltage by
    arranged as shown in the figure so that thermal mis- the ratio for the root desired and drives the buffer
    matches between cans appear as inaccuracies in amplifier. A2. A2 has a second level shifting diode.
    scale factor (0.3-percenttC) rather than a balance 03. its feedback network wh ich gives the output
    error (8-percenttC). R12 is a balance potentiom- voltage needed to get a 1 V output from the antilog
    eter which nulls out the offset voltages of all the generator. consisting of A3 and 04. with a unity
    logging transistors. It is adjusted by setting all input
    *The "extraction" used here doubtless has origin in the
    voltages equal to 2V and adjusting for a 2V output dental operation most of us would fear less than having
    voltage. to find even a square root without tables or other aids.

    AN4-6
    R8
    lSDK

    RIO

    '"'
    RI
    'OK
    1MI.......41-!1
    INPUT .......

    R9
    '"" '"'
    CI C2 C3
    JOOpF loapF 36pF

    ·tZN3128 ml1chld PIU,

    FIGURE 11. Root Extractor

    input. The offset voltages of the transistors are ing, inadequate supply bypassing or improper fre-
    nulled out by imbalancing R6 and RB to give 1V quency compensation.
    output for 1 V input, since any root of one is one.
    In frequency compensating an operational ampli·
    02 and 03 are connected as diodes in order to fier, it is best to follow the manufacturer's rec·
    simplify the circuitry. This doesn't introduce prob- ommendations. However, if operating speed and
    lems because both operate over a very limited cur- frequency response is not a consideration, a greater
    rent range, and it is really only required that they stability margin can ususally be obtained by in-
    match. R7 is a gain-compensating resistor which creasing the size of the compensation capacitors.
    keeps the currents in 02 and 03 equal with changes For example, replacing the 30 pF compensation
    in signal level. capacitor on the LM10l with a 300 pF capacitor
    will make it ten times less susceptible to oscillation
    As with the multiplier/divider, the circuit is insen- problems in the unity-gain connection. Similarly,
    sitive to temperature as long as all the transistors on the LM709, using 0.05 pF, 1.5 k!1, 2000 pF
    are at the same temperature. Using transistor pairs and 51!1 components instead of 5000 pF, 1.5 k!1,
    and matching them as shown minimizes the effects 200 pF and 51!1 will give 20 dB more stability
    of gradients. margin. Capacitor values less than those specified
    by the manufacturer for a particular gain connec·
    The circuit has l-percent accuracy for input volt- tion should not be used since they will make the
    ages between 0.5 and 50V. For lower input volt- amplifier more sensitive to strays and capacitive
    ages, Aland A3 must have their offsets balanced loading, or the circuit can even oscillate with worst-
    out individually. case units.

    The basic requirement for frequency compensating


    a feedback amplifier is to keep the frequency roll-
    FREOUENCY COMPENSATION HINTS off of the loop gain from exceeding 12 dB/octave
    when it goes through unity gain. Figure 12a shows
    The ease of designing with operational amplifiers what is meant by loop gain. The feedback loop is
    sometimes obscures some of the rules which must broken at the output, and the input sources are
    be followed with any feedback amplifier to keep replaced by their equivalent impedance. Then the
    it from oscillating. In general, these problems stem response is measured such that the feedback net-
    from stray capacitance, excessive capacitive load- work is included.

    "
    ,------....-<,,,

    "
    FREQUENCV-HI

    a. Measuring Loop Gain b. TVpical Response

    FIGURE 12. Illustrating Loop Gain

    AN4-7
    Figure 12b gives typical responses for both uncom-
    pensated and compensated amplifiers. An uncom-
    pensated amplifier generally rolls off at 6 dB/octave,
    then 12 dB/octave and even 1B dB/octave as vari-
    "."""'\,.,....- - - 1
    ous frequency-limiting effects within the amplifie~
    ~-~-EQUT
    come into play. If a loop with this kind of response
    were closed, it would oscillate. Frequency compen-
    sation causes the gain to roll off at a uniform 6 dB/
    octave right down through unity gain. This allows
    some margin for excess rolloff in the external
    circuitry. FIGURE 14. Compensating Stray Input
    Capacitance
    Some of the external influences which can affect shown in Figure 15. The capacitive load is isolated
    the stability of an operational amplifier is shown in from the output of the amplifier with R4 which has
    Figure 13. One is the load capacitance which can a value of 50n to lOOn for both the LM 101 and
    come from wiring, cables or an actual capacitor on the LM709. At high frequencies, the feedback path
    the output. This capacitance works against the out- is throU{lh the lead capacitor, Cl, so that the lag
    put impedance of the amplifier to attenuate high produced by the load capacitance does not cause
    frequencies. If this added rolloff occurs before the instability. To use this circuit, the amplifier must
    loop gain goes through zero, it can cause instability. be compensated for unity gain, regardless of the
    It should be remembered that this single rolloff closed loop dc gain. The value of Cl is not too
    point can give more than 6 dB/octave roll off since important, but at a minimum its capacitive reac-
    the output impedance of the amplifier can be in- tance should be one-tenth the resistance of R2 at
    creasing with frequency. the unity-gain crossover frequency of the amplifier.

    ~---......- .....-<''"
    "......."""....-1
    >-....-+''0' >_M_-+_lOUT

    FIGURE 13. External Capacitances That Affect FIGURE 15. Compensating for Very Large
    Stability Capacitive Loads

    A second source of excess rolloff is stray capaci- When an operational amplifier is operated open
    tance on the inverting input. This becomes ex- loop, it might appear at first glance that it needs
    tremely important with large feedback resistors as no frequency compensation. However, this is not
    might be used with an FET-input amplifier. A rela- always the case because the external compensation
    tively simple method of compensating for this stray is sometimes required to stabilize internal feedback
    capacitance is shown in Figure 14: a lead capacitor, loops.
    Cl, put across the feedback resistor. Ideally, the
    ratio of the stray capacitance to the lead capacitor
    The LM10l will not oscillate when operated open
    should be equal to the closed-loop gain of the am- loop, although there may be problems if the capaci-
    plifier. However, the lead capacitor can be made tance between the balance terminal on pin 5 and
    larger as long as the amplifier is compensated for the output is not held to an absolute minimum.
    unity gain. The only disadvantage of doing this is Feedback between these two points is regenerative
    that it will reduce the bandwidth of the amplifier. if it is not balanced out with a larger feedback
    Oscillations can also result if there is a large resis- capacitance across the compensation terminals.
    tance on the non-inverting input of the amplifier. Usually a 3 pF compensation capacitor will com-
    The differential input impedance of the amplifier pletely eliminate the problem. The LM709 will os-
    falls off at high frequencies (especially with bi- cillate when operated open loop unless a 10 pF
    polar input transistors) so this resistor can produce capacitor is connected across the input compensa-
    troublesome roll off if it is much greater than 10K, tion terminals and a 3 pF capacitor is connected on
    with most amplifiers. This is easily corrected by by- the output compensation terminals.
    passing the resistor to ground.

    When the capacitive load on an integrated amplifier Problems encountered with supply bypassing are
    is much greater than 100 pF, some consideration insidious in that they will hardly ever show up in a
    must be given to its effect on stability. Even though Nyquist plot. This problem has not really been
    the amplifier does not oscillate readily, there may thoroughly investigated, probably because one sure
    be a worst-case set of conditions under which it cure is known: bypass the positive and negative
    will. However, the amplifier can be stabilized for supply terminals of each amplifier to ground with
    any value of capacitive loading using the circuit at least a O.OlIlF capacitor.

    AN4-8
    For example, a LM10l can take over 1 mH induc- it is not too helpful in determining if the amplifier
    tance in either supply lead without oscillation. This is indeed stable. The reason is that most problems
    should not suggest that they should be run without in a well-designed system are caused by secondary
    bypass capacitors. It has been established that 100 effects - which occur only under certain conditions
    LM10l's on a single printed circuit board with com- of output Voltage, load current, capacitive loading,
    mon supply busses will oscillate if the supplies are temperature, etc. Making frequency-phase plots
    not bypassed about every fifth device. This happens under all these conditions would require unreason-
    even though the inputs and outputs are completely able amounts of time, so it is invariably not done.
    isolated.

    The LM709, on the other hand, will oscillate under A better check on stability is the small-signal tran-
    many load conditions with as little as 18 inches of sient response. It can be shown mathematically that
    wire between the negative supply lead and a bypass the transient response of a network has a one-for-
    capacitor. Therefore, it is almost essential to have a one correspondence with the frequency domain
    set of bypass capacitors for every device. response. t The advantage of transient response tests
    is that they are displayed instantaneously on an
    oscilloscope, so it is reasonable to test a circuit
    under a wide range of conditions.
    Operational amplifiers are specified for power sup-
    ply rejection at frequencies less than the first break
    frequency of the open loop gain. At higher fre-
    quencies, the rejection can be reduced depending Exact methods of analysis using transient response
    on how the amplifier is frequency compensated. will not be presented here. Th is is not because these
    For both the LM 101 and LM709, the rejection of methods are difficult, although they are. Instead, it
    high frequency signals on the positive supply is is because it is very easy to determine which condi-
    excellent. However, the situation is different for tions are unfavorable from the overshoot and ring-
    the negative supplies. These two amplifiers have ing on the step response. The stability margin can
    compensation capacitors from the output down to be determined much more easily by how much
    a signal point which is referred to the negative sup- greater the aggravating conditions can be made
    ply, causing the high frequency rejection for the before the circuit oscillates than by analysis of the
    negative supply to be much reduced. It is therefore response under given conditions. A little practice
    important to have sufficient bypassing on the nega- with this technique can quickly yield much better
    tive supply to remove transients if they can cause results than classical methods even for the inexpe-
    trouble appearing on the output. One fairlY large rienced engineer.
    (22 j.!F) tantalum capacitor on the negative power
    lead for each printed-circuit card is usually enough
    to solve potential problems.
    SUMMARY

    A number of circuits using operational amplifiers


    When high-current buffers are used in conjunction have been proposed to show their versatility in cir-
    with operational amplifiers, supply bypassing and cuit design. These have ranged from low frequency
    decoupling are even more important since they can oscillators through circuits for complex analog
    feed a considerable amount of signal back into the computation. Because of the low cost of monolithic
    supply lines. For reference, bypass capacitors of at amplifiers, it is almost foolish to design dc ampli-
    least 0.1 j.!F are required for a 50 mA buffer. fiers without integrated circuits. Moreover, the price
    makes it practical to take advantage of operational-
    amplifier performance in a variety of circuits where
    they are not normally used.
    When emitter followers are used to drive long ca-
    bles, additional precautions are required. An emitter
    follower by itself - which is not contained in a Many of the potential oscillation problems that
    feedback loop - will frequently oscillate when con- can be encountered in both discrete and integrated
    nected to a long length of cable. When an emitter operational amplifiers were described, and some
    follower is connected to the output of an opera- conservative solutions to these problems were pre-
    tional amplifier, it can produce oscillations that sented. The areas discussed included stray capaci-
    will persist no matter how the loop gain is compen- tance, capacitive loading and supply bypassing.
    sated. An analysis of why this happens is not very Finally, a simplified method of quickly testing the
    enlightening, so suffice it to say that these oscilla- stability of amplifier circuits over a wide range of
    tions can usually be eliminated by putting a ferrite operating conditions was suggested.
    bead8 between the emitter follower and the cable.

    tThe frequency·domain characteristics can be determined


    Considering the loop gain of an amplifier is a valu- from the impulse response of a network and this is di-
    able tool in understanding the influence of various rectly relatable to the step response through the convo-
    factors on the stability of feedback amplifiers_ But lution integral.

    AN4-9
    REFERENC.ES

    1. R. J. Widlar, "Monolithic Op Amp with Simpli· 5. "Handbook of Operational Amplifier Appli-


    fied Frequency Compensation," EEE, Vol. IS, cations," Burr-Brown Research Corporation,
    No.7, pp. 58·63, July. 1967. Tucson, Arizona.

    2. R. J. Widlar, "A Unique Circuit Design for a 6. J. F. Gibbons and H. S. Horn, "A Circuit with
    High Performance Operational Ampl ifier Espe- Logarithmic Transfer Response ov.er Nine De-
    cially Suited to Monolithic Construction," Proc. cades," IEEE Trans. on Circuit Theory, Vol.
    of NEC, Vol. XXI, pp. 85-89, October, 1965. CT-ll, pp. 378-384, September, 1964.

    3. R. J. Widlar, "A Fast Integrated Voltage Fol· 7. R. J. Widlar and J. N. Giles, "Avoid Over-
    lower with Low Input Current," National Semi- Integration," Electronic Design, Vol. 14, No.3,
    conductor AN-5, March, 1968. pp. 56-62, Feb. I, 1966_

    4. R. J. Widlar, "The Operation and Use of a Fast 8. Leslie Solomon, "Ferrite 8eads," Electronics
    Integrated Circuit Comparator," Fairchild Semi- World, pp. 42-43, October, 1966.
    conductorAPP-116, Februarv,1966.

    AN4-10'
    r-----------------------------------------------------------------~
    »2
    May 1968 .
    c.n

    »
    ."
    »
    en
    -f
    A FAST INTEGRATED VOLTAGE
    FOLLOWER WITH LOW INPUT 2
    -f
    CURRENT m
    C)
    ::D
    INTRODUCTION

    Most integrated operational amplifiers on the mar- follower output. Since current sources are used on
    ~
    m
    ket today have serious limitations in many voltage the emitter of {he differential pair and as a col- C
    follower applications. They are often too slow lector load, it is practical to get an open loop
    because a voltage follower requires maximum
    frequency compensation, reducing slew rate to
    voltage gain of 3000 from a single stage. The
    collector of the input transistor, 01, is boot-
    o<
    somewhere between 0.1 Vl/1s and 1 Vl/1s.1,2 strapped to the output to increase gain and raise !:t
    Secondly, voltage followers are most frequently the input resistance. It also eliminates leakage »
    C)
    used as buffer amplifiers from high impedance currents by operating the input at zero collector-
    sources; but the input current of popular ampli- base voltage. A class-A output stage is used since it
    m
    fiers gives excessive dc offset when operated with behaves better at high frequencies with capacitive ."
    sou rce resistances much above 10 KD.. loads. Although frequency compensation is not or-
    always required with this configuration, R 1 and r-
    The design of a monolithic voltage follower which C1 have been included to improve stability with o
    combines low offset voltage with an input current
    of 2 nA and a 10 Vl/1s slew rate is described here.
    capacitive loading. The compensation network is
    placed such that the circuit has good transient re-
    :E
    m
    This performance is realized using improved bi- jection on both the positive and the negative ::D
    polar transistors along with an operational ampli- supplies.
    fier circuit design which is optimized for the :E
    J
    .------.---,.
    voltage follower configuration. The device, which :::j
    Isa~1 ~
    is designed to operate from supply voltages be- ~
    tween ±12V and ±15V, features a 10 MHz band-
    r-
    width along with a 3 pF input capacitance and a
    minimum input resistance of 10,000 MD.. In addi- ~... Ol
    o
    tion, it requires no external components for fre- :E
    quency compensation and incorporates continuous
    short circuit protection. 2
    "'tI
    CIRCUIT DESCRIPTION INPUT
    c:
    -f
    There are fewer problems encountered in designing B )'m' n
    a high performance voltage follower than a similar L-_ _ _ _ _ _ _ _- - , -
    c:
    general purpose amplifier. For one, no level shift- ::D
    ing is required so complementary transistors are ::D
    unnecessary as gain stages. Hence, it is possible to FIGURE 1. Basic Configuration of the Voltage m
    Follower 2
    get better high frequency performance since this -f
    has been limited in the past by the performance of
    the PNp3 transistors that can be made in mono- INPUT STAGE
    lith ic circuits. Secondly, because 1DO-percent feed-
    back is used, the open loop gai n does not have to In order to get fast slewing, it is necessary to
    be as high as a general purpose amplifier; so a operate the differential amplifier at a fairly high
    simpler circuit, which is easier to frequency com- current for an input stage. Therefore, a Darlington
    pensate, can be used. Finally, with a fixed configu- connection is used on the input transistors to get
    ration such as a voltage follower, the input stage low input current. However, as can be seen from
    can be included within the compensation network. Figure 2, bleed resistors, R 1 and R2, operate the
    This makes it easier to get fast slewing without input transistors at a current wh ich is large by
    having to provide unreasonably large small-signal comparison to the base current of 03 and 04. This
    bandwidths which would make the amplifier more keeps 01 and 02 from seeing mismatches in the
    prone to instabilities. base currents of 03 and 04, which is the largest
    source of offset voltage in an ordinary Darlington
    Figure 1 demonstrates how simple a voltage differential stage. This bleed current also doubles
    follower circuit can be. This circuit uses a single- the gain of the stage and improves the high fre-
    stage differential amplifier with an emitter- quency performance.

    AN5-1
    Using a Darlington stage is not the entire secret to circuitry which is represented by current sources
    getting low input currents. 4 With the integrated in Figures 1 and 2. In order to realize low offset
    circuit transistors that have been available in the voltage, the current source on the collector of 02
    past, reducing the collector current by a factor must supply a current which is exactly one-half of
    of 10 would only reduce the base current by a the input pair emitter current.
    factor of 3, since the current gain falls off rapidly
    at low collector currents. In order to get any real To do this, diode-connected transistors, 014 and
    improvement from operating at low currents, it 015, provide a bias voltage which is regulated
    was necessary to make better transistors. The against supply voltage variations for the current
    devices used here have a typical cu rrent gain of source transistors, 010, 012 and 013. 012 is the
    1000 at 2 /J.A collector current. current source for the input pair, while 013 gen-

    ,--.....- ....-,. r---.----~---.---,.

    11 SmA

    "'
    no

    ~--~--~----.---,-
    FIGURE 2. Partial Schematic of the
    LM102 Voltage Follower FIGURE 3. Simplified Schematic of
    Biasing Circuitry
    Operating at 2 /J.A currents requires large resistance
    values which are not easily fabricated in integrated erates a current which is one-half the output cur-
    circuits. Therefore, the bleed circuit on the input rent of 012. This is accomplished by making R9
    stage had to be designed to minimize this resis- twice as large as R8 and 013 one-half the size of
    tance. R1 and R2 are operated with a 160 m V 012. The output current of 013 is fed to 018,
    drop across them, which is determined by the drop which biases 019. If it is assumed that 018 and
    across R3 plus the emitter-base voltage difference 019 are well matched and have large current gains,
    between 05 and the differential transistors, 03 the output current of 019 wi II be equal to the
    and 04. This difference is 100 mV since the differ- collector current of 013 - or one-half the emitter
    ential transistors are operated at roughly 35 times current of the input pair, as required.
    the current through 05. 5
    ADDITIONAL DETAILS
    Pinch resistors had to be used for R1 and R2 to
    get 80 KD within a reasonable surface area. They In practice, it cannot be assumed that the current
    were also necessary to keep the parasitic capaci- gain of the PNP transistors, 018 and 019, is
    tance of the resistors small, as it could severely large. 6 In fact, the current gain could be as low as
    degrade the large signal pulse response. However, unity. As a result, additional circuitry is required
    pinch resistors have a large positive temperature to get proper operation. Figure 4 shows how this is
    coefficient wh ich causes the operating current of done.
    01 and 02 to increase to 3.5/J.A at -55°C and
    decrease to 1.4 /J.A at 125°C. Instead of connecting the base directly back to the
    collector, emitter follower buffers, 016 and 017,
    Figure 2 shows that an extra transistor, 08, has are used to isolate the base current from the col-
    been added on the collectors of 02 and 04. Th is lector of 018. Level shifting diodes, Dl and D2,
    forms a casco de stage which operates 02 at near are included so that 018 is operated at approxi-
    zero collector base voltage, as is 01. An additional mately the same collector base voltage as 019,
    emitter follower is included on the output to when the output of the amplifier is at zero, further
    further reduce output resistance. improving the match.

    BIASING CIRCUITRY The RC network, R 11 and C2, is included to sup·


    press oscillations in this feedback loop. The volt-
    Figure 3 is a simplified schematic of the biasing age drop across C2 is less than a couple of volts so

    AN5-2
    a junction capacitor can be fabricated from the creasing gain. Taps on these resistors are brough t
    emitter and base diffusions of the NPN transistors. out to provide for offset balancing. The tap point
    With this, the required capacitance can be ob· is selected to give a smooth ±20 mV adjustment
    tained in a reasonable area of the chip with no range when a 1 K potentiometer is connected be·
    additional process steps, as would be required if an tween the balance terminals and the positive
    MOS capacitor were used. The same is true, inci· supply.
    dentally, for Cl.
    The output is inherently short·circuit proof in the
    A class·A output stage is used primarily for sim· negative direction. Current limiting for positive
    plicity, although the higher quiescent current in outputs is provided by 09 and R6. Howeyer, when
    the output stage improves stability with capacitive operating from low source resistances, a 2 Kn to
    loads. The emitter of the current sink, 010, is 10 Kn resistor must be added in series with the
    brought out so that an external resistor can be input, since the input is clamped directly to the
    connected between it and the negative supply for output through D3 and 011 which protect the
    increased output current in applications where the input transistors from overvoltage. This resistor
    was not included on the chip because it is difficult
    to locate a diffused resistor in an isolation region
    r---~+-+-~---------------T--~---V' where it would be effective yet not contribute to
    input leakage current at high temperatures.

    A photomicrograph of the LM 102 is shown in Fig·


    ure 5. Although the schematic diagram of the
    circuit appears complicated, it fits neatly on a
    49 x 49 mil·square die.

    PERFORMANCE
    J-___.....-+-"-------OUTPUT
    The electrical characteristics of the LM102 are
    summarized in Table I. It is evident from this that
    the primary design objectives, high speed and low
    input current, have indeed been achieved.

    Offset Voltage 2.5mV


    Input Current 3 nA
    Input Resistance 1012n
    FIGURE 4. Complete Schematic Diagram
    Voltage Gain 0.9995
    OUtput Resistance 1.0n
    OutP~t Voltage Swing ±13V
    Slew R'ate 10V/lIs
    Bandwidth 10MHz
    I npu t Capacitance 3 pF
    Supply Current 3.5mA

    TABLE I. Typical Electrical Characteristics of the


    LM102

    The low input bias current of the voltage follower


    is illustrated in Figure 6. It can be seen that the
    input current reaches a minimum at 85°C but
    remains low up to 125°C. This suggests operating
    the LM102 in a temperature stabilized component
    oven fo~ wide temperature range applications. If
    this is done, the LM102 will give input currents
    FIGURE 5. Photomicrograph of the LM102 wh ich are considerably better than can be realized
    with FET amplifiers over a ·55°C to 125°C tem·
    higher dissipation can be tolerated. The current perature range. In addition, the temperature stabi·
    source is biased from the collector of a low gain lization will greatly reduce the offset voltage drift.
    lateral PNP transistor, 014, so that the bias voltage
    for the input stage current sources will not be Figure 7 is a plot of the frequency response of the
    greatly affected when 010 saturates on negative lMl02. The low frequency gain figure corre-
    signals. sponds to an open loop gain of about 2000.
    Although this sounds low for an operational ampli·
    Resistors are included in series with the emitters of fier, it should be remembered that a voltage
    the PNP current source transistors, 018 and 019, follower has 100·percent feedback so thp. gain
    to reduce their output conductance, thereby in· error is o,,!ly O.05·percent. Further; because of its

    AN5-3
    100 09999
    TA "'_55°C r-
    ~
    TA=25"C
    TA = 125°C
    1>- 0999 ~~
    z ~
    ~ 10
    ~
    >-
    ~
    0.99
    ~
    z
    f- Vs=±15V ~ r-
    I' 1/ ~
    ..... I"- ~ II I 11'"11
    1.0 0.9
    -55 -35 -15 5 25 45 85105125 lK 10K lOOK 1M
    TEMPERATURE lOCI " FREOUENCY (Hz)

    FIGURE 6. Input Bias Current FIGURE 7. Voltage Gain at Moderate


    Frequencies

    10 14
    v,.mv"'"
    5 I 12 TA " 25°C
    DISTORTION <5%
    IJ"'0 1,,,1 ~
    ~ 0
    10
    z
    ~ ... ,~=30kn '"z
    ~ -5 ~
    8
    w
    ;:'" .~~-? >-
    ~

    >-
    6
    ~ -10
    r, ~
    0
    4

    -15

    -20
    f- Vs: ±1;V
    T(iI 2

    0
    "-
    lOOK ,M 10M 10K lOOK ,M
    FREOUENCV (Hz) FREQUENCY (Hz)

    FIGURE 8. High Frequency Response FIGURE 9. Frequency Limited Output Swing

    100 10

    f= ~;~ "~V
    III -VOUT" ±IOV
    - Vs=±15V - r-
    ~~ t
    -
    z
    ""
    10f-

    f=
    TA " 12SoC::bll.
    TA = 25°C
    TA =_55°C_
    :::tIT rL
    , ~
    ~50
    - ,. ......,...
    I I
    ~~~ ~
    -- ....--
    in
    ~
    ~
    ~
    -.... ,.
    ,. ~

    1+
    >-
    ~
    1.0
    f- ~'
    >-
    ~
    ~20 P"
    0

    io-'"
    0.1 'O~
    lK 'OK lOOK 'M -55 -35 -15 5 25 45 65 85 105125
    FREOUENCY (Hz) TEMPERATURE (~CI

    FIGURE 10. Output Resistance FIGURE 11. Minimum Load Resistance for Rated
    Output Swing

    -..
    15 -15
    Vs= =15V
    !;a,.

    t"'oo.. . Vs=±15V - Rs" 10K

    ~ 10 ~
    =
    -10
    '"z ;-:. ~;-L
    ;.,~",-
    ~
    >- - -
    I-- -
    ~;<-
    "-"
    ~ I--I--
    ;< 1.1-- I-- ~
    >- ~
    ~-l ~~~
    <1'0,$0- -
    ~
    - - ~-:;: ::;f- - ~
    r-
    5- - {_ n >-
    ~ In ~ -5
    0 \
    I

    0
    0 '0 20 30 40
    0
    0 , 2 3
    '\
    4 5
    LOAD CURAENT {mAl LOAD CURRENTtmAI

    FIGURE 12. Positive Current Limiting FIGURE 13. Negative Current Limiting

    ANS-4
    8 while a lOOn resistor will enable the amplifier to
    1 give a ±10V swing with l.4K loads. The figure also
    6 shows the effect of temperature on the drive capa-
    5
    bility.
    4
    T""" l- i-- ... It should be remembered that increasing the drive
    3
    i"'" I-
    current will increase dissipation in the micro·
    1
    circuit. For example, when the amplifier is set up
    1
    Vr''i'" to drive ±lOV into a 2K load at 12SoC, the worst
    case dissipation increase will be lS0 mW (for a
    - -15
    -5535 5 25456585105125
    steady +10V output with load).
    TEMPERATURE (Oel

    FIGURE 14. Supply Current Figures 12 and 13 show the current limiting char-
    acteristics of the LM102. Figure 12, which gives
    better high frequency response, the LM102
    the positive output level as a function of load cur-
    actually has 10 times more gain than either the
    rent demonstrates the sharpness of the current
    LM 101 or the LM709 at frequencies greater than
    limiting. The short circuit current also drops as the
    10kHz. The gain of all these amplifiers is equal at
    chip heats up, reducing power dissipation.
    SOO Hz.

    It is difficult to measure the low frequency gain of Figure 13 gives the limiting characteristics in the
    a voltage follower directly because the gain error is negative direction. The circuit begins to limit at
    so small. However, it can be accomplished by lower currents since the available current is deter-
    grounding the input of the amplifier and driving mined by a fixed·current source. It should be
    both power supplies simultaneously with the noted that after the output swing first starts to fall
    desired input signal. The amplifier error can then off, further increases in load current are supplied
    be observed directly on the output. by the input through the protective clamp diodes,
    D3andQll.

    Figu re 8 gives the response of the amplifier at fre-


    Figure 14 is a plot of the current drain over a
    quencies up to 10 MHz. With a 10K source resis-
    -SSoC to 12SoC temperature range. The supply
    tance, the bandwidth is nearly 10 MHz. Some
    current does not increase appreciably over the
    peaking is evident, although it is not serious. At
    entire output voltage range, including saturation.
    higher source resistances, the bandwidth is reduced
    It is evident here that fast operation is obtained in
    by the 3 pF input capacitance as shown in the
    the follower without excessive power dissipation.
    figure.

    Feedback amplifiers generally have a full-signal SLEWING


    bandwidth which is considerably less than the
    small signal bandwidth. The LM102 is no excep· The fast slewing of the follower is demonstrated in
    tion. It can only deliver its rated output swing at Figure lS. A fairly large overshoot is evident for
    frequencies less than 60 kHz, as shown in Figure 9. positive-going input signals above about 4V. As
    shown in the figure, this can be eliminated by
    There is no standard way of measuring the fre- using a high speed clamp diode between the input
    quency limited output swing,7 but the criterion and the output (with the anode on the input).
    used here was that the total harmonic distortion Although there is an internal clamp diode in this
    be less than S-percent. position (D3 in Figure 4), it is of necessity a col·
    lector base diode which stores excess charge when
    it turns on with input signals wh ich rise faster than
    The output resistance of the follower is about H1 the output can follow. This stored charge causes
    as shown in Figure 10. This gives a gain error less the oversh oot.
    than O.01·percent with load resistances above 10K.
    At high frequencies as well as high temperatures, If the LM102 is driven from source resistances
    the output resistance increases because the open higher than 30K, the leading edge of the input
    loop gain of the amplifier falls off. pulse will always be slowed down enough by the
    input capacitance that the output can follow the
    input and the clamp diode is not needed. This is
    INCREASED OUTPUT SWING shown in Figure lSa.
    Figure 11 illustrates the function of the booster
    terminal on the output stage current sink. By Figure lSbdemonstratesthat the slew rate is about
    itself, the amplifier can only deliver its rated ±10V 10 VliJ.s in the slowest direction even including the
    output swing into load resistances greater than effects of overshoot. But because of its restricted
    S.7 Kn at 2SOC. With heavier loads, it will clip in output current swing in the negative direction, the
    the negative direction. A 300n resistor between device will not give this slew rate with capacitive
    pins Sand 4 extends the drive capability to 2.SK loads greater than 100 pF unless the output sink

    ANS-S
    a. 3K Source Resistance b. 30K Source Resistance

    FIGURE 15. Large Signal Pulse Response With and Without a Clamp Diode

    i-
    I
    __:___L
    . _,_L
    11_:
    I
    r
    I '
    j- j-- I -- .
    _-t_L __L_ . -
    1'+~:-'LL_!~t~: !
    -i-+--:WITHCLAMP:l-J-~
    --"-,

    .J..;j~~~'-I--HI
    + ..... _. . --. -.
    HORIZONTAL O.51'S/DIV.
    . ; I 'J-: I I
    a. 3K Source Resistance b. 30K Source Resistance

    FIGURE 16. Error Signal for 8V Input Pulse - With and Without a Clamp Diode

    current is increased with an external resistor on a ·55°C to +125°C temperature range. Again, the
    th e booster term inal. conditions here are 200 pF capacitive load with
    bypassed supplies.
    Figure 16 illustrates the fact that the settling time
    of the LM 102 to within 5 mV of its final value is The effect of unbypassed supplies is demonstrated
    less than 1.5 ps for an BV input pulse. These in Figure 19. The response was measured under
    photographs show the error signal, which is the the same conditions as Figure 17, except that
    difference between the input and the output, with there is 16" of wire between the device and the
    a ±4V rectangular pulse applied. bypass capacitors on the power supply. It is
    evident that the circuit is on the verge of becoming
    unstable with capacitive loading. This clearly
    STABILITY
    proves the advisability of properly bypassing the
    supplies on any high frequency amplifier.
    Figures 17 through 19 are indicative of the sta-
    bility of the amplifier under varying conditions of
    capacitive loading, temperature and supply by-
    passing. B Figure 17 gives the small signal transient OPERATING HINTS
    response with capacitive loading. These pictures
    were taken with both supplies bypassed to ground A number of precautions concerning the proper
    wi th 0.01 pF ceramic capacitors. With loads use of the LM102 have alreadY been given along
    approaching 200 pF, the circuit tends toward with hints on optimizing the performance in cer-
    instability. With capacitive loads much above this tain applications. These are worth repeating here.
    it will oscillate, although it will be stable again
    with more than 0.01 pF on the output. With the
    • The output is short circuit protected; how-
    larger capacitances, however, both the small signal
    ever, the input is clamped to the output to
    risetime and the slew rate will be reduced.
    prevent excessive voltage from being devel-
    oped across the input transistors. If the
    FigUre 18 shows how the stability is affected over ampl ifier is driven from low source imped-

    AN5-6
    ances, excessive current can flow through • The amplifier may oscillate when operated
    these clamp diodes when the output is with capacitive loads between 200 pF and
    shorted. This can be prevented by inserting a 0.01 MF.
    resistor larger than 3 KQ in series with the
    input. • As is the case with any high frequency
    amplifier, the power supply leads of the
    • The circuit cannot deliver its full slew rate LM 102 should be bypassed with capacitors
    into capacitive loads greater than 100 p F greater than 0.01 MF located as close as
    unless more sink current is provided on the possible to the device. This is particularly
    output with a resistor between pins 4 and 5. true if it is driving capacitive loads.

    ~~~--~-' i-
    Figure 20a gives the connection for getting full
    output swing into loads less than BK. The external
    resistor, R 1, should not be made less than 100Q as
    this could cause limiting on positive peaks. Fig-
    I ure 20b shows how to connect a potentiometer to
    balance out the offset voltage. Figure 20e gives the
    placement of a clamp diode which can be used to
    reduce the overshoot that occurs when the fol-
    lower is driven with large input pulses with a
    leading-edge slope greater than 10 V IMs. The diode
    is only needed, however, when the source resis-
    tance is less than 30K since the slope seen by the
    amplifier will be reduced by the input capacitance
    I with the higher source resistances.
    FIGURE 17. Small Signal Transient Response for
    C L = 10 pF (Top) and C L = 200 pF APPLICATIONS*
    (Bottom)
    The use of the LM102 in a switch circuit for
    driving the ladder network in an analog to digital
    converter is shown in Figure 21. Simple transistor
    switches, connected in the reverse mode for low
    saturation voltage, generate the OV and 5V levels
    for the ladder network. The switch output is
    buffered by A2 and A3 to give a low driving
    impedance in both the high and low states.

    The switch transistors can be driven directly from


    integrated logic circuits. Resistors R7 and RB limit
    the base drive; the values indicated are for opera-
    tion with standard TTL or DTL circuits. If neces-
    sary, the switching speed can be increased some-
    what by bypassing the resistors with 100 pF
    capacitors.
    FIGURE 18. Transient Response for C L = 200 pF
    at 125 D C (Top) and _55°C (Bottom) Even with operation at maximum speed, clamp
    diodes are not needed on the voltage followers to
    , I I reduce overshoot. The pullup resistors on the
    switches, R5 and R6, can be made large enough so

    "_Itl·Li··I·! that the LM 102 does not see a positive-going input


    pulse that is much faster than the output slew rate _

    _-l==L--f I I
    .VER/IeAL 1 ---d.1\II[i'IV,
    HORIZONTAL 0.5 J,lS/OIV,
    The main advantage of this circuit is that it gives
    much lower output resistance than push-pull
    switches. Furthermore, the drive circuitry for
    --II ---,--
    I 3K
    these switches is considerably simpler.

    -i' -l~-+--+--+ The LM 102 can also be used as a buffer for the
    temperature compensated voltage reference, as
    shown in Figure 21. The output of the reference
    diode is divided down with a resistive divider, and
    it can be set to the desired value with R3.
    FIGURE 19. Transient Response With Unbypassed
    Supplies, CL = 10 pF (Top) and
    C L = 200 pF (Bottom) *Other applications are given in reference 8.

    AN5-7
    ""

    ,-

    a. For Increased Swing b. For Offset Balancing c. For Eliminating Overshoot

    FIGURE 20. Auxiliary Circuits for the LM102

    "'OK
    .
    "
    '" D1
    lN4611

    '"

    ...----------1,...-----.- :~~::NING

    DIGITAL
    :I~~H_ ..
    ,~-...

    FIGURE 21. Using the LM102 to Drive the Ladder


    Network in an AID Converter

    ANALOG COMMUTATOR through at the clock frequency, turning on each


    analog switch in sequence. The "clear" input is
    The low input current and fast slewing of the used to reset the register such that all analog
    LM 102 make it well suited as a buffer amplifier in switches are off. The channel capacity can be
    high speed analog commutators. The low input expanded by connecting registers in series and
    current permits operation with switch resistances hooking the output of additional analog switches
    even higher than 10 Kn without affecting the dc to the inpilt of the buffer amplifiers.
    stability.
    When the output of a large number of MOS
    switches are connected together, the capacitance
    Figure 22 shows an expandable four·channel on the output node can become high enough to
    analog commutator. Two DM7501 dual flip flops reduce accuracy at a given operating speed. This
    form a four-bit static shift register. The parallel problem can be avoided, however, by breaking up
    outputs drive DM7800 level translators which con- the total number of channels, buffering these seg·
    vert the TTL logic levels to voltages suitable for ments with voltage followers and then subcom-
    driving MOS devices, and this is coupled into an mutate them into the AID converter.
    MM451 four-channel analog switch. An extra gate
    on the input of the translator can be used, as SAMPLE AND HOLD
    shown, to shut off all the analog switches.
    Although there are many ways to make a sample
    In operation, a bit enters the register and cycles and hold device, the circuit shown in Figure 23 is

    ANS-8
    rOA/O
    CDtNERTER

    , ;>o-tl 4-11=--+-
    L -rsl-I'H
    .L
    ':"
    10
    . ." I
    1 4 5 SUBSTRATE
    L __ -.l
    I

    DISABLE

    V
    CLEAR

    CLOCK
    u
    ..J\.JLJ\.
    FIGURE 22. Analog Commutator With Buffered
    Output

    undoubtedly one of the simplest. When a negative Figure 24 illustrates a method of bootstrapping
    going sample pulse is appl ied to the MOS switch, it the bias resistor to get higher input resistance.
    will turn on hard and charge the holding capacitor Even though a 200 Kn bias resistor is used for
    to the instantaneous value of the input voltage. good dc stability, the input resistance is about
    After the switch is turned off, the capacitor is 12 Mn at 100 Hz, increasing to 100 Mn at 1 kHz.
    isolated from any loading by the LM 102; and it
    will hold the voltage impressed upon it.
    ACTIVE FILTERS
    The maximum input current of the LM102 is
    10 nA, so with a 10 J.lF holding capacitor the drift
    Active RC filters have been replacing passive LC
    rate in hold will be less than 1 mV /sec. If accu-
    filters at an ever-increasing rate because of the
    racies of about 1-percent or better are requ ired, it
    declining price and smaller size of active compo-
    is necessary to use a capacitor with polycarbonate,
    nents_ Figure 25 is a low-pass filter which is one of
    polyethylene or teflon dielectric. Most other
    the simplest forms of active filters_ The circuit has
    capacitors exhibit a polarization phenomenon 9
    the filter characteristics of two isolated RC filter
    which causes the stored voltage to fall off after the
    sections and also has a buffered, low-impedance
    sample interval with a time constant of several
    output.
    seconds_ For example, if the capacitor is charged
    from 0 to 5V during the sample interval, the mag-
    nitude of the falloff is about 50 to 100 mY. The attenuation is roughly 12 dB at twice the
    cutoff frequency and the ultimate attenuation is
    40 dB/decade. A third low-pass RC section can be
    AC AMPLI FI ER added on the output of the amplifier for an ulti-
    mate attenuation of 60 dB/decade,10 although
    this means that the output is no longer buffered.
    The LM 102 has a minimum input resistance of
    10,000 Mn, so for dc amplifier applications this
    can be completely neglected. However, with an ac There are two basic designs for th is type of filter.
    coupled amplifier a biasing resistor must be used One is the Butterworth filter with maximally flat
    to supply the input current. This drastically re- frequency response. For this characteristic, the
    duces the input resistance. component values are determined from 11

    AN5-9
    OUTPUT OUTPUT

    INPUT

    R1
    lOOK

    R2
    lOOK

    ·Polytlrbon81e·dielectriccapacltor

    FIGURE 23. Sample and Hold Circuit FIGURE 24. High Input Impedance ac Amplifier

    R1
    TlOK

    OUTPUT OUTPUT
    R1
    14K
    INPUT-"'V\".,..........W .........-::t
    R2
    1I0K
    ·Values are for 10KHz cutoff. Use ·Valuesarefor 100 Hz cutoff. Use
    slivered mIca capaCItors lor good metah.zedpolycarbollBtecap8citofS
    temperaturestabdlty. for good temperaturtstabdlty,

    FIGURE 25. Low Pass Active Filter FIGURE 26. High Pass Active Filter

    C1 = R1 + R2 CONCLUSIONS
    .J2R1R2wc
    The LM 102 represents a significant advance in the
    state of the art of linear circu its manufacturing.
    and The device incorporates transistors which have
    higher current gain than is available with discrete
    components. Further, a factor of three to five
    improvement over this can be expected in the near
    future.
    C2= (R1 + R2)wc'
    The performance realized challenges that of field
    effect transistors, if operation over the military
    The second kind is the linear phase filter with temperature range is considered. This is especially
    minimum settling time for a pulse input. The true if the components. are included in a
    design equations for this are temperature-stabilized oven.

    Although the circuit introduced here is restricted


    C1 = R1 + R2 to voltage follower applications, many of the tech-
    ..j3 R1R2wc niques used here can be applied to general purpose
    amplifiers. This is indicative of the performance
    that can ultimately be realized with monolithic
    and amplifiers.

    Even though it's only a voltage follower, the


    LM 102 can be used in a wide variety of appl ica-
    C2=(R1+R2)WC tions ranging from low drift sample and hold cir·
    cuits to a buffer amplifier for high·speed analog
    commutators. Its usefulness is enhanced by the
    fact that it is a plug-in replacement for both the
    Substituting capacitors for resistors and resistors LM 101 and the LM709 in voltage follower applica-
    for capacitors in the circuit of Figure 25, a similar tions_ The circuit will work in the same socket,
    high-pass filter is obtained. This is shown in Fig- unaffected if the compensation components for
    ure 26. the other amplifiers are installed or not.

    AN5-10
    7

    REFERENCES

    1. R. J. Widlar, "A Unique Circuit Design for a 8. R. J. Widlar, "Monolithic Operational Ampli·
    High Performance Operational Amplifier fiers - The Universal Linear Component,"
    Especially Suited to Monolithic Construc· National Semiconductor Corporation ANA.
    tion," Proc. of NEC, Vol. XXI, pp.85-89,
    October, 1965. 9. Pau I C. Dow, Jr., "An Analysis of Certain
    Errors in Electronic Differential Analyzers,
    2. R. J. Widlar, "Monolithic Op Amp with Sim- II - Capacitor Dielectric Absorption," IRE
    plified Frequency Compensation," EEE, Trans. on Electronic Computers, pp. 17-22,
    Vol. 15, No.7, pp. 58-63, July, 1967. March, 1958.

    3. J. Lindmayer and W. Schneider, "Theory of 10. L. Scott, "Criteria for the Design of Active
    Lateral Transistors," Solid State Electronics, Filters Using Resistance and Capacitance Ele·
    Vol. 10, pp. 225-234, 1967. ments in Feedback Circuits," Solid State Elec-
    tronics, Vol. 9, pp. 641-651, 1966.
    4. R. J. Widlar, "Future Trends in DC Ampli-
    fiers," National Semiconductor Corporation 11. R. S. Melsheimer, "If You Need Active Fil·
    TP-4. ters," Electronic Design, pp. 78·82, April 12,
    1967.
    5. R. J. Widlar, "Some Circuit Design Tech·
    niques for Linear Integrated Circuits," IEEE
    Trans. on Circuit Theory, Vol. CT-12, No.4,
    pp. 586-590, December, 1965.

    6. H. C. Lin, T. B. Tan, G. Y. Chang, B. Van Der


    Leest, and N. Formigoni, "Lateral Comple-
    mentary Transistor Structure for the Simu Ita- ACKNOWLEDGMENTS
    neous Fabrication of Functional Blocks,"
    Proc. of the IEEE, pp. 1491·1495, December, The author would like to recognize the contribu·
    1964. tions of Dave Talbert in developing and establish·
    ing the manufacturing processes for this integrated
    7. R. Stata, "User's Guide to Applying and Mea- circuit. In addition, the invaluable contributions of
    suring Operational Amplifier Specifications," Mineo Yamatake in the design, development and
    A na I og 0 ialogue, Vol. 1, No.3, pp. 1-8, evaluation of the device must be gratefully
    September, 1967. acknowledged.

    AN5-ll
    »
    z
    March 1968 ~

    -i
    c:
    Z
    m
    C
    (")
    TUNED CIRCUIT DESIGN USING
    MONOLITHIC RF/IF AMPLIFIERS :xJ
    C')
    c:
    INTRODUCTION ::j
    C
    In replacing conventional tuned high frequency VAGC ~
    FOR QAIN TEST
    0 Vcc ··'2V
    m
    stages, monolithic RF/IF amplifiers can provide en
    performance, as well as economic advantages. Large II
    G')
    available gain per stage, inherent stability, self-con-
    tained biasing, and excellent limiting or AGC capa-
    z
    bilities allow such amplifiers to improve conven- W. c:
    tional designs, while their very small chip size makes
    CUT
    en
    them competitive with single transistor stages. \ zG')
    Vcc· 12V
    3:
    o
    z
    or-
    CUT ::j
    son
    ::t
    C')
    C2

    IN
    5,n :xJ
    son e!
    IN
    .."
    ........
    .."
    »
    FIGURE 2. Cascade RF Amplifier s:"'0
    is permanently connected as an emitter coupled
    amplifier, in an economical six pin package, or as !:
    .."
    the more versatile type LM171 (Figure 4). in which
    a ten pin package allows the user to select either m
    emitter coupled or cascode configurations. Since
    :xJ
    the 171, when externally connected as an emitter
    en
    coupled amplifier, is essentially identical in perfor-
    mance to the 703, references will be made only to
    FIGURE 1. Emitter Coupled RF Amplifier
    "cascode" or "emitter coupled" configurations.
    Two especially useful RF/IF amplifiers are the
    "emitter coupled" differential amplifier, Figure 1, 5••
    R2

    and the modified "cascode", Figure 2. Emitter


    coupled operation is advantageous because of its AI

    symmetrical, non-saturated limiting action, and cor- '"


    responding fast recovery from large signal overdrive,
    making a nearly ideal FM IF stage. The" cascode"
    combines the large available stable gain and low
    noise figure, for which the configuration is well
    known, with a highly effective remote gain con-
    trol capability, via a second common-base stage,
    which overcomes many of the interstage detuning FIGURE 3_ LM703 Configuration
    and bandwidth variation problems found in con-
    ventional transistor AGC stages. DC Biasing
    The "emitter coupled" and "cascode" configura- Both the 703 and 171 are biased by using the
    tions contain essentially the same components; they inherent match between adjacent monolithic com-
    are available as either type 703 (Figure 3). which ponents. They are designed for use with conven-

    AN6-1
    tional tuned interstages, in which DC bias currents
    flow through the input and output tuning induc-
    tances.
    2-
    R2
    '"
    '- "',S< ,

    'f'
    ,_ I Ql 02 I

    01
    _. , QJ
    -250 -1511 -50
    INPUT VOLTAGE - mV
    50 150 250

    FIGURE S. Emitter Coupled Transfer


    !~ Characteristic
    The transfer characteristic of Figure S is represented
    FIGURE 4. 171 Configuration
    by the equation:

    In either case, a resistor forces DC current from I (curran, sourcol= 1 +J~~N) (1)
    the positive supply into a chain of diodes (two for '(output)
    the 703, three for the 171), proportional to the
    difference between supply and forward diode-chain Calculating the difference in V1N required to change
    voltages, and inversely to the value of the resistor. this ratio from 10% to 90%, it may be seen that:
    The forced current, Ibias establishes a voltage drop kT
    across the bottom diode (in reality, an NPN tran· V1N (10%)- V1N (90%) = 2 q (Ina 9) = (2)
    sistor with collector-base short), which is identical
    0.384T (mV)
    to the base-emitter voltage required to force a col-
    lector current of Ibias in a matched common-emitter This quantity, the transition width of an emitter
    stage. Since the transistor is monolithically matched coupled amplifier, is independent of supply voltage
    to the bottom diode, and of fairly high DC "beta", and current, and proportional to absolute tempera-
    an efficient, reliably biased current source is created. ture, varying from 84 mV at -SSoC to 153 mV at
    +12SoC, and is approximately 114 mV at 2SoC.
    Forward transconductance, however, is directly pro-
    Total current through an NPN differential pair is portional to total supply current, taking the ap-
    determined by the current source, while current prox imate form:
    "split" depends on the differential base voltage.
    Common·mode base voltage is readily available by I Y21! = 3.6 (lsupply, mAl mmhos (3)
    using the tap at the top of the diode chain. In the
    703, the differential emitters operate at a forced at 25°C, 10.7 MHz, for either 703 or emitter-cou-
    voltage of one forward diode drop, V be' the cur- pled 171. Thus, emitter coupled amplifier gain may
    rent source still being effective with zero volts, be controlled by externally varying "bias chain"
    collector to base. Because the 171, as a cascode, current, changing the current source by the same
    requires high frequency performance of the cur- amount, but without affecting transition width.
    rent source, three biasing diodes are used, fixing
    the differential emitters at 2 V be • Because an emitter coupled amplifier's input im-
    pedance is a function of drive level (Figure 6),
    Both 703 and 171 function as ordinary differential interstages designed with small-signal y-parameters
    amplifiers, splitting available current source drive may exhibit center frequency shifts and bandwidth
    equally, when base voltages are equal, and being decreases as signal level increases. This is less of a
    capable of either complete cutoff, or full conduc- problem in FM IF strips, where input signal am-
    tion of available current into one of the pair, de- plitude is essentially constant, dictated by the limit-
    pending on differential input. In emitter coupled ing characteristics of the previous stage (Figure 7).
    service, the input signal is injected in series with
    ",-,--,--,--,--,--,--,--,--,-,14
    the differential pair's DC bias, while, in the cascode, Vee= +12V, 101 MHz
    it is in series with the current source's base bias. 30 12
    ! 25 10 .J
    Emitter Coupled Operation ~
    1.... tt!., ~
    ~ R~
    20
    ~
    To assure symmetrical limiting, and max imum small-
    signal linearity, it is necessary that the differential
    in
    ~
    15
    ..... C,

    .... ~~ ," 6
    §"
    ~
    10
    pair be closely balanced, so that quiescent operation 1; .....
    -
    occurs in the center ofthe amplifier's transfer char- 5

    acteristic (Figure S). Typical V ba matches better ~


    0 0
    than ±0.3 mV, for both 703 and 171 assure this, 0 100 200 JOO 400 500

    provided that DC resistance of the input inductor rms INPUT VOLTAGE (mV)

    is so low that input bias currents in the SO /lA


    region do not induce appreciable input offset volt- FIGURE 6. Effect of Drive Level on Emitter
    ages. Coupled Input Impedance

    AN6-2
    +10 IAlF~HR(O TO \ MILLIWATT
    INlO ~O OIIMS!J.,',-+-J,...,j,.,,+-+-
    - --~:""'--V(r"12V-r-

    o ~ _ i I

    _Io f 101 r"oHt MATCHED TO 50 OHM SOURCE


    AND LOAD BANOWIDTH APPX 410 kHz

    -20 '-'-'-'-'-'-'-'-'-J.......J
    -50 ~40 -30 ~20 -10
    INPUT POWER IdBm)

    FIGURE 7. Emitter Coupled Limiting FIGURE 9. Tuned Cascade Power Gain vs AGC
    Characteristics
    and 100 MHz, for exam pie, 171 Yo is about
    Cascode Operation 50 mmhos. From Equation (4), it may be seen
    that balanced conditions (V. go = 3 Vb.) result in
    The cascode configuration exhibits the same input the exponential term equaling unity, so that for·
    characteristics as a common·emitter stage, and near· ward transconductance is half of its maximum
    Iy the same output characteristics, but has superior value.
    available gain and stability; thus, it may directly reo
    place many existing AM·I F designs. The modified The combined second·stage input admittance seen
    cascode possible with the 171 allows the effective by the collector of the input transistor remains
    forward transconductance to be controlled by a essentially constant, as balance of the differential
    small DC voltage, applied differentially between pair is varied; thus, input admittance of the cascode
    Pins 1 and 7, as in Figure 2. With the AGC input remains constant over a wide AGC range, allowing
    near ground, and the base of the output common· interstages to be sharply tuned without fear of
    base transistor at 3 Vb. (from the bias chain). the center frequency or bandwidth shift when AGC
    output transistor acts as it would in an ordinary is applied (Figure 10). Moreover, the exceptionally
    cascode circuit. As the AGC transistor's base volt· low reverse transconductance (.001 mmhos or less
    age is increased, it begins to conduct part of the at 200 MHz) allows high·Q interstages to be aligned
    available DC current and a proportional amount of in an IF strip with minimal interaction between
    signal, from the input stage. As emitter current in· succeeding tuning operations.
    creases in the AGC transistor, its emitter resistance
    decreases, while the emitter resistance of the output I
    transistor increases proportionally; when the differ·
    1401)
    4!l'J kHz C~ "14
    ential pair is balanced, output is reduced by half,
    and increased AGC voltage causes all DC current,
    I.: 1201)

    looOf--155kJtR p 20 ~
    as well as nearly all signal, to be shunted to the i" BOO Hi ~
    4'JMHz Cp
    AGC transistor (Figure B). Infinite gain reduction in 600 lL~ "
    is not possible, because of capacitive leakages in the ~ 400
    I V{.{.: +12V
    8 ~

    cut-off output transistor; nevertheless, large AGC


    range per stage is possible (Figure 9).
    ~

    200
    4!lMHz Rp

    250MHzC p
    , z

    250MHI Rp
    a a
    " r-1-'-'-'-'-'-'-'-'--''' +\1)0 +200

    '+'~l1vl
    ~200 ~100 0
    VAGC 1m V) PIN 1 TO 1
    4OHI;;;;;l:-f-i-i-i-i-t-t-j4O
    LBo.;21~ioi' H''->IrG2,J..::,J:;O::;MH.;.J-I-I-lJO I
    ';,,;oo':""i
    1 Ja'J lIIIiI/... ~ .s
    FIGURE 10. Effect of AGC on Cascode
    Input Impedance

    :; 20
    ",,'~M~"'l
    ~
    , 20 T
    Gain reduction may be accomplished with either

    ~~I- - -
    positive·going or negative·going AGe, simply by
    10 choosing the appropriate input base of the differ·
    G21,,'.MH' 10
    ential pair. Approximately 200 mV peak·to·peak
    -:Ii1i!b. a
    is sufficient to operate the AGC from full conduc·
    -200 -100 0 +1110 +200
    VAGC (mV) PIN 1 TO 7 tion to cutoff at 25°C; adjacent AGC stages may
    be connected with the AGC inputs in parallel, if
    FIGURE 8. Cascode Y21 vsAGC
    the DC "reference" is obtained for each differen·
    The magnitude of forward transadmittance is ap· tial pair from a common point, such as the bias
    proximately proportional to the fraction of avail· chain of one of the amplifiers. Alternatively, sensi·
    able DC current shunted into the output stage; it tivity to differences in individual bias chain refer·
    can be related to the AGCvoltage by the expression: ences may be reduced, as well as AGC voltage
    sensitivity, by using an external voltage divider for

    IY211 =( rq(V agc -3 Vbell)


    mmhos
    (4)
    each AGC input.

    1+ eL kT J Data Sheet Parameters as Design Aids


    where Yo is the maximum (no-AGC) magnitude of While production measurement to guarantee "black
    Y21 for given conditions. At 25°C, Vee = 12 volts, box" parameters for all possible operating condi·

    AN6-3
    tions and frequencies is impractical, both the 703
    805 (5)
    and 171 data sheets supply a wealth of parameter (4X 6.6X 1O- 3 X .11 X 10- 3 )
    information. The most convenient characterization
    for practical R F circuit design appears to be the = 29.2 d8 (neglecting Y12)
    four complex "y·parameters", which define input,
    As a check, the stability criterion, C, is calculated:
    output, and transfer admittances. In some cases,
    capacitance and resistance values are presented, as
    they are easier than pure y·parameters to verify in
    the laboratory, but they may easily be converted
    to equivalent y-parameters. A number of system-
    atized design approaches are available, in the litera-
    ture, and will not be treated here in detail.

    Interstage Configurations (6)


    =.0325
    Tuned interstages for emitter coupled and cascode Since the criterion O<C< 1 is satisfied, the cascode
    amplifiers can take a wide variety of forms, pro- is unconditionally stable at 100 MHz, for any source
    vided that they meet the DC biasing requirements and load. In a practical circuit, power gain nearly
    previously outlined. The "tapped capacitor" par- equal to MAG may be attained with conjugate input
    allel resonant circuit of Figures 1 and 2 is especially and output matching, provided that physical cou-
    useful when transformers are to be avoided, or when pling (external feedback) between interstages is
    adjustment capability is required to match different minimized by shielding or careful layout.
    source and load admittances. A second common
    approach is the single or double tuned interstage While circuit optimization must unavoidably be
    transformer, currently used in the majority of com- done in the laboratory, the procedure shown below
    merical designs. While the transformer requires more will provide initial component values. To conjugate
    careful initial design, to obtain desired matching, match a 50 ohm resistive source to 150 ohms, and
    gain and bandwidth, it is better suited to mass- 11 pF at the cascode input, consider Figure 11. An
    produced systems. Capacitively coupled interstages, overall bandwidth of about 5 MHz is desired; how-
    such as three terminal ceramic filters, or crystal ever a preliminary calculation reveals that the re-
    lattice filters, require RF chokes or external resis- quired Q, for equal effect from input and output
    tors to supply the required DC bias levels. tuned circu its, requ ires impractical component
    values at the input, because of the low input re-
    Practical Circuits sistance. The input coupling circuit is therefore de-
    signed with practical values, leaving the frequency
    Two interstage designs wi II be briefly presented; shaping function primarily to the output network,
    one, a 10.7 MHz emitter-coupled stage, is useful in in this example.
    an FM IF strip, while the other, a 100 MHz cas-
    code, might find application in a VHF receiver front Choosing a total input capacitance of 15 pF, the
    end, or a radar I F strip. No attempt will be made value of Ll is:
    to give optimized designs; however, considerations
    involved in such optimization are pointed out.
    (7)

    100 MHz Cascade


    = 0.17,uH
    The objective is to build a high gain, narrow-band
    stage, with input and output matched to 50 ohms. The series combination of C 1 and C 2 must equal
    To obtain high Q, and ease of matching, a capaci- the difference between Ctin and 11 pF, or 4 pF.
    tive, divider is used for input and output, rather For the circu it of Figure 2, the rea I part of input
    than a transformer (Figure 2). At 100 MHz, the impedance, R in , seen by the cascode input, may be
    following parameters may be read from typical calcu lated:
    curves on the 171 data sheet:

    RIN ~ 150 ohms, CIN = 11 pF


    (Vee = 12V, connected to Pin 9)
    or Yl1 ~ 6.6 + j 6.6 mmhos
    after,some rearranging,
    ROUT = 9000 ohms, COUT = 3 pF
    or Y22 = 0.11 + j 1.8 mmhos
    and Y21 = 38 + j 30 mmhos (no AGC applied)
    Y12'" .001 + jO mmhos (negligible)
    ~: = ~I~ (21if 1Rs C Y-1
    - o 2
    (9)

    Maximum available power gain may be calculated it may be shown that


    for these parameters:

    ~I: ~(i1Tfo~sCS ' (10)

    thus,

    AN6-4
    llpF
    "F

    R~' 50n

    FIGURE 11. Equivalent 100 mHz Cascode Networks

    eters must be weighed against each other. Since


    (11) design techniques are well covered in the litera·
    ture(4,5,6,7), only a brief discussion of design con·
    siderations will be included in this report.
    and
    Maximum available power gain may be calculated
    for either 171 or 703 as emitter coupled amplifier,
    (12) using the formula of the preceding example. At
    10.7 MHz, 25°C, and Vee = 12V,using703values,

    substituting, Y11 = 0.35 + j 0.61 mmho (R ,N =2.9k, C,N =9pF)


    Y21 = -33.4 + j 5.88 mmho (note negative
    real part)
    Y12"" 0.002 + j 0 mmho
    solving, Y22 = 0.03 + j 0.18 mmho (ROUT = 33k,
    COUT = 2.6 pF)
    C1 = 6.8 pF, C2 = 9.4 pF
    1 ·2 (X .3)2
    MAG=--.!'.nL= 34 10 =2.75Xl0 3
    The same procedure and equivalent circuit may be 4911 g22 4(.35X 10.3 X .03X 10.3)
    used to determine values for the output network;
    in this case, however, the choice of total output = 34.4 dB
    capacitance is not arbitrary, since a known band·
    (Due to somewhat different typical y'parameters,
    width is desired. For a 5 MHz bandwidth, conjugate
    MAG for an Emitter Coupled 171 = 39 dB.)
    matched to 9000 ohms,
    Calculating the stability criterion:

    20 = 7.1 F
    211(10 8 )(4500) p
    (.002Xl 0·3X34Xl 0. 3 )

    6.8XlO·8

    sC "" )9000
    2 50
    -1=13.4-1 = 12.4
    = 0.775
    C2 C 1 For the conditions given, 0 < C < 1, making the
    C2+C 1 = 7.1 -3= 4.1 device unconditionally stable for all sources and
    loads. In a practical 10.7 MHz I F strip, however,
    solving, external coupling, especially from the strip's output
    to its input, can cause instability without careful
    C 1 = 4.4 pF, physical design.

    Laboratory measurements, in which circuit values A modern FM tuner I F strip capable of low·distor·
    given above were used as design centers for adjust· tion multiplex reception, requires:
    ment, give typical cascode power gain of 27.5 dB,
    A. Bandwidth at least 300 kHz. In a four stage
    with the desired 5 MHz bandwidth, using carefully
    design, with five interstage networks, band·
    constructed, low loss inductors.
    width per stage may be calculated from overall
    bandwidth by use of the "shrinkage" formula:
    10.7 MHz FM IF Using Emitter Coupled Amplifiers
    BW(overalll
    Complete design of a high quality FM I F strip is a BW(per stage ) = - = (n= number 0 f
    painstaking process, in which a number of paramo y2 1/n -1 interstages)

    AN6-5
    300 300 F. The interstages should be designed to minimize
    (13)
    =../2 1/5 -1 = .388 the effects of varying drive levels upon center
    frequency and bandwidth. since very weak sig-
    nals may operate the first one or two stages
    = 773 kHz linearly. rather than as limiters.

    B. Sharp skirt selectivity without phase/frequency


    nonlinearity 'within the passband. This usually
    implies double-tuned interstage transformers.
    Stover. et. al. (5). show that a transformer cou-
    pling factor between 0.6 and 0.8 gives minimum
    phase nonlinearity. the higher value being pre· References
    ferred for higher gain per stage.
    1. R. Hirschfeld. "Design Freedom Through User
    C. Overall power gain of at least 100 dB. or 25 dB Options in Monolithic RF/IF Amplifiers". Pro-
    per stage in a four stage strip. to obtain ade· ceedings EEE Linear I/C Clinic. 3/24/67. Mactier
    quate sensitivity and AM rejection. Pub. Corp.
    D. A maximum value of load resistance across the
    output of each stage. given by: 2. J. Robertson and R. Hirschfeld. "Application of
    Microelectronics to IF Amplifiers". IEEE Trans.
    Vehicular Communications. Vol. VC·14. No.1.
    (14) pp. 162. 3/65.

    3. J. Solomon and J. Narud. "Final Report. Vol. II.


    where N = number of bias chain diodes USAF contract No. AF33(657)11664". Wright·
    N = 2 for the 703. or 3 for the 171 Patterson AF B. 9/64.
    IOUT(MAX) is approximately 5 mAo for 4. J. LinvillandJ. Gibbons. "Transistors and Active
    both types. Circuits". Ch. 9-18 McGraw Hill. Inc .• New York.
    1961.
    This relationship assures that maximum output
    current limiting is reached before the output 5. IN. Stover. et. al.. "Circuit Design for Audio.
    transistor can saturate. guaranteeing non-satu· AM/FM. and TV". Ch. 7·11 McGraw Hill. Inc .•
    rated limiting action. New York. 1967.
    E. The input admittance used in making interstage
    6. IN. Gartner. "Transistors: Principles. Design and
    calculations should be the value resulting from
    Applications". Ch. 14. 15 D. Van Nostrand.lnc .•
    a given value of input swing. (see Figure 6).
    New York. 1960.
    rather than the small-signal value. The input
    swing. however. depends upon the transformer 7. J. Lauchner and M. Silverstein. "Design High-
    ratio. so that transformer optimization is a Frequency Amplifiers Graphically". Electronic
    mu Iti·approx imation procedure. Design. 4/12/66.

    AN6-6
    l>
    Z,
    June 1968
    CO

    Z
    m
    NEW USES FOR THE LM100 REGULATOR ~
    C
    vi
    INTRODUCTION THE LM100 m
    en
    One might think that an integrated circuit like a Before going into the various circuits, it is in order "T1
    voltage regulator would be limited to one spe-
    cialized application_ Such is not the case, as was
    to describe briefly the operation of the LM 1 00. A
    schematic diagram of the integrated circuit is given
    o
    ::D
    proven by the results of an applications contest in Figure 1. Generation of the reference voltage
    that was conducted recently for our LM100 volt- starts with zener diode, Dl, which is supplied with
    -I
    ::I:
    age regulator. a fixed current from one of the collectors of Q2. m
    This regulated voltage, which has a positive
    r-
    The LM 100 is a monolithic integrated circuit that
    was designed as a series regulator to operate in
    either a linear or a switching mode. Its output volt-
    temperature coefficient, is buffered by Q4, divided
    down by Rl and R2 and connected in series with a
    diode-connected transistor, Q7. The negative tem-
    ...s:
    o
    age can be set anywhere between 2 and 30V with a perature coefficient of Q7 cancels out the positive o
    pair of external resistors. By itself it can deliver coefficient of the voltage across R2, producing a ::D
    output currents of 10 to 20 mA, but discrete tran- temperature-compensated 1.8V on the base of Q8. m
    sistors can be added to boost the output current to This point is also brought outside the circuit so G')
    any desired level. The integrated circuit design is that an external capacitor can be added to bypass C
    described along with its applications as a series any noise from the zener diode. r-
    regulator in references 1 and 2. l>
    -I
    The contest brought out a number of novel ways
    Transistors Q8 and Q9 make up the error amp Iifier
    of the circuit. A gain of 2000 is obtained from this
    o
    ::D
    to use the LM 100 in other voltage-regu lator appli- single stage by using a current source, another
    cations such as a shunt regulator. Included were collector on Q2, as a collector load. The output of
    temperature regulators and light-level regulators. It the amplifier is buffered by Ql1 and used to drive
    was also shown that the LM100 could effectively the series-pass transistor, Q12. The collector of
    be used as an operational amplifier, especially if Q12 is brought out so that an external PNP tran-
    the application required a reference voltage or if it sistor, or PNP-NPN combination, can be added for
    was necessary to add transistors for increased out- increased output current.
    put power.
    Current limiting is provided by Ql0. When the
    It is appropriate to point out that all the circuits voltage across an external resistor connected be-
    described here for the LM100 will work equally tween Pins 1 and 8 becomes high enough to turn
    well with the LM200 or LM300, within their on Q 10, it removes the base drive from Q 11 so the
    respective temperature and operating-voltage regulator exhibits a constant-current characteristic.
    ranges. As for the remaining details, the collector of the
    amplifier, Q9, is brought out so that external
    collector-base capacitance can be added to
    frequency-stabilize the circuit when it is used as a
    linear regulator. R9 and R4 are used to start up
    the regulator, while the rest of the circuitry estab-
    r-t------<p--.....- - - t - UNREGULATED INPUT lishes the proper operating levels for the current
    sou rce transistor, Q2.
    BOOSTER OUTPUT

    Now that some understanding of the internal


    .r-+-"'~>- CURRENT liMIT workings of the LM 100 has been established, we
    +"li'.'W>'W'tG~----i- REGUtAT£O OUTPUT can discuss the applications for the circuit.

    ~----- COMPENSATION

    SHUNT REGULATOR
    ~~ ....~r---- rHOBACK
    Shunt regulators are sometimes substituted for
    '-----if------- REfERENCE BYPASS
    series regulators even though they are less
    '-_--<11-_ _ ,.-=-_____ GROUND efficient. The reason is that they are not as sensi-
    tive to input voltage transients, they do not feed
    load current transients back into the unregulated
    supply, they are inherently short-circuit proof and
    they are less prone to failures where the output
    FIGURE 1_ LM100 Schematic voltage becomes excessive.

    AN8-1
    Although the LM100 was designed primarily as a This circuit was submitted by Bob Dobkin of
    series regulator, it can also be used in shunt· Philbrick/Nexus Research, Dedham, Massachusetts
    regulator applications. Figure 2 shows a 3A shunt and R. F. Downs of LTV Research Center,
    regulator. The output of the LM 100 drives a com· Anaheim, California.

    r------------.----~--_._GROUNO SWITCHING REGULATOR WITH OVERLOAD


    R3 SHUTOFF
    100
    HI
    1&.7K It is difficult to current limit a switching regulator
    1%
    because the circuit must continue to operate in a
    high efficiency switching mode even when the out·
    put is short circuited. Otherwise, the power dissi·
    pation in the switch transistor will be excessive,
    more than ten times the full load dissipation, even
    RS
    lK though the current is limited.
    R4 HZ
    3 Z.Z7K
    SOW 1%
    R&
    V'N' ....._+---------+-----------+----+--VOUT A unique solution to this problem is the overload
    shutoff scheme shown in Figure 3. When the
    output current becomes excessive, the voltage
    FIGURE 2. Negative Shunt Regulator drop across a current sense resistor fires an SCR
    whic~ shuts off the regulator. The regulator
    remains off, dissipating practically no power, until
    pound emitter follower which conducts the excess it is reset by removing the input voltage.
    input current. A zener diode, D 1, provides a level
    shift so that the output transistors within the
    LM100 are properly biased. R5 supplies base drive In the actual circuit, complementary transistors,
    for 02 and also the minimum load current for the 01 and 02, replace the SCR since it is difficult to
    LM100. R4 is included to minimize dissipation in find devices with a low enough holding current
    the power transistors when the regulator is lightly (about 50 /J-AL When the voltage drop across R4
    loaded. The output voltage is determined in the rises to about 0.7V, 02 turns on, removing the
    normal fashion by R 1 and R2. Although no out· base drive to the output transistors on the LM 100
    put capacitor is used, it may be advisable to through Pin 7. Then 01 latches 02, holding the
    include one to reduce the output impedance at regulator off until the input voltage is removed. It
    high frequencies. will then start when power is applied if the over·
    load has been removed.

    Because a shunt regulator is a two terminal device,


    one design, using an LM 1~O, can be used as either This circuit was designed by Dan Lubarsky of
    a positive or a negative regulator. Moore Associates, San Carlos, California.

    Rl
    3.1K

    8.5~;5V'--+------i....----+------...J t Solid Tantalum


    R8
    1M
    l6D Turns =20 on Arnold Engineering
    A 930157·2 Molybdenum Permllloy Cone

    FIGURE 3. 3A Switching Regulator With Overload Shutoff

    AN8-2
    Llf

    r---__~----~----_G~~~~__~----__~------~----__~--_I~----_i._---- __ ~VouT=5V

    03
    R4 2NJ668
    68

    02
    2NJ445

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    8.5-J5V
    Fl t Solid Tantalum
    R5
    2A 1M
    f 60 Turns #20 on Arnold Engineering
    A 930157·2 Molybdenum Permallov Core

    FIGURE 4. Switching Regulator with Crowbar Overvoltage Protection

    OVERVOLTAGE PROTECTION FOCUS CONTROL CURRENT SOURCE

    A switching regulator can be used in place of a Although the LM 100 is most frequently used as a
    power converter to reduce high input voltages voltage regulator, it is also useful as a current regu-
    down to a considerably lower output voltage with lator. A current regulator can be made by regula-
    good efficiency. In addition, it simultaneously ting the voltage across a known resistor, producing
    regu lates the output voltage. As a resu It, a a fixed current.
    switching regulator is simpler and more efficient
    than a power converter/regulator combination. The focus control current source shown in
    One objection brought up against switching regula- Figure 5 is an example of such a current regulator.
    tors is that they can fail with the output voltage
    going up to the unregulated input voltage which is
    frequently several times the regulated output volt-
    age. This can destroy the equipment that the
    regulator is supplying. A power converter has the
    advantage that it will usually fail with the output
    voltage going to zero.

    A circuit which protects the load from over-


    voltages is shown in Figure 4. If the output voltage
    should rise significantly above 6V, the zener diode,
    D2, breaks down and fires the SCR, 013, shorting
    the output and blowing the fuse on the input line.
    C3 keeps the SCR from firing on the voltage tran-
    sients which can be present around a switching
    regulator, and R7 is included to make sure that
    excessive gate current does not flow when it fires.
    Since the SCR is located on the output of the FIGURE 5. Focus Control Current Source
    regulator. it is not prone to dV /dt firing on fast
    transients which might be present on the unregu-
    lated input.
    The output current from the pass transistor, 01, is
    set by selecting an appropriate value for R5 and
    It is important to design the regulator so that the then adjusting the voltage drop across it with R4.
    overshoot in the output voltage 2 caused by With the arrangement used, most of the power is
    suddenly removing full load current does not fire dissipated in R5 rather than the control potentio-
    the SCR. If this is done, about the only thing that meter. R2 is included in the adjustment circuit so
    can cause an overvoltage output is failure of the that the LM 100 feedback terminal operates from
    regulator switching transistors. approximately 2.2 kn source resistance. This is
    the optimum design value for minimum thermal
    drift and proper frequency compensation.
    This circuit comes from E. S. Madson of ESM,
    Copenhagen, Denmark and Don Learned, Heath The regulator is protected against shorts to
    Company, Benton Harbor, Michigan. ground, from the focus coil or its leads, by R 1. D 1

    ANS-3
    prevents voltage reversals on the integrated circuit The maximum supply voltage (V+) that can be
    or the pass element, caused by the inductive kick- used with this circuit is limited only by the break-
    back of the focus coil, when the input voltage is down voltage of the control transistors. If this
    switched off. C2 and C3 are required to keep the voltage is less than 40V, this supply can also be
    circuit from oscillating. used to power the LM 100.

    A particular advantage of the LM 100 in this appli-


    cation is that its low reference voltage enables it to The regulator can be switched off electrically by
    regulate a current with a minimum of voltage clamping Pin 7 of the LM100 with a 1 k.l1 resistor,
    dropped across the sense resistor. This is important a diode, and a transistor to ground. If it is desirable
    both to increase the efficiency and to minimize to operate the circuit as a fast switch, however, 01
    dissipation in the sense resistor which usually must should be replaced with a faster transistor like the
    be a precision resistor. 2N3445 and Cl should be reduced to 47 pF. It
    would also be advisable to use a 1 N3880, which is
    This design was submitted by H. J. Weber of a faster device, for D1.
    EG&G, Boston, Massachusetts. Similar circuits
    were sent in by C. M. Katkic of Michigan Bell
    Telephone Company, Southfield, Michigan and C. This circuit was contributed by Bob Dobkin of
    H. Ristad. Philbrick/Nexus Research, Dedham, Massa-
    chusetts; Tom Hall of Bausch and Lomb, Bellaire,
    Texas and Steve Menasian of the University of
    Washington, Seattle, Washington.
    1A CURRENT SOURCE

    Another current source circuit is shown in Fig-


    ure 6. Here the LM100 regulates the emitter cur-
    SWITCHING CURRENT REGULATOR

    Current regulators generally operate with a large


    voltage drop across the control transistors since
    they must accommodate large variations in the
    voltage across the load. Consequently, the power
    dissipation in the transistors can be quite high.

    The switching regulator principle can be applied to


    a current regulator to greatly increase efficiency
    and reduce the power dissipation in the control
    transistors. Figure 7a gives the schematic of a
    switching current regulator wherein the input
    power, for a fixed load current, is roughly pro-
    portional to the voltage across the load. A
    standard switching regulator is used, except that
    the load is connected from the output to the feed-
    back terminal of the LM100. A current sense resis-
    tor, R 1, is connected from the feedback terminal
    to ground to set the output current. If desired, an
    adjustment potentiometer can be connected across
    FIGURE 6. 1A Current Source the current sense resistor as shown in Figure 6.

    An additional filter capacitor, C2, is put across the


    load terminals to reduce output ripple. If it is not
    rent of a Darlington-connected transistor, and the needed, it can be removed if an 0.1 pF capacitor is
    output current is taken from the collectors. The connected from the top of Cl to Pin 6 of the
    use of a Darlington connection for 01 and 02 LM 100 to make sure all the output ripple of the
    improves the accuracy of the circuit by minimizing regulator appears at the feedback terminal.
    the base-current error between the emitter and
    collector current.
    An alternate scheme wh ich has the current output
    The output of the LM 100, wh ich drives the con- referenced to ground is given in Figure 7b. This
    trol transistors, must be short-circuit protected circuit is identical to that in Figure 7a except that
    with R6 to limit the current when 02 saturates. the load is inserted in the ground line. The
    R7 is required to provide the minimum load cur- quiescent current of the regulator, flowing out of
    rent for the integrated circuit. D 1 is included to Pin 4, introduces an error term. However, since
    absorb the kickback of inductive loads when this current is only about 2 mA and is reasonably
    power is shut off. The output current of the cir- independent of changes in the input or load volt-
    cuit is adjusted with R2. ages, the error is usually not significant.

    AN8-4
    "7

    __
    Ll_l_

    01
    lNl81D R4
    68

    R2
    2K Rl
    0.9

    8.~~NJ5::':V-t---·---4I""'-----""" '::'
    R5 t Solid Tan'bllum
    1M l60 Tarm #20 on Arnold Engineering
    A 930151·2 Molybdenum Perm.lloy COft

    a. Current Source With Floating Load

    __
    Ll_1_

    + CIt
    T l5V 1DO l-'F

    R2
    2K

    Rl
    0.9
    V'N--+--~~-""""------...1

    R5
    1M
    tSolid Tantalum OUTPUT
    f &0 Turns #20 on Arnold EnginHting
    A 930151·2 Molybdenum Permalloy Core
    '----+'iC~t-t--""l_t--
    41 pF
    l5V

    b. Current Source With Grounded Load

    FIGURE 7. Switching Current Regulators

    With this circuit, the difference between the input TEMPERATURE CONTROLLER
    voltage and the load voltage cannot drop below
    8.5V, or the circuit will drop out of regulation A circuit for an oven·temperature controller using
    because the voltage across the LM 100 is insuffi· the LM100 is given in Figure 8. Temperature
    cient to bias the reference circuitry. changes in the oven are sensed by a thermistor.
    This signal is fed to the LM100 which controls
    power to the heater by switching the series pass
    transistor, Q2, on and off. Since the pass transistor
    This circuit was sent in by T. H. Lynch of Bunker· will be nearly saturated in the on condition, its
    Ramo Corporation, Canoga Park, California. power dissipation is minimized.

    AN8-5
    27±4V V~ ~~ POWER AMPLIFIER

    DZ The versatility of the LM100 is demonstrated by


    lav
    the power amplifier circuit in Figure 9. The
    LM100 is used as a high·gain amplifier and con·
    nected to a quasi·complementary power output
    stage. Feedback around the entire circuit stabilizes
    the gain and reduces distortion. I n addition, the
    regulation characteristics of the LM 100 are used to
    stabilize the quiescent output voltage and
    minimize ripple feedthrough from the power
    Cl
    l00pF supply.

    The LM 100 drives the output transistors, 05 and


    ;0. Approximately 10K @ +85°C
    06, for positive·going output signals while 01,
    operating as a current source from the 1.8V on the
    reference terminal of the LM 1~O, supplies base
    drive to 03 and 04 for negative·going signals. 02
    eliminates the dead zone of the class·B output
    stage, and it is bypassed by C5 to present a lower
    driving impedance to 03 at high frequencies. The
    FIGURE 8. Switching Temperature Controller voltage drop across 02 will be a mu Itiple of its
    emitter·base voltage, determined by R9 and Rl0.
    These resistors can therefore be selected to give
    the desired quiescent current in 04 and 06. It is
    In operation, if the oven temperature should try to important that 02 be mounted on the heat sink
    increase, the thermistor resistance will drop, with the output and driver transistors to prevent
    increasing the voltage on the feedback terminal of thermal runaway.
    the regulator. This action shuts off power to the
    heater. The opposite would be true if the tempera· Output current limiting is obtained with D2 and
    ture dropped. D3. D2 clamps the base drive of 03 when the
    voltage drop across R6 exceeds one diode drop,
    and D3 clamps the base of 05 when the voltage
    Variable·duty·cycle switching action is obtained across R7 becomes greater than two diode drops.
    by applying positive feedback around the regulator R11 is needed to limit the output current of the
    from the output to the reference bypass terminal LM 100 when D3 becomes forward biased.
    (which is also the non·inverting input to the error
    amplifier) through Cl and R4. When the circuit The power supply ripple is peak detected by D 1
    switches on or off, it will remain in that state for a and Cl to get increased positive output swing by
    time determined by this RC time constant. operating the LM 100 at a higher voltage than 05
    and 06 during the troughs of the ripple. This also
    reduces the ripple seen by the LM 100. C5 bypasses
    Additional details of the circuit are that base drive any zener noise on the reference terminal of the
    to 01 is limited, to a value determined by R2, by LM 100 that would otherwise be seen on the out·
    the internal current·limiting circuitry of the put.
    LM 100. D2 provides a roughly regulated supply
    for Dl in addition to fixing the output level of the The quiescent output voltage is set with R2 and
    LM 100 at a level which properly biases the inter· R3 in the same way as with a voltage regulator.
    nal transistors. The reference diode for the The ac voltage gain is determined by the ratio of
    thermistor sensor, D 1, need not be a temperature· Rl and R3, since the circuit is connected as a
    compensated device as long as it is put in the oven summing amplifier.
    with the thermistor. Finally, the temperature is
    adjusted with R5. This circuit was designed by Bob Dobkin of
    Philbrick/Nexus Research, Dedham, Massachusetts
    and H. D. Carlstrom, Sanders Associates, Nashua,
    New Hampshire.
    Using a thermistor with a temperature coefficient
    higher than l%tC, control accuracy should be
    better than ±l°C for a wide range of ambient con·
    HIGH EFFICIENCY SINGLE-SIDEBAND
    ditions, even if the LM 100 is not put inside the
    TRANSMITTER
    oven.
    A circuit which can be used to improve the effi-
    ciency of a single-sideband transmitter is shown in
    This circuit was contributed by C. W. Andreasen Figure 10. A switching regulator operates the
    of Stromberg·Carlson, San Diego, California and linear output amplifiers of a conventional single-
    A. B. Williams of Stelma Incorporated, Stamford, sideband transmitter at a voltage just higher than
    Connecticut. that required to accommodate the envelope of the

    AN8-6
    V+--~------------------------------------------------~-----,
    J6V

    D1
    1N4002

    TO LOW
    LEVEL - -. .- - - - {
    STAGES

    R1
    2.2K

    C2
    10 ll FT R2
    2.4K
    RJ
    22K
    * Mount an Heat Sink With
    Power Transistors
    INPUT t Can be Selected 'Of Desired
    Quiescent CUlTent

    FIGURE 9. Power Amplifier With Current Limiting

    AUDIO INPUT

    1.8V-NO MODULATION
    L1. 20V -PEAK FOR MODULATlDN

    01
    1N3880

    Q2
    2NJ879·

    UNREGULATED * 95 Turns #22 on Arnold Engineering


    INPUT ---t------4.------4.-------------' A 193105-2 Molvbdenum Permilloy Core
    +28V t Solid Tantalum
    R1
    1M

    FIGURE 10. High Efficiencv Modulation Scheme for Single Sideband Transmitter

    rf output signal. With no modulating signal, the form is detected and used to drive the regu lator so
    driver and output amplifiers are operated at 1.8V, that its output voltage follows the shape of the
    which is the reference voltage of the LM100. When envelope. Hence, the amplifiers are alwavs
    ·modulation is present, the envelope of the rf wave- supplied just enough voltage to keep them from

    AN8-7
    ,-
    ....

    saturating. Since the switching regulator converts


    the dc input voltage down to the lower voltage
    driving the amplifiers with high efficiency, the
    overall transmitter efficiency is increased.

    The amplitude of the envelope on the output of


    the switching regulator is determined by R5, as the
    detected envelope will be multiplied by the ratio
    R4/R5. The output signal of the envelope detector
    must be negative·going so that the drive voltage
    will be positive·going. In addition, it is necessary
    to dc couple or clamp the detected envelope so
    that the supply voltage to the amplifiers does not
    drop below their minimum operating level on the =
    troughs of the signal. It is also important that the
    output amplifiers be designed so that their gain
    V'N-4...--------------....J
    does not vary with the voltage supplied to them or
    distortion will be introduced.
    FIGURE 11. Light Intensity Regulator
    This technique can be used to increase efficiency
    with AM transmission. Here, the switching regu·
    lator is driven with a negative·going modulation
    signal, which has been clamped to 1.8V, instead of This circuit is adapted from one submitted by
    the detected envelope. The regulator output drives Geoffrey Hedrick of Lear Siegler/Astek Division,
    a class·C rf power stage. The output waveform of Armonk, New York.
    the regulator must accurately follow the modula·
    ting signal, and the ripple on the output of the
    switching regulator must be eliminated because the
    drive signal to the output amplifier appears di· HIGH VOLTAGE REGULATOR
    rectly on the envelope of the rf output. These con·
    ditions can be satisfied by operating the switching Although the LM 100 was designed primarily for
    regulator at 100 kHz and using additional filtering applications with output voltages below 30V, it
    between the regu lator and the output stage. can be used as a high voltage regulator under
    certain circumstances. An example of this, a cir-
    With either modulation scheme, the output voltage cuit regulating the output of a 2 KV supply, is
    of the regulator/amplifier can be limited by given in Figure 12.
    putting a zener diode across R4. This protects the
    rf output amplifier from excessive voltage caused
    by overmodulation or high dc input voltage. The LM100 senses the output of the high voltage
    supply through a resistive divider and varies the
    This design comes from Ben Stopka of Collins input to a dc/dc converter, which generates the
    Radio, Cedar Rapids, Iowa. high voltage. Hence, the circuit regulates without
    having any high voltages impressed across it.

    lIGHT·INTENSITY REGULATOR
    Under ordinary circumstances, the feedback
    terminal of the LM100 wants to operate from a
    Figure 11 gives the circuit for a light· intensity 2K divider impedance. Satisfying this condition on
    regulator using the LM 100. A phototransistor a 2 KV regulator would require that about 2W be
    senses the light level and drives the feedback dissipated in the divider. This, however, is reduced
    terminal of the LM 100 to control current flow to 40 mW by the addition of 01 which acts as a
    into an incandescent bulb. R 1 serves to limit the buffer for a high impedance divider, operating the
    inrush current to the bulb when the circuit is first LM 100 from the proper source resistance. The
    turned on. other half of the transistor, 02, is required to com·
    pensate for the temperature drift in the emitter·
    The current gain of the phototransistor, 02, is base voltage of Q1, so that it is not multiplied by
    fixed at 10, to make it less temperature sensitive, the divider ratio. The circuit does have an uncom·
    by R3 and the temperature compensating diode, pensated drift of 2 mVtC; but this is added
    D 1. A photodiode, such as the 1N2175, could be directly to the output, not multiplied by the
    substituted for the phototransistor if it had suffi· divider ratio, so it will be insignificant with a 2 KV
    cient light sensitivity; and R3 and D 1 could be regulator.
    eliminated. The input voltage does not have to be
    regulated as the sensitivity of a phototransistor or
    photodiode is not greatly affected by the voltage This circuit was contributed by Don Sobel of
    drop across it. A photoconductor can also be used Federal Scientific Corporation, New York, New
    in place of the phototransistor, except that input York and A. A. Frank of the University of
    voltage would have to be regulated. Southern California, Los Angeles, California.

    AN8-8
    "7

    R4
    0.2

    DC/~C
    CONVERTER
    RS 12V/2 KV
    68

    03
    2NJ055

    RI
    04 100M
    2N2905 1%

    ~V---O-----<~-C3-t----~
    T 2.2 /1F
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    FIGURE 12. High Voltage Regulator

    SIGNAL
    OUTPUT CATHODE Cl C2 C3 C4 C5
    n,Ol/1F O.DlpF O.D1JlF O.OlpF O.OIp.F
    RL
    .-""''v-......- AND 0 E
    RI * RCA
    OV9 OVI
    DVNQOE
    01 VIDER -O-~I'v-~--____
    STRING R9
    R8
    2K 500
    1% 1%

    R3 R4 R5 R6 R7
    lOOK lOOK lOOK lOOK lOOK 05
    lN456

    20pf RIO
    20/1F 390
    600V 600V
    1%

    + +
    07

    08 09
    06 390
    VAC
    -=
    ~

    FIGURE 13. Photomultiplier Tube Supply L..-----------'_ 15V J

    PHOTOMULTIPLIER TUBE SUPPLY Five cascode-connected transistors, 01 through


    05, are used as the pass transistors, This is pres-
    A second high voltage supply is diagrammed in ently the lowest-cost solution to the problem of
    Figure 13. This is a high voltage supply for a handling the required voltage and power levels.
    9-dynode photomultiplier tube. In this circuit, a Base drive is provided for the cascode string, by
    full wave rectifier operating off one winding of a R3 through R7, in a manner which does not affect
    power transformer provides a 15V bias voltage for regulation. Capacitors, C1 through C5, suppress
    the LM 100. The high voltage is produced from a and equalize transients across the pass transistors;
    voltage doubler which operates from a second and clamp diodes across the sensitive emitter-base
    winding. The circuit actually functions as a current junctions of the transistors prevent damage from
    regulator similar to that shown in Figure 6. The voltage transients.
    output current is passed through a resistive divider
    which develops the operating voltages for the This circuit was designed by J. P. Ekstrand of
    cathode and dynodes of the photomultiplier tube. Spectra Physics, Mountain View, California.

    AN8-9
    LINE RESISTANCE COMPENSATOR This circuit was suggested by W. J. Godsey of
    Hayes International Corporation, Birmingham,
    Remote sensing of the load voltage to eliminate Alabama.
    the effects of line resistance can be done with the
    L M100 by connecting the feedback resistors
    directly across the load, rather than at the regu-
    lator output_ However, it may be necessary to USING ALL NPN PASS TRANSISTORS
    increase the size of the frequency compensation
    capacitor ordinarily used with the regulator. In The LM 100 was designed to use a PNP or
    certain applications, remote sensing is undesirable PNP/NPN combination for the series pass element.
    or the actual load is not directly accessible_ An With this configuration, the minimum output-
    example of this is a dc motor application where it input voltage differential is not increased by the
    is desirable to reduce the effects of the armature addition of booster transistors_ However, the
    resistance_ device can also be used with all NPN pass tran-
    sistors as shown in Figure 15.

    r--------~~- ...
    ----IV,N

    R4
    R6
    t Solid Tlntalum 0.1

    ,"--"-'voU>'

    FIGURE 14_ Line Resistance Compensator for


    High Current Regulators

    A circuit which permits compensation of line resis-


    tance is shown in Figure 14_ A negative-going volt-
    age which is proportional to the load current is FIGURE 15_ Circuit for Using the LM100 With all
    produced across R6. Divider resistor, R2, is NPN Pass Elements .
    returned to this voltage so that t~e output voltage
    will increase with increasing load current. The
    ground terminal of the regulator is returned to the
    arm of the potentiometer connected across R6 so With this configuration, it is not possible to use
    that the compensation can be set to exactly cancel the internal current limiting of the LM100, so an
    out the line resistance. With the arm of the external transistor, 03, must be added to provide
    potentiometer on grou nd, the output resistance this function_ Limiting occurs when the voltage
    will be reduced by R6 multiplied by the ratio of drop across R4 is equal to the emitter-base voltage
    R1 to R2_ With the potentiometer set to the of 03_ R5 is also required to make sure that the
    opposite extreme, the output resistance will be LM 100 is operated above its minimum load cur-
    increased by the value of R6. rent.

    There is a reason why R5 is included, and R6 is Th e main advantage of using all NPN pass
    not just made a potentiometer_ It is practically transistors is that the circu it can be operated with
    impossible to find a potentiometer witli a low less capacitance on the output of the regu lator.
    enough resistance value and high enough power When NPN and PNP transistors are used, relatively
    rating. In fact, with higher currents, it is even hard large (1-10 j,lF) bypass capacitors must be con-
    to find a suitable resistor for R6. A 0_1 n, lOW nected on both the input and output of the regu-
    resistor is not easy to find. One way of getting it is lator. Without these, the circuit is susceptible to
    to take a ln, lOW, adjustable, wire-wound resistor oscillations_
    and put two taps at the 1/3 resistance points. The
    three resistor segments are then connected in This design was based on a circuit submitted by E_
    parallel to make a O.lln, lOW resistor_ F. Donner of Lockheed, San Jose, California_

    AN8-10
    '?

    HIGH STABILITY REGULATOR Although the circuit shown is a low current regu-
    lator, this idea is equally useful for high-power
    The performance of regulators with output volt- linear regulators and even switching regulators.
    ages above 10V can be improved considerably by
    the addition of an external temperature-
    compensated reference diode_ Normally, the volt- 14
    age change at the feedback terminal of the LM 100
    due to changes in temperature, load or input volt- 12
    ·11
    age are multiplied by the divider ratio of the feed- 110
    back resistors which determine the output voltage.
    This effect can be reduced by putting a reference
    ..
    t-

    ~
    a:
    8
    "
    :-25"C

    diode in the feedback divider as shown in Fig- '"ffi


    ure 16. The diode permits a lower divider ratio to
    be used and, therefore, improves regulation and ill 4
    6
    l
    '/h--~5"C
    N
    tOD~C-
    drift characteristics.
    o -.e
    10.4 10.6 10.B 11.0 11.2 11.4 11.6 11.8
    ZENER VOLTAGE IV)

    r-----4I~-------t.--VoUT·15V
    FIGURE 17_ Drift Characteristics of an 1N944A as
    R4 a Function of Operating Current
    10

    Cl
    47 pF
    This contribution was made by Ahti Aintila,
    V,N Helsinki, Finland.

    R2
    10K

    PULSE REGULATOR

    Because of the relatively fast operation possible


    with the LM 100, it can be used as a pulse squarer
    t MaV be Adjusted to Improve
    Temperature Drift or pulse regulator. A circuit which accomplishes
    this is shown in Figure 18.

    OUTPUT
    FIGURE 16. High Stability Regulator

    R2

    02
    The regulation of the circuit in Figure 16 is given 2N2369

    by R3
    -=
    R5

    R4
    where Vz is the breakdown voltage of D 1 and V FB
    is the voltage on the feedback terminal of the regu- -= PULSE
    INPUT
    lator. Hence, the improvement in regulation and
    temperature drift (assumi ng no drift in the exter-
    V
    nal diode) will be V OUTV ,which is equal to FIGURE 18_ Pulse Regulator
    OUT- z
    4.5 in the example given.

    The temperature drift can be improved still further


    by adjusting R3 to compensate for the combined In this circuit, R2 and R3 are set up to give the
    drift of D 1 and the LM 1 00. Changing the diode desired pulse height (dc) from the LM100. A
    current changes its drift, as shown in Figure 17. positive-pulse input turns on 01, which disables
    Larger values of R3 make the output voltage tem- the LM100 by grounding the base of the NPN
    perature coefficient more negative, while decreas- emitter followers on the output of the integrated
    ing the resistor makes the temperature coefficient circuit. At the same time, 02 grounds the regu-
    more positive. lator output, providing current-sinking capability.

    AN8-11
    If additional output-current drive is needed, an CONCLUSION
    NPN buffer, similar to that shown in Figure 15,
    should be used on the LM100 in place of a PNP These examples show that certain integrated cir·
    because of the difficulties encountered in sta- cu its can be treated like a component, rather than
    bilizing the PNP circuit without capacitance on the a specialized circuit function. This seems to be
    output_ particularly true for linear integrated circuits. It is
    possible to use almost any standard circu it in a
    This method of pUlsing the circuit on and off, that wide variety of applications by designing imagina-
    is pulling Pin 7 down within one diode drop of tively. If this is done, it is possible to reap the
    ground, can be used as an electrical shutoff for any rewards of standard circuits - low cost and
    of the voltage or current regulators_ immediate availability - in practically any equip-
    ment design.
    Credit for this circuit is given to Don Maurer of
    Medtronic Incorporated, Minneapolis, Minnesota REFERENCES
    and E_ E. Cunningham of Ectron Corporation, San
    Diego, California. 1. R. J. Widlar, "A Versatile, Monolithic Voltage
    Regulator," National Semiconductor Corpora-
    tion AN·1, February, 1967. .
    2. R. J. Widlar, "Designing Switching Regulators,"
    National Semiconductor Corporation AN·2,
    April, 1967.

    ANB-12
    "7

    »z
    I
    December 1968 ~

    "'tJ
    LOW POWER OPERATIONAL o
    LH0001 AMPLIFIER ~
    m
    ::D
    INTRODUCTION CIRCUIT OPERATION
    o
    Although many Integrated Circuit Operational 01,02, R1 and R2 form a simple constant current "'tJ
    Amplifiers are available with excellent character· supply of ""16 /-LA at 25°C, 8 /-LA at +125°C and m
    istics, two areas leave considerable room for 22/-LA at ·55°C. This current is supplied to the ::D
    improvement; namely, offset voltage and power
    requirements. The LHOOOl operational amplifier
    common emitters of the input pair 03 and 04
    which, along with their load resistors R3 and R4,
    ~
    has been designed to provide extremely low offset form a simple differential amplifier. The low fre· o
    z
    voltages (typically 0.2 millivolts at 25°C) and qui·
    escent supply currents in the 100 /-LA range, while
    quency gain of this stage is approximately 30,
    minimizing the effect on the input of changes in »
    r-
    still providing reasonable loaded output swings and offset voltage in the second stage pair, 05 and 06.
    a compensated gain bandwidth in the 0.5 to r-
    1.0 MHz range. The circuit diagram (Figure 1A and The second stage differential pair with high imped· ::I:
    1 B) shows the simplicity of the LH0001; the only ance load, 08, form the main voltage gain of the
    o
    o
    unusual characteristic being the use of PNP tran' amplifier. Typical values of collector currents in o
    ~
    sistors in the input stages for improved beta vs. 05 and 06 are 20/-LA each and the voltage gain of
    temperature linearity and lower noise. th is stage is approx imately 2000.
    »
    The output section is simply a compound s:"'tJ
    NPN - PNP pair providing isolation between the
    high impedance junction of the collectors of 06 !:
    ."
    and 08, and the load.
    R6 R7 m
    SDK SDK Operation from Single Power Supply ::D

    When operating from ±V supplies, pin 7 is


    normally returned to ground. When operating
    from a single supply, or when no ground is avail·
    able, pin 7 may be directly connected to pin 3, for
    voltages equal to or less than 20 volts between
    pins 3 and 9. This will increase the quiescent cur·
    L-~I--l0
    rent since the effect of connecting pin 7 to pin 3 is
    _C:,:O:;:M::.,P+_+_ _ _+ _ + - - , ~~~MP to connect the 600K resistor, R 1, across the full
    COMPENSATION power supplies. Since the minimum current reo
    5 COMP quired from pin 7 is 10/-LA, an external resistor
    Rl R4
    (Rx) may be inserted in series with R 1 from pin 7
    lOOK lOOK to pin 3.
    ~~~---~~---~~v=- l
    Recommended range for value of Rx is shown in
    Figure 2.
    Figure lA. LHOOOl Schematic.

    V
    :L
    f"
    - l - t- MAX.
    1/
    .....
    -:;. p.- ~ ~
    , ~ ~ f"" I-
    10 20 30 40
    COMPENSATION
    VOLTAGE BETWEEN PINS 3 & 9
    TOPVIEW
    Figure 2. Range of Resistor Values Inserted from Pin 7
    Figura 18. LH0001 Pin Configuration. to Pin 3 when Pin 7 is not grounded.

    AN1Q-1
    Clamped Output Swing
    The output voltage can be quite effectively held
    between specified limits by means of diode clamps • VOUT

    on pin 10. From Figure 3 which is the output sec-


    tion of the LH0001, clamping pin 10 will maintain • V"'EF

    the output within one VBe of pin 10. Since IB(+)


    and IBH are limited to approximately 75IJ.A at
    • v,.
    J
    25°C, the extra quiescent current is quite nominal. •
    'v
    o Z 4 6810121416 II za
    TIME (j,lsec)

    Figure 5B. Output Waveform When Used in Circuit of


    OUTPUf Fig. 5A.
    .NO

    For driving MOS inputs or clocks, the LHOOOl is


    connected as follows:
    'v
    tiDY
    Figure 3. Output of LHOOOI

    A specified output range may be obtained by


    appropriate connection of diodes from pin 10 to
    the reference limits. Figure 4 shows the connec-
    .3V
    tions for various reference levels.
    A typical use of a clamp on pin 10 is to provide
    compatible drive for either DTL or T2 L logic cir-.
    cuits. This is usually accomplished with a 5 volt
    Zener diode or the emitter·base junction of a Figure 6A. LHOOOI As Comparator For Driving MOS.

    Delay and storage times of 3 to 5 IJ.sec will be


    INPUTS
    observed with rise and fall voltage rates of 2 to
    4 volts/lJ.sec. Capacitance loads of up to 1000 pF
    will not noticeably increase the switching times.

    I I
    -", INPUT

    INPUTS
    l- I I-- l- I-
    IS 'I-- P I-- Vz~1.5V "
    ~ -10
    -15

    -.,,
    1\
    , \lz=15V

    I
    Ivz "25V J
    J

    -. I
    -311
    o 10 203048 506D 1080
    TIMEj.l1IK

    Figure 6B. Output Waveform For Circuit of Fig. 6A.

    Input Offset Voltage Balancing


    Figure 4. Methods of Restricting Output Voltage Swing.
    Although the offset voltage of the LH0001. is
    switching transistor such as the 2N2369. Figure 5 quite low, it is possible that even lower values are
    shows the LHOOOl used as a comparator with a required. Figure 7 shows the recommended balanc-
    diode clamp on pin 10. ing technique.
    +ISV

    OUTPUT

    -ISV

    Figure 5A. LHOOOI As Comparator For Driving DTL or T 2 L. Figure 7. Method of Balancing Input Offset Voltaga.

    AN10-2
    Input Bias Current Compensation pins 1 to 5 in opposite directions, the short circuit
    Methods of compensation recommended in NS current will be reduced in both the positive and
    Application Note AN-3 can all be successfully used negative direction.
    with the LHOOOl with the exception that all po-
    Figure 9 shows the connections and Figure 10
    larities are reversed and NPN bias transistors sub-
    gives the typical short circuit currents available
    stituted for the PNP uni~s_ Transistor type 2N2484
    both with and without the diode clamps.
    units are recommended, For optimum compensa-
    tion over a wide temperature range, the method of

    INPUTS~HODD15
    generating the emitter current of the compensating
    transistor shown in Figure 4 and 6 of AN-3 should
    be modified to be similar to the current source lOUT

    used in the LH0001. Figure 8 shows the recom- , ....


    mended circuit.

    Figure 9. Method of Reducing Output Short Circuit


    Current.

    If this control is not adequate, external limiting as


    shown in Figure 11 can be used to limit lOUT to
    less than 1 mAo

    Referring to Figure 2, in the limiting mode, the


    VBE of the conducting output transistors (09 or
    010) will add to the drop across RUM to be equal
    Qt-az"Ql·IN2""'OAEQUIVAlUll
    "AOJUST FOR ZERO INPIJTCURRENT
    to the sum of the two forward drops of conduct-
    ing diodes between pin 10 and the output. Thus
    the output current will be limited to that value
    Figure 8. Method of Compensating for Input Bias Current.
    which causes approximately one diode forward
    Increased Output Swing OJ
    POSITIVE OUTPU~.l, Ys = !15V
    For lightly loaded outputs (RL ~ 10K), the maxi-
    mum negative output swing will exceed the posi- . ..,.... WITHOUT CLAMP

    .......
    tive swing by approximately a volt. If the maxi- WITH tAMP
    mum positive swing is required, it may be obtained
    by connecting a low capacitance (C ~ 2 pF at zero ".
    volts) diode between pins 1 and 5, with the cath- ,
    ode on pin 1. Table 1 shows the typical positive
    and negative swing with RL ~ 100 Kn both with
    and without the diode clamp.
    , 50
    -50 '01 '50
    TEMPERATURE ~c

    TABLE 1 Maximum Output Swings vs Supply Figure 10A. Short Circuit Output Current.
    Voltage
    Supply Voltage ±5V ±10V ±15V ±20V
    .. NEGATIV~ OUTPUT
    Vs· !15V

    Typical Negative ,
    Output 3.8 8.8 13.5 18.4

    -
    WITHOUT CLAMP

    Typical Positive ' ...... WITH CLAMP


    Output without
    Diode Clamp
    Typical Positive
    2.7 7.6 12.2 17.0 ,"""'"
    Output with ,-so
    " 10' 15'
    Diode Clamp 3.6 8.4 13.0 18.0 TEMPERATURE °c

    TA ~ 25°C Figure 10B. Short Circuit Output Current.

    As explained in the following section, the inclu- drop across R LIM' In addition, the diode current
    sion of a diode from pin 1 to 5, in addition to which may be as high as 75 p.A at 25°C will be
    increasing the available positive output. voltage, added to the output current.
    will also reduce the maximum positive short cir-
    cuit current.
    Reducing the Short-Circuit Current
    As mentioned above, a diode connected from
    pin 1 to pin 5 will reduce the positive output short
    circuit current. If the polarity of the diode is re-
    versed, the negative short circuit current will be Figure 11. Alternate Method of Limiting Output Short
    similarly reduced. If 2 diodes are connected from Circuit Current.

    AN10-3
    Typical Performance of the LHOOOl Operational
    Amplifier (V s = ±15V, T = 25°C)
    PARAMETER CONDITION VALUE
    Input Offset
    Voltage RsS5K 0.2 mV

    Input Offset
    Current 3 nA

    Input Bias
    Current 30 nA

    Positive Supply
    Current 80 llA

    Negative Supply
    Current 551lA

    Voltage Gain RL = 100K 60,000


    Output Voltage RL = lOOK ±12V
    CMRR RsS5K 90 dB
    PSRR RsS5K 96 dB
    Temperature
    -55°C to 125°C
    Range
    Temperature
    4IlV/oC
    Drift
    Supply Voltage
    Range ±5V to ±20V

    REFERENCE:

    R. J. Widlar, "Drift Compensation Techniques for


    Integrated DC Amplifiers" AN·3, National Semi-
    conductor, April, 1968_

    AN10-4
    "7

    Septem ber '1968 ...


    Z
    I

    eN

    ~
    "tJ
    "tJ
    !::
    APPLICATION OF THE LH0002 (")

    ~
    CURRENT AMPLIFIER

    INTRODUCTION o
    The LH0002 Current Amplifier integrated build-
    z
    v+ v+
    ing block provides a wide band unity gain ampli-
    fier capable of providing peak currents of up to
    1 2 o
    ±200 mA into a 50 ohm load.
    R2
    "-I
    The circuit uses thick film technology to integrate
    5kn ::I:
    L QJ
    m
    2 NPN and 2 PNP complementary matched silicon t..
    transistors with 4 cermet resistors on a single r-
    alumina ceramic substrate. A circuit schematic is ~ ~3
    J:
    shown in Figure 1. The negative thermal feedback RJ o
    provided by the close proximity of the compo- zn o
    nents on a single substrate eliminates any thermal o
    INPUT 8~ ~4 OUTPUT N
    runaway problem that could occur if this circuit
    were constructed using discrete components. R4 (")
    zn
    ___ 5 C
    A typical circuit features a dynamic input imped- ---K; Q2 ::c
    ance of 200 Kohms, an output impedance of ::c
    6 ohms, DC'to 50 MHz bandwidth, and an output
    I'" Q4
    ..... m
    voltage swing that approaches supply voltage. A
    Z
    Rl -I
    complete list of the guaranteed and typical values 5kn
    for the electrical characteristics under the stated
    E~
    »
    conditions is given in Table 1. These features make 1 6 ~
    the LH0002 ideal for integration with an opera- v- v- "tJ
    tional amplifier inside a closed loop configuration FIGURE 1. Circuit Schematic !::
    "::cm
    TABLE 1. Electrical characteristics, specification applies for TA = 25°C with +12.0V on pins 1 and 2; -12.0V on pins 6 and 7.

    PARAMETERS CONDITIONS MIN TYP MAX UNITS

    Voltage Gain Rs = 10 kU, RL = 1.0 kU .95 .97


    VIN :::; 3.0 V pp, f = 1.0 kHz
    T A::: -5Soc to 12SoC

    Input Impedance Rs =200 kil, V IN ::: 1.0 Vrms• 180 200 - kU


    f = 1.0 kHz, RL = 1.0 kU

    Output Impedance VIN == 1.0 V rms • f '" 1.0 kHz - 6 10 U


    RL = SOU, Rs = 10 kU

    Output Voltage Swing RL = 1.0 kU, f· 1.0 kHz ±10 ±11 - V

    DC Input Offset Voltage Rs· 10kU, RL = 1.0kU - ±40 ±100 rnV


    T A ~ -5SQ c to 12SoC

    DC Input Offset Current Rs= 10kU, RL = 1.0kU - ±6.0 ±10 itA


    TA = -5SQ C to 12SoC

    Harmonic Distortion VIN '" 5.0 V rms• f:::: 1.0 kHz - 0.1 - %

    Bandwidth V IN ::: 1.0 V rms • RL = son, 30 50 - MHz


    f= 1 MHz

    Positive Supply Current Rs = 10 kU, RL = 1 kU - +6.0 +10.0 rnA

    Negative Supply Current Rs =10kU,R L =lkU - -6.0 -10.0 rnA

    AN13-1
    to increase its current output. The symmetrical impedances over a wide frequency range. The out-
    class B output portion of the circuit also provides put impedance of the amplifier is very low,
    a constant low output impedance for both the pos· 6 ohms typically, and in conjunction with a volt-
    itive and negative slopes of output pulses. age bandwidth of approximately 50 MHz can be
    considered to be insignificant for most applica-
    CIRCUIT OPERATION tions for this type of device.

    The majority of circuit applications will use A plot of the voltage bandwidth is shown in Figure
    symmetrical power supplies, with equal positive 3. Inspection of this plot shows that phase infor-
    voltage being applied to pins 1 and 2, and equal mation as well as gain information was included to
    negative voltage applied to pins 6 and 7. The rea· assist users of this device. For example, at 10 MHz,
    son that pin 2 and pin 6 are not connected inter- less than an 8° phase lag would be subtracted from
    nally to pin 1 and pin 7, respectively, is to increase the phase margin of an operational amplifier when
    the versatility of circuit operation by allowing a it is integrated with this device. The open loop
    decreased voltage to be applied to pins 2 and 6 to gain of the operational amplifier would be de-
    minimize the power dissipation in 03 and 04. The creased by less than 10% at 10 MHz and therefore
    larger voltage applied to the input stage also pro- can be considered to be insignificant for most ap-
    vides increased current drive as required to the plications.
    output stage.
    1.0 -40
    The operation of the circuit can be understood by VOLTAGE GAIN
    considering that the input pin 8 is at VIN. The ! 0.8 ~ -32
    emitter of 01 will be approximately 0.6 volt more
    positive than VIN at 25°C, and the converse is true
    for 02. This 0.6 volt will provide a forward bias on
    ~

    .
    ~

    ~ 0.6

    C
    fREDUENCY RESPONSE
    ",r- 1.
    VIN· t.IV Ins. RL '" 50 ohms,. VI" !1Z.DY
    TA"2S·C
    - -24 ll'
    ~

    03 to cancel out the 01 base to emitter drop


    which in turn would provide VIN at the output if
    all junctions, resistors, power supplies, etc., were
    ..~
    ~ '0.4
    /
    -1& ~
    ~
    ~ 0.2 . / PHASi- -8 iE
    electrically identical. The greatest error is intro- ./
    duced because the forward drops in the base- 0.1 .......... I 0
    emitter junctions for the NPN and PNP devices are 1.0 2.0 5.0 10.0 20.0 50.0 100
    slightly different. For example, the V Be of the FREQUENCY (MHz)
    NPN will be typically 0.6V and the VBe of the
    PNP will be typically 0.64V under the same condi- FIGURE 3. Frequency Response
    tions of Ic; 2.4 mA at Vce; 12.0V at 25°C.
    These are the approximate input stage circuit con-
    ditions for Oland 02 for plus and minus 12V APPLICATIONS
    supplies. Fortunately, this error in both input and
    output offset voltage is almost always negligible Figure 4 shows the LH0002 integrated with the
    when it is used inside the closed loop of a high LH0005 to provide differential inputs and out-
    gain operational amplifier. puts. In order for this circuit to funtion properly,
    a load must be floated between the outputs of the
    A plot of input impedance vs frequency is shown two devices to provide a comp lete loop of feed-
    in Figure 2. Inspection of this plot shows that the back. A differential head on a scope across the
    input impedance can be closely approximated to load presents a true waveform of the actual signal
    that of a simple first order linear network with a being applied to it. If only one end of the load is
    45° phase lag at 0.6 MHz and a 90° phase lag at displayed, it will appear distorted because this in-
    approximately one decade higher in frequency. formation is being fed back negatively to the input
    This information is very useful for designers who in order to cancel out the loop distortion or the
    have to integrate circu its wh ich have large source overall amplifier. With the compensation shown, a
    20V peak to peak signal can be applied to a
    IN'UTI"'IDANCElM"G.ITUOEAIIOIII~
    -100 100 ohm load to 80 KHz. The overall circuit is
    V, .. ·IIV.IM,RL·SB ....... ' .... UDV
    o R,'IGIC-.,T.. ·ZS·C
    approximately 33% efficient under these condi-
    YPHASE
    tions. A derating factor and/or heat sink must be
    used at higher temperatures, as shown by the
    o~ / III LH0002 and LH0005 data sheets.
    III
    0
    1-0.. MAGNITUDE
    Additional output power could also be obtained
    r--. by connecting another LH0002 to pin 9 of the·
    1 1/ -20 operational amplifier. The overall load distortion
    ./
    under high circuit voltage gain configurations
    o o would also be reduced using two LH0002's be-
    0.1 0.2 0.5 10
    cause the LH0002 is more linear than the simple
    FREQUENCY (MHz)
    output circuits of these particular operational
    FIGURE 2. Input Impedance vs Frequency amplifiers.

    AN13-2
    lOOK ± 1/4%

    +12V

    V'N (1) o-'VII'r"'--~l'

    V'N (2) o-'VII'r... -+-.,...,f

    VOUT (1)

    100
    LOAD
    VOUT (2)

    DiH. VOUT (VOUT (1) - VOUT (2)


    ·'0 (V'N (2) - V'N (1)

    FIGURE 4. Differential Input-Output Operational Amplifier Integration

    Figure 5 shows the LH0002 integrated with the A breadboard of this configuration was assembled
    LH10l in a booster follower configuration. The to empirically check the increase in offset voltage
    configuration is stable without the requirement for due to the addition of the LH0002. The offset
    any external compensation; however, it would be- voltage was measured with and without an
    hoove the designer to be conservative and bypass LH0002 inside the loop with a voltage gain of
    both the negative and positive power supplies with 100, at _55°C, 25°C and 125"C. The additional
    at least a O.Olllf capacitor to cancel out any offset voltage was less than 0.3% for all three tem-
    p ower supply lead inductance. A 100 ohm perature conditions even though the offset voltage
    damping resistor, located right at the input of the of the LH0002 is much higher than that of the
    'LH0002, might also be required between the oper- LH101. The high open loop gain of the LH10l
    ational amplifier and the booster amplifier. The divides out this source of circuit error. The integra-
    physical layout will determine the requirement for tion of this device also allows higher closed loop
    this type of oscillation suppression. Current limit- circuit gain without excessive cross-over distortion
    ing can be added by incorporating series resistors than would be obtainable with the simple booster
    from pins 2 and 6 to their respective power sup- amplifier shown in Figure 6.
    plies. The exact value would be a function of
    power supply voltage and required operating tem-
    perature.
    V+

    R2

    Rl
    INPUT --"INIt"4....:.t,

    OUTPUT V'N VOUT

    V-

    FIGURE 5. lHl0l-lH0002 Booster Amplifier Integration. FIGURE 6. Simple Booster Amplifier

    AN13-3
    Figure 7 shows the LH0002 being used as a level
    shifter with a high pass filter on the input in order
    to reference the output to zero quiescent volts.
    V,N

    r~"'
    The purpose of the 10 Kohm resistor is to provide
    current bias to the circuit's input transistors to
    reduce the output offset voltage. Figure 3, Input
    Impedance vs Frequency, provides a useful design
    aid in order to determine the value of the capaci-
    PULSE·TRANSfORMER
    tor for the particular application. The 10 Kohm
    resistor, of course, has to be considered as being in FIGURE B. Driver for a Pulse-Transformer
    parallel with the circuit's input impedance.

    For a pulse input signal, the output impedance of


    the circuit remains low for both the positive and The LH0002 can also be used to drive long tran-
    negative portions of the output pulse. This circuit smission lines. Figure 9 shows a circuit configura-
    provides both fast rise and fall times for pulse tion to match the output impedance of the ampli-
    signals, even with capacitive loading. The LH0002 fier to the load and coaxial cable for proper line
    data sheet shows typical rise and fall times for terminatiol'l to minimize reflections. A capacitor
    both positive and negative pulses into a 50 ohm can be added to empirically adjust the time re-
    load. sponse of the waveform.

    Select tlp.citor to adjust time response of pur..

    "'>--4,....-4,....-0 VOUT

    V,N

    FIG UR E 7. Level Shifter

    FIGURE 9. Transmission Line Driver

    Figure 8 shows the LH0002 being used to drive a


    pulse-transformer. The low output offset voltage SUMMARY
    allows the pulse transformer to be directly coupled
    to the amplifier without using a coupling capacitor The mu Ititude of different applications suggested
    to prevent saturation. The pulse transformer can be in this article shows the versatility of the LH0002.
    used to change the amplitude and impedance level The applications specially covered were for a dif-
    of the pulse, the polarity of the pulses, or, with ferential input-output operational amplifier, boost-
    the aid of a center-tapped winding, positive and er amplifier, level shifter, driver for a pulse-
    negative pulses simultaneously. transformer, and transmission line driver.

    AN13-4
    »z
    August 1968 ...,
    U1

    »
    n
    o
    A COMPLETE MONOLITHIC IF STRIP
    s:
    "U
    r
    FOR AM/AGC APPLICATIONS m
    -I
    m
    INTRODUCTION
    s
    Intermediate-frequency amplifiers in superhetero- Economics dictated the simplest detector schemes, o
    dyne receivers and signal-frequency amplifiers in usually a single diode, biased from a tuned trans- :2
    T_R_F _ receivers have traditionally been parti- former secondary_ AGC voltage was usually or
    tioned into a number of discrete power-gain stages, obtained directly from the diode detector. Gener-
    with interstage networks performing both DC ally, because of large tuned gain and, often, mar- ::j
    decoupling and bandpass shaping functions_ As ginal stability in the conventional common-emitter :J:
    long as the active components (vacuum tubes or stage, power-supply decoupling was required for n
    transistors) comprised a substantial part of the each stage_
    "strip's" total cost, it made sense to design on a "T1
    "cost-per-stage" basis_ Suppose, however, that the above requirements are CJ)
    largely eliminated by availability of almost un- -I
    A number of currently available microcircuits, limited monolithic 'complexity and inherent inter- :XI
    such as types LM703 and LM171, provided a nal biasing. It would be much more efficient to ."
    transitional opportunity for RF system designers put all power gain in a single, lumped stage, pre-
    "T1
    to use proven interstage network designs, substi-
    tuting the self-contained, inherently stable, high
    ceded by a single (perhaps mu Itisection, for selec-
    tivity) bandpass filter. This would considerably
    o
    :XI
    gain-bandwidth product microcircuit directly for a reduce the assembly and alignment labor in an AM
    conventional common-emitter IF stage_ While the receiver. Rather than deal with the sizeable prob- »
    excellent FM limiting and AGC characteristics of
    such monolithic stages have already proven them-
    lems of AGC in direct-coupled, high-gain ampli-
    fiers, a simpler approach is to achieve full gain-
    s:
    .......
    selves in commercial and entertainment equip- control range through a high-performance variable »
    G)
    ment, they have usually constituted performance, attenuator stage, between the input bandpass filter
    rather than cost, advantages to the system manu- and the input to the lumped gain stage, leaving the n
    facturer. lumped gain stage at its maximum gain at all times.
    Finally, an AM detector is desirable which can be
    »
    ."
    Monolithic technology has already emerged, in the directly coupled to the gain stage output, which is ."
    digital area, from an initial period of novelty and a insensitive to DC biasing, and which reliably pro- C
    subsequent period of superior performance, into vides a DC AGC voltage compatible with the input n
    the current realization that, against MSI or LSI,
    discrete transistor computing systems cannot be
    variable attenuator. A block diagram of the new
    subsystem appears in Figure 1. ~
    competitive_ The linear circuit to be described, a o
    multifunction IF strip, is a step in the same direc- z
    CJ)
    tion, in which a number of discrete circuit func-
    tions have been combined, replacing not only the AUDIO
    OUT
    active elements and DC biasing components, but AGC R4
    eliminating many of the peripheral IF elements as
    well_
    C4

    A SYSTEM APPROACH

    Monolithic techniques allow a rethinking of tra-


    ditional IF strip partitioning_ Previously, the
    *"
    ~CJ
    most efficient utilization of available power gain
    was obtained by matched, tuned, interstage net-
    works_ Because of the limited AGC range obtain-
    able by varying DC emitter current in a conven- CI
    tional common-emitter I F stage, several stages IN~
    received AGC voltage from the detector at once_
    This dictated combersome DC biasing to obtain
    the desired AGC characteristic, and made an input
    and an output transformer mandatory for each
    stage, to decouple DC-operating point shifts due to
    AGC operation_ FIGURE 1_ LM172 Block Diagram

    AN15-1
    A PRACTICAL MONOLITH

    A complete schematic for National Semicon- follower, with R2as load_ When VAGe equals3 Vbe ,
    ductor's AM IF Strip, the LMl72/272, appears in 02 and 03 form a balanced differential pair, con-
    Figure 2_ All capacitors shown are external to ducting equal emitter currents from "current
    the 8 pin, T05 package; these capacitors establish source" R2, and as VAGe increases, 03 turns
    the minimal amount of decoupling and time con- increasingly on, with 02 turning off_ As this
    stants required to operate such a complex, high occurs, the effective emitter resistance of 02
    gain-bandwidth product microcircuit_ increases, in series with the input signal, while the
    emitter resistance of 03 decreases, shunting across
    the signal. Thus, 02 and 03 form a series-shunt
    Examining first the AGC section, Figure 3, it may attenuator, with minimum attenuation of 0 dB_
    be seen that an emitter-coupled pair is used as a Since the base of 02 remains at a fixed bias, while
    series-shunt variable attenuator_ The base of 02 is that of 03 increases with AGC, the DC output
    held at a DC voltage of two forward diode drops, voltage at the common emitter point rises slightly
    2 Vbe, by emitter follower 01 and R1, with only as gain is decreased_ Consequently, a decoupling
    AC signals coupled through an input capacitor_ If capacitor is needed between the AGC stage and
    V AGe is held below 3 Vbe , 03 will becompletely the lumped-gain stage, to prevent unbiasing the
    off, and 02 behaves as an ordinary emitter gain stage with AGC variations.

    Vee

    07

    06

    D.

    D.

    GND

    o pin numbers appear in circles

    FIGURE 2. LM172 AGe AM IF Strip

    AN15-2
    ,---e---..--..., +vcc
    4 V.. 5 v..

    R9 R1D R11
    G.OII 6.0K 6.DK
    RD
    15K
    _>--e~tV~~--~-~o--RFOUT
    RF-I
    IN
    Cl
    R7
    15K
    CJ

    RF IN T
    r---1
    CZ CZ

    FIGURE 3. AGe Section FIGURE 4. Lumped Gain Stage

    The lumped·gain stage, Figure 4, is basically a cas· A number of improvements may be made over the
    cade of three common-emitter amplifiers, direct- conventional AM diode detector. Unless simple
    coupled. A conventional, discrete transistor ver- diodes are slightly forward·biased by additional
    sion of this cascade would require much more circuitry, they will not respond to small-input sig·
    complex, less-efficient DC biasing. Notice that no nals, because of the voltage required to overcome
    emitter resistors are used; this gives maximum vol- forward Vbe • Moreover, diode detectors are ineffi-
    tage gain per stage, but still allows reliable biasing, cient, generally giving less audio output than is
    since an overall DC feedback loop, R8, C3, 05 and available from the modulated carrier. A more
    R6, automatically sets the DC output voltage of nearly ideal detector, Figure 5, is one found in
    each transistor to exactly the right level to cor- most operational amplifier handbooks. If gain of
    rectly bias the followi ng transistor. The feedback the operational amplifier is sufficiently high, audio
    loop is effective only for DC, because of the output exactly follows modulation envelope; since
    R8-C3 rolloff; thus maximum AC gain is always the diode is inside a feedback loop, the operational
    attained with DC stability. Notice that the collec- amplifier will automatically bias the diode to
    tors of 06 and 07 are operated at Vbe' to satisfy respond to small signals. When no carrier is pres-
    biasing of following stages; thus, they operate with ent, DC output voltage is zero. An unmodulated
    zero volts collector to base, and still exhibit excel- carrier causes DC output vol tage to rise to one-half
    lent current gain and gain-bandwidth product, by the peak-to-peak R F level. Superimposing audio
    virtue of their very small geometries and low- modulation on the carrier has no effect on the
    saturation voltages. The three collector-load resis- average, or DC output voltage, but causes the RC
    tances, R9, R 10 and R 11, are biased from their network to "follow" the modulation envelope
    own emitter-follower voltage regulators, which on the positive side of the carrier.
    eliminate supply decoupling problems, and allow
    the active part of the circuit to operate with con-
    stant bias conditions, regardless of power-supply A simple modification to the active detector of
    voltage. Since each part of the circuit is supply- Figure 5 is the addition of a resistive divider,
    regulated in this way, supply current does not Figure 6. While basic operation remains un-
    increase linearly with supply voltage, as in most changed, the active detector now has an audio and
    designs, but remains relatively constant. Thus, the DC voltage gain equal to (R1 + R2)/R2. Such a
    circuit remains highly efficient at low-supply vol- detector can perform some of the audio preampli-
    tages, without excessive drain at higher voltages. fication necessary in the radio receiver.

    AN15-3
    +Vee

    1 V..

    IN
    Rll
    6.2K

    F1GURE 5. Unity Gain Active Deetor


    RI6
    014 soon

    OUT
    RI4
    4K ~cs

    RF IN 012
    RI
    RIS
    RI2 2K
    3K

    09
    ':::' 08

    ':::'

    FIGURE 6. Active Detector with Voltage Gain FIGURE 7. Active Detector

    The actual active detector used in the LM 172 is a


    differential amplifier, Figure 7. with an emitter
    follower performi ng the function of the feedback
    diode. While not an operational amplifier, the
    circuit's voltage gain of about 40 dB is sufficient
    to provide excellent detection. Because an emitter
    follower was substituted for the diode, output
    impedance is low; it would, in fact, be too low for
    effective carrier ripple filtering by C5, if it were
    not for the addition of R 16. A resistive divider,
    R 14 and R 15, give the detector an audio voltage
    gain of 3, with D8 and D9 compensating for the
    DC voltage (2 V bo) superimposed on the R F input
    voltage by the preceding lumped gain stage. Q 13
    acts as a supply regulator for the differential
    amplifier.

    The entire circuit fits on a small 33 x 33.5 mil


    monolithic chip (Figure 8), and in view of the
    self·contained feedback loops, which automat·
    ically compensate for component parameter varia-
    tions, is an unusually reproducible microcircuit. FIGURE 8. Chip Photo

    AN15-4
    7"

    LM172 APPLICATIONS

    SUPERHETERODYNE RECEIVER IF STRI:>

    By far the most popular receiver configuration, in Total Supply drain into LMl72, Vcc =+6V:
    military, two·way·radio and entertainment use, is 1,4 mA, or 8,4 mW.
    one in which the incoming signal is amplified, and Improved selectivity mal' be obtained by substitut·
    then translated, via a mixer, to a standard inter· ing another ceramic filter between Pins 1 and 3,
    mediate frequency, where most of the receiver's instead of C2. The 3K impedances at Pins 1, 2
    voltage gain and selectivity is achieved. A typical and 3 are especially suited to tile inel:pensive
    system appears in Figure 9. Conventional circuitry Murata filters. While audio distortion occurs for
    may be used ahead of the LM 172; although a voltages at Pin 2 much above 100 mV rms. distor·
    double·section 455 kHz ceramic filter is shown, tion is low for signals within the AGC range of the
    LC filtering may be used if desired. The circuit circuit. Gain in the RF amplifier and mixer must
    works effectively for I F frequencies between therefore be chosen to provide signals less than
    50 kHz and 2 MHz, depending on input bandpass 100 mV into Pin 2 for the desired range of RF
    components. Capacitors C2, C3 and C5 should be input levels. Additional AGe is possible by using
    scaled proportionately at frequencies other than the DC voltage appearing at Pin 7 to control the
    455 kHz. gain of the input R F ampl ifier. Since AGC action
    occurs at and above 3 Vb., the National LM171
    RF/I F Amplifier, operated as a cascode, is ideally
    The circuit of Figure 9 exhibits the following IF
    suited to such front·end control, as its gain· control
    characteristics:
    voltage region coincides with that of the LM 172.
    AGC Range (referred to Pin 2) from 50/1V to Because of the built·in supply regulation, the strip
    50 mV: 60 dB operates with supply voltage varying from +6 to
    Audio output for 80% modulated carrier, with· +15 volts with no perceptible changes in receiver
    in AGC range: 0.8V p.p performance.

    FIGURE 9. Superheterodyne Block Diagram

    AN15-5
    LOW FREQUENCY T.R.F. RECEIVER

    Because the LM 172 is a broadband functional A ferrite "Ioopstick" antenna, LI, resonates with a
    module. it may be used to amplify and detect sig- small, polyethylene dielectric tuning capacitor
    nals below 2 MHz directly, without the more com- within the broadcast band. The LM 172 performs
    plex frequency conversion of superheterodyne its gain function just as it would in an IF applica-
    receivers. In the AM Broadcast Band tion, but in this case, directly drives a class A
    (550-1650 kHz), the strip has sufficient sensitivity power amplifier. Since the DC output voltage at
    to operate alone in urban reception areas, since Pin 6 is relatively constant (from 2.1 to about
    AGC action is useful down to about 50 microvolts 2.4 volts as a function of AGC), it is used to bias
    at Pin 2. With additional gain either preceding the the class A stage directly, eliminating a number of
    module, or inserted between Pins 1 and 3, it may components. C7 and C8 are needed to prevent
    also be useful in monitoring Loran (1.8-2.0 MHz). regenerative audio oscillations with weak batteries.
    or the numerous directional and informational Total receiver drain from the. 9-volt supply is
    channels below 550 kHz. 10 mA, of which only 1.9 mA is used in the
    LMl72; the rest is needed for the audio amplifier.
    While the complete T.R.F. (Tuned Radio Fre-
    quency) broadcast receiver of Figure 10 has rela-
    tively poor selectivity, because only a single, low
    "a" tuned circuit is used in the entire receiver, it A volume control was not provided in the proto-
    serves to illustrate the straightforward design pos- type, as volume was excellent with the small (2"
    sible in T.R.F. construction. More sophisticated diameter) speaker used, and AGC was so effective
    designs might use multisection tuning, ahead of that no perceptible difference in stations was
    the strip. The prototype was constructed using heard. Volume control is possible by inserting a
    very inexpensive imported "transistor-radio" com- potentiometer between the emitter of the audio
    ponents. output transistor and R 1.

    1t
    +9V BATTERY

    9
    365pF

    ':' Cl

    .01pf
    FERRITE
    LOOPSTICK C2
    Ll .01 ",t

    l1 - Ferrite Loopstick - Philmore FF15 (plebged IS set of J sizesl


    C9 - Sub·miniature variabl! capacitor - Philmore 1949G - 365 pF miX.
    T1 - Midget Audio Transformer. 10000.:80 - Archer 273-1380 (Radio ShiCk, Inc.)
    SPKR - 2" PM Speaker, an, 0.1 watt - Philmore TS20

    FIGURE 10. T.R.F. Broadcast Receiver

    AN15-6
    7

    l>
    2
    February 1969 N
    o
    l>
    2
    l>
    "'tJ
    "tI
    C
    AN APPLICATIONS GUIDE FOR n
    OPERATIONAL AMPLIFIERS l>
    ::!
    o
    2
    en
    G')
    INTRODUCTION c
    The general utility of the operational amplifier is sated so frequency stabilization components are o
    not shown; however, other amplifiers may be used
    m
    derived from the fact that it is intended for use in
    a feedback loop whose feedback properties deter- to achieve greater operating speed in many circuits -n
    mine the feed-forward characteristics of the ampli- as will be shown in the text. Amplifier parameter o;:.1.'.1
    fier and loop combination. To suit it for this definitions are contained in Appendix I.
    usage, the ideal operational amplifier would have
    infinite input impedance, zero output impedance, THE INVERTING AMPLIFIER
    o"tI
    infinite gain and an open·loop 3 dB point at m
    infinite frequency rolling off at 6 dB per octave. The basic operational amplifier circuit is shown in ::c
    Unfortunately, the unit cost-in quantity-would Figure 1. This circuit gives closed-loop gain of
    R2/R1 when this ratio is small compared with the ~
    also be infinite.
    amplifier open·loop gain and, as the name implies,
    is an inverting circuit. The input impedance is
    o
    ;2
    Intensive development of the operational ampli-
    fier, particularly in integrated form, has yielded equal to R1. The closed· loop bandwidth is equal l>
    circuits which are quite good engineering approxi· to the unity·gain frequency divided by one plus r-
    mations of the ideal for finite cost. Quantity prices the closed·loop gain. »
    for the best contemporary integrated amplifiers
    The only cautions to be observed are that R3
    s:
    are low compared with transistor prices of five "tI
    years ago. The low cost and high quality of these should be chosen to be equal to the parallel com- C
    amplifiers allows the implementation of equip· bination of R1 and R2 to minimize the offset volt- -n
    ment and systems functions impractical with age error due to bias current and that there will be m
    discrete components. An example is the low fre· an offset voltage at the amplifier output equal to :xl
    quency function generator which may use 15 to closed-loop gain times the offset voltage at the en
    20 operational ampl ifiers in generation, wave amplifier input.
    shaping, triggering and phase-locking.

    The availability of the low-cost integrated ampli- .2


    fier makes it mandatory that systems and equip·
    ments engineers be familiar with operational
    amplifier applications. This paper will present
    amplifier usages ranging from the simple unity-gain
    ., ~
    VON ......'IJ\<1I.-...~2 -
    LH101 6 P- "OUl
    buffer to relatively complex generator and wave· .2.
    shaping circuits. The general theory of operational VOUT= -~VII\I
    .3
    amplifiers is not within the scope of this paper and RJ= Rl11R2
    FOR MINIMUM ERROR DUE
    many excellent references are available in the TO INPUT BIAS CURRENT
    literature.1,2,3,4 The approach will be shaded
    toward the practical, amplifier parameters will be
    discussed as they affect circuit performance, and FIGURE 1. Inverting Amplifier
    application restrictions will be outlined.

    The applications discussed will be arranged in Offset voltage at the input of an operational ampli·
    order of increasing complexity in five categories: fier is comprised of two components, these com·
    simple amplifiers, operational circuits, transducer ponents are identified in specifying the amplifier
    amplifiers, wave shapers and generators, and power as input offset voltage and input bias current.
    supplies. The integrated amplifiers shown in the The input offset voltage is fixed for a particular
    figures are for the most part internally com pen- amplifier, however the contribution due to input

    AN20-1
    bias current is dependent on the circu it configu- THE NON-INVERTING AMPLIFIER
    ration used_ For minimum offset voltage at the
    amplifier input without circuit adjustment the Figure 2 shows a high input impedance non-
    source resistance for both inputs should be equal. inverting circuit. This circuit gives a closed-loop
    In this case the muximum offset voltage would be gain equal to the ratio of the sum of R1 and R2 to
    the algebraic sum of amplifier offset voltage and R 1 and a closed-loop 3 dB bandwidth equal to the
    the voltage drop across the source resistance due amplifier unity-gain frequency divided by the
    to offset cLirrent. Amplifier offset voltage is the closed-loop gain.
    predominant error term for low source resistances
    and offset current causes the main error for high The primary differences between"" this connection
    source resistances. and the inverting circuit are that thfl output is not
    inverted and that the input impedance is very high
    and is equal to the differential input impedance
    In high source resistance applications, offset volt-
    multiplied by loop gain. (Open loop gain/Closed
    age at the amplifier output may be adjusted by
    loop gain.) In DC coupled applications, input
    adjusting the value of R3 and using the variation in
    impedance is not as important as input current and
    voltage drop across it as an input offset voltage
    its voltage drop across the source resistance.
    trim.
    Applications cautions are the same for this ampli-
    Offset voltage at the amplifier output is not as
    fier as for the inverting ampl ifier with one
    important in AC coupled applications. Here the
    exception. The amplifier output will go into satu-
    only consideration is that any offset voltage at the
    ration if the input is allowed to float. This may be
    output reduces the peak to peak linear output
    important if the amplifier must be switched from
    swi ng of the amplifier.
    source to source. The compensation trade off dis-
    cussed for the inverting amplifier is also valid for
    The gain-frequency characteristic of the amplifier this connection.
    and its feedback network must be such that oscil-
    lation does not occur. To meet this condition, the
    phase shift through amplifier and feedback v,"
    network must never exceed 1800 for any fre- VOUT

    quency where the gain of the amplifier and its


    feedback network is greater than unity. In
    practical applications, the phase shift should not
    R1
    approach 1800 since this is the situation of con-
    ditional stability. Obviously the most critical case R'
    VOUT '" R1 R+1A2 V1N
    occurs when the attenuation of the feedback net-
    work is zero. -= Rll:R2= RSOURCE
    FOR MINIMUM ERROR DUE
    TO INPUT BIAS CURRENT

    Amplifiers which are not internally compensated FIGURE 2. Non-Inverting Amplifier


    may be used to achieve increased performance in
    circuits where feedback network attenuation is
    high. As an example, the LM10l may be operated THE UNITY-GAIN BUFFER
    at unity gain in the inverting amplifier circuit with
    a 15 pF compensating capacitor, since" the feedback The unity-gain buffer is shown in Figure 3. The
    network has an attenuation of 6 dB, while it circuit gives the highest input impedance of any
    requires 30 pF in the non-inverting unity gain con- operational amplifier circuit. Input impedance is
    nection where the feedback network has zero equal to the differential input impedance multi-
    attenuation. Since amplifier slew rate is dependent plied by the open-loop gain, in parallel with com-
    on compensation, the LM101 slew rate in the mon mode input impedance. The gain error of this
    inverting unity gain connection will be twice that circuit is equal to the reciprocal of the amplifier
    for the non-inverting connection and the inverting open-loop gain or to the common mode rejection,
    gain of ten connection will yield eleven times the wh ichever is less.
    slew rate of the non-inverting unity gain connec-
    tion. The compensation trade·off for a particular
    connection is stability versus bandwidth, larger Your
    values of compensation capacitor yield greater
    stability and lower bandwidth and vice versa.

    The preceding discussion of offset voltage, bias VOUT =VIN


    current and stability is applicable to most ampli- RI = "SOURCE
    fier appl ications and will be referenced in later FOR MINIMUM ERROR DUE
    TO INPUT BIAS CURRENT
    sections. A more complete treatment is contained
    in Reference 4. FIGURE 3. Unity Gain Buffer

    AN20-2
    Input impedance is a misleading concept in a DC is shown in Figure 5 and is useful as a computa-
    coupled unity-gain buffer. Bias current for the tional amplifier, in making a differential to single-
    amplifier will be supplied by the source resistance ended conversion or in rejecting a common mode
    and will cause an error at the amplifier input due signal.
    to its voltage drop across the source resistance.
    Since this is the case, a low bias current amplifier
    such as the LH 1026 should be chosen as a unity-
    gain buffer when working from high source resis- V,-"v"l;
    .,
    tances. Bias current compensation techniques are VOUT
    discussed in Reference 5.
    .3
    AI + R2)R4 R2
    The cautions to be observed in applying this cir- R4 VOUT= ( RJ+R4 Ri V2-Ri V,
    cuit are three: the amplifier must be compensated FOR AI = A3 AND R2 = R4
    for unity gain operation, the output swing of the
    amplifier may be limited by the amplifier common RlIIR2= R311A4
    mode range, and some amplifiers exhibit a latch-up FOR MINIMUM OfFSET ERROR
    DUE TO INPUT BIAS CURRENT
    mode when the amplifier common mode range is
    exceeded. The LH 101 may be used in this circuit
    FIGURE 5. Difference Amplifier
    with none of these problems; or, for faster opera-
    tion, the LM 102 may be chosen.
    Circuit bandwidth may be calculated in the same
    manner as for the inverting amplifier, but input
    V,-"",..,....- . . .
    01
    M~-. impedance is somewhat more complicated. Input
    V,.-IV\,.,."
    .2
    04
    impedance for the two inputs is not necessarily
    equal; inverting input impedance is the same as for
    the inverting amplifier of Figure 1 and the
    Your non-inverting input impedance is the sum of R3
    and R4. Gain for either input is the ratio of R 1 to
    R2 for the special case of a differential input
    .5 VOUT:-R4(~+~+~) single-ended output where R 1 = R3 and R2 = R4.
    R5=Rl11R211R311R4 The general expression for gain is given in the
    FOR MINIMUM OFFSET ERROR figure. Compensation should be chosen on the
    DUE TO INPUT BIAS CURRENT
    basis of amplifier bandwidth.
    FIGURE 4. Summing Amplifier Care must be exercised in applying this circuit
    since input impedances are not equal for minimum
    SUMMING AMPLIFIER bias current error.

    The summing amplifier, a special case of the in- DIFFERENTIATOR


    verting amplifier, is shown in Figure 4. The circuit
    gives an inverted output which is equal to the The differentiator is shown in Figure 6 and, as the
    weighted algebraic sum of all three inputs. The name implies, is used to perform the mathematical
    gain of any input of this circuit is equal to the operation of differentiation. The form shown is
    ratio of the appropriate input resistor to the feed- not the practical form, it is a true differentiator
    back resistor, R4. Amplifier bandwidth may be and is extremely susceptible to high frequency
    calculated as in the inverting amplifier shown in noise since AC gain increases at the rate of 6dB per
    Figure 1 by assuming the input resistor to be the octave. In addition, the feedback network of the
    parallel combination of R1, R2, and R3. Applica- differentiator, R2C1, is an RC low pass filter
    tion cautions are the same as for the inverting which contributes 90° phase shift to the loop and
    amplifier. If an uncompensated amplifier is used, may cause stability problems even with an ampli-
    compensation is calculated on the basis of this fier which is compensated for unity gain.
    bandwidth as is. discussed in the section describing
    the simple inverting amplifier.
    _ ~I .,
    VO" - - , I-. .-JV'.~--.
    The advantage of this circuit is that there is no Cl
    interaction between inputs and operations such as
    summing and weighted averaging are implemented YOUT
    very easily.

    THE DIFFERENCE AMPLIFIER VouT =-R1CI £fV uOj)

    AI =R2
    The difference amplifier is the complement of the ~ FOR MINIMUM OFFSET ERROR
    DUE TO INPUT BIAS CURRENT
    summing amplifier and allows the subtraction of
    two voltages or, as a special case, the cancellation
    of a signal common to the two inputs. This circuit FIGURE 6. Differentiator

    AN20-3
    circuit is essentially a low-pass filter with a fre-
    quency response decreasing at 6 dB per octave. An
    R2 amplitude-frequency plot is shown in Figure 10.

    ---,,!'.. --.I
    V1N-VV",,---,
    c,

    fc=b~2Cl ''""
    z 2.1--+-~ ........--I----1
    ftl=Zll'~,Cl =21i'~2C2 ~
    fc «fh « fun •ty , •• "

    FIGURE 7. Practical Differentiator


    -20 L--'Of'--'::-!.':-:.f-~::----='
    A practical differentiator is shown in Figure 7.
    RELATIVE FREQUENCY
    Here both the stability and noise problems are cor-
    rected by addition of two additional components, FIGURE 10. Integrator Frequency Response
    R 1 and C2. R2 and C2 form a 6 dB per octave
    high frequency roll-off in the feedback network The circuit must be provided with an external
    and R1Cl form a 6 dB per octave roll-off network method of establishing initial conditions. This is
    in the input network for a total high fre.quency shown in the figure as S,. When S, is in
    roll-off of 12 dB per octave to reduce the effect of position 1, the ampl ifier is connected in unity-gain
    high frequency input and amplifier noise. In addi- and capacitor Cl is discharged, setting an initial
    tion R1Cl and R2C2 form lead networks in the condition of zero volts. When S, is in position 2,
    feedback loop which, if placed below the amplifier the amplifier is connected as an integrator and its
    unity gain frequency, provide 90° phase lead to output will change in accordance with a constant
    compensate the 90° phase lag of R2Cl and pre- times the time integral of the input voltage.
    vent loop instability. A gain frequency plot is
    shown in Figure 8 for clarity. The cautions to be observed with this circuit are
    two: the amplifier used should generally be
    ,
    60 ,---r,-:O=PE:-::N":":LO;-;O:;;-PG;:';.::-:'N:-:C:::CUR:::-V;;:'lE
    stabilized for unity-gain operation and R2 must
    equal Rl for minimum error due to bias current.
    401--+--'\0;:---+-----;

    ''"z" 2.1--+-~f_----''Io:_
    SIMPLE LOW-PASS FI LTER
    ~
    The simple low-pass filter is shown in Figure 11.
    This circuit has a 6 dB per octave roll-off after a
    closed-loop 3 dB point defined by f e. Gain below
    this corner frequency is defined by the ratio of R3
    RELATIVE FREQUENCY to R 1. The circuit may be considered as an AC
    integrator at frequencies well above fe; however,
    FIGURE S. Differentiator Frequency Response
    the time domain response is that of a single RC
    rather than an integral.
    INTEGRATOR

    The integrator is shown in Figure 9 and performs


    the mathematical operation of integration. This

    r-------, Sib
    R3

    I I
    VOUT
    I
    I
    I R2
    I fL=211"~'Ct
    v,. I
    fC=2'Ir~3C1
    VOUT AL=~

    R2 VOUT = -Rtel , f" VIN dt FIGURE 11. Simple Low Pass Filter
    "
    Ie '" Zll'~'Cl R2 should be chosen equal to the parallel com-
    Rt" AZ bination of R1 and R3 to minimize errors due to
    FOR MINIMUM OFFSET ERROR
    DUE TO INPUT BIAS CURRENT bias current. The amplifier should be compensated
    for unity-gain or an internally compensated ampli-
    FIGURE 9. Integrator fier can be used.

    AN20-4
    6D

    ~"lDO
    .,
    f,
    4D

    -
    "~
    20

    -20
    I'" ~f'
    ~
    V OUT

    101 1001 10001 100001 FIGURE 14. Amplifier for Photoconductive Cell
    RELATIVE FREOUENCY

    FIGURE 12. Low Pass Filter Response

    PHOTOCELL AMPLI FI ERS


    A gain frequency plot of circuit response is shown
    in Figure 12 to illustrate the difference between Amplifiers for photoconductive, photodiode and
    this circuit and the true integrator. photovoltaic cells are shown in Figures 14, 15, and
    16 respectively.
    THE CURRENT-TO-VOL TAGE CONVERTER
    All photogenerators display "ome voltage depend·
    Current may be measured in two ways with an ence of both speed and linearity. I t is obvious that
    operational amplifier. The current may be con- the current through a photoconductive cell will
    verted into a voltage with a resistor and then not display strict proportionality to incident light
    amplified or the current may be injected directly if the cell terminal voltage is allowed to vary with
    into a summing node. Converting into voltage is cell conductance. Somewhat less obvious is the
    undesirable for two reasons: first, an impedance is fact that photodiode leakage and photo'Joltaic cell
    inserted into the measuring line causing an error; internal losses are also functions of terminal volt-
    second, amplifier offset voltage is also amplified age. The current-to·voltage converter neatly side-
    with a subsequent loss of accuracy. The use of a steps gross linearity problems by fixing a constant
    current-to-voltage transducer avoids both of these terminal voltage, zero in the case of photovoltaic
    problems. cells and a fixed bias voltage in the case of photo·
    conductors or photodiodes.
    The current-to-voltage transducer is shown in Fig-
    ure 13. The input current is fed directly into the
    summing node and the amplifier output voltage
    changes to extract the same current from the sum-
    ming node through R1. The scale factor of this

    Vour
    Rl

    FIGURE 15. Photodiode Amplifier

    Photodetector speed is optimized by operating


    FIGURE 13. Current to Voltage Converter into a fixed low load impedance. Currently avail-
    able photovoltaic detectors show response times in
    circuit is R 1 volts per amp. The only conversion the microsecond range at zero load impedance and
    error in this circuit is Ibias which is summed photoconductors, even though slow, are materially
    algebraically with liN. faster at low load resistances.

    Rl
    This basic circuit is useful for many applications
    other than current measurement. It is shown as a
    photocell amplifier in the following section.
    Your
    The only design constraints are that scale factors
    must be chosen to minimize errors due to bias
    current and since voltage gain and source imped-
    ance are often indeterminate (as with photocells) Vour" ICELL AI
    the amplifier must be compensated for unity·gain
    operation. Valuable techniques for bias current
    compensation are contained in Reference 5. FIGURE 16. PhotoYoltaic Cell Amplifier

    AN20-5
    .--
    '"

    The feedback resistance, R1, is dependent on cell where the output current is high and the base cur-
    sensitivity and should be chosen for either maxi- rent of the Darlington input would not cause a
    mu m dynamic range or for a desired scale factor. significant error.
    R2 is elective: in the case of photovoltaic cells or
    of photodiodes, it is not required in the case of The amplifiers used must be compensated for
    photoconductive cells, it should be chosen to unity-gain and additional compensation may be
    minimize bias current error over the operating required depending on load reactance and external
    range. transistor parameters.

    01
    PRECISION CURRENT SOURCE 1N4611
    &.6V
    The precision current source is shown in Fig·
    ures 17 and 18. The configurations shown will sink
    or source conventional current respectively.

    v+ >~"'-VOUT

    t R2

    L..._ _ _ _ +<R3
    v,.
    R4

    FIGURE 19•• Positive Voltage Reference

    ADJUSTABLE VOLTAGE REFERENCES


    IO=~ RI

    VIN~OV
    Adjustable voltage reference circuits are shown in
    Figures 19 and 20. The two circuits shown have
    different areas of applicability. The basic
    FIGURE 17. Precision Current Sink difference between the two is that Figure 19 illus-
    trates a voltage source which provides a voltage
    Caution must be exercised in applying these greater than the reference diode while Figure 20
    circuits. The voltage compliance of the source ex· illustrates a voltage source which provides a volt-
    tends from BV CER of the external transistor to age lower than the reference diode. The figu res
    approximately 1 volt more negative than Y,N' The show both positive and negative voltage sources.
    compliance of the current sink is the same in the
    positive direction. 01
    1N4611
    6.6V
    The impedance of these current generators is
    essentially infinite for small currents and they are
    accurate so long as Y'N is much greater than Ves
    and 10 is much greater than Ibias •
    VOUT
    The source and sink illustrated in Figures 17 and
    18 use an FET to drive a bipolar output transistor. R2
    It is possible to use a Darlington connection in V'
    place of the FET·bipolar combination in cases
    ....----+<R3
    RI
    R4

    v,. FIGURE 19b. Negative Voltage Reference

    IO=fi1
    v,. RZ
    10K
    High precision extended temperature applications
    of the circuit of Figure 19 require that the range
    V1N::!OV
    of adjustment of VOUT be restricted. When this is
    done, R1 may be chosen to provide optimum
    zener current for minimum zener T.C. Since Iz is
    not a function of V+, reference T.C. will be in-
    FIGURE 18. Precision Current Source dependent of V+.

    AN20-6
    7

    r-----~~-v· R1
    lOOK

    V<N~

    ri~S1
    Rl
    01 Your
    470K
    lN4611
    6.6V

    RJ
    R'
    "

    J
    RJ
    ·SEE TEXT
    C2 410K
    ,., PF
    = =
    FIGURE 20a. Positive Voltage Reference
    FIGURE 21. Reset Stabilized Amplifier

    The connection is useful in eliminating errors due


    to offset voltage and bias current. The output of
    = this circuit is a pulse whose amplitude is equal to
    01 VOUT V IN • Operation may be understood by considering
    lN4611 the two conditions corresponding to the position
    B.GV
    of 5,. When 5, is in position 2, the amplifier is
    connected in the unity gain connection and the
    voltage at the output will be equal to the sum of
    the input offset voltage and the drop across R2
    due to input bias current. The voltage at the in-
    verting input will be equal to input offset voltage.
    Capacitor C1 will charge to the sum of input offset
    voltage and V IN through R1. When C1 is charged,
    no current flows through the source resistance and
    FIGURE 20b. Negative Voltage Reference R 1 so there is no error due to input resistance. 5,
    is then changed to position 1. The voltage stored
    on C1 is inserted between the output and inverting
    The circuit of Figure 20 is suited for high precision input of the amplifier and the output of the ampli·
    extended temperature service if V+ is reasonably fier changes by V IN to maintain the amplifier input
    constant since Iz is dependent on V+ R 1, R2, R3, at the input offset voltage. The output then
    and R4 are chosen to provide 'the proper Iz for changes from (Vos + Ibias R2) to V IN + Ibias R2) as
    minimum T.C. and to minimize errors due to Ibias' 5, is changed from position 2 to position 1.
    Amplifier bias current is supplied through R2 from
    The circuits shown should both be compensated the output of the amplifier or from C2 when 5, is
    for unity·gain operation or, if large capacitive in position 2 and position 1 respectively. R3 serves
    loads are expected, should be overcompensated. to reduce the offset at the ampl ifier output if the
    Output noise may be reduced in both circuits by amplifier must have maximum linear range or if it
    bypassing the amplifier input. is desired to DC couple the amplifier.

    The circuits shown employ a single power supply, An additional advantage of this connection is that
    this requires that common mode range be con· input resistance approaches infinity as the
    sidered in choosing an amplifier for these applica· capacitor Cl approaches full charge, eliminating
    tions. If the common mode range requ irements are errors due to loading of the source resistance. The
    in excess of the capability of the amplifier, two time spent in position 2 should be long with
    power supplies may be used. The LH 101 may be respect to the changing time of C1 for maximum
    used with a single power supply since the common accuracy.
    mode range is from V+ to within approximately
    2 volts of V-. The amplifier used must be compensated for unity
    gain operation and it may be necessary to over-
    THE RESET STABI LlZED AMPLI FIER compensate because of the phase shift across R2
    due to Cl and the amplifier input capacity. 5ince
    The reset stabilized amplifier is a form of this connection is usually used at very low switch·
    chopper·stabilized amplifier and is shown in Fig· ing speeds, slew rate is not normally a practical
    u re 21. As shown, the amplifier is operated consideration and overcompensation does not
    closed·loop with a gain of one. reduce accuracy.

    AN20-7
    V'

    "'
    Your

    - RS = R1(¥ij)
    v,>o
    VOUT=~
    V, V2

    V, V- V,

    FIGURE 22. Analog Multiplier

    THE ANALOG MUL TIPLI ER is to mount the cells in holes in an aluminum


    block and to mount the lamp midway between
    A simple embodiment of the analog multiplier is them. This mounting method provides controlled
    shown in Figure 22. This circuit circumvents many spacing and also provides a thermal bridge between
    of the problems associated with the log·antilog cir- the two cells to reduce differences in cell tempera·
    cuit and provides three quadrant analog multiplica· ture. This technique may be extended to the use
    tion which is relatively temperature insensitive and of FET's or other devices to meet special resis·
    which is not subject to the bias current errors tance or environment requ irements.
    which plague most multipliers.
    The circuit as shown gives an inverting output
    Circuit operation may be understood by consider- whose magnitude is equal to one·tenth the product
    ing A2 as a controlled gain amplifier, amplifying of the two analog inputs. Input VIis restricted to
    V2 , whose gain is dependent on the ratio of the positive values, but V2 may assume both positive
    resistance of PC2 to R5 and by consideri ng A 1 as a and negative values. This circuit is restricted to low
    control amplifier which establishes the resistance frequency operation by the lamp time constant.
    of PC2 as a function of VI. In this way it is seen
    that VOUT is a function of both VIand V2. R2 and R4 are chosen to minimize errors due to
    input offset current as outlined in the section
    A 1, the control amplifier, provides drive for the describing the photocell amplifier. R3 is included
    lamp, L1, When an input voltage, VI, is present, to reduce i'n·rush current when first turning on the
    L1 is driven by A 1 until the current to the sum· lamp, Ll.
    ming junction from the negative supply through
    PCl is equal to the current to the summing junco THE FULL-WAVE RECTIFIER
    tion from VI through R 1. Since the negative AND AVERAGING FILTER
    supply voltage is fixed, this forces the resistance of
    PCl to a value proportional to Rl and to the ratio The circuit shown in Figure 23 is the heart of an
    of VIto V-. L1 also illuminated PC2 and, if the average reading, rms calibrated AC voltmeter. As
    photoconductors are matched, causes PC2 to have shown, it is a rectifier and averaging filter. Dele·
    a resistance equal to PC1. tion of C2 removes the averaging function and pro·
    vides a precision full·wave rectifier, and deletion of
    A2, the controlled gain amplifier, acts as an invert- Cl provides an absolute value generator.
    ing amplifier whose gain is equal to the ratio of the
    resistance of PC2 to R5. If R5 is chosen equal to Circuit operation may be understood by following
    the product of Rl and V-, then VOUT becomes the signal path for negative and then for positive
    simply the product of VIand V2 . R5 may be inputs. For negative signals, the output of ampli·
    scaled in powers of ten to provide any required fier A 1 is clamped to +0.7V by D 1 and discon·
    output scale factor. nected from the summing point of A2 by D2. A2
    then functions as a simple unity·gain inverter with
    PCl and PC2 should be matched for best tracking input resistor, Rl, and feedback resistor, R2,
    over temperature since the T.C. of resistance is giving a positive going output.
    related to resistance match for cells of the same
    geometry. Small mismatches may be compensated For positive inputs, A 1 operates as a normal ampli·
    by varying the value of R5 as a scale factor adjust· fier connected to the A2 summing point through
    ment. The photoconductive cells shou Id receive resistor, R5. Amplifier A 1 then acts as a simple
    equal illumination from L1, a convenient method unity·gain inverter with input resistor, R3, and

    AN20-8
    7'

    .,
    20K
    .2
    20K 2.SK
    1% 1%
    . . . - - - - - - - - - " " , . . . , . . - - - - -. .JVVV-..IIJIQI.,.....- OU~;UT
    Rl R4 CAL
    Cl 20K 20K
    1% 1%
    1~~T~~~·-e~VV~.-----~~~-,
    01 02
    4.7 pF 4.7/-1F FD6666 FD6666

    .&
    10K

    FIGURE 23. Full·Wave Rectifier and Averaging Filter

    feedback resistor, R5. A 1 gain accuracy is not The Wi en Bridge oscillator is widely used and takes
    affected by 02 since it is inside the feedback loop. advantage of the fact that the phase of the voltage
    Positive current enters the A2 summing point across the parallel branch of a series and a parallel
    through resistor, R 1, and negative current is drawn RC network connected in series, is the same as the
    from the A2 summing point through resistor, R5. phase of the applied voltage across the two net-
    Since the voltages across R1 and R5 are equal and works at one particular frequency and that the
    opposite, and R5 is one-half the value of R1, the phase lags with increasing frequency and leads
    net input current at the A2 summing point is equal with decreasing frequency. When this network-
    to and opposite from the current through R1 and the Wien Bridge-is used as a positive feedback ele-
    amplifier A2 operates as a summing inverter with ment around an amplifier, oscillation occurs at the
    unity gain, again giving a positive output. frequency at which the phase shift is zero. Addi-
    tional negative feedback is provided to set loop
    The circuit becomes an averaging filter when C2 is gain to unity at the oscillation frequency. To
    connected across R2. Operation of A2 then is stabilize the frequency of oscillation, and to
    similar to the Simple Low Pass Filter previously reduce harmonic distortion.
    described. The time constant R2C2 should be
    chosen to be much larger than the maximum Cl C2
    period of the input voltage which is to be aver· 2.2,1lf O.068,1lF
    aged.

    Capacitor C1 may be deleted if the circuit is to be


    used as an absolute value generator. When this is V OUT =16.5V pp
    done, the circuit output will be the positive 10Hz

    absolute value of the input voltage.

    The amplifiers chosen must be compensated for


    01
    unity·gain operation and R6 and R7 must be lN457
    chosen to minimize output errors due to input off- 02
    set current. 1N155
    7,5V

    SINE WAVE OSCILLATOR

    An amplitude·stabilized sine·wave oscillator is


    shown in Figure 24. This circuit provides high
    purity sine-wave output down to low frequencies
    with minimum circuit complexity. An important
    advantage of this circuit is that the traditional FIGURE 24. Wien Bridge Sine Wave Oscillator
    tungsten filament lamp amplitude regulator is
    eliminated along with its time constant and The circu it presented here differs from the classic
    linearity problems. usage only in the form of the negative feedback
    sta b i Iization scheme. Circuit operation is as
    In addition, the reliability problems associated follows: negative peaks in excess of -8.25V cause
    with a lamp are eliminated. 01 and 02 to conduct, charging C4. The charge

    AN 20-9
    stored in C4 provides bias to Ql, which determines The integrator then generates a negative-going
    amplifier gain. C3 is a low frequency roll-off ramp with a rate of 1+ICl volts per second until its
    capacitor in the feedback network and prevents output equals the negative trip point of the thres-
    offset voltage and offset current errors from being hold detector. The threshold detector then
    multiplied by amplifier gain. changes to the negative output state and supplies a
    negative current, 1-, at the integrator summing
    Distortion is determined by amplifier open-loop point. The integrator now generates a positive-
    gain and by the response time of the negative feed- going ramp with a rate of 1-ICl volts per second
    back loop filter, R5 and C4. A trade-off is neces- until its output equals the positive trip point of
    sary in determining amplitude stabilization time the threshold detector where the detector again
    constant and oscillator distortion. R4 is chosen to changes output state and the cycle repeats.
    adjust the negative feedback loop so that the F ET
    is operated at a small negative gate bias. The cir- Triangular-wave frequency is determined by R3,
    cuit shown provides optimum values for a general- R4 and Cl and the positive and negative saturation
    purpose oscillator. voltages of the amplifier A 1. Amplitude is deter-
    mined by the ratio of R5 to the combination of
    TRIANGLE-WAVE GENERATOR R1 and R2 and the threshold detector saturation
    voltages. Positive and negative ramp rates are equal
    A constant amplitude triangular-wave generator is and positive and negative peaks are equal if the
    shown in Figure 25. This circuit provides a variable detector has equal positive and negative saturation
    frequency triangular wave whose amplitude is in- voltages. The output waveform may be offset with
    dependent of frequency. respect to ground if the inverting input of the
    threshold detector, A I, is offset with respect to
    INTEGRATOR
    ground.
    C1
    D.lpF The generator may be made independent of
    temperature and supply voltage if the detector is
    clamped with matched zener diodes as shown in
    Figure 26.
    VOUT
    The integrator should be compensated for unity-
    gain and the detector may be compensated if
    power supply impedance causes oscillation during
    its transition time. The current into the integrator
    .s should be large with respect to Ibias for maximum
    u.
    symmetry, and offset voltage should be small with
    FIGURE 25. Triangular-Wave Generator respect to VOUT peak.

    The generator embodies an integrator as a ramp


    generator and a threshold detector with hysterisis
    as a reset circuit. The integrator has been described
    in a previous section and requires no further
    explanation. The threshold detector is similar to a
    SchmittTrigger in that it is a latch circuit with a >-I\I\(vo-....- TO INTEGRATOR I.PUT
    R&
    large dead zone. This function is implemented by 10K
    using positive feedback around an operational
    AMP
    amplifier. When the amplifier output is in either
    the positive or negative saturated state, the posi- R1 R2
    10K 1M
    tive feedback network provides a voltage at the ....-----JtlV'v----( ~~~~UI:TEGRATOR
    non-inverting input which is determined by the R5
    attenuation of the feed-back loop and the satura- B.2K

    tion voltage of the amplifier. To cause the ampli-


    fier to change states, the voltage at the input of FIGURE 26. Threshold Detector with Regulated Output
    the amplifier must be caused to change polarity by
    an amount in excess of the amplifier input offset
    voltage. When this is done the amplifier saturates TRACKING REGULATED POWER SUPPLY
    in the opposite direction and remains in that state
    until the voltage at its input again reverses. The A tracking regulated power supply is shown in Fig-
    complete circuit operation may be understood by ure 27. This supply is very suitable for powering
    examining the operation with the output of the an operational amplifier system since positive and
    threshold detector in the positive state. The negative voltages track, eliminating common mode
    detector positive saturation voltage is applied to signals originating in the supply voltage. In addi-
    the integrator summing junction through the com- tion, only one voltage reference and a minimum
    bination R3 and R4 causing a current 1+ to flow. number of passive components are required.

    AN20-10
    +4DV UNREGULATED
    PROGRAMMABLE BENCH POWER SUPPL V

    The complete power supply shown in Figure 28 is


    a programmable positive and negative power
    supply. The regulator section of the supply com·
    prises two voltage followers whose input is pro-
    vided by the voltage drop across a reference
    A3 resistor of a precision current source.
    18K

    T1
    TRIAD90X
    .,
    IN4001

    A,
    UK
    '-......t--1~-t--~ -'IV
    >--"'--"'--~""---4II .....-t-••.s.c.
    300pF
    A1
    39K a.

    >.,......-----...... ~-VDUT (REG)


    <4IV

    OUTPUT VOLTAGE IS VARIABLE


    FROM ±5V TO ±3SV.
    NEGATIVE OUTPUT TRACKS
    POSITIVE OUTPUT TO WITHIN
    THE RATIO OF RI TO R7.

    FIGURE 27. Tracking Power Supply


    03
    lN7S9
    ,2V
    04
    lMIDl
    2.1V
    Jm" FDA
    Ic:z=1.00mA

    Power supply operation may be understood by


    considering first the positive regulator. The posi- A6
    tive regulator compares the voltage at the wiper of A'
    12K
    R4 to the voltage reference, D2. The difference
    between these two voltages is the input voltage for
    the amplifier and since R3, R4, and R5 form a A2
    =
    C3
    'OK 30DpF
    negative feedback loop, the amplifier output volt·
    age changes in such a way as to minimize this
    difference. The voltage reference current is =
    supplied from the amplifier output to increase
    b. V+
    power supply line regulation. This allows the regu-
    lator to operate from supplies with large ripple
    voltages_ Regulating the reference current in this -4'V
    way requires a separate source of current for
    supply start-up. Resistor R1 and diode D1 provide
    this start-up current. D1 decouples the reference
    string from the amplifier output during start-up
    and R 1 supplies the start-up current from the un-
    regulated positive supply. After start-up, the low
    05
    1N7S9
    '2V
    A"
    1.2K
    ,%

    03
    J," FDA
    IC4:1.0DmA

    amplifier output impedance reduces reference cur- 2N2484


    rent variations due to the current through R 1.

    The negative regulator is simply a unity-gain in-


    verter with input resistor, R6, and feedback
    resistor, R7.

    The amplifiers must be compensated for unity-gain


    operation.

    The power supply may be modulated by injecting


    current into the wiper of R4. In this case, the c. V-
    output voltage variations will be equal and
    opposite at the positive and negative outputs. The
    power supply voltage may be controlled by replac-
    ing D1, D2, R 1 and R2 with a variable voltage FIGURE 28. Low-Power Supply for Integrated
    reference. Circuit Testing

    AN20-11
    Programming sensitivity of the positive and nega· externally compensated amplifier should be used
    tive supply is 1V /1 ooon of resistors R6 and R 12 and the amplifier should be overcompensated for
    respectively. The output voltage of the positive additional stability. Power supply noise may be
    regulator may be varied from approximately +2V reduced by bypassing the amplifier inputs to
    to +38V with respect to ground and the negative ground with capacitors in the 0.1 to 1.0 JlF range.
    regulator output voltage may be varied from -38V
    to OV with respect to ground. Since LH10l ampli'
    fiers are used, the supplies are inherently short cir· CONCLUSIONS
    cuit proof. This current limiting feature also serves
    to protect a test circuit if this supply is used in The foregoing circuits are illustrative of the versa·
    integrated circuit testing. tility of the integrated operational amplifier and
    provide a guide to a number of useful applications.
    Internally compensated amplifiers may be used in The cautions noted in each section will show the
    this application if the expected capacitive loading more common pitfalls encountered in amplifier
    is small. If large capacitive loads are expected, an usage.

    APPENDIX I
    DEFINITION OF TERMS

    Input Offset Voltage: That voltage which must be Power Supply Rejection: The ratio of the change
    applied between the input terminals through two in input offset voltage to the change in power
    equal resistances to obtain zero output voltage. supply voltage producing it.

    Input Offset Current: The difference in the cur· Slew Rate: The internally·limited rate of change
    rents into the two input terminals when the out· in output voltage with a large·amplitude step func·
    put is at zero. tion applied to the input.

    Input Bias Current: The average of the two input


    currents.

    Input Voltage Range: The range of voltages on


    the input terminals for which the amplifier REFERENCES
    operates within specifications.
    1. D.C. Amplifier Stabilized for Zero and Gain;
    Common Mode Rejection Ratio: The ratio of the Williams, Tapley, and Clark; AlEE Trans·
    input voltage range to the peak·to·peak change in actions, Vol. 67, 1948.
    input offset voltage over this range.
    2. Active Network Synthesis; K. L Su, McGraw·
    Input Resistance: The ratio of the change in input Hill Book Co., Inc., New York, New York.
    voltage to the change in input current on either
    input with the other gounded. 3. Analog Computation; A. S. Jackson, McGraw·
    Hill Book Co., Inc., New York, New York.
    Supply Current: The current required from the
    power supply to operate the amplifier with no 4. A Palimpsest on the Electronic Analog Art;
    load and the output at zero. H. M. Paynter, Editor. Published by George A.
    Philbrick Researches, Inc., Boston, Mass.
    Output Voltage Swing: The peak output voltage
    swing, referred to zero, that can be obtained 5. Drift Compensation Techniques for Integrated
    without clipping. D.C. Amplifiers; R. J. Widlar, EDN, June 10,
    1968.
    Large·Signal Voltage Gain: The ratio of the out·
    put voltage swing to the change in input voltage 6. A Fast Integrated Voltage Follower With Low
    required to drive the output from zero to this volt· Input Current; R. J. Widlar, Microelectronics,
    age. Vol. 1 No.7, June 1968.

    AN20-12
    »
    :2
    December 1968
    ...
    N

    o
    m
    fJ)
    G')
    2
    DESIGNS FOR NEGATIVE fJ)

    VOLTAGE REGULATORS .."


    o
    :JJ
    :2
    m
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    »
    -I
    <:m
    o<
    r-
    ~
    G')
    m
    INTRODUCTION
    :JJ
    m
    G')
    C
    r-
    r------------
    9
    A number of IC voltage regulators have been
    introduced to date, but these have been designed I
    -- .. -
    I
    GROUND
    »
    -I
    I RI
    primarily to regulate positive voltages. Most can be I
    I
    '" .I
    -'-
    'i'
    CI
    41~F
    o
    adapted as negative regulators, at some sacrifice in I :JJ
    I fJ)
    complexity, performance and flexibility. This I R2
    I
    note, however, describes an IC, which is designed
    R'O'~ '" --t- 8 I
    OUTPUT
    specifically as a negative regulator. It is intended
    I I
    to complement the LM100 and LM105 positive I
    Rl
    I
    regulators, providing a line of IC's for practically I " 1_(03
    I
    every regulator application. I I
    I I
    Unique features of the circuit are that it supplies 6_ _ J
    any output voltage from OV down to -40V, while
    operating from a single unregulated supply. The 5
    output voltage is proportional to a single pro· ----INPUT

    gramming resistor, and remote sensing can be done A functional diagram of the LM 104 regulator and
    at the load. It also regulates within 0.01 % in cir· external circuitry (dash line) is shown in the figure.
    cuits using a separate, floating bias supply, where The internal reference is a temperature compen-
    the maximum output voltage is limited only by sated current source, l ref • A voltage which is
    the breakdown of external pass transistors. The proportional to an external programming resistor,
    device is designed for either linear or switching Radj , is fed into an error amplifier, A1. This drives
    regulator applications. an internal series pass transistor, 01, to supply an
    output voltage equal to twice the voltage across
    In the circuits described, emphasis is placed on the programming resistor. External pass transistors
    practical considerations for the design of reliable can be added, as is 03, to increase the output-
    regulators. Many of the pitfalls which cause un· current capability. Short-circuit protection makes
    expected failures are explained, and protection the circuit exhibit a constant-current characteristic
    schemes for many of the hazards facing regulators when 02 is turned on by the voltage drop across
    are given. Most of the design hints are sufficiently an external current-limit resistor, Rlim • A more
    general to apply equally to other IC's or even regu· complete description of the integrated circuit itself
    lators designed entirely with discrete components. is given in the back of the text.

    AN21-1
    LOW POWER REGULATOR
    OR BIAS SUPPLY

    This circuit can provide output voltages between An output capacitor of at least l/LF is required to
    OV and -40V at currents up to 25 mAo The output keep the regulator from oscillating. This should be
    voltage is linearly dependent on the value of R2, a low inductance capacitor, preferably solid
    giving approximately 2V for each 1 K.I1 of resis- tantalum, installed with short leads. It is not
    tance. The exact scale factor can be set up by usually necessary to bypass the input, but at least
    trimming Rl. This should be done at the maxi- a 0.01 /LF bypass is advisable when there are long
    mum output voltage setting in ord.er to com- leads connecting the circuit to the unregulated
    pensate for any mismatch in the internal divider power source.
    resistors of the integrated circuit_

    Short-circuit protection is provided by R3. The .............--....-- ...


    value of this resistor should;be chosen so that the 'If
    I,.
    voltage drop across it is 300 mV at the maximum
    load current. This insures worst-case operation up
    to full load over a _55°C to 125°C temperature
    range. With a lower maximum operating tempera-
    ture, the design value for this voltage can be in-
    creased linearly to 525 mV at 25°C.
    .
    RI'
    UK

    tSol,lITlnblulII
    For an output voltage setting of 15V, the regula-
    tion, no load to full load, is better than 0.05%; and
    .......---...--4--- V'lli
    'rnIllR1for ..at
    .... flCtar

    the line regulation is better than 0.2% for a ±20%


    input voltage variation. Noise and ripple can be
    greatly reduced by bypassing R2 with a 10/LF It is important to watch power dissipation in the
    capacitor_ This will keep the ripple on the output integrated circuit even with load currents of
    less than 0.5 mV for a lV, 120 Hz ripple on the 25 mA or less. The dissipation can be in excess of
    unregulated input_ The capacitor also improves the lW with large input-output voltage differentials,
    line-transient response by a factor of five_ and this is above ratings for the device.

    AN21-2
    INCREASED OUTPUT CURRENT

    When output currents above 25 mA are required transistor will be 300 mA; and the dissipation in it
    or when the dissipation in the series pass transistor will be 7.5W. This clearly establishes the need for
    can be higher than about 0.2W, under worst·case an efficient heat sink.
    conditions, it is advisable to add an external tran-
    sistor to the LM 104 to handle the power. The con- For lower-power operation, a 2N2905 with a clip
    nection of an external booster transistor is shown on heat sink can be used for the external pass
    here. The output current capability of the regu- transistor. However, when the worst case dissipa-
    lator is increased by the current gain of the added tion is above 0.5W, it is advisable to employ a
    PNP transistor, but it is still necessary to watch power device such as the 2N3740 with a good heat
    dissipation in the external pass transistor. Exces- sink.
    sive dissipation can burn out both the series pass
    transistor and the integrated circuit. The current limit resistor is chosen so that the
    ---.....-
    ,......-..... ... voltage drop across it is 300 mV, with maximum
    load current, for operation to 125°C. With lower
    maximum ambients this voltage drop could be
    increased by 2.2 mVfC. If possible, a fast·acting
    YQUT--1SV fuse rated about 25% higher than the maximum
    , · ' -........-IDUT'SZOD.A
    load current should be included in series with the
    unregulated input.

    When a booster transistor is used, the minimum


    input·output voltage differential of the regulator
    L..._ _ _~~-....- - _ V.,,~-l'V
    will be increased by the emitter-base voltage of the
    For example, with the circuit shown, the worst- added transistor. This establishes the minimum
    case input voltage can be 25V. With a shorted out- differential at 2 to 3V, depending on the base
    put at 125°C, the current through the pass drive required by the external transistor.

    AN21-3
    HIGH CURRENT REGULATOR

    When output currents in the ampere range are resistance between the regulator and the load. This
    needed, it is necessary to add a second booster can be accomplished by returning R2 and Pin 9 of
    transistor to the LM104 circuitry. This connection the LM 104 to the ground end of the load and
    is shown in the accompanying figure. The output connecting P.in 8 directly to the high end of the
    current capability of the LM 104 is increased by load.
    the product of the current gains of 01 and 02.
    However, it is still necessary to watch the dissipa- The low resistance values required for the current
    tion in both the series pass transistor, 02, and its limit resistor, R3, are sometimes not readily avail-
    driver, 01. A clip-on heat sink is definitely able. A suitable resistor can be made using a piece
    required for aI, and it is advisable to replace the of resistance wire or even a short length of kovar
    2N2905 with a 2N3740 which has a good heat lead wire from a standard TO-5 transistor.
    sink when output currents greater than 1A are
    needed. A 1000 pF capacitor should also be added The current limit sense voltage can be reduced to
    between Pins 4 and 5 to compensate for the about 400 mV by inserting a germanium diode (or
    poorer frequency response of the 2N3740. The a diode-connected germanium transistor) in series
    need for an efficient heat sink on 02 should be with Pin 6 of the LM104. This diode will also com-
    obvious. pensate the sense voltage and make the short cir-
    cuit current essentially independent of
    Experience shows that a single-diffused transistor temperature.
    such as a 2N3055 (or a 2N3772 for higher cur·
    rents) is preferred over a double diffused, high-
    frequency transistor for the series pass element. .---....-_,....____....._GN.
    The slower, single-diffused devices are less prone
    to secondary breakdown and oscillations in linear
    regulator applications.

    As with the lower-current regulators, Cl is


    required to frequency compensate the regulator .,'OK
    and prevent oscillations. It is also advisable to 1%

    bypass the input with C2 if the regulator is located


    any distance from the output filter of the unregu-
    lated supply. The resistor across the emitter base
    junction of 02 fixes the minimum collector cur-
    rent of 01 to minimize oscillation problems with
    light loads. It is still possible to experience oscilla- .,
    tions with certain physical layouts, but these can "
    ' - _. ._ _ _ _ _ V,,,~.12V

    almost always be eliminated by stringing a ferrite


    bead, such as a Ferroxcube K5-001-00/3B, on the
    emitter lead of 02.
    With high current regulators it is especially impor-
    The use of two booster transistors does not tant to use a low-inductance capacitor on the out·
    appreciably increase the minimum input·output put. The lead length on this capacitor must also be
    voltage differential over that for a single transistor. made short. Otherwise, the capacitor leads can
    The minimum differential will be 2 to 3V, depend· resonate with smaller bypass capacitors (like
    ing on the drive current required from the inte· 0.1 J.lF ceramic) which may be connected to the
    grated circuit. output. These resonances can lead to oscillations.
    With short leads on the output capacitor, the a of
    With high current regulators, remote sensing is the tuned circuit can be made low enough so that
    sometimes required to eliminate the effect of line it cannot cause trouble.

    AN21-4
    7

    FOLDBACK CURRENT LIMITING

    High current regulators dissipate a considerable tion of the full load current, minimizing dissipa-
    amount of power in the series pass transistor under tion in the pass transistor.
    full-load conditions. When the output is shorted,
    this dissipation can easily increase by a factor of The circuit shown here accomplishes just this.
    four. Hence, with normal current limiting, the heat Normally 03 is held in a non-conducting state by
    sink must be designed to handle much more power the voltage developed across R4. However, when
    than the worst case full load dissipation if the cir- the voltage across the current limit resistor, R7,
    cuit is to survive short-circuit conditions. This can increases to where it equals the voltage across R4
    increase the bulk of the regulator substantially. (about 1V), 03 turns on and begins to rob base
    drive from the driver transistor, 01. This causes an
    increase in the output current of the LM104, and
    it will go into current limiting at a current deter-
    mined by R5. Since the base drive to 01 is
    clamped, the output voltage will drop with heavier
    loads. This reduces the voltage drop across R4 and,
    Rl tlt
    12K 22~f therefore, the available output current. With the
    output completely shorted, the current will be
    }-_+_....__... _~':~;~2V
    about one-fifth the full-load current.
    R1
    DZ
    RI
    In design, R7 is chosen so that the voltage drop
    '"
    1%
    across it wi II be 1 to 2V under full load conditions.
    The resistance of R3 should be one-thousand times
    the output voltage. R4 is then determined from

    where IFL is the load current at which limiting will


    This situation can be eased considerably by using occur.
    foldback current limiting. With this method of cur-
    rent limiting, the available output current actually If it is desired to reduce the ratio of full load to
    decreases as the maximum load on the regulator is short circuit current, this can be done by connect-
    exceeded and the output voltage falls off. The ing a resistance of 2 to 10 Kn across the emitter-
    short-circuit current can be adjusted to be a frac- base of 03.

    AN21-5
    SYMMETRICAL POWER SUPPLIES

    In many applications, such as powering opera- ~ ......""'iiiI.-....______....__... VOUT·+1iV


    tional amplifiers, there is a need for symmetrical IOUTSHlIIIA

    t ~.t,
    positive and negative supply voltages. A circuit
    "'
    13.21e

    -~:-.'..... "
    which is a particularly-economical solution to this
    design problem is shown in the adjoining figure. It (i"l..-.....
    uses a minimum number of components, and the
    voltage at both outputs can be set up within ±1.5%
    by a single adjustment. Further, the output volt·
    ages will tend to track with temperature and varia- V,~>l'V ........- - '

    tions on the unregulated supply.

    The positive voltage is regulated by an LM105,


    while an LM 104 regulates the negative supply. The
    unusual feature is that the two regulators are inter-
    connected by R3. This not only eliminates one
    precision resistor, but the reference current of the
    LM104 stabilizes the LM105 so that a ±10% varia-
    tion in its reference voltage is only seen as a ±3%
    change in output voltage. This means that in many
    cases the output voltage of both regulators can be .,.
    set up with sufficient accuracy by trimming a
    single resistor, R 1.
    14K

    " .... tWIIT.Mal ...


    "TnllltlltdM'f\ltl
    of IIoth Jllllllton
    The line regulation and temperature drift of the V.NS-IIV . . .- ....- -. . .- - . . J
    circuit is determined primarily by the LM 104, so
    both output voltages will tend to track. Output LM 104 to ground with a 10/lF capacitor. A
    ripple can be reduced by about a factor of five to center·tapped transformer with a bridge rectifier
    less than 2 mV/V by bypassing Pin 1 of the can be used for the unregulated power source.

    AN21-6
    ADJUSTABLE CURRENT LIMITING

    In laboratory power supplies, it is often necessary


    to adjust the limiting current of a regulator. This,
    of course, can be done by using a variable resis·
    tance for the current limit resistor. However, the
    current-limit resistor can easily have a value below
    that of commercially·available potentiometers.
    Discrete resistance values can be switched to vary
    the limiting current, but this does not provide
    continuously-variable adjustment.

    -4IIV.$.Vour .:;.D
    4DIIIA=>.I" .. s.2DOmA

    '-...----c.....- '" IMPROVING LINE REGULATION

    The circuit shown here solves this problem, giving


    a linear adjustment of limiting current over a
    five·to·one range. A silicon diode, D1, is included
    to reduce the current limit sense voltage to The Ii ne regu lation for voltage variations on the
    approximately 50 mV. Approximately 1.3 mA reference supply terminal of the LM 104 is about
    from the reference supply is passed through a five times worse than it is for changes on the
    potentiometer, R4, to buck out the diode voltage. unregulated input. Therefore, a zener·diode pre-
    Therefore, the effective current limit sense voltage regulator can be used on the reference supply to
    is nearly proportional to the resistance of R4. The improve line regulation. This is shown in the fig·
    current through R4 is fairly insensitive to changes ure.
    in ambient temperature, and D1 compensates for
    temperature variations in the current limit sense
    voltage of the LM104. Therefore, the limiting cur·
    ...
    ...-- ---....--....-- --". ...
    rent will not be greatly affected by temperature.

    It is important that a potentiometer be used for VouT -·I5V

    R4 and connected as shown. If a rheostat connec·


    tion were used, it could open while it was being
    adjusted and momentarily increase the current fs.:.r," Tanbllum

    limit sense voltage to many times its normal value.


    This could destroy the series pass transistors under
    short-circuit conditions.
    ' - - - - -.....__- ....---V... :..-IIV

    The inclusion of R4 will soften the current The design of this circuit is fairly simple. It is only
    limiting characteristics of the LM 104 somewhat necessary that the minimum current through R4
    because it acts as an emitter-degeneration resistor be greater than 2 mA with low input voltage.
    for the current·limit transistor. This can be Further, the zener voltage of D1 must be five volts
    avoided by reducing the value of R4 and develop· greater than one·half the maximum output voltage
    ing the voltage across R4 with additional bleed to keep the transistors in the reference current
    current to ground. source from saturating.

    AN21-7
    USING PROTECTIVE DIODES

    It is a little known fact that most voltage regu· Heavy loads operating from the unregulated
    lators can be damaged by shorting out the unregu· supply can also destroy a voltage regulator. When
    lated input voltage while the circuit is operating- the input power is switched off, the input voltage
    even though the output may have short·circuit can drop faster than the output voltage, causing a
    protection. When the input voltage to the regu· voltage reversal across the regulator, especially
    lator falls instantaneously to zero, the output when the output of the regulator is lightly loaded.
    capacitor is still charged to the nominal output Inductive loads such as a solenoid are particularly
    voltage. This applies voltage of the wrong polarity troublesome in this respect. In addition to causing
    across the series pass transistor and other parts of a voltage reversal between the input and the out·
    the regulator, and they try to discharge the output put, they can reverse the input voltage causing
    capacitor into the short. The resulting current additional damage.
    surge can damage or destroy these parts.
    In cases like this, it is advisable to use a multiple·
    When the LM 104 is used as the control element of pole switch or relay to disconnect the regulator
    the regulator, the discharge path is through inter· from the unregulated supply separate from the
    n al junctions forward biased by the voltage other loads. If this cannot be done, it is necessary
    reversal. If the charge on the output capacitor is in to put a diode across the input of the regulator to
    the order of 40 volt· J.l.F, the circuit can be clamp any reverse voltages, in addition to the pro·
    damaged during the discharge interval. However, tective diode between the input and the output.
    the problem is not only seen with integrated cir-
    cuit regulators. It also happens with discrete regu· .--_ _...._ _. -_ _ _--<....._ ....._GND
    lators where the series'pass transistor usually gets
    blown out. D1
    UTR3l1J5

    The problem can be el iminated by connecting a


    diode between the output and the input such that
    it discharges the output capacitor when the input
    is shorted. The diode should be capable of handl·
    ing large current surges without excessive voltage
    D2
    drop, but it does not have to be a power diode UTR330S

    since it does not carry current continuously. It


    should also be relatively fast. Ordinary rectifier
    diodes will not do because they look like an open
    .--I4t-.....---<.....- - - - - - <.....-v,"
    circuit in the forward direction until minority D3
    '=' UTRJ3.S
    carriers are injected into the intrinsic base region
    of the PIN structure.
    Yet another failure mode can occur if the regu·
    This problem is not just caused by accidental lated supply drives inductive loads. When power is
    physical shorts on the input. It has shown up more shut off, the inductive current can reverse the out·
    than once when regulators are driven from high· put voltage polarity, damaging the regulator and
    frequency dc·dc converters. Tantalum capacitors the output capacitor. This can be cured with a
    are frequently used as output filters for the recti· clamp diode on the output. Even without induc·
    fiers. When these capacitors are operated near their tive loads it is usually good practice to include this
    maximum voltage ratings with excessive high fre· clamp diode to protect the regulator if its output
    quency ripple across them, they have a tendency is accidentally shorted to a negative supply.
    to sputter-that is, short momentarily and clear
    themselves. When they short, they can blowout A regulator with all these protective diodes is
    the regulator; but they look innocent after the shown here. D1 protects against output voltage
    smoke has cleared. reversal. D2 prevents a voltage reversal between
    the input and the output of the regulator. And D3
    The solution to this problem is to use capacitors prevents a reversal of the input·voltage polarity. In
    with conservative voltage ratings, to observe the many cases, D3 is not needed if D 1 and D2 are
    maximum ripple ratings for the capacitor and to used, since these diodes will clamp the input volt·
    include a protective diode between the input and age within two diode drops of ground. This is
    output of the regulator to protect it in case adequate if the input voltage reversals are of short
    sputtering does occur. duration.

    AN21-8
    HIGH VOLTAGE REGULATOR

    In the design of commercial power supplies, it is supply, and its breakdown voltage will determine
    common practice to use a floating bias supply to the maximum operating voltage of the complete
    power the control circuitry of the regulator. As regulator.
    shown here, this connection can be used with the
    LM104 to regulate output voltages that are higher The connection of the LM 104 is somewhat differ·
    than the ratings of the integrated circuit. Better ent than usual: the internal divider for the error
    regulation can also be obtained because it is a amplifier is shorted out by connecting Pins 8 and 9
    simple matter to preregulate the low current bias together. This makes the output voltage equal to
    supply so that the integrated circuit does not see the voltage drop across the adjustment resistor,
    ripple or line voltage variations and because the R2, instead of twice this voltage as is normally the
    reduced operating voltage minimizes power dis· case. C2 and C3 must also be added to prevent
    sipation and associated thermal effects from the oscillation. The value of C3 can be increased to
    current delivered to the booster transistor. 4.7 IlF to reduce noise on the output.

    It is necessary to add 02 and R5 to provide cur·


    rent limiting. When the output current becomes
    CIt high enough to turn on 02, there will be an abrupt
    U"F
    rise in the output current of the LM 104 as 02 tries
    to remove base drive from the booster transistor.
    -r--~'----f----""'-""~'--VOUT~~
    Any further increases in load current will cause the
    LM104 to limit at a current determined by R3,
    and the output voltage will collapse. The value of
    R3 must be selected so that the integrated circuit
    can deliver the base current of 01, at full load,
    without limiting.
    tSoII~Tlntlll"m

    A second, NPN booster transistor can be used in a


    compound connection with Q1 to increase the
    output current of the regulator. However, with
    very·high·voltage regulators. the most economical
    The bias for the LM104, which is normally solution may be to use a high voltage PNP driving
    obtained from a separate winding on the main a vacuum tube for the series pass element.
    power transformer, is preregulated by D1. R4 is
    selected so that it can provide the 3 mA operating Remote sensing, which eliminates the effects of
    current for the integrated circuit as well as the voltage dropped in the leads connecting the regu·
    base drive of the booster transistor, 01, with full lator to the load, can be provided by connecting
    load and minimum line voltage. The booster R2 to the ground end of the load and Pins 8 and 9
    transistor regulates the voltage from the main to the high end of the load.

    AN21-9
    SWITCHING REGULATOR

    Linear regu lators have the advantages of fast the switch transistor, 01, the catch diode, D1, and
    response to load transients as well as low noise and the LC filter. The inductor is made large enough so
    ripple. However, since they must dissipate the that the current through it is essentially constant
    difference between the unregulated·supply power throughout the switching cycle. When 01 turns
    and the output power, they sometimes have a low on, the voltage on its collector will be nearly equal
    efficiency. This is not always a problem with ac to the unregulated input voltage. When it turns
    line·operated equipment because the power loss is off, the magnetic field in L1 begins to collapse,
    easily afforded, because the input voltage is driving the collector voltage of 01 to ground
    already fairly,well regulated and because losses can where it is clamped by D1.
    be minimized by adjustment of transformer ratios
    in the power supply. In systems operating from a If, for example, the input voltage is 10V and the
    fixed dc input voltage, the situation is often much switch transistor is driven at a 50% duty cycle, the
    different. It might be necessary to regulate a 28V average voltage on the collector of 01 will be 5V.
    input voltage down to 5V. In this case, the power This waveform will be filtered by L1 and C1 and
    loss can quickly become excessive. This is true appear as a 5V dc voltage on the output. Since the
    even if efficiency is not one of the more important inductor current comes from the input while 01 is
    criteria, since high power dissipation calls for on but from ground through D1 while 01 is off,
    expensive power transistors and elaborate heat the average value of the input current will be half
    sinking methods. the output current. The power output will there-
    fore equal the input power if !.witching losses are
    Switching regulators can be used to greatly reduce neglected.
    dissipation. Efficiencies approaching 90% can be
    realized even though the regulated output voltage
    ...-_ _....._ _....._ _....._ ...._ _ GND
    is only a fraction of the input voltage. With proper
    design, transient response and ripple can also be
    made quite acceptable. t$abdT ..... lum
    -IZ5IUfnINoZZu

    This circuit, which uses the LM104 as a self·


    oscillating switching regulator, operates in much
    the same way as a Ii near regu lator. The reference
    current is set up at 1 mA with R1, and R2 deter·
    mines the output voltage in the normal fashion.
    The circuit is made to oscillate by applying posi·
    tive feedback through R5' to' the non-inverting ..
    AI
    UK
    D1
    UTXZIO
    input on the error ampl ifier of the LM 104. When
    the output voltage is low, the internal pass tran-
    sistor of the integrated circuit turns on and drives ' -. . ._ _ _ _ _. ._ _ _. . ._ _ Vtlf S;-11V

    01 into saturation. The current feedback through


    R5 then increases the magnitude of the reference
    voltage developed across R2. 01 will remain on
    until the output voltage comes up to twice this In design, the value of R3 is chosen to provide
    reference voltage. At this point, the error amplifier sufficient base drive to 01 at the maximum load
    goes into linear operation, and the positive feed- current. R4 must be low enough so that the bias
    back makes the circuit switch off. When this current coming out of Pin 5 of the LM 104
    happens, the reference voltage is lowered by feed- (approximately 300 IlA) does not turn on the
    back through R5, and the circuit will stay off until switch transistor. The purpose of C2 is to remove
    the output voltage drops to where the error ampli- transients that can appear across R2 and cause
    fier again goes into linear operation. Hence, the erratic switching. It should not be made so large
    circuit regulates with the output voltage oscillating that it severely integrates the waveform fed back
    about the nominal value with a peak-to-peak ripple to this point.
    of around 40 mV.
    For additional information on switching regulators
    The power conversion from the input voltage to a see "Designing Switching Regulators," National
    lower output voltage is obtained by the action of Semiconductor AN-2, August, 1968.

    AN21-10
    7

    HIGH CURRENT SWITCHING REGULATOR

    Output currents up to 3A can be obtained using sipation in the diode, but the diode also presents a
    the switching regulator circuit shown here. The cir· short circuit to the switch transistor, when it first
    cuit is identical to the one described previously, turns on, until all the charge stored in the base
    except that Q2 has been added to increase the region of the diode is removed. Similarly, a high
    output current capability by about an order of frequency switch transistor must be used as exces·
    magnitude. It should be noted that the reference sive switching losses in low frequency transistors,
    supply terminal is returned to the base of 02, like the 2N3055, make them overheat.
    rather than the unregulated input. This is done
    because the LM 104 will not function properly if It is important that the core material llsed for the
    Pin 5 gets more than 2V more positive than Pin 3. inductor have a soft saturation characteristic.
    The reference current, as well as the bias currents Cores that saturate abruptly produce excessive
    for Pins 3 and 5, is supplied from the unregulated peak currents in the switch transistor if the output
    input through R5, so its resistance must be low current becomes high enough to run the core close
    enough so that 02 is not turned on with about to saturation. Powdered molybdenum·permalloy
    2 mA flowing through it. cores, on the other hand, exhibit a gradual reduc·
    tion in permeability with excessive current, so the
    The line regulation of this circuit is worsened only effect of output currents above the design
    somewhat by the unregulated input voltage being value is a gradual increase in switching frequency.
    fed back into the reference for the regulator
    through R6. This effect can be eliminated by con- One thing that is frequently overlooked in the
    necting a 0.01 JlF capacitor in series with R6 to design of switching circuits is the ripple rating of
    remove the dc component of the feedback. tho filter capacitors. Excessive high·frequency
    rir Ie can cause these capacitors to fail. This is an
    r----1--...- - - - . - - -...- -GN • es ecially·important consideration for capacitors
    HZ us&d on the unregulated input as the ripple current
    UK
    1% " lDDpF
    through them can be higher than the dc load cur·
    rent. The situation is eased somewhat for the filter
    capacitor on the output of the regulator since the
    ripple current is only a fraction of the load cur-
    rent. Nonetheless, proper design usually requires
    that the voltage rating of this capacitor be higher
    than that dictated by the de voltage across it for
    reliable operation.
    D1
    IN3110 One unusual problem that has been noted in work·
    ing with switching regulators is excessive dissipa·
    tion in the switch transistors caused by high
    emitter-base saturation voltage. This can also show
    tSohdTlnl.1u1ll up as erratic operation if 01 is the defective
    ·60lurnINa.ZDan RS
    device. This saturation voltage can be as high as 5V
    Arngl.En."...... ftl
    AUD,S}Z
    MolvW,nq ..
    "
    ~--"'--V'P4:i.1.5V and is the result of poor alloying on the base con·
    ,..."oye,.,
    tact of the transistor. A defective transistor will
    not usually show up on a curve tracer because the
    There are a number of precautions that should be low base current needed for linear operation does
    observed with all switching regulators, although not produce a large voltage drop across the
    they are more inclined to cause problems in high· poorly·alloyed contact. However, a bad device can
    current applications: be spotted by probing on the bases of the switch
    transistors while the circuit is operating.
    For one, fast switching diodes and transistors must
    be used. If D1 is an ordinary junction rectifier, It is necessary that the catch diode, D1, and any
    voltages in the order of 10V can be developed bypass capacitance on the unregulated input be
    across it in the forward direction when the switch returned to ground separately from the other parts
    transistor turns off. This happens because low· of the circuit. These components carry large cur·
    frequency rectifiers are usually manufactured with rent transients and can develop appreciable voltage
    a PI N structure which presents a high forward transients across even a short length of wire. If C1,
    impedance until enough minority carriers are C2, or R2 have any common ground impedance
    injected into the diode base region to increase its with the catch diode or the input bypass capacitor,
    conductance. This not only causes excessive dis- the transients can appear directly on the output.

    AN21-11
    SWITCHING REGULATOR WITH
    CURRENT LIMITING

    The switching regulator circuits described pre- age becomes large enough to turn on 03, current
    viously are not protected from overloads or a limiting is initiated. This occurs because 03 takes
    short-circuited output. The current limiting of the over as the control transistor and regu lates the
    LM 104 is used to limit the base drive of the switch voltage on Pin 8 of the LM 104. This point, which
    transistor, but this does not effectively protect the is the feedback terminal of the error amplifier, is
    switch transistor from excessive current. Providing separated from the actual output of the regulator
    short circuit protection is no simple problem, by not shorting the regulated output and booster
    since it is necessary to keep the regulator output terminals of the integrated circuit. Hence,
    operating in the switching mode when thil output with excessive output current, the circuit still oper-
    is shorted. Otherwise, the dissipation in the switch ates as a switching regulator with 03 regulating the
    transistor will become excessive even though the voltage fed back to the error amplifier as the out-
    current is limited_ put voltage falls off.

    A resistor, R7, is included so that excessive base


    r---~""'-""----+---"'-GND
    current will not be driven into the base of 03. C4
    insures that 03 does not turn on from the current
    spikes through the switch transistor caused by
    pulling the stored charge out of the catch diode
    (these are about twice the load current). This ca-
    pacitor also operates in conjunction with C2 to
    produce sufficient phase delay in the feedback
    loop so that the circuit will oscillate in current
    limiting. However, C4 should not be made so large
    that it appreciably integrates the rectangular wave-
    D1
    form of the current through the switch transistor.
    IUUO

    As the output voltage falls below half the design


    value, D1 pulls down the reference voltage across
    R2. This permits the current limiting circuitry to
    'C.rallMtDr ,.,n
    fSul •• untllum keep operating when the unregulated input voltage
    ·&OI"nINoZDun
    A•• aldE",,,,",,,,, drops below the design value of output voltage,
    AI301512Mlry .. ,"UIII
    ",""alloyeu" with a short on the output of the regulator.
    "" A transistor with good high-current capability was
    chosen for 03 so that it does not suffer from
    secondary breakdown effects from the large peak
    A circuit which provides current limiting and pro- currents (about 200 mAl through it. With a
    tects the regulator from short circuits is shown shorted output, these peak currents occur with the
    here_ The current through the switch transistor full input voltage across 03_ The average dissipa-
    produces a voltage drop across R9. When this volt- tion in 03 is, however, low_

    AN21-12
    SWITCHING REGULATOR WITH
    OVERLOAD SHUTOFF

    An alternate method for protecting a switching no power, until it is reset by removing the input
    regulator from excessive output currents is shown voltage.
    here. When the output current becomes too high,
    the voltage drop across the current·sense resistor, In the actual circuit, complementary transistors,
    RS, fires an SCR which shuts off the regulator. Q3 and 04, replace the SC R since it is difficult to
    The regulator remains off, dissipating practically find devices with a low enough holding current
    (about 25 fJA). When the voltage drop across RS
    becomes large enough to turn on 04, this removes
    the base drive for the output transistors of the
    LM 104 through Pin 4. When this happens 03
    "'
    '" latches 04, holding the regulator off until the
    " input voltage is removed. It will then start when
    power is applied if the overload has been removed.

    With this circuit, it is necessary that the shutoff


    current be 1.5 times the full load current. Other-
    wise, the circuit will shut off when it is switched
    on with a full load because of the excess current
    required to charge the output capacitor. The shut-
    D1
    1,.3110
    off current can be made closer to the full load
    current by connecting a 10 fJF capacitor across R2
    which will limit the charging current for C1 by
    slowing the risetime of the output voltage when
    the circuit is turned on. However, this capacitor
    Ai "
    4P tSot.dTIII,lIuIII
    will also bypass the positive feedback from R6
    which makes the regulator oscillate. Therefore, it
    J-~~-...""""","---,,,,--..J ·::::~~~,":~n~
    ASlDISJ·2Malybdlllum is necessary to put a 270n resistor in the ground
    AI ••• lftIllaytorl
    O.ll end of the added capacitor and provide feedback
    L..._...._ _ _ _ _ _...._ _ _ _ _ V,~5-.SV

    to this resistor from the collector of 01 through a


    1 Mn resistor.

    AN21-13
    DRIVEN SWITCHING REGULATOR

    When" a number of switching regulators are oper- input of the error amplifier. The waveform is
    ated from a common power source, it is desirable obtained by integrating the square wave synchro-
    to synchronize their operation to more uniformly nizing signa'- This triangular wave causes the error
    distribute the switched current waveforms in the amplifier to switch because its gain is high enough
    input line_ Synchronous operation can also be that the waveform easily overdrives it. The switch-
    beneficial when a switching regulator is operated ing duty cycle is controlled by the output voltage
    in conjunction with a power converter. fed back to the error amplifier. If the output volt-
    age goes up, the duty cycle will decrease since the
    error amplifier will pick off a smaller portion of
    r - -....>-~~-....- - -....-".
    the triangular wave. Similarly, the duty cycle will
    decrease if the output voltage drops. Hence, the
    J'U"L.
    IIV... _!illlb
    ......,.'Y-4I-... duty cycle is controlled to produce the desired
    output voltage.

    Without a synchronous drive signal, the circuit will


    self oscillate at a frequency determined by L1 and
    Cl. This self·oscillation frequency must be lower
    ., than the synchronous drive frequency. Therefore,
    more filtering is required for a driven regulator
    ,.
    UK

    than for a self-oscillating regulator operating at the


    "
    UTX21'
    same frequency. This also means that a driven
    regulator will have less output ripple.
    ' - _....._ _ _ _ _--<....._ ....._v, .. s_.v
    The value of C2 is chosen so that its capacitive
    reactance at the drive frequency is less than one-
    A circuit which synchronizes the switching regu- tenth the resistance of R2. The amplitude of the
    lator with a square wave drive signal is shown here. triangular wave is set at 25 mV with R5. It is advis-
    It differs from the switching regulators described able to ac couple the drive signal by putting a
    previously in that positive feedback is not used. capacitor in series with R5 so that it does not
    Instead, a triangular wave with a peak-to·peak disturb the dc reference voltage developed for the
    amplitude of 25 mV is applied to the noninverting error ampl ifier.

    AN21-14
    THE LM104 REGULATOR

    The basic reference for the regulator is zener diode The reference supply terminal is normally con·
    01. The reference diode is supplied from a PNP nected to the unregulated supply. However,
    current source, OB, which has a fixed current gain improved line regulation can be obtained by pre·
    of 2. This arrangement permits the circuit to regulating the voltage on this terminal. This
    operate with unregulated input voltages as low as improvement occurs because 01, 02, and 07 do
    7V, substantially increasing the efficiency of low· not see changes in input voltage. Normally, it is
    voltage regulators. the change in the emitter·base voltage of these
    transistors with changes in collector·base voltage
    The reference supply is temperature compensated which determines the line regulation.
    by using the negative temperature coefficient of
    the transistor em itter·base voltages to cancel the When the reference supply and unregulated input
    positive coefficient of the zener diode. The design terminals are operated from separate voltage
    produces a nominal 2.4V between the reference sources, it is important to make sure that the un·
    and reference supply terminals of the integrated regulated input terminal of the integrated circuit
    circuit. Connecting an external 2.4 Kn resistor does not get more than 2V more positive than the
    between those terminals gives a 1 mA reference reference supply terminal. If this happens, the
    current from the collectors of 01 and 02, which is collector·isolation junction of 06 becomes
    independent of temperature. The reference voltage forward biased and disrupts the reference.
    supplied to the error amplifier is developed across
    a second external resistor connected between the The error amplifier of the regulator is quite similar
    adjustment terminal and ground. to the LM101 operational amplifier. Emitter

    ADJUSTMENT
    r - - -. .- - - - -....- -. .--------~~~~...:.. GRQUIlO
    R1I
    15K

    ""
    15K

    .,
    • REGULATED
    OUTPUT

    ""
    " llOOUlR
    OUTPUT

    :"--...- -..--+-+---1---....- .... 1


    ....0 ~~M~~lNT
    L..._ _ _ _ _ _ _ _ _ _-I-_......../. ."-'~~~--...:.5 ~II~~\GULATED

    REfERENCE REFERENCE COMPENSATION


    SUPPLY

    AN21-15
    follower input transistors, 018 and 019, drive a characteristic. The pre-load current, provided for
    dual PNP which is operated in the common-base 024 by 010 before current limiting is initiated,
    configuration. The current gain of these PNP tran- gives a much sharper current-limit characteristic.
    sistors is fixed at 4 so that the base can be driven Cl and R11 are included in the limiting circuitry
    by a current source (013). Active collector loads to suppress oscillations.
    are used for the input stage so that a voltage gain
    of 2000 is obtained. 021 and 022 provide enough The error amplifier is connected to a divider on
    current gain to keep the internal, series-pass tran- the output (R 15 and R16) to keep the reference
    current generator from saturating with low input-
    sistor from loading the input stage. R14 limits the
    output voltage differentials. A compensating
    base drive on 023 when it saturates with low, un-
    resistor, R17, which is equal to the equivalent
    regulated input voltages. The collector of 023 is
    brought out separately so that an external booster resistance of the divider is included to minimize
    offset error in the error ampl ifier.
    transistor can be added for increased output cur-
    rent capability. R13 established the minimum The major feedback loop is frequency compen-
    operating current in 023 when booster transistors sated by the brute-force method of rolling off the
    are used. response with a relatively large capacitor on the
    output. C2 is included on the integrated circuit to
    One feature of the error amplifier is that it oper- compensate for the effects of series resistance in
    ates properly with common mode voltages all the the output capacitor. A compensation point is also
    way up to ground. Because of this, the circuit will brought out so that more capacitance can be
    regulate with output voltages to zero volts. added across C2 for certain regulator configura-
    tions. R8 improves the load-transient response,
    Current limiting is provided by 024. When the especially when compensation is added on Pin 4.
    voltage between the current limit and unregulated
    input terminals becomes large enough to turn on The purpose of 09, which is a collector FET, is to
    024, it will pull 010 out of saturationandremove bias the current-source transistors, 012 and 013.
    base drive from 021 through 020. This causes the It also supplies the preload current for the
    series pass transistor to exhibit a constant current current-limit transistor, 024, through 010.

    AN21-16
    »
    z
    January 1969 N
    w
    -I
    ::t
    m
    r-
    ...s:
    o
    U1
    :i>
    THE LM105 - AN IMPROVED z
    POSITIVE REGULATOR ~:
    "tI
    ::J:I
    o
    <
    m
    C
    INTRODUCTION "tI
    o
    IC voltage regulators are seeing rapidly increasing J
    en
    usage. The LM lOa, one of the first, has already
    been widely accepted. Designed for versatility, this ..
    g
    =
    ~ -0.2
    I'ot
    1"\
    ..... I
    LM105
    =i
    <:m
    circuit can be used as a linear regulator, a switch· LM100
    ing regulator, a shunt regulator, or even a current ~ \ I
    regulator. The output voltage can be set between
    :: -0.4 ::J:I
    2V and 30V with a pair of external resistors, and it
    "'~ m
    is -0.6 SHORT CIRCUIT C')
    CURRENT
    works with unregulated input voltages down to > C
    t-
    \1 L...' I
    7V. Dissipation limitations of the IC package reo
    strict the output current to less than 20 mA, but
    external transistors can be added to obtain output
    ~ -.08
    !;
    = -1.0
    Rsc -l0n
    T,= 25"C

    10 20
    I
    ,
    ,

    3D 40
    >
    -I
    o
    currents in excess of 5A. The LM 100 and an
    LOAD CURRENT (mAl ::J:I
    extensive description of its use in many practical
    i. TJ'" 25°C
    circuits are described in References 1·3.

    One complaint about the LM 100 has been that it L I I


    does not have good enough regulation for certain g -,...., ...... 1 I
    z
    applications. In addition, it becomes difficult to ~ -0.2 LM100 \. IILM1051-
    prove that the load regulation is satisfactory under «
    :;; II I
    worst·case design conditions. These problems ~ -0.4
    w \ II I
    prompted development of the LM 105, wh ich is "'
    « SHORT CIRCUIT
    ~ -0.6
    nearly identical to the LM 100 except that a gain CURRENT
    =
    >
    stage has been added for improved regulation. In 1,..-"1
    the great majority of appl ications, the LM 105 is a
    !; -O.B
    ~
    Rsc'" 10n
    T. '" 125°C
    I
    .II I
    plug·in replacement for the LM100. CI -1.0
    10 20 3D
    THE IMPROVED REGULATOR LOAD CURRENT (mAl
    b. T, = 125"C
    The load regulation of the LM 100 is about 0.1 %,
    no load to full load, without current limiting. FIGURE 1. Comparison Between the Load Regulation of
    When short circuit protection is added, the regula· the LM 100 and LM 105 for Equal Short Cir·
    tion begins to degrade as the output current cuit Currents
    becomes greater than about half the limiting cur·
    rent. This is illustrated in Figure 1. The LM105, on places that the probability of it becoming shorted
    the other hand, gives 0.1 % regulation up to cur· is quite high. Secondly, the sharpness of the limit-
    rents closely approaching the short circuit current. ing characteristics is not improved by the addition
    As shown in Figure lb, this is particularly signifi· of external booster transistors. External transistors
    cant at high temperatures. can i'ncrease the maximum output current, but
    they do not improve the load regulation at cur-
    The current limiting characteristics of a regulator rents approaching the short circuit current. Thus,
    are important for two reasons: First, it is almost it can be seen that the LM 105 provides more than
    mandatory that a regulator be short·circuit pro· ten times better load regulation in practical power
    tected because the output is distributed to enough supply designs.

    AN23-1
    Figure 2 shows that the LM105 also provides r---:;;-t----.,...-~..:...UNREGUlATEOIN'UT
    better line regulation than the LM 100. These
    curves give the percentage change in output volt· IOOSTERDurrUT

    age for an incremental change in the unregulated


    input voltage. They show that the line regulation is
    worst for small differences between the input and CURREMYLIMIT

    output voltages. The LM 105 provides about three


    REGULATEOOUTflUT
    times better regulation under worst case condi·
    tions. Bypassing the internal reference of the regu·
    lator makes the ripple rejection of the LM 105
    al most a factor of ten better than the LM 100 over
    the entire operating range, as shown in the figure.
    This bypass capacitor also eliminates noise gener·
    ated in the internal reference zener of the IC.
    ~-+- ..... . :. fEEDIACt(

    0.1
    '-t..:""-l,----..--:. REFERENCE ,.,'ASS

    ~z
    VOUT "10V '-.+-..........--..-. .=---.....:.GIIOUIO
    .. 0.05
    ~~IOO==
    t
    ;;; 0.02 , ~~
    1"'- FIGURE 4. Schematic Diagram of the LM105 Regulator.

    .
    ::
    ;'!
    ~ 0.005
    0.01
    In the LM100, generation of the reference voltage
    starts with zener diode, Dl, which is supplied with
    > LMI05 RIPPLE RElECTION~ ..... j;;;; a fixed current from one of the collectors of 02.
    ~ 0.002
    ill I IIIII C,,,=IOpF
    f>120Hz
    This regulated voltage, which has a positive tem·
    perature coefficient, is buffered by 04, divided
    0.001
    10 20 50 down by R 1 and R2 and connected in series with a
    INPUT·OUTPUT VOLTAGE DIFFERENTIAL (VI diode-connected transistor, 07. The negative tem·
    perature coefficient of 07 cancels out the positive
    FIGURE 2. Comparison Between the Line Regulation
    coefficient of the voltage across R2, producing a
    Characteristics of the LM100 and LM105. temperature·compensated 1.BV on the base of OB.
    This point is also brought outside the circuit so
    that an external capacitor can be added to bypass
    The LM 105 has also benefited from the use of new any noise from the zener diode.
    IC components developed after the LM 100 was
    designed. These have reduced the internal power Transistors OB and 09 make up the error amplifier
    consumption so that the LM 105 can be specified of the circuit. A gain of 2000 is obtained from this
    for input voltages up to 50V and output voltages single stage by using a current source, another col·
    to 40V. The minimum preload current required by lector on 02, as a collector load. The output of
    the LM 100 is not needed on the LM 105. the amplifier is buffered by all and used to drive
    the series'pass transistor, a 12. The collector of
    012 is brought out so that an external PNP tran·
    CIRCUIT DESCRIPTION
    sistor, or PNP-NPN combination, can be added
    for increased output current.
    The differences between the LM100 and the
    LM 105 can be seen by comparing the schematic
    Current limiting is provided by 010. When the
    diagrams in Figures 3 and 4. 04 and 05 have been
    voltage across an external resistor connected
    added to the LM 105 to form a common·collector,
    betwe"en Pins 1 and B becomes high enough to turn
    common·base, common·emitter amplifier, rather
    on 010, it removes the base drive from all so the
    than the single common·emitter differential ampli·
    regulator eXhibits a constant·current characteristic.
    fier on the LM 100.
    Prebiasing the current limit transistor with a por·
    . -...._ _ _ _- ._ _--<t-_ _...._3 ~N~~iGUlATED tion of the emitter·base voltage of 012 from R6
    and R7 reduces the current limit sense voltage.
    This increases the efficiency of the regulator,
    especially "l'hen foldback current limiting is used.
    "1-..........,.__..'_r~.:I~ENT With foldback limiting, the voltage dropped across
    ...,v.-..Nv-H>----f-"-8 ~~~~~:TED
    D3
    the current .sense resistor is about four times larger
    than the sense voltage.
    As for the remaining details, the collector of the
    amplifier, 09, is brought out so that external
    collector-base capacitance can be added to
    h..'!'!........_~..~----...:.& FEEDBACK frequency·stabilize the circuit when it is used as a
    '-__+-______...:.5 :~~:~NCE linear regulator. This terminal can also be grounded
    .3
    ZlK
    to shut the regulator off. R9 and R4 are used to
    '-_-<1>-_ _....._ _ _ _ _ _---""4 GROUND start up the regulator, while the rest of the cir-
    cuitry establishes the proper op~rating levels for
    FIGURE 3. Schematic Diagram of the LM100 Regulator. the current source transistor, 02.

    AN23-2
    The reference circuitry of the LM105 is the same, massive heat sink would be required if the pass
    except that the current through the reference transistor was included in the IC.
    divider, R2, R3 and R4, has been reduced by a
    factor of two on the LM 105 for reduced power Assuming that these problems could be solved, it is
    consumption. In the LM 105, 02 and 03 form an still not advisable to put the pass transistor on the
    emitter coupled amplifier, with 03 being the same chip with the reference and control circuitry:
    emitter· follower input and 02 the common·base changes in the unregulated input voltage or load
    output amplifier. R6 is the collector load for this current produce gross variations in chip tempera,
    stage, which has a voltage gain of about 20. The ture. These variations worsen load and line regula·
    second stage is a differential amplifier, using 04 tion due to temperature interaction with the con·
    and 05. 05 actually provides the gain. Since it has trol and reference circuitry.
    a current source as a collector load, one of the
    collectors of 012, the gain is quite high: about
    To elaborate, it is reasonable to neglect the pack·
    1500. This gives a total gain in the error amplifier
    age problem since it is potentially solvable. The
    of about 30,000, which is ten times higher than
    lower, maximum operating temperatures of IC's,
    the LM 100.
    however, present a more basic problem. The con·
    It is not obvious from the schematic, but the first trol circuitry in an IC regulator runs at fairly low
    stage (02 and 03) and second stage (04 and 05) currents. As a result, it is more sensitive to leakage
    of the error amplifier are closely balanced when currents and other phenomena which degrades the
    the circuit is operating. This will be true regardless performance of semiconductors at high tempera·
    of the absolute value of components and over the tures. Hence, the maximum operating temperature
    operating temperature range. The. only' thing is limited to 150°C in military temperature range
    affecting balance is component matching, which is applications. On the other hand, a power transistor
    good in a monolithic integrated circuit, so the operating at high currents may be run at tempera·
    error amplifier has good drift characteristics over a tures up to 200° C, because even almA leakage
    wide temperature range. current would not affect its operation in a prop·
    erly designed circuit. Even if the pass transistor
    Frequency compensation is accomplished with an developed a permanent 1 mA leakage from chan·
    external integrating capacitor around the error neling, operating under these conditions of high
    amplifier, as with the LM 100. This scheme makes stress, it would not affect circuit operation. These
    the stability insensitive to loading conditions- conditions would not trouble the pass transistor,
    resistive or reactive-while giving good transient but they would most certainly cause complete fail·
    response. However, an internal capacitor, Cl, is ure of the control circuitry.
    added to prevent minor·loop oscillations due to
    the increased gain. These problems are not eliminated in applications
    with a lower maximum operating temperature.
    Additional differences between the LM 100 and Integrated circuits are sold for limited temperature
    LM105 are that a field·effect transistor, 018, con· range appl ications at considerably lower cost. This
    nected as a current source starts the regulator is mainly based on a lower maximum junction
    when power is first applied. Since this current temperature. They may be rated so that they do
    source is connected to ground, rather than the out· not blow up at higher temperatures, but they are
    put, the minimum load current before the regu·
    not guaranteed to operate within specifications at
    lator drops out of operation with large input· these temperatures. Therefore, in applications with
    output voltage differentials is greatly reduced. This
    a lower maximum ambient temperature, it is
    also minimizes power dissipation in the integrated necessary to purchase an expensive full tempera·
    circuit when the difference between the input and
    ture range part in order to take advantage of the
    output voltage is at the worst·case value. With the theoretical maximum operating temperatures of
    LM 105 circuit configuration, it was also necessary
    the IC.
    to add 017 to eliminate a latch·up mechanism
    which could exist with lower output·voltage set·
    tings. Without 017, this could occur when 03
    Figure 5 makes the point about dissipation limita·
    saturated and cut off the second stage amplifiers,
    tions more strongly. It gives the maximum short
    04 and 05, causing the output to latch at a volt·
    circuit output current for an IC regulator in a
    age nearly equal to the unregulated input. TO·5 package, assuming a 25°C temperature rise
    between the chip and ambient and a quiescent cur·
    POWER LIMITATIONS rent of 2 mAo Dual·in·line or flat packages give
    results which are, at best, slightly better, but are
    Although it is desirous to put as much of the regu- usually' worse. If the short circuit current is not of
    lator as possible on the IC chip, there are certain prime concern, Figure 5 can also be used to give
    basic limitations. For one, it is not a good idea to the maximum output current as a function of
    put the series pass transistor on the chip. The input-output voltage differential. However, the
    power that must be dissipated in the pass tran· increased dissipation due to the quiescent current
    sistor is too much for practical IC packages. Fur· flowing at the maximum input voltage must be
    ther, IC's must be rated at a lower maximum oper· taken into account. In addition, the input·output
    ating temperature than power transistors. This differential must be measured with the maximum
    means that even with a power package, a more· expected input voltages.

    AN 23-3
    ~
    &0

    40
    \ , I II
    j
    iO 5 ·
    1
    base transistor like the 2N3740 is recommended
    because it causes fewer oscillation problems than
    double-diffused, planar devices. In addition, it
    \ INFINITE HEAT seems to be less prone to failure under overload
    =
    c
    !::; 30
    \SINK - 500 mW conditions; and low cost devices are available in
    "....
    > \ power packages like the TO-66 or even TO-3.

    ~ 20 NO HEATSINj
    161mW When the maximum dissipation in the pass tran-
    sistor is less than about 0.5W, a 2N2905 may be
    10
    ~T=125!C I I ""- \,.
    lo=2mA I used as a pass transistor. However, it is generally
    necessary to carefully observe thermal deratings
    1.0 10 100
    and provide some sort of heat sink.
    OUTPUT CURRENT (mAl
    In the circuit of Figure 6, the output voltage is
    FIGURE 5. Dissipation Limited Short Circuit Output determined by R 1 and R2. The resistor values are
    Current for an Ie Regulator in <I TO-S Pack- selected based on a feedback voltage of 1.8V to
    age.
    Pin 6 of the LM105. To keep thermal drift of the
    The 25°C temperature rise assumed in arriving at output voltage within specifications, the parallel
    Figure 5 is not at all unreasonable. With military combination of R 1 and R2 should be approxi-
    temperature range parts, this is valid for a maxi- mately 2K. However, this resistance is not critical.
    mum junction temperature of 150°C with a 125°C Variations of ±30% will not cause an appreciable
    ambient_ For low cost parts, marketed for limited degradation of temperature drift.
    temperature range applications, this maximum dif-
    ferential appropriately derates the maximum junc- The 1 IlF output capacitor, C2, is required to sup-
    tion temperature. press oscillations in the feedback loop involving
    the external booster transistor, 01, and the output
    In practical designs, the maximum permissible transistor of the LM 1 05. C 1 compensates the
    dissipation will always be to the left of the curve internal regulator circuitry to make the stability
    shown for an infinite heat sink in Figure 5_ This independent for all loading conditions. C3 is not
    curve is realized with the package immersed in normally required if the lead length between the
    circulating acetone, freon or mineral oil. Most heat regulator and the output filter of the rectifier is
    sinks are not quite as good. short.

    To summarize, power transistors can be run with a Current limiting is provided by R3. The current
    temperature differential, junction to ambient, 3 to limit resistor should be selected so that the maxi-
    5 times as great as an integrated circuit. This mum voltage drop across it, at full load current, is
    means that they can dissipate much more power, equal to the voltage given in Figure 7 at the maxi-
    even with a smaller heat sink. This, coupled with mum junction temperature of the IC. This assures
    the fact that low cost, multilead power packages a no load to full load regulation better than 0.1%
    are not available and that there can be thermal under worst-case conditions_
    interactions between the control circuitry and the
    260 r-r--,-,--,-,.--r->-.--r-r-"-"'--'-J-'
    pass transistor, strongly suggests that the pass tran-
    sistors be kept separate from the integrated circuit. 10 ~ 12mA
    >
    .§
    220
    ~
    USING BOOSTER TRANSISTORS
    '"
    ~ 110
    Figure 6 shows how an external pass transistor is
    added to the LM 105. The addition of an external
    PNP transistor does not increase the minimum
    >
    ~
    w
    \:j 140
    " " t-.
    input output voltage differential. This would
    happen if an NPN transistor was used in a com-
    pound emitter follower connection with the NPN
    output transistor of the IC_ A single-diffused, wide
    100
    20 40 60 80 100 120
    JUNCTION TEMPERATURE ('C)
    "
    140 160

    FIGURE 7. Maximum Voltage Drop Across Current


    Limit Resistor at Full Load for Worst Case
    Load Regulation of 0.1%.
    , - -....--"".,.,.....-----~.__+-Vou, .. 5V

    ., .,
    11.1

    .
    0.&5
    5.15K The short circuit output current is also determined
    I
    • 7
    4Jpf
    by ·R3. Figure 8 shows the voltage drop across this
    01
    2N314C1 2 lMl05 , -:~C2t
    "f'i",
    resistor, when the output is shorted, as a function
    , of junction temperature· in the IC.
    V,.

    ~~~.:I~F
    3
    • .
    .2
    3.1SK tSalidtlntllum

    GRDUND
    With the type of current limiting used in Figure 6,
    the dissipation under short circuit conditions can
    be more than three times the worst-case full load
    FIGURE 6. O.2A Regulator. dissipation. Hence, the heat sink for the pass tran-

    AN 23-4
    "

    R3. Therefore, more voltage must be developed


    across R3 before current limiting is initiated. After
    the output voltage begins to fall, the bucking
    voltage is reduced, as it is proportional to the out-
    put voltage. With the output shorted, the current
    is reduced to a value determined by the current
    limit resistor and the current limit sense voltage of
    the LM1 05.

    0.2 L-J......L.....1-....L...L...L-L-1.--.l 16
    -75 -50 -25 0 25 50 75 100 125 150
    14
    JUNCTION TEMPERATURE rCI
    ~ 12

    '"~'"
    FIGURE 8. Voltage Drop Across Current Limit Resistor 10
    Required to Initiate Current Limiting.
    NORMAL ./1) I
    > 8 LOAD LIN~ .,f-~ CURRENT-
    !; II" J SOURCE I
    6 HI-t/-.f---t.''+L-Tt-, L~AI LI,NE
    sistor must be designed to accommodate the in- .,~ 4
    creased dissipation if the regulator is to survive
    2 " ·F STABLE +-+-H
    more than momentarily with a shorted output. It 1t. ... rJ OPERATING POINT
    is encouraging to note, however, that the short o
    0.5 1.0 1.5 2.0 2.5
    circuit current will decrease at higher ambient tem-
    peratures. This assists in protecting the pass tran- OUTPUT CURRENT (AI
    sistor from excessive heating.
    FIGURE 10. Limiting Characteristics of Regulator Using
    Foldback Current limiting.
    FOLDBACI< CURRENT LIMITING

    With high current regulators, the heat sink for the


    pass transistor must be made quite large in order
    to handle the power dissipated under worst-case Figure 10 illustrates the limiting characteristics.
    conditions. Making it more than three times larger The circuit regulates for load currents up to 2A.
    Heavier loads will cause the output voltage to
    to withstand short circuits is sometimes incon·
    venient in the extreme. This problem can be solved drop, reducing the available current. With a short
    with foldback current limiting, which makes the on the output, the current is only 0.5A.
    output current under overload conditions decrease
    below the full load current as the output voltage is In design, the value of R3 is determined from
    pulled down. The short circuit current can be
    made but a fraction of the full load current. (1)

    A high current regulator using foldback limiting is


    shown in Figure 9. A second booster transistor, where V lim is the current limit sense voltage of the
    01, has been added to provide 2A output current LM105, given in Figure 8, and Isc is the design
    without causing excessive dissipation in the value of short circuit current. R5 is then obtained
    LM 105. The resistor across its emitter base june· from
    tion bleeds off any collector base leakage and
    establishes a minimum collector current for 02 to R5~ VOUT+V,.,nse (2)
    make the circuit easier to stabilize with light loads. I bleed + I bias
    The foldback characteristic is produced with R4
    and R5. The voltage across R4 bucks out the where V OUT is the regulated output voltage, Vsense
    voltage dropped across the current sense resistor, is maximum voltage across the current limit resis·
    tor for 0.1% regulation as indicated in Figure 7,
    Ibleed is the preload current on the regulator out·
    put provided by R5 and Ibias is the maximum cur·
    rent coming out of Pin 1 of the LM105 under full
    load conditions.lbiaswill be equal to 2 mA plus the
    worst·case base drive for the PNP booster tran·
    sistor, 02. Ibleed should be made about ten times
    greater than Ibias'

    Finally, R4 is given by

    (3)

    FIGURE 9. 2A Regulator with Foldback Current Limit- where I FL is the output current of the regulator at
    ing. full load.

    AN 23-5
    It is recommended that a ferrite bead be strung on With foldback limiting, power dissipation in the
    the emitter of the pass transistor, as shown in Fig- pass transistor reaches a maximum at some point
    ure 9, to suppress oscillations that may show up between full load and short circuited output. This
    with certain physical configurations_ It is advisable is illustrated in Figure 11. However, if the
    to also include C4 across the current limit resistor. maximum dissipation is calculated with the
    worst-case input voltage, as it should be, the power
    In some applications, the power dissipated in Q2 peak is not too high.
    becomes too great for a 2N2905 under worst-case
    conditions_ This can be true even if a heat sink is 25
    used, as it should be in almost all applications.
    When dissipation is a problem, the 2N2905 can be ,." ......
    20
    replaced with a 2N3740. With a 2N3740, the fer- ~
    rite bead and C4 are not needed because this tran- 15
    ;:: IS
    sistor has a lower cutoff frequency. ~ V
    2i
    a 10
    One of the advantages of foldback limiting is that '"~ r- VIN '" 25V
    it sharpens the limiting characteristics of the IC_ In f I--IFl '" 2.DA
    addition, the maximum output current is less sen- r l se· D•5A
    sitive to variations in the current limit sense volt- o
    age of the IC: in this circuit, a 20% change in sense o Big· 12 14 16
    voltage will only affect the trip current by 5%. The OUTPUT VOLTAGE (V)
    temperature sensitivity of the full load current is
    likewise reduced by a factor of four, while the FIGURE 11. Power Dissipation in Series Pass Transistors
    short circuit current is not. Under Overload Conditions in Regulator
    Using Foldback Current Limiting.
    Even though the voltage dropped across the sense
    resistor is larger with foldback limiting, the mini- HIGH CURRENT REGULATOR
    mum input-output voltage differential of the com-
    plete regulator is not increased above the 3V speci- The output current of a regulator using the LM 105
    fied for the LM 105 as long as this drop is less than as a control element can be increased to any de-
    2V. This can be attributed to the low sense voltage sired level by adding more booster transistors, in-
    of the IC by itself. creasing the effective cu rrent gai n of the pass tran-
    sistors. A circuit for a lOA regulator is shown in
    Figure 10 shows that foldback limiting can only be Figure 12. A third NPN transistor has been in-
    used with certain kinds of loads. When the load cluded to get higher current. A low frequency
    looks predominately like a current source, the load device is used for Q3 because it seems to better
    line can intersect the foldback characteristic at a withstand abuse. However, high frequency transis-
    point where it will prevent the regulator from tors must be used to drive it. Q2 and Q3 are both
    coming up to voltage, even without an overload. double-diffused transistors with good frequency
    Fortunately, most solid state circuitry presents a response. This insures that Q3 will present the
    load line which does not intersect. However, the dominant lag in the feedback loop through the
    possibility cannot be ignored, and the regulator booster transistors, and back around the output
    must be designed with some knowledge of the transistor of the LM 105. This is further insured by
    load. the addition of C3.

    r---1t---1I,....----1II-..."".,.--4...- - - - - - - 4...- -. .- VOUT"sv

    I, , '
    '3
    AS 01.
    51

    ••
    47
    C1-

    "
    5!i5K
    IOV

    "
    47pf

    .,
    315K
    ,,1 fSohdtlntilum
    4").1FI
    35V
    ·EleellotVllc

    FIGURE 12_ lOA Regulator with Foldbaek Current


    Limiting.

    AN23-6
    The circuit, as shown, has a full load capability of The problem can be eliminated completely by
    lOA. Foldback limiting is used to give a short installing a diode between the input and output of
    circuit output current of 2.5A. The addition of 03 the regulator such that the capacitor on the output
    increases the minimum input-output voltage dif- is discharged through this diode if the input is
    ferential, by 1 V, to 4V. shorted. A fast switching diode should be used as
    ordinary rectifier diodes are not always effective.
    DOMINANT FAILURE MECHANISMS
    Another cause of problems with regulators is se-
    By far, the biggest reason for regulator failures is vere voltage transients on the unregulated input_
    overdissipation in the series pass transistors. This Even if these transients do not cause immediate
    has been borne out by experience with the failure in the regulator, they can feed through and
    LM 100. Excessive heating in the pass transistors destroy the load. If the load shorts out, as is fre-
    causes them to short out, destroying the IC. This quently the case, the regulator can be destroyed
    has happened most frequently when PNP booster by subsequent transients.
    transistors in a TO-5 can, like the 2N2905, were
    used. Even with a good heat sink, these transistors This problem can be solved by specifying all parts
    cannot dissipate much more than lW. The maxi- of the regulator to withstand the transient condi-
    mum dissipation is less in many applications. When tions. However, when ultimate reliability is
    a single PNP booster is used and power can be a needed, this is not a good solution. Especially
    problem, it is best to go to a transistor like the since the regulator can withstand the transient, yet
    2N3740, in a TO-66 power package, using a good severely overstress the circuitry on its output by
    heat sink. feeding the transients through. Hence, a more logi-
    cal recourse is to include circuitry which suppres-
    Using a compound PNP/NPN booster does not ses the transients. A method of doing this is shown
    solve all problems. Even when breadboarding with in Figure 13. A zener diode, which can handle
    transistors in TO-3 power packages, heat sinks
    Ll
    must be used. The TO-3 package is not very good, 10DmH
    thermally, without a heat sink. Dissipation in the
    PNP transistor driving the NPN series pass transis- J\o
    INPUT"" ...,
    :;::vv:;;::::;
    tor cannot be ignored either. Dissipation in the Fl
    driver with worst-case current gain in the pass tran-
    sistor must be taken into account. In certain cases, Dl* .. ~
    UZ58411·..~.
    this could require that a PNP transistor in a power 40V -r
    package be used to drive the NPN pass transistor.
    In almost all cases, a heat sink is required if a PNP
    driver transistor in a TO-5 package is selected. ·Unitrode

    With output currents above 3.A, it is good practice FIGURE 13. Suppression Circuitry to Remove Large
    to replace a 2N3055 pass transistor with a 2N3772. Voltage Spikes from Unregulated Supplies.
    The 2N3055 is rated for higher currents than 3A,
    but its current gain falls off rapidly. This is espe-
    cially true at either high temperatures or low large peak currents, clamps the input voltage to
    input-output voltage differentials. A 2N3772 will the regulator while an inductor limits the current
    give substantially better performance at high cur- through the zener during the transient. The size of
    rents, and it makes life much easier for the PNP the inductor is determined from
    driver.
    LIN Llt
    L=-- (4)
    The second biggest cause of failures has been the I
    output filter capacitors on power inverters provid-
    ing unregulated power to the regulator. If these where Ll V is the voltage by which the input tran-
    capacitors are operated with excessive ripple across sient exceeds the breakdown voltage of the diode,
    them, and simultaneously near their maximum dc Llt is the duration of the transient and I is the peak
    voltage rating, they will sputter. That is, they short current the zener can handle while still clamping
    momentarily and clear themselves. When they the input voltage to the regulator. As shown, the
    short, the output capacitor of the regulator is dis- suppression circuit will clamp 70V, 4 ms transients
    charged back through the reverse biased pass tran- on the unregulated supply_
    sistors or the control circuitry, frequently causing
    destruction. This phenomenon is especially preva- CONCLUSIONS
    lent when solid tantalum capacitors are used with
    high-frequency power inverters. The maximum The LM 105 is an exact replacement for the
    ripple allowed on these capacitors decreases lin- LM100 in the majority of applications, providing
    early with frequency. about ten times better regulation. There are, how-
    ever, a few differences:
    The solution to this problem is to use capacitors
    with conservative voltage ratings. In addition, the In switching regulator applications,> the size of
    maximum ripple allowed by the manufacturer at the resistor used to provide positive feedback
    the operating frequency should also be observed. should be doubled as the impedance seen looking

    AN23-7
    back into the reference bypass terminal is twice all the driver and pass transistors. Devices must
    that of the LM100 (2 Kn versus 1 Kn). In addi· then be selected which can handle the power. Fur·
    tion, the minimum output voltage of the LM105 is ther, adequate heat sinks must be provided as even
    4.5V, compared with 2V for the LM 100. In low power transistors cannot dissipate much power by
    voltage regulator applications, the effect of this is themselves.
    obvious. However, it also imposes some limitations
    on current regulator and shunt regulator designs. 3 Normally, the highest power dissipation occurs
    Lastly, clamping the compensation terminal when the output of the regulator is shorted. If this
    (Pin 7) within a diode drop of ground or the out· condition requires heat sinks which are so large as
    put terminal will not guarantee that the regulator to be impractical, foldback current limiting can be
    is shut off, as it will with the LM100. This restricts used. With fold back limiting, the power dissipated
    the LM 105 in the overload shutoff schemes 3 under short circuit conditions can actually be
    wh ich can be used with the LM 100. made less than the dissipation at full load.

    Dissipation limitations of practical packages dic· The LM 105 is designed primarily as a positive volt-
    tate that the output current of an IC regulator be age regulator. A negative regulator, the LM104,
    less than 20 mAo However, external booster tran· which is a functional complement to the LM105,
    sistors can be added to get any output current is described in Reference 4.
    desired. Even with satisfactory packages, consid·
    erably larger heat sinks would be needed if the REFERENCES
    pass transistors were put on the same chip as the
    reference and control circuitry, because an IC 1. R. J. Widlar, "A Versatile, Monolithic Voltage
    must be run at a lower maximum temperature Regulator," National Semiconductor AN·l,
    than a power transistor. In addition, heat dissi- February, 1967.
    pated in the pass transistor couples into the low
    level circuitry and degrades performance. All this 2. R. J. Widlar, "Designing Switching Regulators,"
    suggests that the pass transistor be kept separate National Semiconductor AN·2, April, 1967.
    from the IC.
    3. R. J. Widlar, "New Uses for the LM 100 Regula·
    Overstressing series pass transistors has been the tor," National Semiconductor AN·8, June,
    biggest cause of failures with IC regulators. This 1968.
    not only applies to the transistors within the IC,
    but also to the external booster transistors. Hence, 4. R. J. Widlar, "Designs for Negative Voltage
    in designing a regulator, it is of utmost importance Regulators," National Semiconductor AN·21,
    to determine the worst·case power dissipation in October, 1968.

    AN23-8
    M. Yamatake
    June 1969

    l>
    rJ)

    :is:
    "'U
    !:
    ."
    m
    C
    -I
    m
    rJ)
    A SIMPLIFIED TEST SET FOR -I
    rJ)
    OPERATIONAL AMPLIFIER CHARACTERIZATION m
    -I
    ."
    o
    ::D
    o
    "'0
    m
    ::D
    l>
    ::!
    o
    Z
    INTRODUCTION
    l>
    r-
    The test set described in this paper allows com· Function Test. In the first two of these tests, the l>
    plete quantitative characterization of all dc opera- amplifier under test is exercised throughout its full :is:
    tional amplifier parameters quickly and with a common mode range. In all three tests, power "'0
    minimum of additional equipment. The method supply voltages for the circuit under test may be !:
    used is accurate and is equally suitable for labora- set at ±5V, ±10V, ±15V or ±20V. ."
    tory or production test-for quantitative readout m
    or for limit testing. As embodied here, the test set POWER SUPPLY ::D
    is conditioned for testing the LM709 and LM 101 Basic waveforms and dc operating voltages for the (')
    amplifiers; however, simple changes discussed in test set are derived from a power supply section J:
    the text will allow testing of any of the generally comprising a positive and a negative rectifier and l>
    available operational amplifiers. filter, a test set voltage regulator, a test circuit ::D
    voltage regulator, and a function generator. The l>
    Amplifier parameters are tested over the full range (')
    dc supplies will be discussed in the section dealing
    of common mode and power supply voltages with -I
    either of two output loads. Test set sensitivity and
    with detailed circuit description. m
    ::D
    stabil ity are adequate for testing all presently The waveform generator provides three output
    available integrated amplifiers. N
    functions, a ±19V square wave, a -19V to +19V l>
    pulse with a 1% duty cycle, and a ±5V triangular -I
    The paper will be divided into two sections, i.e., a
    functional description, and a discussion of circuit
    wave. The square wave is the basic waveform from
    which both the pulse and triangular wave outputs
    o
    operation. Complete construction information wi II Z
    are derived.
    be given including a layout for the tester circuit
    boards. The square wave generator is an operational ampli-
    fier connected as an astable multivibrator. This
    FUNCTIONAL DESCRIPTION amplifier provides an output of approximately
    The test set operates in one of three basic modes. ±19V at 16 Hz. This square wave is used to drive
    These are: (1) Bias Current Test; (2) Offset junction FET switches in the test set and to gen·
    VOltage, Offset Current Test; and (3) Transfer erate the pu lse and triangular waveforms.

    AN24-1
    ,.....------------------0 !::~:::TAL
    r-____Oll\._-_~ ~~:~~~EL

    03
    si5;lr------1 R7

    I
    I
    I
    I
    I
    I
    SSbL.:-----...J
    O'

    FIGURE 1. Functional Diagram of Bias Current Test


    Circuit

    The pulse generator is a monostable multivibrator co.l")figuration by R I , R 2 , R 3 , and R4 • The inputs


    driven by the output of the square wave generator. of this differential amplifier are driven in common
    This multivibrator is allowed to swing from nega- from the output of the triangular wave generator
    tive saturation to positive saturation on the through attenuator Rs and amplifier As. The
    positive going edge of the square wave input and inputs of the device under test are connected to
    has a time constant which will provide a duty the feedback network through resistors Rs and
    cycle of approximately 1%. The output is approxi- R6 , shunted by the switch S5. and S5 b'
    mately -19V to +19V.
    The feedback network provides a closed loop gain
    The triangular wave generator is a dc stabilized of 1,000 and the integrator time constant serves to
    integrator driven by the output of the square wave reduce noise at the output of the test circuit as
    generator and provides a ±5V output at the square well as allowing the output of the device under
    wave frequency, inverted with respect to the test to remain near zero volts.
    square wave.
    The bias current test is accomplished by allowing
    The purpose of these various outputs from the the device under test to draw input current to one
    power supply section will be discussed in the func· of its inputs through the corresponding input resis·
    tional description. tor on positive going or negative going halves of
    the triangular wave generator output. This is
    BIAS CURRENT TEST accomplished by closing S5. or S5 b on alternate
    halves of the triangular wave input. The voltage
    A functional diagram of the bias current test appearing across the input resistor is equal to input
    circuit is shown in Figure 1. The output of the current times the input resistor. This voltage is
    triangular wave generator and the output of the multiplied by 1,000 by the feedback loop and
    test circuit, respectively, drive the horizontal and appears at the integrator output and the vertical
    vertical deflection of an oscilloscope. input of the oscilloscope. The vertical separation
    of the traces representing the two input currents
    The device under test, (cascaded with the inte· of the amplifier under test is equivalent to the
    grator, A 7 ), is connected in a differential amplifier total bias current of the amplifier under test.

    AN24-2
    The bias current over the entire common mode current test. The only difference is that the
    range may be examined by setting the output of switches S5 a and S5 b are closed on the same half·
    As equal to the amplifier common mode range. A cycle of the triangular wave input.
    photograph of the bias current oscilloscope display
    is given as Figure 2. In this figure, the total input The synchronous operation of S5 a and S5 b forces
    the amplifier under test to draw its input currents
    through matched high and low input resistors on
    alternate halves of the input triangular wave. The
    difference between the voltage drop across the two
    values of input resistors is proportional to the dif-
    ference in input current to the two inputs of the
    amplifier under test and may be measured as the
    vertical spacing between the two traces appearing
    on the face of the oscilloscope.

    Offset voltage is measured as the vertical spacing


    between the trace corresponding to one of the two
    values of source resistance and the zero volt base·
    line. Switch S6 and Resistor R. are a base line
    chopper whose purpose is to provide a baseline
    reference which is independent of test set and
    oscilloscope drift. S6 is driven from the pulse out-
    put of the function generator and has a duty cycle
    of approximately 1% of the triangular wave.

    FIGURE 2. Bias Current and Common Mode Rejection Figure 3 is a photograph of the various waveforms
    Display presented during this test. Offset voltage and off-
    set current are displayed at a sensitivity of 1 mV
    and 100 nA per division, respectively, and both
    parameters are displayed over a common mode
    current of an amplifier is displayed over a ±10V range of ±1 OV.
    common mode range with a sensitivity of 100 nA
    per vertical division.

    The bias current display of Figure 2 has the added


    advantage that incipient breakdown of the input
    stage of the device under test at the extremes of
    the common mode range is easily detected.

    If either or both the upper or lower trace in the


    bias current display exhibits curvature near the
    horizontal ends of the oscilloscope face, then the
    bias current of that input of the amplifier is shown
    to be dependent on common mode voltage. The
    usual causes of this dependency are low break·
    down voltage of the differential input stage or
    current sink.

    OFFSET VOLTAGE, OFFSET CURRENT TEST

    The offset voltage and offset current tests are FIGURE 3. Offset Voltage, Offset Current and Common
    performed in the same general way as the bias Mode Rejection Display

    AN24-3
    ,------------------0 ~~:~:O':_rAL
    TO SCOPE
    VERTICAL

    R12

    1
    FIGURE 4. Functional Diagram of Transfer Function
    Circuit

    TRANSFER FUNCTION TEST Figure 5 is a photograph of the output of the test


    A functional diagram of the transfer function test set during the transfer function test. This figure
    is shown in Figure 4. The output of the triangular illustrates the function of amplifier A7 in adjusting
    wave generator and the output of the circuit under the dc input of the test device so that its transfer
    test, respectively, drive the horizontal and vertical function is displayed on the center of the oscillo·
    inputs of an oscilloscope. scope face.

    The device under test is driven by a ±2.5 mV trio The transfer function display is a plot of Von vs
    angular wave derived from the ±5V output of the Vou • for an amplifier. This display provides infor-
    triangular wave generator through the attenuators mation about three amplifier parameters: gain.
    R11, R 1 2, and R 1, R 3 and through the voltage
    follower, A 7. The output of the device under test
    is fed to the vertical input of an oscilloscope.

    Amplifier A, performs a dual function in this test.


    When S7 is closed during the bias current test, a
    voltage is developed across C1 equal to the ampli·
    fier offset voltage multiplied by the gain of the
    feedback loop. When S7 is opened in the transfer
    function test, the charge stored in C 1 continues to
    provide this offset correction voltage. In addition,
    A7 sums the triangular wave test signal with the
    offset correction voltage and applies this sum to
    the input of the amplifier under test through the
    attenuator R 1, R3 • This input sweeps the input of
    the amplifier under test ±2.5 mV around its offset
    voltage. FIGURE 5. Transfer Function Display

    AN24-4
    R1
    ID ADJUST R2 FOR +ZOOV
    "'
    ZUKI"

    ,."'
    22.2K

    "'
    2.2K
    C3
    SYSTEM
    -20Y

    '" :I:'"F
    ':' TANT

    .2&
    10K
    ,,'+--------+----------==---
    I
    SYSTEM
    +2DV
    1% 1
    R1 I D.U.T.
    UK I V·
    1%1
    "' I
    UK I D.U.T.
    1%1 V-
    "' I
    2.5KI
    1%1
    RID I
    Z.SK I
    ,% L_

    RESISTORS
    ONS2.

    NOTE: All RESISTOR VALVES -RU 'ID


    IN OHMS.
    ALL RESISTORS 1I4W, 5%
    UNLESS SPECIFIED
    ,.
    lOOK
    O.Dlpf

    OTHERWISE

    .11
    11K

    .
    .11
    lOOK

    11 01-04
    lN4001 t21V

    C15

    58 -ZIY
    ~ ~~::ALUM

    FIGURE 6. Power Supply and Function Generator

    gain linearity, and output swing. Gain is displayed two power supplies are provided in the test set.
    as the slope, AVou,/f:N in of the transfer function. One supply provides a fixed ±20V to power the
    Gain linearity is indicated change in slope of the circuitry in the test set; the other provides ±5V to
    Vou,/V in display as a function of output voltage. ±20V to power the circuit under test.
    This display is particularly useful in detecting
    crossover distortion in a Class B output stage. Out- The test set power supply regulator accepts +28V
    put swing is measured as the vertical deflection of from the positive rectifier and filter and provides
    the transfer function at the horizontal extremes of +20V through the LM 100 positive regulator.
    the display. Amplifier AI is powered from the negative recti-
    fier and filter and operates as a unity gain inverter
    DETAILED CIRCUIT DESCRIPTION whose input is +20V from the positive regulator,
    and whose output is -20V.
    POWER SUPPLIES
    As shown in Figure 6, which is a complete sche- The test circuit power supply is referenced to the
    matic of the power supply and function generator, +20V output of the positive regulator through the

    AN24-5
    variable divider comprising R 7 , R8 , R9 , R 10 , and is high enough so that the integrator action at the
    R26 . The output of this divider is +10V to +2.5V square wave frequency is not degraded.
    according to the position of S2 a and is fed to the
    non-inverting, gain-of-two amplifier, A2 . A2 is Operating frequency of the function generator
    powered from +28V and provides +20V to +5V at may be varied by adjusting the time constants
    its output. A3 is a unity gain inverter whose input associated with A 4 , As, and A6 in the same ratio.
    is the output of A2 and which is powered from
    -28V. The complementary outputs of amplifiers TEST CIRCUIT
    A2 and A3 provide dc power to the circuit under
    test_ A complete schematic diagram of the test circuit is
    shown in Figure 7. The test circuit accepts the out-
    puts of the power supplies and function generator
    LM101 amplifiers are used as A2 and A3 to allow
    and provides horizontal and vertical outputs for an
    operation from one ground referenced voltage
    each and to provide protective current limiting for X-V oscilloscope, which is used as the measure-
    the device under test. ment system.

    The primary elements of the test circuit are the


    FUNCTION GENERATOR feedback buffer and integrator, comprising ampli-
    fier A7 and its feedback network C 16 , R 31, R 3 2,
    The function generator provides three outputs, a and C 1 7, and the differential amplifier network,
    ±19V square wave, a -19V to+19V pulse having a
    comprising the device under test and the feedback
    1% duty cycle, and a ±5V triangular wave. The
    network R40, R43 , R44 , and R S2 ' The remainder
    square wave is the basic function from which the of the test circuit provides the proper conditioning
    pulse and triangular wave are derived, the pulse is
    for the device under test and scaling for the oscil·
    referenced to the leading edge of the square wave, loscope, on which the test results are displayed.
    and the triangular wave is the inverted and inte-
    grated square wave.
    The amplifier A8 provides a variable amplitude
    Amplifier A4 is an astable multivibrator generating source of common mode signal to exercise the
    a square wave from positive to negative saturation. amplifier under test over its common mode range.
    Th.e amplitude of this square wave is approxi- This amplifier is connected as a non-inverting gain-
    mately ±19V. The square wave frequency is of-3.6 amplifier and receives its input from the
    determined by the ratio of R 18 to R 16 and by the triangular wave generator. Potentiometer R 3 7
    time constant, R 1 7C9' The operating frequency is allows the output of this amplifier to be varied
    stabilized against temperature and power regula- from ±O volts to ± 18 volts. The output of this
    tion effects by regulating the feedback signal with amplifier drives the differential input resistors,
    the divider R 19 , Ds and D6 . R43 and R44 , for the device under test.

    Amplifier As is a monostable multivibrator trig- The resistors R46 and R47 are current sensing
    gered by the positive going output of A 4 . The resistors wh ich sense the input current of the
    pulse width of As is determined by the ratio of device under test. These resistors are switched into
    R20 to R22 and by the time constant R21 C 10 . the circuit in the proper sequence by the field
    The output pulse of As is an approximately 1% effect transistors 0 6 and 0 7 , 0 6 and 0 7 are driven
    duty cycle pulse from approximately -19V from the square wave output of the function
    to +19V. generator by the PNP pair, 0 10 and 0 11 , and the
    NPN pair, 0 8 and 0 9 , Switch sections S1 band
    Amplifier A6 is a dc stabilized integrator driven S1 c select the switching sequence for 0 8 and 0 9
    from the amplitude-regulated output of A4 . Its and hence for 0 6 and 0 7 , In the bias current test,
    output is a ±5V triangular wave. The amplitude of the F ET drivers, 0 8 and 0 9 , are switched by out
    the output of A6 is determined by the square wave of phase signals from 0 10 and 0 11 , This opens the
    voltage developed across Ds and D6 and the time F ET switches 0 6 and 0 7 on alternate half cycles
    constant Radi C, 4. DC stabil ization is accom- of the square wave output of the function gen-
    plished by the feedback network R24 , R, s' and erator. During the offset voltage, offset current
    C, s. The ac attenuation of this feedback network test, the FET drivers are operated synchronously

    AN24-6
    vo,
    I",

    TF
    RZ>
    ,.
    5. '"
    .Dt,..F R3I
    3.
    R3Z
    3D.
    I,
    Sid

    PRE~OR-1 S3
    ~O~I~S5 1.

    R35
    ZM

    L___~::-______--, Z.,,~::Jf-"'-" czo


    ~'.,'"
    R4I
    1M R3&
    ZM
    -lOV

    .,,=-.. . .;...J'j(!~ '"


    (SCALE)
    R5Z VlOIV
    SD. RESISTORS ON
    L..._...._ ....._ ... _ZIV ~0.01"10 '= sn

    ALL RESISTOR VALUES IN OHMS


    TF
    NOTE: ALL RESISTORS t/4W, 5% UNLESS SPECIFIED OTHERWISE
    -ZN3It9MATCHED FOR ON RESISTANCE WITHIN ZOOU
    SELECT FOR BVGS>45V

    FIGURE 7. Test Circuit

    from the output of 011. During the transfer func· The input for the integrator·feedback buffer, A7 ,
    tion test, 0 6 and 0 7 are switched on continuously is selected by the FET switches O. and 05. During
    by turning off 011. R42 and R45 maintain the the bias current and offset voltage offset current
    gates of the F ET switches at zero gate to source tests, A7 is connected as an integrator and receives
    voltage for maximum conductance during their on its input from the output of the device under test.
    cycle. Since the sources of these switches are at The output of A7 drives the feedback resistor,
    the common mode input voltage of the device R40 • In this connection, the integrator holds the
    under test, these resistors are connected to the output of the device under test near ground and
    output of the common mode driver amplifier, As. serves to amplify the voltages corresponding to

    AN24-7
    bias current, offset current, and offset voltage by a reference which is independent of instrument or
    factor of 1,000 before presenting them to the mea- oscilloscope calibration. The gate of Q, is driven
    surement system. FET switches ~ and Qs are by the output of monostable multivibrator As,
    turned on by switch section S, b during these tests. and shorts the vertical oscilloscope drive signal to
    ground during the time that As output is positive.
    FET switches Q 4 and Q s are turned off during the
    transfer function test. This disconnects A7 from Switch S3' R2 7, and R28 provide a 5X scale
    the output of the device under test and changes it increase during input parameter tests to allow
    from an integrator to a non·inverting unity gain measurement of amplifiers with large offset
    amplifier driven from the triangular wave output voltage, offset current, or bias current.
    of the function generator through the attenuator
    R33 and R34 and switch section SI •. In this con· Switch Ss allows amplifier compensation to be
    nection, amplifier A7 serves two functions; first, changed for 101 or 709 type amplifiers.
    to provide an offset voltage correction to the input
    of the device under test and, second, to drive the CALIBRATION
    input of the device under test with a ±2.5 mV
    triangular wave centered about the offset voltage. Calibration of the test system is relatively simple
    During this test, the common mode driver ampli· and requires only two adjustments. First, the out·
    fier is disabled by switch section S I. and the put of the main regulator is set up for 20V. Then,
    the triangular wave generator is adjusted to pro·
    vertical input of the measurement oscilloscope is
    vide ±5V output by selecting Rad;. This sets the
    transferred from the output of the integrator·
    horizontal sweep for the X·Y oscilloscope used as
    buffer, A 7, to the output of the device under test
    the measurement system. The oscilloscope is then
    by switch section S'd. S2. allows supply voltages
    set up for 1VIdivision vertical and for a full 10
    for the device under test to be set at ±5, ±10, ±15,
    division horizontal sweep.
    or ±20V. S2 b changes the vertical scale factor for
    the measurement oscilloscope to maintain Scale factors for the three test positions are:
    optimum vertical deflection for the particular
    power supply voltage used. S4 is a ml?mentary 1. Bias Current Display (Figure 2)
    contact pushbutton switch which is used to change Ibias total 100 nA/div. vertical
    the load on the device under test from 10kQ Common Mode Voltage Variable horizontal
    to 2kQ. 2. Offset Voltage-Offset Current (Figure 3)
    IOffse' 100 nA/div. vertical
    A delay must be provided when switching from Vo_ ' 1 mV/div. vertical
    the input tests to the transfer function tests. The Common Mode Voltage Variable horizontal
    purpose of this delay is to disable the integrator
    3. Transfer Function (Figure 5)
    function of A7 before driving it with the triangular
    Vin 0.5 mV/div.
    wave. If this is not done, the offset correction volt·
    age, stored on C I ., will be lost. This delay be· Vou , 5V/div. @ Vs ±20V
    5V/div.@Vs ±15V
    tween opening FET switch 0 4 , and switch as, is
    provided by the RC filter, R3S and C 19 • 2V/div. @ Vs ±10V
    lV/div.@V s ± 5V

    Resistor R41 and diodes D7 and DB are provided Gain = AV ou,


    to control the integrator when no test device is AV in
    present, or when a faulty test device is inserted.
    R41 provides a dc feedback path in the absence of
    CONSTRUCTION
    a test device and resets the integrator to zero.
    Diodes D7 and De clamp the input to the inte· Test set construction is simplified through the use
    grator to approximately !.7 volts when a faulty of integrated circuits and etched circuit layout.
    device is inserted.
    Figure 8 gives photographs of the completed
    FET switch Q, and resistor R28 provide a ground tester. Figure 9 shows the parts location for the
    reference at the beginning of the 50·ohm·source, components on the circuit board layout of Fig-
    offset-voltage trace. This trace provides a ground ure 10_ An attempt should be made to adhere to

    AN24-8
    this layout to insure that parasitic coupling be- S3. S4 Grayhill 30-1 Series 30 subminiature
    tween elements will not cause osci lIations or give pushbutton switch
    cal ibration problems.
    S5. S6 Alcoswitch MST-105D SPDT
    Table 1 is a listing of special components which
    are needed to fit the physical layout given for the CONCLUSIONS
    tester.
    A semi-automatic test system has been described
    which will completely test the important opera-
    TABLE 1- Partial Parts List
    tional amplifier parameters over the full power
    T1 Triad F-90X supply and common mode ranges. The system is
    simple. inexpensive. easily calibrated. and is
    S1 Centralab PA2003 non-shorting equally suitable for engineering or quality assur-
    Centralab PA20 15 non-shorting ance usage.

    FIGURE 8a. Bottom of Test Set

    AN24-9
    Tr:ms(l'r Input O((sd
    F'\\twtion yoltage/Current

    Vertical: Vo Vt'rticai: Vos, los


    Sc-C' Vs switch ImV/div •• lOOnA/div.
    Horio-:ontal: Yin Horizontal: CMY
    O.5mV/div. Sl'(' eM control

    FIGURE 8b. Front Panel

    FIGURE 8c. Jacks

    AN24-10
    --1L--+
    _Cl3 _+-
    ~L...--- ------I+~~~OO~
    T1

    _Cl2

    Vos.los

    FIGURE 9. Component Location, Top View

    AN24-11
    FIGURE 10. Circuit Board Layout

    AN24-12
    l>
    zI
    Dale Mrazek N
    January 1970 00

    HIGH-SPEED MOS COMMUTATORS I

    en
    Speed and accuracy of MOS analog commutators Although they switch analog voltages, the MOS i':l
    are being improved sharply by techniques initially field-effect transistors in these commutators can
    m
    m
    developed to make large-scale MOS digital inte- be interfaced with logic ICs almost as readily as C
    grated circuits compatible with bipolar logic cir- low-voltage MOS ICs. Either MOS or bipolar logic
    cuits. Now, TIL logic can drive an MOS commuta- can control the MOSFET gate voltages. Only a few s:
    tor at rates up to 20 MHz, with signal accura- volts change in the gate voltage will turn the o
    cies better than 90%. And at lower frequencies, MOSFETs on or off. en
    accuracies very close to 100% can be achieved. (')
    Examples of new multichannel designs for analog/
    o
    In the past, MOS monolithic commutators and
    multiplexers were recommended for precision ana-
    digital data-gathering applications are shown in
    Figures 1 and 2. Circuit impedances have been s:
    log switching only at relatively low rates, on the optimized in each so that commutation rates are s:C
    order of 10kHz. Commutation at higher rates was much higher than the normal 200 to 500 kHz
    considered risky because of large noise transients rate of low-voltage MOS commutators (rates, in- -I
    produced by the MOS switching transistors. Con· cidentally, about twice as high as the maximum ~
    siderable time had to be allowed for the transients
    to settle down before the signal could be sampled
    rates of high-threshold commutators). The all-MOS
    system in Figure 1 operates at 1 MHz, while the
    o
    ::D
    accurately. MOSITTL system in Figure 2 achieves 20 MHz. en
    Transient noises have been reduced to at least half LOWERING THRESHOLD VOLTAGES
    their former level by processes that lower the
    switching-voltage threshold of the MOS transistors. Reducing the MOSFET switching-threshold volt-
    The processes also cut impedance and leakage cur- age, VTH, improves most of the characteristics that
    rent, permitting low-impedance designs that fur- affect commutator performance. Chief result is a
    ther enhance commutator performance. reduction in the gate-voltage change needed to

    Vx " tlOV
    ANALOG INPUTS
    IZ'N"ZKnl

    ANALOG
    1--+----0 (Zouy=41KI OUTPUT

    Yoo"'OV
    YGG"-24W
    CLOCK INPUT
    Va=Vss= +lZV FOR tlDV ANALOG INPUTS
    IFmu ~ I MHd
    RON "'ZDOn

    FIGURE 1. AII-MOS 1-MHz Multiplexer or Commutator

    AN28-1
    VII." ±IV TO ±2V
    ANALOG INPUTS
    Il w -S:2aanl
    ANALOG
    r - - - - - -....>-t--------....-o fZ~:'TU!10Kn)

    I
    I
    ~
    "'--"1 V..

    .o-----~--+_~--~--~~--~_, I
    VCC "'+5V V' I
    _J
    '"
    " DMl142
    DECODER
    INTER·
    fA"
    Re
    I------.J
    ITTLJ N£T· F",u"ZOMHz

    " WORK ~::::::::::::::::::::~-~ V'" = +IDV OR +12V


    VSIS =+10R"'ZV
    RON "21tDn

    Va

    FIGURE 2. Hybrid MOS/TTL 2O·MHz Commutator for Low·Level Signals

    switch the MOSFET on and off. In turn, switching source and drain (the source is the most positive
    times and the noise transients and circuit imped· terminal). VTH is the bias at which the layer of
    ances that produce signal errors can all be reo intrinsic semiconductor, with no surplus of elec·
    duced. The benefits of lowering VTH are additive, trons or holes, and the p·channel reach the drain
    particularly in multichannel commutators. The diffusion. Conduction begins at this point and
    signal may go through several switches in series. increases as VG goes more negative than VTH
    (that is, when the gate·to·source voltage -V GS is
    The importance of the threshold voltage is iIIus· more than VTH ).
    trated in Figure 3, which shows schematically the
    operation of a p·channel enhancement type of The (1·0-0) silicon process described in the appen-
    MOSFET (the basic element of most MOS inte· dix produces MOSFETs whose VTH is 1.8 to 2.5
    grated circuits). It conducts when the gate voltage volts when there is no bias between bulk (sub-
    is more negative than the potential of the source strate) and source (Vas = 0). In comparison, a
    and the bulk semiconductor substrate Vss by at conventional MOSFET made with (1-1-1) silicon
    least VTH • The oxide under the gate electrode acts has a VTH of about 4V. Practical MOS circuits do
    as the dielectric of a capacitor. The electric field have some VBS bias and usually some additional
    applied to the gate electrode cause holes (absence signal voltage at the source, which raise the work-
    of electrons) to appear in the channel region ing value of VTH . As the typical VTH curves in
    starting from the source. The n·type silicon there Figure 4 show, the threshold of a device rises with
    is converted to p·type, eliminating the p·n diode VBS'
    junctions that had blocked current flow between
    -VOS<VTH
    GATE

    SUBSTRATE VelVSlSI
    (BULKI
    Off THRESHOLD ON
    (IMPEDANCE ROfF ", UJI On) (IMPEDANCE RON ""'lOOn)

    FIGURE 3. Channel Enhancement in MOS Transistors (P Channel)

    AN 28-2
    A general equation describing these relationships is accurate commutation. In contrast, a 2V threshold
    makes the necessary swing only from +10V to
    about -20V. The difference becomes more signifi·
    cant at lower signal voltages. At V x = ± 1V, for
    where K is a device constant (usually 0.8 to 1.2) instance, the high VTH device requires a swing
    and ±2<PF is the zero·bias threshold. This equation from at least +lV to -10V, while the low VTH
    produces curves such as those in Figure 4. device does the job with +1 V to -6V - about a
    third less. High·speed, low·impedance TTL gates
    ID r--.---r--,---r--, can control a commutator in the latter voltage
    '~~--+--+--+--1 range, as shown in Figure 2, because such small
    BI--+--+--l-c=--I--""I
    , '-- v" . ,,!v~q-r-
    __+-l transitions can be made very rapidly. They are
    • /'f close enough to bipolar logic transitions for the
    5 V use of simple, high·speed TTL·to·MOS interfaces.
    ,~~.'v-j-­
    , ~~--+-+--I-~
    ,1/ Multichannel switches made with (1·0·0) silicon
    1~~--+--+--+--1 typically operate with a maximum change in
    control voltage of from +14V to -30V, which
    o
    permits Vx = ±14V. Relatively few practical ap·
    5 10 15 20 25
    VaUU:TOSOURCE
    plications require so large a swing. If larger signal
    FIGURE 4. Typical Threshold-Voltage Curves voltage must be handled, it would be cheaper to
    use a scaler than to pay the cost of a high·voltage
    The MOSFET equivalent circuit (Figure 5) offers multiplexer with beefed·up control circuitry.
    further insight into the importance of lowering
    VTH . The smaller change in VG means that smaller ON AND OFF RESISTANCES
    transient voltages will appear at source and drain.
    The transients are caused by charging and dis- For best signal accuracy and maximum switching
    charging of the capacitances. The time required to rate, impedances should be low. The resistance of
    change VG and the duration of the transients will a MOSFET while on, RON, varies with signal volt·
    be smaller, too. The value of RON, the MOSFET's age, so it cannot be compensated readily. This pro·
    impedance while conducting, will also be less at duces a variable error term called RON modulation.
    any given value of VG more negative than VTH .
    Any reduction in RON will make V OUT more MOS commutators are usually structured as series
    nearly equal to V IN. The accuracy of an analog switches (Figure 6a). Two or more ranks of com·
    switch is determined by the ratio VouT/VIN' mutators are generally used, as in Figure 1, to
    minimize the control circuitry. The added ranks
    CONTROL VOLTAGES put additional MOSFETs in each signal channel
    and enlarge the amount and variation in RON of
    Signal voltage V x often varies between positive the conducting channel. If Vx varies, the error
    and negative values in commutator applications. ratio VouTIV IN tends to vary because RON is a
    To make certain that the MOSFET switches on function of the effective switch ing threshold
    under all signal conditions, VG must swing from at which rises and falls with V x.
    least Vx to (VSS-VTH-AV-VX), where ±Vx are
    the signal limits and AV is the overdrive needed to There is no simpie way of keeping RON constant.
    lower the switch's series resistance to the desired Usually, the effect of the variation is reduced by
    level (mainly, reduction in Ro N obtained by increasing the other impedances, but that lowers
    making -VGS more negative). the maximum switching r;3te. A 10w,VTH eases this
    problem greatly. All other conditions being equal,
    If the signal range is fairly wide, say ±10V, the the MOSFET with the lowest VTH will conduct
    gate voltage of a MOSFET with a 4V to 6V thresh- better at any given value of VG more negative than
    old must swing from +10V to about -26V for VTH . The p·channel enhancement will be greater
    v- v, v'
    lCO'''-AOl
    GATE

    VI,. ~ Vx SOURCE RON DRAIN VOUT ~ Vx

    ,,-,
    ROfF
    ....

    BULK

    FIGURE 5. Equivalent Circuit of P-Channel MOSFET

    AN 28-3
    and the channel electrically larger. Figure 6c is a output and degrading the accuracy of the signal
    typical curve of RON versus gate bias. Low,V TH through the on channel (V x in the figurel. ROFF
    analog switches made with (1·0-01 silicon by Na- is usually around 10' 0 ohms. If V y is a high-
    tional Semiconductor as integrated circuits achieve frequency signal, there may be significant AC
    RON values comparable to those of larger, but feedthrough, but this can be prevented by tech-
    niques to be discussed shortly.
    higher-V TH , discrete MOSFETs--from 250 to 300
    ohms at Vx = -10V and about 100 ohms when SWITCHING SPEED AND NOISE
    Vx = +10V. The RON of a high-VTH integrated
    commutator, in contrast, is typically a few hun- The absolute switching speed of a commutator is
    dred ohms higher and some reportedly reach a few limited by the time required to charge and dis-
    kilohms. charge the device capacitances. Circuit impedances
    affect speed by contributing to the RC time con-
    To swamp out the voltage-divider effect in Figure stants. However, the practical switching rate of a
    6b, it has been customary to make the load, R L, precision commutator depends upon the time re-
    much larger than the combination of RON and quired for the output signal to recover from
    Rs. Output impedances in the megohm range the noise transients produced during the charge-
    are often used with high-V TH devices. But note in discharge cycles. Low-VTH processing cuts tran-
    Figure 2 that very low values of source and load sient recovery time because the transients' dura-
    impedance can be used with low-VTH commu- tion and amplitude are reduced. Some designs
    tators. These low impedances and the very low make the recovery time negligible.
    impedance of the TTL circuit controlling the gate
    are two of the main reasons for this commutator's In all MOSFETs, transmission of a turn-on or turn-
    exceptionally high speed. off signal is followed by a delay whose length de-
    pends upon the magnitude and rate of change of
    Source impedance is usually made equal or less the gate-control voltage. At turn-on, the delay is
    than RON so that leakage currents of the turned- lengthened by the RC time constant of the gate-
    off MOSFETs can return to a low-impedance bulk capacitance (see Figure 51 and the imped-
    turned-on channel signal source. Leakage per ance in the control circuit. Capacitances and im-
    switch is small in an integrated circuit commuta- pedances in the signal path cause a similar delay at
    tor, but there are several switching devices with a turn-off. As VGS goes negative, turning the switch
    common output in the same semiconductor sub- on, energy is pulled from the source and load
    strate. Leakage currents could add up to a value impedances through the gate-source and gate-drain
    that seriously degrades signal accuracy. In any capacitances, as in the simplified equivalent circuit
    semiconductor device, leakage increases rapidly of Figure la. At turn-off, VGS goes to zero volts
    with temperature. However, the leakage specifica- or positive, and energy is pushed out through the
    tion is so small in our commutator made with same paths.
    (1-0-01 silicon that they will work well up to a
    temperature of 125°C, while commutators made Thus, negative turn-on and positive turn-off tran-
    with (1-1-11 silicon have been specified for a sients' appear at the summing node. The transient
    maximum operating temperature of only 85°C. waveforms of low VTH and high VTH MOSFETs
    are shown simplified and superimposed in Figure
    Regardless of the process, the OFF resistance, lb. The levels are typical for devices with VTH
    ROFF ' of a well-made MOSFET is generally high = 2V and VTH = 4V at Vx = ±lV. The larger gate
    enough to prevent the signal in the 0 F F channel voltages used at higher signal voltages wou Id make
    (channel Vy in Figure 6al from appearing at the durations and amplitudes proportionately larger
    Z.D nr-rn--r--r-r,~,;;u,;;:";;;,,;;;,,;;;,,.. ::-rr
    •.• J--1t-ITl-t-r FORtEl",~ ."V.U~I[ -

    1.1 I-l-f+l-+-+ ~tE -

    1.1 I-tTt-;t---t--t-..,uu " T "'= _Ih -

    \/'N= Vx O-_."'.."'u"'"'_'_.....·"'·"'''II--o-.....,~4~'''··''''"'..,, ~'OA. 1.& +-i £ATl 1" -


    SUMMING NODE
    VOUT "Y x ::: •• ,MAX·~..l~_U..l~-
    TO OTHER
    SUBMUlTIPLEXERS
    C 1.2
    1.3 :::':::o":::",.~': L
    ¥,(~;:~A:~;:':QM_14VTO~'I~1
    +
    (611 MOSSERIES SWITCHES III: 1.0 I-t-HHH-±-±+"**:174::::+:-l
    ; 0.9 I-H--!lK..l\-t-==,=~~
    D.' HH-r\l-\t-::::;.-: ..,Ilooo.__ ._,.tII. . . .
    0.7 I-H-f--\--\+++++-+-t-H
    Rs RON or ROFF
    D.' H".:>.-,;!;M.",
    ••!\1\:t-++-t-t-H:-i--i
    D.' H-'1'''-'t:::.,*''t-++t-t-t-H-l
    D.' H-+-++-+'-.r....+-+-+-t-H-I
    D.J r+-t+~~~
    ClotH-

    11Ib) VOLTAGE DIVIDER EFFECT


    D.' H-+-++++++-+-+-t-H-I
    -14-15-16-17-11-19-20-21-22-23-24-25-2&-21
    VOG VOLTS
    {&cl CHANGE IN RON WITH VGG

    FIGURE 6. MOS Commutator Switching Impedances

    AN28-4
    +1av

    BULK OR SUBSTRATE

    Te,.
    ~
    UMMING
    o S NODE

    i'---~""- "OUT

    'N:~g~&
    t DG
    ~ CGS TO DTHE R
    TURN ON TURN ON SWITCHES

    ~~ -6V

    -1av

    Ual EnUIVALENT CIRCUIT Ubi TRANSIENT NOISE VOLTAGE

    FIGURE 7. Transient Noise Generation

    (another reason why the Figure 2 circuit is faster itance. The noise energy that does get into the
    than the Figure 1 circuit). summing node should be dissipated quickly to
    improve the data channel's recovery time. The
    The transients can be much larger than signal volt· energy is dissipated in the parallel combination of
    ages, so even the relatively small transients of a the summing node resistance and channel-source
    low-V TH MOSFET can saturate the buffer ampli- impedance. The RC time constant of the equiva-
    fier. One of the ways that designers of discrete lent circuit in Figure 8 should be optimized to
    commutators minimized transients at the summing obtain the maximum commutation frequency.
    node was to drive adjacent channels with coinci-
    dent turn-on and turn-off signals. In this way, Fmax; [(Rs/Rnode) Cnodel [(C, + C2 )/2Cnod el
    negative-going transients from the channels turning [V G1 -VGol to 1
    on will partially cancel out positive-going tran-
    sients from the channels turning off. When the This equation relates the time constants, gate and
    output amplifier is an integrator, the amounts of transient voltages and transient recovery tolerance.
    energy pulled through the summing node will be
    VGland V GO are the turn-on and turn-off values
    minimized by, in effect, being averaged out. of V G; other terms are defined in Figure 8.
    Coincident drive, discrete component circuits are
    fairly complex and expensive. Essentially the same
    effect is obtained in the Figure 2 commutator, at
    ., ·0'
    V,o-,"",""'~~-'II\f'v--"-"-"'-OVOUT
    much less cost. The TTL decoder selects channels
    e,
    at such a high rate of speed that a channel is turn-
    ing on while another channel is turning off. Transi-
    tions of the control voltage occur in less time than
    the turn-on and turn-off delays of the MOSFETs.
    So the transients are suppressed in a matter of
    nanoseconds. In fact, when the gate voltage is FIGURE B. RC Network Governing Switching Frequency
    going negative or positive simultaneously, the
    transient is practically invisible at the output. That
    is, the transient actually helps change the output HIGH-FREQUENCY NOISE CONTROL
    signal to the correct level more rapidly.
    In some cases, the analog input signal is AC rather
    You might say that the high commutation rate than DC. That is, it may fluctuate rapidly between
    makes the high commutation rate possible, but it positive and negative values. This can vary the
    is more pertinent to stress that the TTL decoder effective values of VSG , RON and perhaps R OFF ,
    could not directly control a high-VTH commuta- and may also cause spurious charging or discharg-
    tor. Low-impedance drivers are essential for high ing of the MOSF ET capacitance. The condition
    commutation rates, because they quickly source results in output-voltage fluctuations due to the
    and sink transients. In this respect, TTL integrated appearance at the summing node of signal volt-
    circuits make almost ideal drivers. ages from a channel that is supposed to be off-
    a problem known as AC feedthrough or channel-
    In principle, the gate turning on and the gate turn- feedthrough noise. The main cause is charge trans-
    ing off in a multichannel IC commutator are part fer through the gate-source and gate-drain capac-
    of a closed-loop circuit charging the gate capac- itances of the turned-off MOSFETs.

    AN28-5
    Fortunately, most transducer voltage outputs are interface and its voltage levels are shown in Fig-
    below 10kHz in frequency and simply using a ure 10. The author used discrete components, but
    low-impedance gate driver prevents the problem. all 16 resistors in the network could be made as a
    The transients sink into the driver rather than go thick-film printed circuit because the values are
    to the output. A high signal source impedance not large and the tolerances are not critical.
    would make this technique more effective, but
    would also cause larger transients in the turned- TTL logic outputs are positive, while MOSFETs
    on channel, imposing longer recovery times and require negative or positive gate biases to turn on
    slower commutation rates. or off. The necessary voltage changes are made
    with the capacitor in Figure 10.
    There is a simple detour around this impasse, too.
    The dynamic impedance of the gate driver is al- Assume first that the TTL output is at a logic "1".
    lowed to approach a zero-ohm impedance when Rl will pull the decoder output up to V+ = +10V.
    the channel is turned off (Figure 9). Theoretically, With Vss = +2V, there will be +8V across the cap-
    this will prevent any channel feedthrough noise at acitor, VG will be equal to Vss , and that channel
    signal frequencies up to 2 MHz. In practical cir- will be held off.
    cuits, signal frequency is limited by load imped-
    ance, but can usually be pushed above 1 MHz. When the TTL output switches from a logic "1" to
    The driver impedance itself must also be low at a logic "0" level, the decoder output will go from
    high frequencies, of course. V+ = 10V to about 0.4V. Bias on the gate will
    therefore drop from +2V to about -6V, turning
    the channel on. The commutator is controlled,

    ··'"~::TI·
    '.-~ ~
    '
    lfr:1'1 0
    then, by selecting the location of an "0" bit in the
    decoder output and making all other outputs "1".

    R1 is connected to a voltage higher than +6V to


    assure that the TTL output rises rapidly during a
    transition from logic "0" to logic "1". This is
    f9a) LOW·IMPEDANCE GATE DRIVER ":" needed for quick, clean turnoff of a channel (a
    similar technique of interfacing TTL and low-
    VTH MOS digital circuits enables the MOS circuits
    to operate at about twice the normal MOS rate).
    The opposite transition, to the more negative
    level, is normally quite fast and is assisted by the
    ~" ~'l
    - ~ I 1_ z~:I-. ,"+-'-",-O
    excellent current-sinking capability of TTL.

    o--l;'~
    Y+=10VORI2V ~

    z.
    ~~~~~~" crT
    19b) EQUIVALENT CIRCUIT ":"

    v, - -
    FIGURE 9. Zero-Impedance Driver Return lOOOpF RZ
    Prevents AC Feedthrough 2D.
    VSS=VBULK=+2V
    HIGH-SPEED SYSTEMS
    (lib) INTERFACE NETWORK (1 CHANNEL)

    All of these factors have been optimized in the


    OFF
    Figure 2 system. At 20 MHz, its accuracy with
    Vx = ±lV is nearly as good as 99%. Source and
    load impedance are made very low because RON is
    not greater than about 200 ohms per channel. The "DV
    gate change is only 8V (from +2V to -6V), and DECODER I ON
    OUTPUT + D.4V I +DAV
    the high-speed TTL control makes the transients I I
    coincide. 10TOI5NSDELAV-......J ~
    I I

    iv.",,~
    The 8-channel configuration shown can be the
    building block of very large solid-state commu-
    tators. Each 4-channel MOSFET switch is a mono-
    lithic chip (National Semiconductor MM451). The
    TTL channel selector is a decoder (DM7842)
    designed to convert 4-bit binary-coded-decimal
    inputs into decimal-number outputs. Only 8 out-
    puts are needed here, so the decoder's fourth in-
    110b) VOLTAGE TRANSLATION
    l VaUlI{-BV

    put is grounded. FIGURE 10. High·Speed TTL-to-MeS Control Interface

    The TTL outputs are translated to MOS control Care must be taken to select TTL drivers that do
    signals with an interface network consisting of not break down when their outputs are pulled up
    identical passive circuits on each control line. An to +10V or +12V. The DM7842 has a diode in the

    AN28-6
    output stage that protects the output transistor at optimized designs at lower than their maximum
    high voltages, and other devices in the National frequency. Longer recovery times would be per·
    TTL familY have similar output stages. These are mitted.
    equivalent to Series 54 TTL. Suitable TTL control
    logic can be assembled from other ICs, but the Each of the MM454 4-channel commutators con-
    DM7842 is convenient because only one driver tains four MOSFETs like those in the MM451 and,
    chip is needed for every eight channels in the in the same chip, a 2·bit MOS counter and decoder
    commutator system. for channel selection and all·channel blanking
    (Figure 11).
    There is a delay of 10 to 15 nanoseconds between
    a transition in the TTL output and the switching As shown, the system samples the 16 channels
    of a channel on or off, mainly due to the RC time sequentially, much like a rotary driven mechanical
    constant of the RC interface. However, the delay commutator. The MM454 is designed as a building
    occurs equally on all channels and does not affect block for large sequential sampling systems. How-
    the commutation rate or significantly reduce the ever, any particular channel could be selected
    50 ns sampling time permitted by a 20 MHz rate. with external output-gating logic. If random chan·
    Commutator output can be kept synchronized to nel selection were the normal operating mode, the
    any following data processing subsystem by put· MM451 and external selection logic can be used.
    ting a comparable delay in the line from the sys· Two ranks of commutators, similar to Figure 1,
    tem clock to the processor. simplify the control logic. For example, one gate
    driver would turn on channels A1, Bl, Cl and Dl,
    The MM451 chip is also available with a DTL and a second driver would select channel A 1 by
    monolithic driver in a f1atpack. This hybrid IC, turning on channel E1-which takes a lot less
    the MH453, does not require an external inter· control circuitry than selecting lout of 16
    face network. It will operate at frequencies to channels directly and requires only one more
    500 kHz and switch analog signals of ± 1OV under monolithic commutator.
    direct control of TTL or DTL logic. The four
    MOSFETs of the MM451 are connected in a dual Either way, a very critical system design require-
    differential configuration, useful for combining ment is to guarantee that only the selected channel
    and comparing signal voltages. conducts during the sampling interval. The single
    3-input NOR gate in Figure 1 accomplishes that.
    ALL-MOS COMMUTATORS Commutator C is used as the master element. It
    divides down the 1 MHz clock signal through a 4: 1
    Commutators built entirely of MOS devices need countdown circuit, which is provided in the
    not be limited to low-frequency operation, despite MM454 to facilitate submultiplexing. Commutator
    their 'larger voltage swings and transients. The E's four channels therefore sequence at a 250 kHz
    system in Figure 2 has better than 99% accuracy at rate. Meanwhile, the four channels in commutators
    1 MHz with Vx = ±10V when the previously A, B, C and D are each sequencing at 1 MHz. The
    discussed characteristics of 10w·VTH devices in this analog sequences through A 1, A2, A3 and A4 in
    signal range are optimized. order when E1 is on, B1 through B4 when E2 is
    on, and so forth.
    Similar systems, optimized for smaller signal-
    voltage ranges, have not been bu i1t by the author The 4: 1 count-down output of commutator E
    but it is reasonable to expect higher frequencies or (1/16 MHz) is fed back through the NOR gate to
    accuracies in such systems. Accuracy, of course, the reset inputs of commutators A, Band D. The
    wou Id be further improved by operating the reset every cycle keeps them in step with commu-

    ANALOG
    OUTPUT

    CLOCK OUTPUT
    INPUT 4:1
    COUNTDOWN

    RESfT--~---------'

    FIGURE 11. MM454 Four·Channel MOS Submultiplexer

    AN28-7
    tator C and therefore commutator E. The NOR oped are similar in principle to commutators,
    gate's output also can be used to maintain except that V x is digital data and scores of
    synchronization of the commutator with other MOSFET switching stages are used in each MOS
    signal processing systems. chip. One data·storage system built by the author
    has achieved data transfer rates up to 16 MHz, by
    ANALOG/DIGITAL SYSTEMS multiplexing high·speed bipolar data into parallel
    MOS storage circuits.
    Techniques developed, and being developed, to
    directly couple bipolar and large-scale MOS pigital With all three classes of bipolar/MOS interfaces-
    circuits also depend heavily upon the lowering of analog/digital, logic/logic and logic/analog-now
    threshold voltages. A report compiling and detail· available, system designs can exploit more fully
    ing coupling techniques is in preparation. In gen- the many speed/cost tradeoffs offered by hybrid
    eral, the ability of the MOS digital circuit to ac· bipolar/MOS systems. Bipolar control logic and
    cept small, positive transitions in signal voltage, MOS large·scale storage is an extremely efficient,
    and to operate with smaller differentials in bias minimum cost combination suitable for medium-
    and gate voltages are the critical requirements for to-high·speed systems.
    direct coupling.
    In other words, low-threshold processing has en-
    Directly coupling MOS digital outputs to bipolar abled MOS to move out of the low-frequency
    logic also enhances operating speed, again because range and into the ranges where most modern
    impedances are lowered. Some of the high·speed analog/digital systems operate.
    TTL/MOS hybrid systems that have been devel-

    AN2S-S
    »z
    I
    December 1969 N
    CD

    n
    o
    '"tJ
    IC OP AMP BEATS FETs
    ON INPUT CURRENT ):;>
    s:"tI
    III
    m
    »
    -I
    en
    ABSTRACT ."
    A monolithic operational amplifier having input transistors match much better than FETs with m
    error currents in the order of 100 pA over a -55"C typical offset voltages of 1 m V and drifts of -I
    III
    to 125°C temperature range is described. Instead 3/lVfc.
    of FETs, the circuit uses bipolar transistors with o
    current gains of 5000 so that offset voltage and ,... z
    drift are not degraded. A power consumption of F=F LM109
    1 mW at low voltage is also featured. 5 Z
    5 10-8 "tI
    A number of novel circuits that make use of the
    a: c:
    ~ -I
    low current characteristics of the amplifier are .... 10-9 I-- j - - LM101A
    given. Further, special design techniques required
    ~
    n
    to take advantage of these low currents are ex· '"~ , FEY = c:
    10" ::x:I
    plored. Component selection and the treatment of 1--1.
    printed circuit boards is also covered.
    ~

    ,
    r== 1= LM!08 ::x:I
    m
    10" Z
    INTRODUCTION ~ ~~ 0 ~ ro ~ 100 rn -I
    TEMPERATURE ("CI
    A year ago, one of the loudest complaints heard
    about IC op amps was that their input currents FIGURE 1. Comparing IC Op Amps With FET-Input
    were too high. This is no longer the case. Today Amplifier
    ICs can provide the ultimate in performance for
    many applications-even surpassing FET ampli-
    Figure 1 compares the typical input offset currents
    fiers.
    of IC op amps and FET amplifiers. Although FETs
    give superior performance at room temperature,
    F ET input stages have long been considered the
    their advantage is rapidly lost as temperature
    best way to get low input currents in an op amp.
    increases. Still, they are clearly better than early
    Low-picoamp input currents can in fact be obtain-
    IC amplifiers like the LM709. 3 Improved devices,
    ed at room temperature. However, this current,
    like the LM101A" equal FET performance over a
    which is the leakage current of the gate junction
    doubles every 10°C, so performance is severel~
    -55°C to 125°C temperature range. Yet they use
    standard transistors in the input stage. SL<per gain
    degraded at high temperatures. Another disad-
    transistors can provide more than an order of
    vantage is that it is difficult to match FETs
    magnitude improvement over the LM101A. The
    closely.! Unless expensive selection and trimming
    LMol0B use~ these to equal FET performance over
    techniques are used, typical offset voltages of
    a 0 C to 70 C temperature range.
    50 mV and drifts of 50 /lV fc must be tolerated.
    In applications involving 125°C operation, the
    Super gain transistors2 are now challenging FETs.
    LM lOB is about two orders of magnitude better
    These devices are standard bipolar transistors
    than FETs. In fact, unless special precautions are
    which have been diffused for extremely high
    taken, overall circuit performance is often limited
    current gains. Typically, current gains of 5000 can
    by leakages in capacitors, diodes, analog switches
    be obtained at 1 /lA collector currents. This makes
    or printed circuit boards, rather than by the op
    it possible to get input currents which are com·
    amp itself.
    petitive with FETs. It is also possible to operate
    these transistors at zero collector base voltage,
    EFFECTS OF ERROR CURRENT
    eliminating the leakage currents that plague the
    FET. Hence they can provide lower error currents In an operational amplifier, the input current
    at elevated temperatures. As a bonus, super gain produces a voltage drop across the source resis·

    Reprinted from EEE. December 1969.

    AN29-1
    tance, causing a dc error. This effect can be mini· they are selected and trimmed. Even though their
    mized by operating the amplifier with equal drift may be well controlled (5/lV fe) over a
    resistances on the two inputs. 5 The error is then limited temperature range, trimmed ampl ifiers
    proportional to the difference in the two input generally exhibit a much higher drift over a -55°e
    currents, or the offset current. Since the current to 125°e temperature range. At any rate, their
    gains of monolithic transistors tend to match well, average drift rate would, at best, be like that of the
    the offset current is typically a factor of ten less LMl 01A where 125°e operation is involved.
    than the input currents.
    Applications that require low error currents
    ;;- 100 include amplifiers for photodiodes or capacitive
    .§ transducers, as these usually operate at megohm
    w
    impedance levels. Sample·and·hold circuits, timers,
    "'"co~ integrators and analog memories also benefit from
    10
    ...> low error currents. For example, with the LM709,
    E
    co
    worst case drift rate.s for these kinds of circuits is
    in the order of 1.5V/sec. The LM108 improves this
    ~ 1.0 to 3 mV /sec.-worst case over a -55°e to 125°e
    :!!
    ... ·temperature range. Low input currents are also
    ~ helpful in oscillators and active filters to get low
    ;; frequency operation with reasonable capacitor
    0.1
    ~ lk 10k lOOk 1M 10M 100M lG values. The LM108 can be used at a frequency of
    INPUT RESISTANCE In) 1 Hz with capacitors no larger than O.01/lF. In
    logarithmic amplifiers, the dynamic range can be
    extended by nearly 60 dB by going from the
    FIGURE 2. Illustrating The Effect Of Source Resistance
    On Typical Input Error Voltage LM709 to the LM108. In other applications,
    having low error currents often permits an entirely
    different design approach which can greatly sim·
    Naturally, error current has the greatest effect in
    plify circuitry.
    high impedance circuitry. Figure 2 illustrates this
    point. The offset voltage of the LM709 is degraded
    THE LM108
    significantly with source resistances greater than
    10 kg. With the LM 101 A this is extended to Figure 4 shows a simplified schematic of the
    source resistances high as 500 kg. The LM108, on LM108. Two kinds of NPN transistors are used on
    the other hand, works well with source resistances the Ie chip: super gain (primary) transistors which
    above 10 Mg. have a current gain of 5000 with a breakdown
    voltage of 4 V and conventional (secondary) tran·
    High source resistances have an even greater effect sistors which have a current gain of 200 with an
    on the drift of an amplifier, as shown in Figure 3. 80V breakdown. These are differentiated on the
    The performance of the LM709 is worsened with schematic by drawing the secondaries with a wider
    sources greater than 3 kg. The LM101A holds out base.
    to 100 kg sources, while the LM108 still works
    well at 3 Mg. Primary transistors (0 1 and O2 ) are used for the
    input stage; and they are operated in a cascode
    connection with 0 5 and 0 6 • The bases of as and
    1000~m 0 6 are bootstrapped to the emitters of 0 , and O2
    through 0 3 and 0 4 , so that the input transistors
    are operated at zero collector·base voltage. Hence,
    e
    >
    -'l
    100 circuit performance is not impaired by the low

    ;
    t 10
    breakdown of the primaries, as the secondary tran·
    sistors stand off the common mode voltage. This
    configuration also improves the common mode
    iii rejection since the input transistors do not see
    variations in the common mode voltage. Further,
    because there is no voltage across their collector·
    lk 10k lOOk 1M 10M 100M lG base junctions, leakage currents in the input tran·
    INPUT RESISTANCE In) sistors are effectively eliminated.

    The second stage is a differential amplifier using


    FIGURE 3. Oegradation Of Typical Drift Characteristics high gain lateral PNPs (09 and 0 , 0 ).6 These de·
    With High Source Resistances vices have current gains of 150 and a breakdown
    voltage of 80V. R 1 and R2 are the collector load
    It is difficult to include FET amplifiers in Figure 3 resistors for the input stage. 0 7 and 0 8 are diode
    because their drift is initially 50 /lV fe, unless connected laterals which compensate for the

    AN29-2
    COMPENSATION
    r-----~------~--~------------_._+--~-----v·

    OUTPUT

    INPUTS 01

    +-4~~+-----+-----~

    L---~__---------------t~-----t----e-----v-

    FIGURE 4. Simplified Schematic Of The LM108

    emitter-base voltage of the second stage so that its make high-impedance circuits fast; and low power
    operating current is set at twice that of the input circuits are very resistant to being made fast. In
    stage by R4 - other respects, it was desirable to make the LM 108
    as much like the LM 101 A as possible.
    The second stage uses an active collector load
    (0, 5 and 0,6) to obtain high gain- It drives a 2.0
    complementary ciass-B output stage which gives a
    substantial load driving capability_ The dead zone
    of the output stage is eliminated by biasing it on <
    '.5
    1.0 ...... " r- -.!~
    -
    oS
    the verge of conduction with 0" and 0, 2 _ 0- 0.5
    15
    =
    Two methods of frequency compensation are ~
    0.15
    available for the amplifier_ In one a 30 pF capaci- f
    !i 0.'0
    tor is connected from the input to the output of
    the second stage (between the compensation 0.05
    i"- ..... OFFSET

    terminals). This method is pin-compatible with the o


    LM,08
    I
    LM10l or LM101A It can also be compensated -55 -35 -15 5 25 45 65 85 105 125
    by connecting a 100 pF capacitor from the output TEMPERATURE ('CI
    of the second stage to ground. This technique has
    the advantage of improving the high frequency
    FIGURE 5. Input Currents
    power supply rejection by a factor of ten.

    A complete schematic of the LM 108 is given in the Figure 5 shows the input current characteristics of
    Appendix along with a description of the circuit. the LM 108 over a _55 0 C to 1250 C temperature
    This includes such essential features as overload range. Not only are the input currents low, but
    protection for the inputs and output. also they do not change radically over tempera-
    ture. Hence, the device lends itself to relatively
    PERFORMANCE simple temperature compensation schemes, that
    The primary design objective for the LM 108 was will be described later.
    to obtain very low input currents without sacrific-
    ing offset voltage or drift. A secondary objective There has been considerable discussion about using
    was to reduce the power consumption. Speed was Darlington input stages rather than super gain tran-
    of little concern, as long as it was comparable with sistors to obtain low input currents. 6,7 It is appro-
    the LM709. This is logical as it is quite difficult to priate to make a few comments about that here.

    AN 29-3
    Darlington inputs can give about the same input volt of the supplies, which is especially important
    bias currents as super gain transistors-at room when operating at low voltages. The output falls
    temperature. However, the bias current varies as off rapidly as the current increases above a certain
    the square of the transistor current gain. At low level and the short circuit protection goes into
    temperatures, super gain devices have a decided effect. The useful output drive is limited to about
    advantage. Additionally, the offset current of ±2 mAo It could have been increased by the addi-
    super gain transistors is considerably lower than tion of Darlington transistors on the output, but
    Darlingtons, when measured as a percentage of this would have restricted the voltage swing at low
    bias current. Further, the offset voltage and offset supply voltages. The amplifier, incidentally, works
    voltage drift of Darlington transistors is both with common mode signals to within a volt of the
    higher and more unpredictable. supplies so it can be used with supply voltages as
    low as ±2V.
    Experience seems to tell the real truth about Dar-
    lingtons. Quite a few op amps with Darlington 120
    180
    ~~ -j- CI" 3 P~,ff
    input stages have been introduced. However, none 100 C, • 3 pF
    have become industry standards. The reason is that
    they are more sensitive to variations in the manu-
    a;
    ~
    aD
    " " " ~, ~ Cs ' 100 pF---' 135 :l!
    ~
    "..
    z
    facturing process. Therefore, satisfactory perform- 60
    ance specifications can only be obtained by sacri- w 90 ~
    ficing the manufacturing yield.
    ...
    c
    !::;
    40
    " " -C;'30pF

    I
    20 GAIN
    -t-
    PH~SE " " 45

    Cs:100:~
    ~
    600
    o
    500 1--+-+-+--+-+-1 -20
    LM1~B-+- C-C,·30.F 0

    TA ", _55°C
    ~
    1 10 100 lk 10k lOOk 1M 10M
    400
    FREQUENCY (Hzl
    I-
    Z
    II! 300
    V TA - 2S'C
    !!l ~~ TA - 125°C
    FIGURE 8. Open Loop Frequency Response
    ~ 200

    ~ 100
    ~
    The open loop frequency response, plotted in
    LM10B Figure 8, indicates that the frequency response is
    0 about the same as that of the LM709 or the
    5 10 15 20
    LM101A. Curves are given for the two compensa-
    SUPPL Y VOLTAGE (tVI

    FIGURE 6. Supply Current


    .,
    -v,.---,VV\~~~..,.".....- ,
    .z
    The supply current of the LM108 is plotted as a

    L~L.'08
    function of supply voltage in Figure 6. The operat-
    ing current is about an order of magnitude lower
    than devices like the LM709. Furthermore, it does
    not vary radically with supply voltage which RJ 3
    . -+ B
    ,-vo",
    means that the device performance is maintained
    at low voltages and power consumption is held
    1 CI~:~ :~2
    Co =30pF
    down at high voltages.
    "
    --
    a SlandlrdCompellSlltlonCnl:Ult
    15
    Vs = ±15V

    '-
    \ .,
    .
    ! 10 .z

    i5
    -VIN

    ~~L.'08·. . .
    LM '0a
    1

    .~ 5
    /" ~
    TA -1Z5°C
    TA :
    TA
    2S~C
    ~ _55°C
    V-
    V +VIN
    • + •
    0"'

    0 C,
    0 2 4 6 a *,'00"
    OUTPUT CURRENT (...AI
    b Alte,nateComprnSilll;mC.,cult
    FIGURE 7. Output Swing

    The output drive capability of the circuit is illus-


    trated in Figure 7. The output swings to within a FIGURE 9. Compensation Circuits

    AN29-4
    tion circuits shown in Figure 9. The standard 16
    compensation is identical to that of the LM10l or I 11111 To\" ZSOC
    Vs= !15V
    LM101A. The alternate compensation scheme 12
    \ 1Tr mTI
    gives much better rejection of high frequency ~ C,:3 pF
    power supply noise, as will be shown later. '"z
    iii 8
    p30pF

    ~
    With unity gain compensation, both methods give
    a 75-degree stability margin. However, the shunt 4
    compensation has a 300 kHz small signal band-
    width as opposed to 1 MHz for the other scheme. LMID8
    Because the compensation capacitor is not includ- a
    ed on the IC chip, it can be tailored to fit the Ik 10k lOOk 1M

    application. When the amplifier is used only at low FREQUENCY IHd


    frequencies, the compensation capacitor can be
    increased to give a greater stability margin. This FIGURE 10. Large Signal Frequency Response
    makes the circuit less sensitive to capacitive load-
    ing, stray capacitances or improper supply bypass-
    ing. Overcompensation also reduces the high fre- and input stages determines the effective output
    quency noise output of the amplifier. resistance, and this cannot be accounted for by
    conventional design theories. Semiconductor man-
    With closed-loop gains greater than' one, the high ufacturers take care of this by specifying the gain
    frequency performance can be optimized by under full load conditions, wh ich combines output
    making the compensation capacitor smaller. If resistance with gain as far as it affects overall cir-
    unity-gain compensation is used for an amplifier cuit performance. This avoids the fictitious pro-
    with a gain of ten, the gain error will exceed blem that can be created by an amplifier with
    l-percent at frequencies above 400 Hz. This can be infinite gain, which is good, that will cause the
    extended to 4 kHz by reducing the compensation open loop output resistance to appear infinite,
    capacitor to 3 pF. The formula for determining which is bad, although none of this affects overall
    the minimum capacitor value is given in Figure 9a. performance significantly.
    It should be noted that the capacitor value does
    not really depend on the closed-loop gain. Instead,
    it depends on the high frequency attenuation in
    the feedback networks and, therefore, the values
    of R 1 and R2 • When it is desirable to optimize
    performance at high frequencies, the standard
    compensation should be used. With small capacitor
    values, the stability margin obtained with shunt
    compensation is inadequate for conservative de-
    signs.

    The frequency response of an operational ampli-


    fier is considerably different for large output sig-
    nals than it is for small signals. This is indicated in
    Figure 10. With unity-gain compensation, the
    small signal bandwidth of the LM108 is 1 MHz.
    FREQUENCY (Hz)
    Yet full output swing cannot be obtained above
    2 kHz. This corresponds to a slew rate of 0.3V /I1S.
    Both the full-output bandwidth and the slew rate FIGURE 11. Closed Loop Output Impedance
    can be increased by using smaller compensation
    capacitors, as is indicated in the figure. However, The closed loop output impedance is, nonetheless,
    this is only applicable for higher closed loop gains. important in some applications. This is plotted for
    The results plotted in Figure 10 are for standard several operating conditions in Figure 11. It can be
    compensations. With unity gain compensation, the seen that the output impedance rises to about
    same curves are obtained for the shunt compensa- 500n at high frequencies. The increase occurs
    tion scheme. because the compensation capacitor rolls off the
    open loop gain. The output resistance can be re-
    Classical op amp theory establishes output resis- duced at the intermediate frequencies, for closed
    tance as an important design parameter. This is not loop gains greater than one, by making the capaci-
    true for IC op amps: The output resistance of tor smaller. This is made apparent in the figure by
    most devices is low enough that it can be ignored, comparing the output rEjsistance with and without
    because they use class-B output stages. At low fre- frequency compensation for a closed loop gain
    quencies, thermal feedback between the output of 1000.

    AN29-5
    The output resistance also tends to increase at low The overall performance of the LM108 is
    frequencies. Thermal feedback is responsible for summarized in Table ,'. It is apparent from the
    this phenomenon. The data for Figure 11 was table and the previous discussion that the de-
    taken under large-signal conditions with ±15V vice is ideally suited for applications that re-
    supplies, the output at zero and a ±1 mA current quire low input currents or reduced power con-
    swing. Hence, the thermal feedback is accentuated sumption. The speed of the amplifier is not
    more than would be the case for most applica- spectacular, but this is not usually a problem in
    tions. high-impedance circuitry. Further, the reduced
    high frequency performance makes the amplifier
    In an op amp, it is desirable that performance easier to use in that less attention need be paid
    be unaffected by variations in supply voltage. to capacitive loading, stray capacitances and
    IC amplifiers are generally better than discretes supply bypassing.
    in this respect because it is necessary for one
    single design to cover a wide range of uses. The APPLICATIONS
    LM108 has a power supply rejection which is Because of its low input current, the LM 108
    typically in excess of 100 dB, and it will oper- opens up many new design possibilities. How-
    ate with supply voltages from ±2V to ±20V. ever, extra care must be taken in component
    Therefore, well-regulated supplies are unneces- selection and the assembly of printed circuit
    sary, for most applications, because a 20-per- boards to take full advantage of its perform-
    cent variation has little effect on performance. ance. Further, unusual design techniques must
    often be apPlied to get around the limitations
    of some components.
    120
    SAMPLE AND HOLD CIRCUITS
    100
    ;;; The holding accuracy of a sample and hold is
    :!! 80
    z
    co directly related to the error currents in the
    5 10 components used. Therefore, it is a good circuit
    ..;5
    ~
    4D
    to start off. with in explaining the problems in-

    ~ 20
    SAMPLE _ _ _~,""""-.

    -20
    100 lk 1Il10 lOOk 1M 10M OUTPUT
    FREQUENCY (Hz)
    INPUT

    FIGURE 12. Power SupplV Rejection cz


    30pF

    The story is different for high-frequency noise


    FIGURE 13. Sample And Hold Circuit
    on the supplies, as is evident from Figure 12.
    Above 1 MHz, practically all the noise is fed
    through to the output. The figure also demon- volved. Figure 13 shows one configuration for a
    strates that shunt compensation is about ten sample and hold. During the sample interval,
    times better at rejecting high frequency noise 0) is turned on, charging the hold capacitor,
    than is standard compensation. This difference C), up to the value of the input signal. When
    is even more pronounced with larger capacitor 0) is turned off, C) retains this voltage. The
    values. The shunt compensation has the added output is obtained from an op amp that buffers
    advantage that it makes the circuit virtually the capacitor so that it is not discharged by
    unaffected by the lack of supply bypassing. any loading_ In the holding mode, an error is
    generated as the capacitor looses charge to
    Power supply rejection is defined as the ratio supply circuit leakages. The accumulation rate
    of the change in offset voltage to the change in for error is given by
    the supply voltage producing it. Using this defi-
    nition, the rejection at low frequencies is un- dV Ie
    affected by the closed loop gain. However, at dt C;-'
    high frequencies, the opposite is true. The high
    frequency rejection is increased by the closed where dV /dt is the time rate of change in out-
    loop gain. Hence, an amplifier with a gain of put voltage and Ie is the sum of the input
    ten will have an order of magnitude better re- current to the op amp, the leakage current of
    jection than that shown in Figure 12 in the the holding capacitor, board leakages and the
    Vicinity of 100 kHz to 1 MHz. "off" current of the F ET switch.

    'See Appendix. page 19.

    AN29-6
    Wh en high-temperature operation is involved, high temperatures; this is not the case with
    the FET leakage can limit circuit performance. junction FETs. If the MOS transistors have pro-
    This can be minimized by using a junction tective diodes on the gates, special arrangements
    FET, as indicated, because commercial junction must be made to drive O2 so the diode does
    FETs have lower leakage than their MOS coun- not become forward biased.
    terparts. However, at 125°C even junction de-
    vices are a problem. Mechanical switches, such In selecting the hold capacitor, low leakage is
    as reed relays, are quite satisfactory from the not the only requirement. The capacitor must
    standpoint of leakage. However, they are often also be free of dielectric polarization phenom-
    undesirable because they are sensitive to vibra- ena. s This rules out such types as paper, mylar,
    tion, they are too slow or they require exces- electrolytic, tantalum or high-K ceramic. For
    sive drive power. If this is the case, the circuit small capacitor values, glass or silvered-mica
    in Figure 14 can be used to eliminate the FET capacitors are recommended. 'For the larger
    leakage. values, ones with teflon, polyethylene or poly-
    carbonate dielectrics should be used.

    The low input current of the LM10B gives a


    INPUT drift rate, in hold, of only 3 mV Isec when a
    1 J-LF hold capacitor is used. And this number is
    worst case over the military temperature range.
    OUTPUT Even if this kind of performance is not needed,
    it may still be beneficial to use the LM 1OB to
    reduce the size of the hold capacitor. High
    quality capacitors in the larger sizes are bulky
    and expensive. Further, the switches must have
    tTIHon,palYllllyllolor polycllbonlte a low "on" resistance and be driven from a low
    'lelltCblCcaplCll1If
    impedance source to charge large capacitors in a
    WorstClMdnh
    lesslh.n3 mV!sec short period of time.

    If the sample interval is less than about 100 J-LS,


    FIGURE 14. Sample And Hold That Eliminate. Leakage the LM 1OB may not be fast enough to work
    In FET Switches properly. If this is the case, it is advisable to
    substitute the LM102A,9 which is a voltage fol-
    When using P-channel MOS switches; the sub- lower designed for both low input current and
    strate must be connected to a voltage which is high speed. It has a 30V/J-Ls slew rate and will
    always more positive than the input signal. The operate with sample intervals as short as 1 J-Ls.
    sou rce-to-substrate junction becomes forward
    biased if this is not done. The troublesome When the hold capacitor is larger than 0.05 J-LF,
    leakage current of a MOS device occurs across an isolation resistor should be included between
    the substrate-to-drain junction. In Figure 14, the capacitor and the input of the amplifier
    this current is routed to the output of the buf- (R 2 in Figure 14). This resistor insures that the
    fer amplifier through R I so that it does not IC will not be damaged by shorting the output
    contribute to the error current. or abruptly shutting down the supplies when
    the capacitor is charged. This precaution is not
    The main sample switch is 0 1 , while O2 iso- peculiar to the LM 1OB and should be observed
    lates the hold capacitor from the leakage of on any IC op amp.
    0 1 , When the sample pulse is applied, both
    FETs turn on charging C I to the input voltage.
    Removing the pulse shuts off both FETs, and INTEGRATORS
    the oui:put leakage of 0 1 goes through R I to Integrators are a lot like sample-and-hold cir-
    the output. The voltage drop across R I is less cuits and have essentially the same design prob-
    than 10 mV, so the substrate of O2 can be lems. In an integrator, a capacitor is used as a
    bootstrapped to the output of the LM10B. storage element; and the error accumulation
    Therefore, the voltage across the substrate-drain rate is again proportional to the input current
    junction is equal to the offset voltage of the of the op amp.
    amplifier. At this low voltage, the leakage of
    the F ET is reduced by about two orders of Figure 15 shows a circuit that can compensate
    magnitude. for the bias current of the ampl ifier. A current
    is fed into the summing node through R I to
    It is necessary to use MOS switches when boot- supply the bias current. The potentiometer, R2 ,
    strapping the leakages in this fashion. The gate is adjusted so that this current exactly equals
    leakage of a MOS device is still negligible at the bias current, reducing the drift rate to zero.

    AN29-7
    .,
    15DK
    turns on Q I and Q2, shorting the integrating ca-
    r--t-"'VI.IV-v· pacitor. When the switches turn off, the leakage
    current of Q2 is absorbed by R2 while Q I isolates
    the output of Q2 from the summing node. Q I has
    practically no voltage across its junctions because

    .
    INPUT-JV\"""....- - - - - ' - - - - ,
    ,
    the substrate is grounded; hence, leakage currents
    are negligible .

    OUTPUT The additional circuitry shown in Figure 16 makes


    the error accumulation rate proportional. to the
    C1 offset current, rather than the bias current. Hence,
    ,*'00 PF the drift is reduced by roughly a factor of 10.
    During the integration interval, the bias current of
    the non-inverting input accumulates an error
    FIGURE 15. Integrator With Bia. Current Compensation across R4 and C2 just as the bias current on the
    inverting input does across R I and C I . Therefore,
    The diode is used for two reasons. First, it acts if R4 is matched with R I and C2 is matched with
    as a regulator, making the compensation rela- CI (within about 5 percent) the output will drift
    tively insensitive to variations in supply voltage. at a rate proportional to the difference in these
    Secondly, the temperature drift of diode voltage currents. At the end of the integration interval, Q3
    is approximately the same as the temperature removes the compensating error accumulated on
    drift of bias cu rrent. Therefore, the compensation C2 'as the circuit is reset.
    is more effective if the temperatu re changes.
    Over a O°C to 70°C temperature range, the com- In a pplications involving large temperature
    pensation wi II give a factor of ten reduction in changes, the circuit in Figure 16 gives better re-
    input current. Even better results are achieved if sults than the compensation scheme in
    the temperature change is less. Figure 15-especially under worst case conditions.
    Over a -55°C to 1/25°C temperature range, the
    Normally, it is necessary to reset an integrator to worst case drift is reduced from 3 mV/sec to
    establish the initial conditions for integration. Re- 0.5 mV/sec when a 1/LF integrating capacitor is
    setting to zero is readily accomplished by shorting used. If this reduction in drift is not needed, the
    the integrating capacitor with a suitable switch. circuit can be simplified by eliminating R4 , C2 and
    However, as with the sample and hold circuits, Q3 and returning the non-inverting input of the
    semiconductor switches can cause problems be- amplifier directly to ground.
    cause of high-temperature leakage.
    In fabricating low drift integrators, it is again nec-
    A connection that gets rid of switch leakages is essary to use high quality components and mini-
    shown in Figure 16. A negative-going reset pulse mize leakage currents in the wiring. lhe comments
    made on capacitors in connection with the
    sample-and-hold circuits also apply here. As an
    v'
    additional precaution, a resistor should be used to
    isolate the inverting input from the integrating
    capacitor if it is larger than 0.05/LF. This resistor
    ' - - t -....-RESET prevents damage that might occur when the sup-
    INPUT-""'''-+--i plies are abruptly shut down while the integrating
    capacitor is charged.
    "
    10K

    Some integrator applications require both speed


    >.-i-0UTPUT and low error current. The output amplifiers for
    photomultiplier tubes or solid-state radiation de-
    tectors are examples of this. Although the LM108
    is relatively slow, there is a way to speed it up
    when it is used as an inverting amplifier. This is
    sh?wn in Figure 17.

    The circuit is arranged so that the high-frequency


    gain characteristics are determined by A2 , while
    Al determines the dc and low-frequency charac-
    -Ol.ndmshDllldnOlh..,. teristics. The non-inverting input of AI is connect-
    inttmll ...protectiondIOdls.
    ed to the summing node through R I' AI is oper-
    ated as an integrator, going through unity gain at
    FIGURE 16. Low Drift Integrator With Reset 500 Hz. Its output drives the non-inverting input

    AN29-8
    R5
    01 2K

    D2

    .,
    INPUT-WV-V----------¢-----1

    ., ••
    5K cs
    10pF
    lS0K
    C1
    DOOZjJF
    Cl
    D002JJF

    .2
    1M
    >:...-....
    _OUTPUT

    .J
    1M

    FIGURE 17. Fast Integrator

    of A 2 . The inverting input of A2 is also connected thermal feedback is virtually eliminated because
    to the summing node through C3 • C3 and R 3 are the LM108 does not see load variations. Lastly,
    chosen to roll off below 750 Hz. Hence, at fre· the open loop gain is nearly infinite at low fre·
    quencies above 750 Hz, the feedback path is di· quencies as it is the product of the gains of the
    rectly around A2 , with A, contributing little. two amplifiers.
    Below 500 Hz, however, the direct feedback path
    to A2 rolls off; and the gain of A, is added to that
    of A2 • SINE WAVE OSCILLATOR
    Although it is comparatively easy to build an oscil·
    The high frequency amplifier, A2 , is an LM101A lator that approximates a sine wave, making one
    connected with feed·forward compensation.' 0 It that delivers a high-purity sinusoid with a stable
    has a 10 MHz equivalent small·signal bandwidth, a frequency and amplitude is another story. Most
    1OV Ills slew rate and a 250 kHz large·signal band· satisfactory designs are relatively complicated and
    width, so these are the high·frequency characteri· require individual trimming and temperature com-
    stics of the complete amplifier. The bias current of pensation to make them work. In addition, they
    A2 is isolated from the summing node by C3 . generally take a long time to stabilize to the final
    Hence, it does not contribute to the dc drift of the output amplitude.
    integrator. The inverting input of A, is the only dc
    connection to the summing junction. Therefore, A unique solution to most of these problems is
    the error current of the composite amplifier is shown in Figure 18. A, is connected as a two·pole
    equal to the bias current of A,. low-pass active filter, and A2 is connected as an
    I integrator. Since the ultimate phase lag introduced
    If A2 is allowed to saturate, A, will then start by the amplifiers is 270 degrees, the circuit can be
    towards saturation. If the output of A, gets far off made to oscillate if the loop gain is high enough at
    zero, recovery from saturation will be slowed dras· the frequency where the lag is 180 degrees. The
    tically. This can be prevented by putting zener gain is actually made somewhat higher than is re-
    clamp diodes across the integrating capacitor. A quired for oscillation to insure starting. Therefore,
    suitable clamping arrangement is shown in the amplitude builds up until it is limited by some
    Figure 17. 0, and O2 are included in the clamp nonlinearity in the system.
    circuit along with Rs to keep the leakage currents
    of the zeners from introducing errors. Amplitude stabilization is accomplished with zener
    clamp diodes, 0, and O2 . This does introduce dis-
    In addition to increasing speed, this circuit has tortion, but it is reduced by the subsequent low
    other advantages. For one, it has the increased out· pass filters. If 0, and O2 have equal breakdown
    put drive capability of the LM101A. Further, voltages, the resulting symmetrical clipping will

    AN29-9
    COSINE
    OUTPUT

    C5
    lO,F

    fo "IHz
    ..
    R2
    22M
    01
    fi.lV
    .
    50K

    02
    fi.lV

    FIGURE 18. Sine Wave Oscillator

    virtually eliminate the even-order harmonics. The but uses capacitors in the order of 0.01 J.lF. This
    dominant harmonic is then the third, and this is makes it much easier to find temperature-stable
    about 40 dB down at the output of AI and about precision capacitors. However, some judgment
    50 dB down on the output of A2 . This means that must be used as large value resistors with low
    the total harmonic distortion on the two outputs temperature coefficients are not exactly easy to
    is 1 percent and 0.3 percent, respectively. come by.*

    The frequency of oscillation and the oscillation The LM108s are useful in this circuit for output
    threshold are determined by R I , R2 , R3 , C I , C2 frequencies up to 1 k Hz. Beyond that, better per-
    and C3 • Therefore precision components with low formance can be realized by substituting an
    temperature coefficients should be used. If R 3 is LM102A for Al and an LM101A with feed-
    made lower than shown, the circuit will accept forward compensation for A2 . The improved
    looser component tolerances before dropping out high-frequency response of these devices extends
    of oscillation. The start up will also be quicker. the operating frequency out to 100 kHz.
    However, the price paid is that distortion is in-
    creased. The value of R4 is not critical, but it CAPACITANCE MULTIPLIER
    should be made much smaller than R2 so that the Large capacitor values can be eliminated from
    effective resistance at R2 does not drop when the most systems just by raising the impedance levels,
    clamp diodes conduct. if suitable op amps are available. However, some-
    times it is not possible because the impedance
    The output amplitude is determined by the break- levels are already fixed by some element of the
    down voltages of DI and D2 . Therefore, the clamp system like a low impedance transducer. If this is
    level should be temperature compensated for the case, a capacitance multiplier can be used to
    stable operation. Diode-connected (collector short- increase the effective capacitance of a small capaci-
    ed to base) NPN transistors with an emitter-base tor and couple it into a low impedance system.
    breakdown of about 6.3V work well, as the posi-
    tive temperature coefficient of the diode in reverse Previously, IC op amps could not be used effec-
    breakdown nearly cancels the negative tempera· tively as capacitance multipliers because the equiv-
    ture coefficient of the forward·biased diode. Add· alent leakages generated due to offset current were
    ed advantages of using transistors are that they significantly greater than the leakages of large
    have less shunt capacitance and sharper break· tantalum capacitors. With the LM108, this has
    downs than conventional zeners. changed. The circuit shown in Figure 19 generates

    The LM108 is particularly useful in this circuit at *Large-value resistors are available from Victoreen Instru-
    low frequencies, since it permits the use of small ment, Cleveland, Ohio and Pyrofilm Resistor Co.,
    capacitors. The circuit shown oscillates at 1 Hz, Whippany, New Jersey.

    AN29-10
    an equivalent capacitance of 100,OOO/lF with a sistor match ing and by balancing of the source re-
    worst case leakage of 8/lA-over a _55°C to sistances. A l-percent deviation in anyone of the
    125°C temperature range. resistor values reduces the common mode rejection
    to 46 dB for a closed loop gain of 1, to 60 dB for a
    gain of 10 and to 80 dB for a gain of 100.
    C~~Cl
    Clearly, the only way to get high input impedance
    'I.. VQ5 ·~l RI "'
    \DM is to use very large resistors in the feedback net-
    RsaRl work. The op amp must operate from a source
    resistance which is orders of magnitude larger than
    ••I. the resistance of the signal source. Older IC op
    "
    ~-"""M~--"'-_c
    amps introduced excessive offset and drift when
    operating from higher resistances and could not be
    used successfully. The LM108, however, is rela-
    tively unaffected by the large resistors, so this
    approach can sometimes be employed.

    FIGURE 19. Capacitance Multiplier With large input resistors, the feedback resistors,
    R 3 and R4 , can get quite large for higher closed
    loop gains. For example, if R 1 and R2 are 1 M!1,
    The performance of the circuit is described by the R3 and R4 must be 100 M!1 for a gain of 100. It is
    equations given in Figure 19, where C is the effec- difficult to accurately match resistors that are this
    tive output capacitance, IL is the leakage current high in value, so common mode rejection may
    of this capacitance and Rs is the series resistance suffer. Nonetheless, anyone of the resistors can be
    of the multiplied capacitance. The series resistance trimmed to take out common mode feedthrough
    is relatively high, so high-Q capacitors cannot be caused either by resistor mismatches or the ampli-
    realized. Hence, such applications as tuned circuits fier itself.
    and filters are ruled out. However, the multiplier
    can still be used in timing circuits or servo com-
    pensation networks where some resistance is
    usually connected in series with the capacitor or R1 Rl

    the effect of the resistance can be compensated


    for.
    INPUTS
    One final point is that the leakage current of the
    OUTPUT
    multiplied capacitance is not a function of the
    applied voltage. It persists even with no voltage on R. N = R2 + R4 ~ ,,"'rv--.....-I
    ..;+......
    the output. Therefore, it can generate offset errors
    in a circuit, rather than the scaling errors caused
    by conventional capacitors.

    INSTRUMENTATION AMPLIFIER
    In many instrumentation applications there is fre- FIGURE 20. Feedback Connection For a Differential
    Amplifier
    quently a need for an amplifier with a high-
    impedance differential input and a single ended
    output. Obvious uses for this are amplifiers for Another problem caused by large feedback re-
    bridge-type signal sources such as strain gages, tem- sistors is that stray capacitance can seriously affect
    perature sensors or pressure transducers. General the high frequency common mode rejection. With
    purpose op amps have satisfactory input character- 1 M!1 input resistors, a 1 pF mismatch in stray
    istics, but feedback must be added to determine capacitance from either input to ground can drop
    the effective gain. And the addition of feedback the common mode rejection to 40 dB at 1500 Hz.
    can drastically reduce the input resistance and The high frequency rejection can be imprOVed at
    degrade common mode rejection. the expense of frequency response by shunting R3
    and R4 with matched capacitors.
    Figure 20 shows the classical op amp circuit for a
    differential amplifier. This circuit has three main With high impedance bridges, the feedback resis-
    disadvantages. First, the input resistance on the tances become prohibitively large even for the
    inverting input is relatively low, being equal to R 1 • LM108, so the circuit in Figure 20 cannot be used.
    Second, there usually is a large difference in the One possible alternative is shown in Figure 21. R2
    input resistance of the two inputs, as is indicated and R3 are chosen so that their equivalent parallel
    by the equations on the schematic. Third, the resistance is equal to R l ' Hence, the output of the
    common mode rejection is greatly affected by re- amplifier will be zero when the bridge is balanced.

    AN29-11
    V' This circuit has the same sensitivity to resistor
    C1
    30pF
    matching as the previous circuits, with a 1 percent
    51 T mismatch between two resistors lowering the com-
    ''''.
    .,
    lOOK
    mon mode rejection to 80 dB_ However, matching
    is more easily accomplished because of the lower
    resistor values_ Further, the high frequency com-
    DUTPUT
    mon mode rejection is less affected by stray ca-
    pacitances. The high frequency rejection is limited,
    though, by the response of A, .

    ,,,." ,,,.
    .!
    .3
    5. LOGARITHMIC CONVERTER
    Rl" R2#R!
    A logarithmic amplifier is another circuit that can
    take advantage of the low input current of an op
    amp to increase dynamic range. Most practical log
    converters make use of the logarithmic relation-
    FIGURE 21. Amplifier For Bridge Transducers
    ship between the emitter-base voltage of standard
    double-diffused transistors and their collector
    current. This logarithmic characteristic has been
    When the bridge goes off balance, the 01' amp proven true for over 9 decades of collector cur-
    maintains the voltage between its input terminals rent. The only problem involved in using transis-
    at zero with current fed back from the output tors as logging elements is that the scale factor has
    through R 3. This circuit does not act like a true a temperature sensitivity of 0.3 percentfC. How-
    differential amplifier for large imbalances in the ever, temperature compensating resistors have
    bridge. The voltage drops across the two sensor been developed to compensate for this character-
    resistors, S, and Sz, become unequal as the bridge istic, making possible log converters that are accu-
    goes off balance, causing some non-linearity in the rate over a wide temperature range.
    transfer function. However, this is not usually
    objectionable for small signal swings. Figure 23 gives a circuit that uses these techniques.
    a, is the logging transistor, while a, provides a
    fixed offset to temperature compensate the

    ,.,
    emitter-base turn on voltage of 0,. oz is operated
    ...
    0.1"
    "'
    1K
    0.1%
    .3
    1K
    0.1%
    ,...
    .c
    D.'"
    at a fixed collector current of 10 J.lA by Az , and
    its emitter-base voltage is subtracted from that of
    a, in determining the output voltage of the cir-
    cuit. The collector current of oz is established by
    R3 and V+ through A,.

    The collector current of a, is proportional to the


    input current through R. and, therefore, propor-
    tional to the input voltage. The emitter-base volt-
    age of a, varies as the log of the input voltage.
    - .....-- INPUTS _ +
    The fixed emitter-base voltage of oz subtracts
    from the voltage on the emitter of a, in determin-
    Rt" M;AZ- R3
    Ay '" tm: ing the voltage on the top end of the temperature-
    compensating resistor, S,.

    The signal on the top of S, will be zero when the


    FIGURE 22. Differential Input Instrumentation Amplifier input current is equal to the current through R 3 at
    any temperature. Further, this voltage will vary
    Figure 22 shows a true differential connection that logarithmically for changes in input current, al-
    has few of the problems mentioned previously. It though the scale factor will have a temperature
    has an input resistance greater than 10' 0 n, yet it coefficient of -0.3%f C. The output of the con-
    does not need large resistors in the feedback cir- verter is essentially multiplied by the ratio of R, .
    cuitry. With the component values shown, A, is to S,. Since S, has a positive temperature coeffi-
    connected as a non-inverting amplifier with a gain cient of 0.3 percentf C, it compensates for the
    of 1.01; and it feeds into Az wh ich has an invert- change in scale factor with temperature.
    ing gain of 100. Hence, the total gain from the
    input of A, to the output of Az is 101, which is In this circuit, an LM101A with feedforward com-
    equal to the non-inverting gain of Az . If all the pensation is used for Az since it is much faster
    resistors are matched, the circuit responds only to than the LM108 used for A,. Since both ampli-
    the differential input signal-not the common fiers are cascaded in the overall feedback loop, the
    mode voltage. reduced phase shift through Az insures stability.

    AN29-12
    v+: 1!'1V
    lN1920
    RJ'
    15M
    1%

    R,
    INPUT-'\M.-4.....- - - j

    R"
    1.5M

    DUTPUT
    C1
    lDDpF

    lDnA<III\I<lmA
    SlnSltlVltv 1i1V pe,dee,de tAvlllablt hom Tel L.bs,lnc.,
    MaRtheslI., N.H., Typ. 011.
    °Dtte,rnlnes current 10' zrro
    cro5$lngonDulpu!',DpA
    nshDWn

    FIGURE 23. Temperature Compensated One~Quadrant Logarithmic Converter

    Certain things must be considered in designing this operated with reverse voltage across the junction.
    circuit. For one, the sensitivity can be changed by At high temperatures, the leakage currents can
    varying R I' But R I must be made considerably approach the signal current. However, photodiodes
    larger than the resis'tance of S I for effective tem· deliver a short-circuit output current, unaffected
    perature "Compensation of the scale factor. 0 1 and by leakage currents, which is not significantly
    O2 should also be matched devices in the same lower than the output current with reverse bias.
    package, and SI should be at the same tempera-
    ture as these transistors. Accuracy for low input The circuit shown in Figure 24 responds to the
    currents is determined by the error caused by the short-circuit output current of the photodiode_
    bias current of AI' At high currents, the behavior Since the voltage across the diode is only the off-
    of 0 1 and O2 limits accuracy. For input currents set voltage of the amplifier, inherent leakage is
    approaching 1 mA, the 2N2920 develops logging reduced by at least two orders of magnitude_ Ne-
    errors in excess of 1 percent. If larger input cur- glecting the offset current of the amplifier, the
    rents are anticipated, bigger transistors must be output current of the sensor is multiplied by RI
    used; and R2 should be reduced to insure that A2 plus R2 in determining the output voltage.
    does not saturate.
    Figure 25 shows an amplifier for high-impedance
    TRANSDUCER AMPLI FIERS ac transducers like a piezoelectric accelerometer.
    With certain transducers, accuracy depends on the These sensors normally require a high-input-
    choice of the circuit configuration as much as it resistance amplifier. The LM108 can provide input
    does on the quality of the components. The ampli- resistances in the range of 10 to 100 Mn, using
    fier for photodiode sensors, shown in Figure 24, conventional circuitry. However, conventional
    illustrates this point. Normally, photodiodes are designs are sometimes ruled out either because

    ,....-...._----~~OUT'UT
    R1
    ,.
    SM

    C1
    IOpf

    S1
    OUTPUT

    I C1

    'DO.' c:::::J TRANSDUCER

    T
    FIGURE 24. Amplifier For PhOlodiode Sensor FIGURE 25. Amplifier For Piezoelectric Transducers

    AN29-13
    large resistors cannot be used or because prohibi- CURRENT SOURCES
    tively large input resistances are needed. Although there are numerous ways to make cur-
    rent sources with op amps, most have limitations
    Using the circuit in Figure 25, input resistances as far as their application is concerned. Figure 27,
    that are orders of magn itude greater than the however, shows a current source which is fairly
    values of the dc return resistors can be obtained. flexible and has few restrictions as far as its use is
    This is accomplished by bootstrapping the resistors concerned. It supplies a current that is propor-
    to the output. With this arrangement, the lower tional to the input voltage and drives a load refer-
    cutoff frequency of a capacitive transducer is de- red to ground or any voltage within the output-
    termined more by the RC product of R I and CI swing capability of the amplifier.
    than it is by resistor values and the equivalent
    capacitance of the transducer.

    RESISTANCE MULTIPLICATION
    v,,-'w_...--I\J..,.,--,
    When an inverting operational amplifier must have
    high input resistance; the resistor values required lOUT = R:,V~~

    can get out of hand. For example, if a 2 Mr! input RJ=R4+R5


    Rl=R2
    resistance is needed for an amplifier with a gain
    of 100, a 200 Mr! feedback resistor is called for.
    This resistance can, however, be reduced using the R5
    ZK
    circuit in Figure 26. A divider with a ratio of 100
    to 1 (R 3 and R,) is added to the output of the
    amplifier: Unity-gain feedback is applied from the
    output of the divider, giving an overall gain of 100 ••
    1M
    1%
    using only 2 Mr! resistors.

    This circuit does increase the offset voltage some- FIGURE 27. Bilateral Current Source
    what. The output offset voltage is given by
    With the output grounded, it is relatively obvious
    RI + R2) that the output current will be determined by Rs
    VOUT = ( --R-2- Av Vos·
    and the gain setting of the op amp, yielding

    The offset voltage is only multiplied by Av + 1 in


    a conventional inverter. Therefore, the circuit in
    Figure 26 multiplies the offset by 200, instead
    of 101. This multiplication factor can be reduced
    When the output is not at zero, it wou Id seem that
    to 110 by increasing R2 to 20 Mr! and R3
    the current through R2 and R, would reduce
    to 5.55k.
    accuracy. Nonetheless, if RI = R2 and
    R3 = R, + Rs , the output current will be inde-
    .,
    1M
    .,
    1M
    .3
    505
    pendent of the output voltage. For
    RI + R3» Rs , the output resistance of the cir-
    1% 1% 1%
    INPUT -W"""''---'Io'W--'''J\III'v--. cuit is given by

    ••
    SOK
    R2;>RI 1%
    R2»Rl
    OUTPUT
    Av = R2~~JR+3 R4!
    where R is anyone of the feedback resistors (R I,
    R2 , R3 or R,) and Ll.R is the incremental change
    .5
    1M in the resistor value from design center. Hence, for
    the circu it in Figure 27, a 1 percent deviation in
    one of the resistor values will drop the output
    resistance of 200 kr!. Such errors can be trimmed
    FIGURE 26. Inverting Amplifier With High Input out by adjusting one of the feedback resistors. In
    Resistance design, it is advisable to make the feedback resis-
    tors as large as possible. Otherwise, resistor toler-
    Another disadvantage of the circuit is that four ances become even more critical.
    resistors determine the gain, instead of two.
    Hence, for a given resistor tolerance, the worst- The circuit must be driven from a source resistance
    case gain deviation is greater, although this is which is low by comparison to R I, since this resis-
    probably more than offset by the ease of getting tance will imbalance the circuit and affect both
    better tolerances in the low resistor values. gain and output resistance. As shown, the circuit

    AN29-14
    .,,)
    gives a negative output current for a positive input .,v
    voltage. This can be reversed by grounding the .,
    input and driving the ground end of R2 . The
    magnitude of the scale factor wi II be unchanged as
    long as R4 » Rs.

    VOLTAGE COMPARATORS
    Like most op amps, it is possible to use the LM10B
    as a voltage comparator. Figure 2B shows the
    device used as a simple zero·crossing detector. The
    inputs of the Ie are protected internally by back-
    FIGURE 29. Voltage Comparator With Output Buffer

    INPUT
    The LM 1OB can also be used as a differential com-
    parator, going through a transition when two input
    voltages are equal. However, resistors must be
    inserted in series with the inputs to limit current
    and minimize loading on the signal sources when
    the input-protection diodes conduct. Figure 29
    also shows how a PNP transistor can be added on
    FIGURE 28. Zero Crossing Detector
    the output to increase the fan out to about 20
    with standard DTL or TTL.
    to-back diodes connected between them, there-
    fore, voltages in excess of 1 V cannot be impressed POWER BOOSTER
    directly across the inputs. This problem is taken
    The LM10B, which was designed for low power
    care of by R 1 which limits the current so that
    consumption, is not able to drive heavy loads.
    input voltages in excess of 1 kV can be tolerated.
    However, a relatively simple booster can be added
    If absolute accuracy is required or if R 1 is made
    much larger than 1 MQ, a compensating resistor of to the output to increase the output current to
    ±50 mAo This circuit, shown in Figure 30, has the
    equal value should be inserted in series with the
    added advantage that it swings the output up to
    other input.
    the supplies, within a fraction of a volt. The in-
    creased voltage swing is particularly helpful in low
    In Figure 2B, the output of the op amp is clamped
    voltage circuits.
    so that it can drive DTL or TTL directly. This is
    accomplished with a clamp diode on pin B. When
    the output swings positive, it is clamped at the
    breakdown voltage of the zener. When it swings .-----e- v•
    negative, it is clamped at a diode drop below
    ground. If the 5V logic supply is used as a positive
    supply for the amplifier, the zener can be replaced
    with an ordinary silicon diode. The maximum fan
    out that can be handled by the device is one for INPUTS OUTPUT
    standard DTL or TTL under worst case conditions.

    As might be expected, the LM10B is not very fast


    when used as a comparator. The response time is
    up in the tens of microseconds. An LM103 11 is
    recommended for D1, rather than a conventional
    alloy zener, because it has lower capacitance and
    will not slow the circuit further. The sharp break-
    down of the LM103 at low currents is also an L-_ _ _ _ *-v·
    advantage as the current through the diode in
    clamp is only 10 p.A.
    FIGURE 30. Power Booster
    Figure 29 shows a comparator for voltages of
    opposite polarity. The output changes state when In Figure 30, the output transistors are driven
    the voltage on the junction of R 1 and R2 is equal from the supply leads of the op amp. It is impor-
    to VTH • Mathematically, this is expressed by tant that R 1 and R2 be made low enough so a,
    and O2 are not turned on by the worst case quies-
    cent current of the amplifier. The output of the op
    amp is loaded heavily to ground with R3 and R4 .

    AN29-15
    When the output swings about 0.5V positive, the vapor when operating in the vicinity of O°C. This
    increasing positive supply current will turn on 0 1 can usually be accomplished by coating the board
    which pulls up the load. A similar situation occurs as mentioned above.
    with O2 for negative output swings.
    GUARDING
    The bootstrapped shunt compensation shown in Even with properly cleaned and coated boards,
    the figure is the only one that seems to work for leakage currents are on the verge of causing
    all loading conditions. This capacitor, CI , can be trouble at 125°C. The standard pin configuration
    made inversely proportional to the closed loop of most IC op amps has the input pins adjacent to
    gain to optimize frequency response. The value pins which are at the supply potentials. Therefore,
    given is for a unity·gain follower connection. C2 is it is advisable to employ guarding to reduce the
    also required for loop stability. voltage difference between the inputs and adjacent
    metal runs.
    The circuit does have a dead zone in the open loop
    transfer characteristic. However, the low frequen·
    cy gain is high enough so that it can be neglected.
    Arou nd 1 k Hz, though, the dead zone becomes COMPENSATION

    quite noticeable.
    v' I~
    Current limiting can be incorporated into the cir·
    cuit by adding resistors in series with the emitters
    of 0 1 and O2 because the short circuit protection
    OUTPUT'e
    './ 1 1

    of the LM10B limits the maximum voltage drop


    across R I and R2 • 0'

    BOARD CONSTRUCTION
    As indicated previously, certain precautions must
    be observed when building circuits that are sensi·
    ~,'
    tive to very low currents. If proper care is not
    BOTTOM VIEW
    taken, board leakage currents can easily become
    much larger than the error currents of the op amp.
    To prevent this, it is necessary to thoroughly clean
    printed circuit boards. Even experimental bread· FIGURE 31. Printed Circuit Lavout For Input Guarding
    With TO·5 Package
    boards must be cleaned with trichloroethlene or
    alcohol to remove solder fluxes, and blown dry
    with compressed air. These fluxes may be insula· A board layout that includes input guarding is
    tors at low impedance levels-like in electric shown in Figure 31 for the eight lead TO·5 pack·
    motors-but they certainly are not in high imped· age. A ten·lead pin circle is used, and the leads of
    ance circuits. In addition to causing gross errors, the IC are formed so that the holes adjacent to the
    their presence can make the circuit behave inputs are vacant when it is inserted in the board.
    erratically, especially as the temperature is The guard, which is a conductive ring surrounding
    changed. the inputs, is then connected to a low impedance
    point that is at the same potential as the inputs.
    At elevated temperatures, even the leakage of The leakage currents from the pins at the supply
    clean boards can be a headache. At 125°C the potentials are absorbed by the guard. The voltage
    leakage resistance between adjacent runs on a difference between the guard and the inputs can
    printed circuit board is about 10 1 I n (0.05·inch be made approximately equal to the offset voltage,
    separation parallel for 1 inch) for high quality reducing the effective leakage by more than three
    epoxy·glass boards that have been properly clean· orders of magn itude. If the leads of the integrated
    ed. Therefore, the boards can easily produce error circuit, or other components connected to the
    currents in the order of 200 pA and much more if input, go through the board, it may be necessary
    they become contaminated. Conservative practice to guard both sides.
    dictates that the boards be coated with epoxy or
    silicone rubber after cleaning to prevent contami· Figure 32 shows how the guard is comm itted on
    nation. Silicone rubber is the easiest to use. How· the more·common op amp circuits. With an inte·
    ever, if the better durability of epoxy is needed, grator or inverting amplifier, where the inputs are
    care must be taken to make sure that it gets close to ground potential, the guard is simply
    thoroughly cured. Otherwise, the epoxy will make grounded. With the voltage follower, the guard is
    high temperature leakage much worse. bootstrapped to the output. If it is desirable to put
    a resistor in the inverting input to compensate for
    Care must also be exercised to insure that the cir· the source resistance, it is connected as shown in
    cuit board is protected from condensed water Figure 32b.

    AN29-16
    INPUT_""'RIIV-...._ _~v., __-, Guarding a non-inverting amplifier is a little more
    complicated_ A low impedance point must be
    created by using relatively low value feedback re-
    sistors to determine the gain (R 1 and R2 in
    DUTPUT Figure 32c)_ The guard is then connected to the
    junction of the feedback resistors_ A resistor, R3 ,
    can be connected as shown in the figure to com-
    pensate for large source resistances_
    C1
    With the dual-in-line and flat packages, it is far
    more difficult to guard the inputs, if the standard
    •. lnvertln,Amplifier pin configuration of the LM709 or LM101A is
    used, because the pin spacings on these packages
    are fixed_ Therefore, the pin configuration of the
    LM 108 was changed, as shown in Figure 33_

    CONCLUSIONS
    OUTPUT IC op amps are now available that equal the input
    current specifications of FET amplifiers in all but
    the most restricted temperature range applications_
    At operating temperatures above 85°C, the IC is
    C1 clearly superior as it uses bipolar transistors that
    b.fGllowtl make it possible to eliminate the leakage currents
    that plague FETs_ Additionally, bipolar transistors
    Rl match better than F ETs, so low offset voltage and
    drifts can be obtained without expensive adjust-
    ments or selection_ Further, the bipolar devices
    lend themselves more readily to low-cost mono-
    lithic construction_
    OUTPUT

    ., These amplifiers open up new application areas


    and vastly improve performance in others_ For
    example, in analog memories, holding intervals can
    be extended to minutes, even where -55°C to
    c. Non·lnmtl"1 Amph'I. 125°C operation is involved_ Instrumentation
    amplifiers and low frequency waveform generators
    FIGURE 32_ Connection Of Input Guards also benefit from the low error currents_

    NO CONNECTION NO CONNECTION NO CONNECTION


    ) COMPENSATION
    BALANCE/COMPENSATION COMPENSATION GUARD

    INPUT y' INPUT y'

    INPUT OUTPUT
    INPUT _ _ _ --n' OUTPUT

    Y- IAlAftlCE GUARD _---...'-_ _ _....;,--


    -'----~.------

    NOTE: PIn 5 C'nnlCld IIII,n'lI!I of 'Khre. NOTE' Pm &connKltd 10 bonom 01 p.ck."


    TOPYIEW TOPYIEW

    14 14

    BALANCE/COMPENSATION J
    LMIOIA
    "
    12 COMPENSATION
    COMPENSATION 2

    GUARD J
    "
    12 COMPENSATION

    INPUT 4 II y+ INPUT 4 11 y+

    INPUT 5 10 OUTPUT INPUT 5 10 OUTPUT

    y- , 9 BALANCE GUARD &

    y- 7

    NOTE: Pin &conntC:l~d 10 b,nom of pith•. NDTE. Pin 1 connmedlo bono.., 01 ~ck ..r

    TOPYIEW TOPYIEW

    FIGURE 33. Comparing Connection Diagrams Of The LM101A And LM10B, Showing Addition Of Guarding

    AN29-17
    When operating above 85° C, overall performance compensate for the current gain falloff of the
    is frequently limited by components other than input transistors at low temperatures without
    the op amp, unless certain precautions are ob- creating stability problems at high temperatures.
    served_ It is generally necessary to redesign circuits
    using semiconductor switches to reduce the effect The biasing circuitry for the input current source
    of their leakage currents_ Further, high quality is nearly identical to that in the LM101 A, and a
    capacitors must be used, and care must be exer- complete description is given in Reference 4. How-
    cised in selecting large value resistors_ Printed cir- ever, a brief explanation follows.
    cuit board leakages can also be troublesome unless
    the boards are properly treated_ And above 100°C, A collector FET/ 0 23 , which has a saturation
    it is almost mandatory to employ guarding on the current of about 30/lA, establishes the collector
    boards to protect the inputs, if the full potential current of 0 24 , This FET provides the initial
    of the amplifier is to be realized. turn-on current for the circuit and insures starting
    under all conditions. The purpose of R 14 is to
    APPENDIX compensate for production and temperature varia-
    A complete schematic of the LM108 is given in tions in the F ET current. It is a collector resistor
    Figure A1. A description of the basic circuit is (indicated by the T through it) made of the same
    presented along with a simplified schematic earlier semiconductor material as the FET channel. As
    in the text. The purpose of this Appendix is to the FET current varies, the drop across R 14 tends
    explain some of the more subtle features of the to compensate for changes in the emitter base volt-
    design. age of 0 24 ,

    The current source supplying the input transistors The collector-emitter voltage of 0 24 is equal to
    is 0 29 , It is designed to supply a total input stage the emitter base voltage of 0 24 plus that of 0 25 ,
    current of 6/lA at 25°C. This current drops, to This voltage is delivered to 0 26 and 0 29 , 0 25 and
    3/lA at -55°C but increases to only 7.5/lA at 0 24 are operated at substantially higher currents
    125°C. This temperature characteristic tends to than 0 26 and 0 29 , Hence, there is a differential in

    COMPENSATION COMPENSATION
    r-----~~4-~~~--~4---~~------------_.------v·

    i11-.............WI_-OUTPUT

    INPUTS

    +-----+-------4~

    FIGURE A1. Complete Schematic Of The LM108

    AN29-18
    their emitter base voltages that is dropped across Input protection is provided by 0 3 and 0 4 which
    R '9 to determine the input stage current. R '8 is a act as clamp diodes between the inputs. The col·
    pinched base resistor, as is indicated by the slash lectors of these transistors are bootstrapped to the
    bar through it. This resistor, which has a large emitter of 0 28 through R3. This keeps the col·
    positive temperature coefficient, operates in con· lector·isolation leakage of the transistors from
    junction with R " to hel p shape the temperature showing up on the inputs. R3 is included so that
    characteristics of the input stage current source. the bootstrapping is not disrupted when 0 3 or 0 4
    saturate with an input overload. Current·limiting
    The output currents of 0 26 , 0 25 and 0 23 are fed resistors were not connected in series with the
    to 0,2, which is a controlled·gain lateral PNP. 6 It inputs, since diffused resistors cannot be employed
    delivers one·half of the combined currents to the such that they work effectively, without causing
    output stage. a" is also connected to 0,2, with high temperature leakages.
    its output current set at approximately 15 JlA by
    R, . Since this type of current source makes use of
    the emitter·base voltage differential between
    similar transistors operating at different collector Table I. Typical Performance of the LM108
    currents, the output of a" is relatively indepen· Operational Amplifier (T A = 25°C and
    dent of the current delivered to a, 2.' 2 This cur· Vs = ±15V).
    rent is used for the input stage bootstrapping cir·
    cuitry. Input Offset Voltage 0.7 mV
    Input Offset Current 50 pA
    0 20 also supplies current to the class-B output Input Bias Current 0.8 nA
    stage. Its output current is determined by the ratio Input Resistance 70 Mn
    of R, 5 to R, 2 and the current through R, 2. R 13 Input Common Mode Range ±14V
    is included so that the biasing circuitry is not upset Common Mode Rejection 100 dB
    when 0 20 saturates. Offset Voltage Drift 3 Jlvtc
    Offset Current Drift 0.5 pAtC
    Voltage Gain 300V/mV
    One major departure from the simplified schemat·
    Small Signal Bandwidth 1.0 MHz
    ic is the bootstrapping of the second stage active
    Slew Rate 0.3VIJls
    loads, O2 , and 0 22 , to the output. This makes the
    Output Swing ±14V
    second stage gain dependent only on how well 0 9
    Supply Current 300 JlA
    and 010 match with variations in output voltage.
    Power Supply Rejection 100dB
    Hence, the second stage gain is quite high. In fact,
    Operating Voltage Range ±2V to ±20V
    the overall .gain of the amplifier is typically in
    excess of 106 at dc.

    The second stage active loads drive 0,4. A high·


    gain primary transistor is used to prevent loading
    of the second stage. Its collector is bootstrapped
    by a, 3 to operate it at zero collector·base voltage. REFERENCES
    The class·B output stage is actually driven by the 1. R. J. Widlar, "Future Trends in Integrated
    emitter of 0,4. Operational Amplifiers," EON, Vol. 13,
    No.6, pp. 24-29, June, 1968.
    A dead zone in the output stage is prevented by
    2. R. J. Widlar, "Super Gain Transistors for ICs,"
    biasing a, 8 and 0'9 on the verge of conduction
    lEE E Journal of Solid·State Circuits,
    with a, 5 and a, 6. R9 is used to compensate for
    Vol. SC·4, No.4, August, 1969.
    the transconductance of a, 5 and 0,6, making the
    output stage quiescent current relatively indepen·
    3. R. J. Widlar, "A Unique Circuit Design for a
    dent of the output current of 0,2. The drop
    High Performance Operational Amplifier
    across this resistor also reduces quiescent current.
    Especially Suited to Monolithic Construc·
    tion," Proc. of NEC, Vol. XXI, pp. 85-89,
    For positive·goi ng outputs, short circu it protection October, 1965.
    is provided by R, 0 and 0 11 • When the voltage
    drop across R, 0 turns on 0 11 , it removes base 4. R. J. Widlar, "I.C. Op Amp with Improved
    drive from a, 8. For negative·going outputs, cur· I nput·Current Characteristics," EEE,
    rent limiting is initiated when the voltage drop pp. 38-41, December, 1968.
    across R" becomes large enough for the collector
    base junction of 0" to become forward biased. 5. R. J. Widlar, "Linear IC's: part 6; Compensa·
    When this happens, the base of a, 9 is clamped so ting for Drift," Electronics, Vol. 41, No.3,
    the output current cannot increase further. pp. 90-93, February, 1968.

    AN29-19
    6. R. J. Widlar, "Design Techniques for Mono· 9. R. J. Widlar, "A Fast Integrated Voltage Fol·
    lithic Operational Amplifiers," IEEE Journal lower with Low Input Current," Microelec-
    of Solid·State Circuits, Vol. SC·4, No.4, tronics, Vol. 1, No.7, June, 1968.
    August, 1969.
    10. R. C. Dobkin, "Feedforward Compensation
    7. D. R. Sullivan and M. A. Maidique, "Charac' Speeds Op Amp," National Semiconductor
    terization and Application of a New High LB-2, March, 1969.
    Input Impedance Monolithic Amplifier,"
    Transitron Electronic Corporation Applica· 11. R. J. Widlar, "A New Low Voltage Break-
    tion Brief. down Diode," National Semiconductor TP-5,
    April,1968.
    8. Paul C. Dow, Jr., "An Analysis of Certain
    Errors in Electronic Differential Analyzers, 12. R. J. Widlar, "Some Circuit Design Tech-
    II-Capacitor Dielectric Absorption," IRE niques for Linear Integrated Circuits," IEEE
    Trans. on Electronic Computers, pp. 17-22, Transactions on Circuit Theorv, Vol. CT-12,
    March, 1958: No.4, pp. 586-590, December, 1965 .

    .I'.N29-20
    »
    2
    Robert C. Dobkin W
    November 1969 o
    r-
    oG')
    LOGARITHMIC CONVERTERS
    »
    ::lJ
    ::::j
    One of the most predictable non-linear elements tron. Combining these two equations and writing ::I:
    commonly available is the bipolar transistor. The the expression for the output voltage gives
    s:
    fl
    relationship between collector current and emitter

    -~T R~ 109.~:~NF ~~~


    base voltage is precisely logarithmic from currents (")
    below one picoamp to currents above one milli- EOUT = R: (3) (")
    amp. Using a matched pair of transistors and inte-
    grated circuit operational amplifiers, it is relatively for EI N ~ O. This shows that the output is propor-
    o
    2
    easy to construct a linear to logarithmic converter
    with a dynamic range in excess of five decades.
    tional to the logarithm of the input voltage. The
    coefficient of the log term is directly proportional
    <
    m
    to absolute temperature. Without compensation, ::D
    The circuit in Figure 1 generates a logarithmic out- the scale factor wi II also vary directly with temper-
    -I
    m
    put voltage for a linear input current. Transistor ature. However, by making R2 directly propor- ::D
    0 1 is used as the non-linear feedback element tional to temperature, constant gain is obtained. rn
    around an LM 108 operational ampl ifier. Negative The temperature compensation is typically 1%
    feedback is applied to the emitter of 0 1 through over a temperature range of _25° C to 100° C for
    divider, R I and R2 , and the emitter base junction of the resistor specified. For limited temperature
    O2 • This forces the collector current of 0 1 to be range applications, such as O°C to 50°C, a 430£2
    exactly equal to the current through the input re- sensistor in series with a 570£2 resistor may be
    sistor. Transistor O2 is used as the feedback ele- substituted for the 1 K resistor, also with 1% accu-
    ment of an LM101A operational amplifier. Nega- racy. The divider, RI and R2, sets the gain while
    tive feedback forces the collector current of O2 to the current through R3 sets the zero. With the
    equal the current through R3 . For the values values given, the scale factor is 1V/decade and
    shown, this current is 10 MA. Since the collector
    current of O2 remains constant, the emitter base
    (4)
    voltage also remains constant. Therefore, only the
    VB E of 0 1 varies with a change of input current.
    However, the output voltage is a function of the where the absolute value sign indicates that the
    difference in emitter base voltages of 0 1 and O2 : dimensions of the quantity inside are to be
    ignored.

    Log generator circuits are not limited to inverting


    operation. In fact, a feature of this circuit is the
    For matched transistors operating at different col- ease with which non-inverting operation is obtain-
    lector currents, the emitter base differential is ed. Supplying the input signal to A2 and the
    given by reference current to Al results in a log output
    that is not inverted from the input. To achieve the
    same 100 dB dynamic range in the non-inverting
    (2)
    configuration, an LM108 should be used for A2 ,
    and an LM101A for AI. Since the LM108 cannot
    where k is Boltzmann's constant, T is temperature use feedforward compensation, it is frequency
    in degrees Kelvin and q is the charge of an elec- compensated with the standard 30 pF capacitor.
    EREF 15V

    R3
    15.
    ,%
    lN2tZO

    R"
    E,.
    +ISV

    R,t
    ,.
    Rl
    R,.

    '00' R'
    1K
    -15V
    ·TEL LABS TYPE Ou
    MANCHESTEA, N H "
    ISGpF "
    OIIlF
    "=" 'OFFSET VIlL TAGE ADJUST

    FIGURE 1. Log Generator with 100 dB Dynamic Range

    AN30-1
    The only other change is the addition of a clamp the transfer functiol)." With the values shown the
    diode connected from the emitter of 0 1 to scale factor is lV/decade and
    ground. This prevents damage to the logging tran-
    sistors if the input signal should go negative.

    The log output is accurate to 1% for any current


    between 10 nA and 1 mAo This is equivalent to from less than 100 nA to 1 rnA.
    about 3% referred to the input. At currents'over
    500 IJA the transistors used deviate from log char- Anti-log or exponential generation is simply a
    acteristics due to resistance in the emitter, while at matter of rearranging the circuitry. Figure 3 shows
    low currents, the offset current of the LM 108 is the circuitry of the log converter connected to
    the major source of error. These errors occur at generate an exponential output from a linear
    the ends of the dynamic range, and from 40 nA to input. Amplifier A, in conjunction with transistor
    400 IJA the log converter is 1% accurate referred 0, drives the emitter of O2 in proportion to the
    to the input. Both of the transistors are used in the input voltage. The collector current of O2 varies
    grounded base connection, rather than the diode exponentially with ·the emitter-base Voltage. This
    connection, to eliminate errors due to base cur- current is converted to a voltage by amplifier A2 .
    rent. Unfortunately, the grounded base connection With the values' given
    increases the loop gain. More frequency compensa-
    EOUT = lO-[E'Nl. (6)
    tion is necessary to prevent oscillation, and the log
    converter is necessarily slow. It may take 1 to 5 ms Many non-linear functions such as X 112 , X2 , X3 ,
    for the output to settle to 1% of its final value. l/X, XV, and X/V are easily generated with the use
    This is especially true at low currents. of logs. Multiplication becomes addition, division

    EREF 15V

    R3
    150K

    "

    R,.
    10.
    E" --'WIoo-'---'i

    C1 cz C3 '"TEL LABS TYPE 0,1


    lOOp' 75pF 'p' MANCHESTER, H.H.

    FIGURE 2. Fast Log Generator

    The circuit shown in Figure 2 is two orders of becomes subtraction and powers become gain
    magnitude faster than the previous circuit and has coefficients of log terms. Figure 4 shows a circuit
    a dynamic range of 80 dB. Operation is the same whose output is tHe cube of the input. Actually,
    as the circuit in Figure 1, except the configuration any power function is available from this circuit
    optimizes speed rather than dynamic range. Tran- by changing the values of Rg and RIo in accor-
    sistor 0, is diode connected to allow the use of dance with the expression:
    feedforward compensation' on an LM101A opera-
    tional amplifier. This compensation extends the 16.7 Ag
    bandwidth to 10 MHz and increases the slew rate. EOUT = EIN Ag + AIO (7)
    To prevent errors due to the finite hF E of 0,
    and the bias current of the LM101A, an LM102 Note that when log and anti-log circuits are used
    voltage follower buffers the base current and to perform an operation with a linear output, no
    input current. Although the log circuit will operate temperature compensating resistors at all are
    without the LM 102, accuracy wi II degrade at needed. If the log and anti-log transistors are at the
    low input currents. Amplifier A2 is also com- same temperature, gain changes with temperature
    pensated for maximum bandwidth. As with the cancel. It is a good idea to use a heat sink which
    previous log converter, R, and R2 control the couples the two transistors to minimize thermal
    sensitivity; and R3 controls the zero crossing of gradients. A 1°C temperature difference between

    AN30-2
    the log and anti·log transistors results in a 0.3% tional to the log of E, /E,. Transistor 0 3 adds a
    error. Also, in the log converters, a 1°C difference voltage proportional to the log of E3 and drives
    between the log transistors and the compensating the anti·log transistor, 0 4 . The collector current of
    resistor results in a 0.3% error. 0 4 is converted to an output voltage by A4 and
    R7,with the scale factor set by R7 at E, E3110E,.
    Either of the circuits in Figures 1 or 2 may be used
    as dividers or reciprocal generators. Equation 3 Measurement of transistor current gains over a
    shows the outputs of the log generators are actu· wide range of operating currents is an application
    ally the ratio of two currents: the input current particularly suited to log multiplier/dividers. Using
    and the current through R3 . When used as a log the circuit in Figure 5, PNP current gains can be

    .3
    1SDK
    1%
    2N2!l2D
    ••
    10K
    1%

    EOUT

    ·TEL lABS TYPE Dtl


    MANCHESTER. N H.

    FIGURE 3: Anti·log Generator

    generator, the current through R3 was held constant measured at currents from 0.4 /lA to 1 mA. The
    by connecting R3 to a fixed voltage. Hence, the out· collector current is the input signal to A" the base
    put was just the log of the input. If R3 is driven by current is the input signal to A" and a fixed volt·
    an input voltage, rather than the l5V reference, age to Rs sets the scale factor. Since A, holds the
    the output of the log generator is the log ratio of base at ground, a single resistor from the emitter
    the input current to the current through R3 . The to the positive supply is all that is needed to estab·
    anti·log of this voltage is the quotient. Of course, lish the operating current. The output is propor·
    if the divisor is constant, the output is the tional to collector current divided by base current,
    reciprocal. or h FE •

    A complete one quadrant multiplier/divider is In addition to their application in performing


    shown in Figure 5. It is basically the log generator functional operations, log generators can provide a
    shown in Figure 1 driving the anti·log generator significant increase in the dynamic range of signal
    shown in Figure 3. The log generator output from processing systems. Also, unlike a linear system,
    A, drives the base of 0 3 with a voltage propor· there is no loss in accuracy or resolution when the
    15V
    .
    ,-- .....- - - .. 1.5M
    1%

    "
    15DpF
    FIGURE 4. Cube Generator

    AN30-3
    input signal is small compared to full scale. Over zeroed, if necessary, to improve accuracy with low
    most of the dynamic range, the accuracy is a input voltages.
    percent·of-signal rather than a percent-of-full-scale.
    For example, using log generators, a simple meter The log converters are low level circuits and some
    can display signals with 100 dB dynamic range or care should be taken during construction. The
    an oscilloscope can display a 10 mV and 10V pulse input leads should be as short as possible and the
    simultaneously. Obviously, without the log genera- input circuitry guarded against leakage currents.
    tor, the low level signals are completely lost. Solder residues can easily conduct leakage cur-
    rents, therefore circuit boards shoUld be cleaned
    To achieve wide dynamic range with high accuracy, before use. High quality glass or mica capacitors
    the input operational amplifier necessarily must should be used on the inputs to minimize leakage
    have low offset voltage, bias current and offset currents. Also, when the +15V supply is used as a
    current. The LM 108 has a maximum bias current reference, it must be well regulated.
    of 3 nA and offset current of 400 pA over a -55°C
    to 125°C temperature range. By using equal source REFERENCES:
    resistors, only the offset current of the LM 108 1. R. C. Dobkin, "Feedforward Compensation
    causes an error. The offset current of the LM108 is Speeds Op Amp," National Semiconductor
    as low as many FET amplifiers. Further, it has a Corporation, Linear Brief 2, April, 1969.
    low and constant temperature coefficient rather 2. R. J. Widlar, "Monolithic Operational Ampli-
    than doubling every lOoC. This results in greater fiers- The Universal Linear Component,"
    accuracy over temperature than can be achieved National Semiconductor Corporation, AN-4,
    with FET amplifiers. The offset voltage may be April, 1968.

    2NZ920

    0'
    '0,.0'

    EOUT"~
    FOO
    E"E 2 .E 3 >0

    150,IF
    ••
    FIGURE 5. MultiplierlDivider

    AN30-4
    l>
    Z,
    Robert C. Dobkin W
    February 1970 ...a

    o"0
    l>
    op amp circuit collection s:."
    section 1 - basic circuits
    "
    ::0
    " "
    C
    :::::j

    "o
    r-
    r-
    Inverting Amplifier Non-Inverting Amplifier
    m
    ~
    o
    v,
    z
    v" ......WH~
    v"~w~....:< VOUT

    VIlUT-(~)MV2-~Vl
    FORRI=R3ANORZ=R4

    VouT·~lvz-V,1
    RURl ~ RJIR4 "=" FOR MINIMUM OFFSET ERROR
    DUE TO INPUT IIASCURRENr
    FOR MINIMUM OFfSET ERROR
    DUETDINPUTBJASCUARENT

    Inverting Summing Amplifier


    Difference Amplifier

    CI
    "F

    INPUT ......W
    .
    "
    'OM
    ..... +--..JIJ""-.....

    -5aurcl.mpedlllcl
    "'1fIInIDDK
    "".I_thln!"

    RJ
    5.IM

    Non-Inverting Summing Amplifier


    Inverting Amplifier with High
    Input Impedance

    R1
    'M "
    "M

    OU1l'UT

    Fast Inverting Amplifier With High Input Impedance Non-Inverting AC Amplifier

    AN31-1
    VOUT

    ""2""~2cl
    Ih~ 27r~IC1 ~ 2'1'~2C2
    '.«fh«'.ft", •••n
    JOpF

    R1 ~ R2
    Practical Differentiator FOR MINIMUM OFFSET ERROR
    DUE TQ INPUT BIAS CURRENT

    Integrator

    C3
    v,.

    R2

    " "
    10pf
    You,

    YOUT

    "fQR MINIMUM ERROR DUE TO


    BIAS CURRENT R2= R1

    C1
    15DpF
    Current to Voltage Converter

    Fast Integrator

    "' ...----1==::;--r- +20V

    +IIV
    ..
    R!
    10K

    +IDV....I_+_ _ _ _::..:..._ _...L..


    ."'
    10K

    Circuit for Operating the LM10l Circuit for Generating the


    without a Negative Supply Second Positive Voltage

    AN31-2
    ..
    r--"'''''''''--V'
    ".

    V,.-"""',..,......---...:;:.--,
    R1

    -Allludh"IIIDlntrglitoldlllt.
    C... ,enl.nfttypl~lIyo.l •• AfC
    OVtf-S5·CI01U·Campllllllllllllga.

    Neutralizing Input Capacitance to Integrator with Bias Current Compensation


    Optimize Response Time

    INPUTS
    Threshold Detector for Photodiodes

    v,.

    Voltage Comparator for Driving


    DTL or TTL Integrated Circuits
    ., v,

    .,

    v"
    .,

    Vouy=OVlor
    VIN<VLyO,VIN>VUT v,

    Double-Ended Limit Detector Multiple Aperture Window Discrim inatar

    AN31-3
    RJ

    R5

    -y R2
    loon
    RANGE-±v(M)

    Offset Voltage Adjustment for Inverting Amplifiers Offset Voltage Adjustment for Non-Inverting
    Using Any Type of Feedback Element Amplifiers

    R2

    OUTPUT

    "' "
    .." .."'VI""".... ;:1(
    OUTPUT
    -C
    -y R2"RJ+R4
    RANGE.tV(~)(~)
    INPUT
    RANGE=tV(~) GAIN"'~

    Offset Voltage Adjustment for Voltage Followers Offset Voltage Adjustment for Differential Ampl ifiers

    Offset Voltage Adjustment for Inverting


    Amplifiers Using 10 kS1 Source Resistance
    or Less

    AN31-4
    section 2 - signal generation

    C2
    o.a2"F
    "

    COSINE
    OUTPUT

    C5
    JOpF

    Rl D1 R4
    ZZM I3Y 'OK
    " D2
    IlY

    Low Frequency Sine Wave Generator with Quadrature Output

    ...C2,F SINE OUTPUT


    Cl
    IOOpf

    " "
    R3
    lOOK R4
    1% &K

    COSINE OUTPUT

    "
    I!iDpF

    ..
    .1
    ZZOK D1
    UV

    D2
    "
    2K
    '0 "'IDkH,
    UV

    High Frequency Sine Wave Generator with Quadrature Output

    AN31-5
    '"50
    R1
    1&01{

    >:"""+--'0"' OUTPUT

    Cl
    Cl'
    RJ
    1601{ "
    0""'1 R2
    9101{ 200K
    R1

    ':'" ":" 'CltoSllntg'IISI;,llllIonIIIOOHI


    AI-R2
    Cl-C2
    1
    '"
    f-Z1rR1CT

    Free-Running Multivibrator
    Wein Bridge Sine Wave Oscillator

    RI RZ
    lOOK 1901(
    Cl
    O.I,JF
    ~5V -""',..,.....---~W..-----......,

    R5
    TmngleW.v, 10K
    Output
    R4
    lOOK

    R1 R2 01
    10K 1M 6lV
    RJ
    R5
    lOon 02
    82< 6.2V

    Function Generator
    Pulse Width Modulator

    lour' R;,V~;
    R3 • R4 ~ R5
    RI·RZ

    115
    2K
    1%

    R4
    1M
    1%

    Bilateral Current Source Bilateral Current Source

    AN31-6
    R2
    10K

    1-_...._ .....__ ..

    Wein Bridge Oscillator with FET Amplitude Stabilization

    OJ D5
    lN759 lN759
    12V 12V

    V·

    low Power Supply for Integrated Circuit Testing

    AN31-7
    ...
    D1
    1N4611
    r-----....- V•

    Vout

    D1
    lN4&lI
    66V

    '------+~"'

    ..
    Positive Voltage Reference Positive Voltage Reference

    D1
    '''4611
    UV

    YOUT

    R2
    R2

    '----....~"' RI

    R4

    Negative Voltage Reference Negative Voltage Reference

    v"
    v,"

    Precision Current Sink Precision Current Source

    AN31-8
    section 3 - signal processing

    OUTPUT

    Differential-Input Instrumentation Amplifier

    Variable Gain, Differential-Input Instrumentation Amplifier

    AN31-9
    ,.1"'
    at. .B
    !OK
    D.'"

    OUTPUT

    R'-R5-,IRZ R1e
    RZ-R3 SOK R3=R4
    RI ~ RI -IDRI

    +_INPUTS_- '" Av-~


    "tMatd!llIIdllbmll •• ComMO.
    IIIOd'''IKtlOIi.

    Instrumentation Amplifier with ±100 Volt Common Mode Range

    R,z- Rrt
    IOIC lOOK
    0.,% 0.,%

    ....,
    to

    OUTPUT

    ..
    .3
    IO•

    ..
    4SKRS·
    C3
    30pF
    R,-R4
    RI-AS
    RI·A7
    ''''OK
    at. t-MIu;hlnIDnertlllnnCMRR

    .,1 Av·~('+W)
    + 'ODIC
    at.
    "
    ,*'OOPF

    Differential Input Instrumentation Amplifier with High Common Mode Rejection

    AN31-10
    AI'

    ""
    RZ'

    "
    Rl'

    "
    ..
    tDDIC
    , y'
    AI .'
    '" DI% DI% DI%
    '"
    D.l% '""
    AI

    " "'
    50'
    OUTPur "
    ~~--DUTPUT

    ·R.~uml"tllnKI"af
    , _...,plyllO.. ltyZOd.
    Cl" .nhlak....pplylly,.."1

    UIO~F t;~:I:CllAmDllmod.
    -_INPUTS_+ ,,,,",,,n
    lG"IIN,..1'I
    ·tMltc~I",.r.I,"mIlIHCMRR
    'MI,lNPdI•• lII!lol!UumlDundMft!l

    High Input Impedance Instrumentation Amplifier Bridge Amplifier with Low Noise Compensation

    ~-----""-Eou,

    y' You,

    AI_HZ
    '"
    RSi-R$i
    VOUT~V+(I-~ )

    Bridge Amplifier Precision Diode

    R,.
    .,.,-"""""'-1------.-- EOUT
    "
    "F
    D1
    INJI4
    t---'\i\tv--......~-.O"'

    "
    IN''4

    "E nlF mllflMff.Jllllfce


    "
    INI14

    Impllbnc.01 leut"'"
    "
    1Hln 20llUrfDZnuud.

    Precision Clamp Fast Half Wave Rectifier

    AN31-11
    20'
    ..
    " .3
    10'
    "
    r-....w ....-1~-'\i..,.,.~~......~-....-'""'
    01
    lN914

    DZ
    INII4

    Precision AC to DC Converter

    OUTPUT

    C1
    lO,f

    Low Drift Peak Detector

    ..
    OUTPUT

    INPUT

    Sample and Hold

    OUTPUT

    v'

    '3

    OUTPUT

    *WomCl• •IhI.. t1Iln


    Z.SmV/iIK
    tTllfton,PulynhyllMDI
    VOUT--m- V,N Pulyc.rbatllt.DotIlCtnt
    IAlllcitor C2
    RZ·R~\':4 lOpF

    Absolute Value Amplifier with Polarity Detector Sample and Hold

    AN31-12
    v' '"

    L..._+-.... _RESET
    R,
    INPUT-W"'""".---------<t--i
    R3
    10K

    OUTPUT

    ":>=....-!-'OUTPUT

    ".
    ..
    ·'11Ih.lM1D1AI._lllp.nd,_
    .."11'.101111:'11$1"'' .... tr-IIndwldlh.25I1KKI
    SmallS..... BInd..... tII· 15 MHI
    fnqu •• ~ ..,•• _outpld SInIIRm.IOVl~
    dllIllClpa.,lrtyan."IIII,..tB
    Wontggdilltiessthill 1....1IIII1__ d;. , C5,,1~~rt"'
    "01 IIId III sbouldnal h"'l 5GO",VlfllCoVll'-55°C
    ,nhmlll ..t .. proIKI,and,odli to+I2S"C

    Low Drift Integrator Fast t Summing Amplifier with Low Input CUrrent

    "
    ZK

    D2

    INPUT-"'V<".... . .- - -_ _ _ _ _ _. ._ _- j

    HI
    "'
    OK C5
    IOpf
    1S0K
    C1
    oQOZ "F
    "
    OOIl2,.F

    ,.
    HZ >~ ..
    -OUTPUT

    ,.
    Rl

    Fast Integrator with Low Input Current

    AN31-13
    OK
    0,1%

    R1
    1O.

    v.. Your

    "
    ....F

    fO- Z1fR\Cl
    s60Hz
    C1 RI ~ Rt ~ tRl
    27DpF Cl = cz ~ et3
    R4=R5
    R4 RI-R]
    R4=112Rl
    50' R4
    f
    2K
    I,,'Z1rR4vcm
    Of%

    AS C2
    2K f,F
    Adjustable Q Notch Filter '"

    Easily Tuned Notch Filter

    VOUT

    OUTPUT

    ,.---'-
    21fJR1R2C1C2

    Tuned Circuit

    Two-Stage Tuned Circuit

    VOUT

    I-~
    ~ - RJ

    RJ ,o·~
    "
    10M
    1%
    5M
    RI·R2=2R3
    CI=C2:ClJ2

    High Q Notch Filter Negative Capacitance Mu!tiplier

    AN31-14
    R1 RZ
    ,. 11K

    cz
    1S1,F

    C1
    1.1jo1F

    Variable Capacitance Multiplier

    RZ
    10.

    cm~C1
    Vos+losR1
    1,--,-,-

    R3
    IK

    "
    L~RI R2CI ...- ...... .... - ,
    ""'-~
    RSER2
    R,=RI
    R1
    10.
    ..
    Simulated Inductor
    Capacitance Multiplier

    y'
    y'

    AI

    OUTPUT

    y,
    INPUT -'VIh-.--{

    CONTROL

    y'

    Two Quadrant Multiplier Voltage Controlled Gain Circuit

    AN31-15
    R1 CI'
    1101( MDpF

    .,,'"
    I"UT~
    CI' ",_~_OUTPUT

    ,.
    AI

    IIilPUT -"""..".... . . JVl,.,.........,


    >'-.... -OU1'UT

    -V......n . . ,00Mlc.tatf.U. ·V".es.nf.r ntH, wtoft. U..


    IMIIIiItdpolVCII'bo ..Itc:....n.rI IIIwn' IIItCI C'plCltDn far ,,01
    forlD··I ...,....... _~ItY. blllp.ntllnsublhty.

    High Pass Active Filter Low Pass Active Filter

    ••
    11151
    AI
    so.
    az
    IIZIIS

    ~"'JVl""'-i______~ZIll2H,.____~'NV·~____•
    ., .. .
    R1
    '.1

    r-·15V .
    RZ
    '00
    T.
    LOAD

    .,
    RZ
    'N •

    10.

    .,
    OUTPUT
    INPUT·-----"""'.....----4~~

    MONITOR
    OUTPUT
    5VfA

    CI
    3UpF

    Current Monitor
    Nonlinear Operational Amplifier with
    Temperature Compensated Breakpoints

    r-----~p-v·

    DI DZ

    INPUTS OUTPUT

    >.;......-OUTPUT "'
    ,oo

    RZ
    3Dpf
    t2
    ."
    Saturating Servo Preamplifier with
    '------_-'v·
    Rate Feedback Power Booster

    AN31-16
    v'

    You,

    Analog Multiplier

    INPUT .....VV\~~

    OUTPUT I

    """ OJ
    LMIOl

    HI
    ..." llV

    15K

    ' - - -....-y-:-l5v
    UK "' "OPlpIIDRdtlIY'PP'n,mltelyZODns
    tDTLoI"TTlllnOYIOflh.H
    MlnllIIlHSI,ayupK'llncl
    ",J

    Long Interval Timer Fast Zero Crossing Detector

    r - -....- - - - -...-DUTPUT

    .,
    "'
    AS
    ~TRANSDUCEA "SnlurOVdO'C
    JllIWfrIllUIIII:YCIIIDH-RICI "
    12'
    "
    ZUx
    tAd,ud'o,IDOraVrC

    -"V--4~-------'

    Amplifier for Piezoelectric Transducer Temperature Probe

    AN31-17
    .,
    1M

    " ., I<

    "
    DIIl",F >.:.......
    -OUTPUT

    IfilPUT--i

    ., "
    h'
    '01'
    .,
    'DO'

    Photodiode Amplifier Photodiode Amplifier High Input Impedance AC Follower

    V+=I5V

    .,.
    1.5M
    I<

    "
    INPUT-.M--4..... --l
    ',.

    ...
    ISM

    "
    JDO,f

    10.A<I'N<II11A
    SenSlI.,.tyIS1Vp!f~de tAVld.ltleilOmTtlhbl,lnc,
    Mlincllester,NH,Typ.OII.
    °Dtllrm,nHUrrenl 101 ze,o
    aCISSIlllannl1l_"a,..A
    "shlMn

    Temperature Compensated Logrithmic Converter

    .,
    "OK
    +15V - -.... -M..--,
    ., ."'"
    '"
    .,
    '"
    .NPUT _"""',.,.....~

    >-"-OUTI'UT

    .,
    'OK ••
    'OK
    Cl
    "
    30Dpf "
    30DpF 30pF

    °tZN3JZ81111tchedPIIiI

    Root Extractor

    AN31-18
    ZNZlZO
    .....
    ,,,

    " J<Vvv-....- - - -.....,.J

    ,,,.
    AI

    Multiplier/Divider

    2NZilZO
    ..
    "M
    1%

    ISv-'l,M. . .- - - - -......'""'

    AI
    "M

    Cube Generator

    AN31-19
    R3
    15011.
    2N2920
    "

    "
    150K

    ."
    1k

    "
    C\
    lDOpF
    "T.HlbITypoQll
    MlnthHl",N,H.

    Fast Log Generator

    E'Uf 1SV
    R3
    150K
    '""
    " "

    """

    "TethlnTypeQIl
    Mlncherte',N,H

    Anti-log Generator

    AN31-20
    »2:
    February 1970 W
    N

    'T1
    m
    FET circuit applications -I
    (")
    ::D
    (")
    C
    ::::j
    »"tI
    .-----4~-oV. "tI
    10M !:
    OUTPUT
    (")
    INPUTo-.... --fI
    ~
    o
    10M
    r-----1~-oOUTPUT
    2:
    en
    R1 2NJ686
    ·Polycarbonlle
    INPUT o-JVVY+-....--,OH-,
    dlelecltlt SAMPLE
    -, r- t15V SAMPLE
    W-15V HOLD

    Sample and Hold With Offset Adjustment JF ET AC Coupled Integrator

    The 2N4339 JFET was selected because of its low This circuit utilizes the "Il-amp" technique to
    IGSS «100 pAl, very-low ID(DF F) «50 pAl and achieve very high voltage gain. Using C, in the cir-
    low pinchoff voltage. Leakages of this level put cuit as a Miller integrator, or capacitance multi-
    the burden of circuit performance on clean, solder- plier, allows this simple circuit to handle very
    resin free, low leakage circu it layout. long time constants.

    RESET

    +JOV
    10.

    2.2M

    .D011J.f

    RIN~
    o---! I--+---+~h
    100M
    CIN::; .25pF
    10M

    OUTPUT
    OUTPUT
    1M I.

    -15V

    Long Time Comparator Ultra-High ZIN AC Unity Gain Amplifier

    The 2N4393 is operated as a Miller integrator. The Nothing is left to chance in reducing input capaci-
    high Vfs of the 2N4393 (over 12,000 Ilmhos @ tance. The 2N4416, which has low capacitance in
    5 mAl yields a stage gain of about 60. Since the the first place, is operated as a source follower
    equivalent capacitance looking into the gate is C with bootstrapped gate bias resistor and drain. Any
    times gain and the gate source resistance can be input capacitance you get with this circuit is due
    as high as 10 Mr!, time constants as long as a to poor layout techniques.
    minute can be achieved.

    AN32-1
    SHUNT
    PEAKING COil

    'V

    1-",,--0 OUTPUT

    2NJB2J

    FET Cascode Video Amplifier JFET Pierce Crystal Oscillator

    The FET cascode video amplifier·features very low The JFET Pierce crystal oscillator allows a wide
    input loading and reduction of feedback to almost frequency range of crystals to be used without cir-
    zero. The 2N3823 is used because ofits low capaci- cuit modification. Since the JFET gate does not
    tance and high Yfs' Bandwidth of this amplifier is load the crystal, good Q is maintained thus insuring
    limited by RL and load capacitance. good frequency stability.

    2M .5V S1

    10M
    S'"
    1V
    OFF
    8M

    5V

    1M
    1M
    "V

    BOOK
    J.3M
    50V 1K

    lOOK

    IOOV

    80K

    500V

    10K

    IOOV

    10K

    FETVM-FET Voltmeter

    This FETVM replaces the function of the VTVM full scale range which is impractical with most vac-
    while at the same time ridding the instrument of uum tubes. The low-leakage, low-noise 2N4340 is
    the usual line cord. In addition, drift rates are far an ideal device for this application.
    superior to vacuum tube circuits allowing a 0.5 volt

    AN32-2
    y.

    OI"F
    INPUTo----1l--...-~>h
    10K

    OJ3",F

    10K

    00331'f DDJ3/JF

    HI-FI Tone Control Circuit (High Z Input)

    The 2N3684 JFET provides the function of a high buffer an op amp·operated feedback type tone
    input impedance and low noise characteristics to control ci rcu it.

    RFC
    '12Yo-_~_.ro"TTL-_o-~)- _ _ _ _ _ _1-'

    'VPAr ---, I
    I
    I
    I
    I
    RFC
    I
    I
    BYPA~ I
    I
    I
    I

    AGe

    100 MHz Converter

    The 2N4416 JFETwil1 provide noise figures of less into an LM171 used as a balanced mixer. This con·
    than 3 dB and power gain of greater than 20 dB. figuration greatly reduces LO. radiation both into
    The JFETs outstanding low crossmodulation and the antenna and into the L F. strip and also reo
    low intermodulation distortion provides an ideal duces RF signal feedthrough.
    characteristic for an input stage. The output feeds

    AN32-3
    ",
    DIFFERENTIAL OUTPUT
    INSTRU~~~~ o--'\I"V'_-'-,

    TOGGLE
    DRIVE - - - TO ADDITIONAL
    _ _ _ MULTIPLEX STAGES

    OIFFERENTlALo---~WIr------'
    ",
    INSTRUMENT Rs
    Rs·SCALING RESISTORS
    INPUTo----WIr-------l

    Differential Analog Switch

    The FM1208 monolithic dual is used in a differ· wide temperature ranges (-25 to +125°C), this
    ential multiplexer application where ROSION) makes it an unusual but ideal choice for an
    should be closely matched. Since RosIO N) for the accurate multiplexer. This close tracking greatly
    monolithic dual tracks at better than ±1% over reduces errors due to common mode signals.

    lK
    ...--'lM,--ot15V

    10K
    1SDK

    01pF
    J"" .Ol;1F

    ~DUTPUT
    004jJF ":'"

    INPUT [O'.....- ...~<+I...., ,. lK

    47'
    22K
    J""
    ""J JJOK

    . .- - - - - - -. .-'\I\I\oo-.()-15V
    IK

    1"'"
    Magnetic-Pickup Phono Preamplifier

    This preamplifier provides proper loading to are· -70 dB (referenced to 10 mV input at 1 kHz) and
    luctance phono cartridge. It provides approximately has a dynamic range of 84 dB (referenced to 1 kHz).
    35 dB of gain at 1 kHz (2.2 mV input for 100 mV The feedback provides for RIAA equalization.
    output). it features S + N/N ratio of better than

    AN 32-4
    '5.
    R2

    R1 BIPOLAR
    IK
    LOGIC
    ELEMENT

    OUTPUT

    MOS
    LOGIC
    elEMENT
    WITH
    NEGATIVE
    SUPPLY

    .y

    Variable Attenuatar Negative to Positive Supply Logic level Shifter

    The 2N3685 acts as a voltage variable resistor with This simple circuit provides for level shifting from
    an ROSION} of 800n max. The 2N3685 JFET will any logic function (such as MOS) operating from
    have linear resistance over several decades of resist- minus to ground supply to any logic level (such as
    ance providing an excellent electronic gain control. TTL) operating from a plus to ground supply. The
    2N3970 provides a low rdslON} and fast switching
    times.

    ZN4391 2N4391
    ...----....--oy.
    VIDEO VIDEO
    INPUT OUTPUT tOM

    2NJ614

    tOM
    1-+--oVOUT
    -IOV

    2N3616
    \
    y" o--f--......lo,,....,)
    \
    ~D""f
    -= \\\M~h----..l Av = ~ = 500 TYPICAL

    \
    ~-
    \
    ---'--0 ~=~

    Voltage Controlled Variable Gain Amplifier Ultra-High Gain Audio Amplifier

    The 2N4391 provides a low ROSION} (less than Sometimes called the "JFET Ii amp," this circuit
    30n). The tee attenuator provides for optimum provides a very low power, high gain amplifying
    dynamic linear range for attenuation and if com· function. Since Ii of a JFET increases as drain cur-
    plete turnoff is desired, attenuation of greater than rent decreases, the lower drain current is, the more
    100 dB can be obtained at 10 MHz providing prop· gain you get. You do sacrifice input dynamic
    er R F construction techniques are employed. range with increasing gain, however.

    \K
    \%

    INPUT

    OUTPUT

    Level-Shifting-Isolation Amplifier

    The 2N4341 JFET is used as a level shifter be· supply voltages. The JFET is ideally suited for this
    tween two op amps operated at different power type of application because 10 = Is.

    AN32-5
    .-"'V\~-o.v

    •sov , - - -....-ov•
    PREBIAS
    LINE
    v,"

    2N2219

    .,v 0-"'-+--"-+--+--
    DTL·TTl
    BIPOLAR
    LOGIC

    -r,lIIlmal. ulthe
    BuTloughseolp.
    Precision Current Sink

    FET Nixie* Drivers

    The 2N3684 JFETs are used as Nixie tube drivers. The 2N3069 JFETand 2N2219 bipolar have inher-
    Their Vp of 2-5 volts ideally matches DTL-TTL ently high output impedance. Using R 1 as a cur-
    logic levels. Diodes are used to a +50 volt rent sensing resistor to provide feedback to the
    prebias line to prevent breakdown of the JFETs. LM10l op amp provides a large amount of loop
    Since the 2N3684 is in a TO-72 (4 lead TO-18) gain for negative feedback to enhance the true cur-
    package, none of the circuit voltages appear on the rent sink nature of this circuit. For small current
    can. The JFET is immune to almost all of the values, the 10k resistor and 2N2219 may be elimi·
    failure mechanisms found in bipolar transistors nated if the source of the JFET is connected to
    used for this application. R1 •

    .---.--o+2DDY

    OUTPUT 0-+-1r----.------,,, +15\1

    +30\1 INPUT

    C1
    Dip"

    r--H--~ 1_
    ~~-----~~~~~o~~~ ·Pol'fCarbonate
    -4-- I
    ,, ,,
    I DETECTOR dlehl"tn.capacitDr

    , I r1 .+16\1 (SAMPLE)
    -l- ....l..- .....J L..J -20V (HOLDI
    -,-
    ,
    T
    Low Drift Sample and Hold
    JFET -Bipolar Cascode Circuit

    The JFET-Bipolar cascode circuit will provide full The JFETs, 0 1 and O2 , provide complete buffer-
    video output for the CRT cathode drive. Gain is ing to C 1 , the sample and hold capacitor. During
    about 90. The cascode configuration eliminates sample, 0 1 is turned on and provides a path,
    Miller capacitance problems with the 2N4091 rds(ON). for charging C 1 • During hold, 0 1 is
    JFET, thus allowing direct drive from the video turned off thus leaving 0 1 IO(OFFI «50 pAl and
    detector. An m derived filter using stray capaci- O2 IGSS «100 pAl as the only discharge paths.
    tance and a variable inductor prevents 4.5 MHz O2 serves a buffering function so feedback to the
    sound frequency from being amplified by the LM10l and output current are supplied from its
    video amplifier. source.

    AN32-6
    +15VON

    -20VOFF

    SIGNAL 0-----'
    >-e---<:> OUTPUT

    '----O+lSV

    = 1-_ _ _ _ _-0 -15V

    Wien Bridge Sine Wave Oscillator JFET Sample and Hold Circuit

    The major problem in producing a low distortion, The logic voltage is applied simultaneously to the
    constant amplitude sine wave is getting the ampli- sample and hold JFETs_ By matching input imped-
    fier loop gain just right_ By using the 2N3069 ance and feedback resistance and capacitance, er-
    JFET as a voltage variable resistor in the amplifier rors due to rdolON) of the JFETs is minimized_
    feedback loop, this can be easily achieved_ The The inherent matched r dolaN) and matched leakage
    LM 103 zener diode provides the voltage reference currents of the FMll09 monolithic dual greatly
    for the peak sine wave amplitude; this is rectified improve circuit performance_
    and fed to the gate of the 2N3069, thus varying its
    channel resistance and, hence, loop gain_

    ,---.--oV'
    100
    1K

    2N5139

    10M
    "---4I~-o VOUT 10M .,,. 1K
    1K

    =
    High Impedance Low Capacitance Wideband Buffer High Impedance Low Capacitance Amplifier

    The 2N4416 features low input capacitance which This compound series-feedback circuit provides
    makes this compound-series feedback buffer a high input impedance and stable, wide-band gain
    wide-band unity gain amplifier. for general purpose video amplifier applications_

    AN32-7
    ",z.V , . . . . - _....- - - - -....- - - - - -. . .-O.I1V

    12K 41K
    41K

    r--~""'--""--4""'O OUTPUT

    2N382l

    Stable Low Frequency Crystal Oscillator o to 360 0 Phase Shifter

    This Colpitts-Crystal oscillator is ideal for low fre- Each stage provides 0 to 1800 phase shift. 8y
    0

    quency crystal oscillator circuits. Excellent stabil- ganging the two stages, 00 to 3600 phase shift is
    ity is assured because the 2N3823 JFET circuit achieved. The 2N3070 JFETs are ideal since they
    loading does not vary with temperature. do not load the phase shift networks_

    r--------..,
    I I

    DTL
    TTL
    INPUT
    CONTROL

    L _________ ..JI
    OM1BDD
    VOLTAGE ADDITIONAL STAGES
    TRANSLATOR IF REQUIRED

    DTL-TTL Controlled Buffered Analog Switch

    This analog switch uses the 2N4860 JFET for its a dual trace oscilloscope chopper. The DM7800
    25 ohm ro N and low leakage. The LM 102 serves monolithic I.C. provides adequate switch drive
    as a voltage buffer. This circuit can be adapted to controlled by DTL-TTL logic levels_

    20 MHz OSCILLATOR VALUES


    Cl ~70DpF II = I.J~H
    C2 = 7SpF L2= 'DT:JII" OIA l/4" lONG
    Voo =16V 10 = , mA

    .....'; ,.i<K...-4J voo 20 ~o: :::~~~~;:: ::::~:::NCE


    2ND HARMONIC - 60 dB
    lRD HARMONIC :- -1D dB

    41pF

    Low Distortion Oscillator

    The 2N4416 JFET is capable of oscillating in a cir- JFET local oscillator is excellent when a low har-
    cuit where harmonic distortion is very low. The monic content is required for a good mixer circuit.

    AN32-8
    .--...-.....,u 2Bpf

    +--:f.JF--tC1 )OUTPUT
    -AGCo-...-'V'VV..........-,/ AGCRANGE59dB
    POWER GAIN 11 dB

    INPUT lo,t--U=-'-
    L1 = Ill .. Hy CENTER TAP
    ':" LZ= O1 ..HyTAP'.4UPFROMGRDUND

    200 MHz Cascode Amplifier

    This 200 MHz JFET cascode circuit features low upper cascode JFET_ The only special requirement
    crossmodulation, large-signal handling ability, no of this circuit is that loss of the upper unit must
    neutralization, and AGe controlled by biasing the be greater than that of the lower unit_

    . - - - - -....--o·v

    OUTPUT

    JOpF

    FET OpAmp

    The FM3954 monolithic-dual provides an ideal teristics of the FM3954 track well over its bias
    low-offset, low-drift buffer function for the current range thus improving common mode
    LM101A op amp_ The excellent matching charac- rejection_

    .v tlDV

    CONDT~e~o-+IIIIIf--;"""''W''''''''''''''''''IO-'ov
    ON +10 lN914 IN914

    OFF_20~FROMDM7800
    IDOpF

    High Toggle Rate High Frequency Analog Switch

    This commutator circuit provides low impedance frequency signal handl ing by providing a low ac
    gate drive to the 2N3970 analog switch for both impedance for off drive and high ac impedance
    on and off drive conditions_ This circuit also ap- for on drive to the 2N3970_ The LH0005 op amp
    proaches the ideal gate drive conditions for high does the job of amplifying megahertz signals_

    AN32-9
    ZN4D91 JFETS

    n-.... -CINPUT I

    1M

    ~-+_-c INPUTZ

    1.

    ~-...-c INPUT 3

    1M
    ,--------,
    I I

    DTL ....-+_--o INPUT4


    TTL
    INPUTS ,.
    •L _____ -.lI L..-------oOUTPUT
    DM710D
    VOLTAGE TRANSLATOR

    4-Channel Commutator

    This 4-channel commutator uses the 2N4091 to from +10V to -20V gate drive to the JFETs while
    achieve low channel ON resistance «30£2) and at the same time providing DTL-TTL logic com-
    low OFF current leakage. The DM7800 voltage patability .
    translator is a monolithic device which provides

    .,
    ZN4392

    DIFFERE~J~~~ o-JV.II.Ir-...------......,~
    ">-....-oVO UT

    t
    "SCALING"
    RESISTORS

    .2
    OIFFERE~:;~i o-Joj."""---+....------......,~
    .3
    .,
    RI =R2
    R3 = R4

    -15V "--....--'
    ADOITIONAL
    CHANNELS

    Wide Band Differential Multiplexer

    This design allows high frequency signal handling up to 1 MHz and MHz signals are possible with this
    and high toggle rates simultaneously. Toggle rates circuit.

    AN32-10
    .,
    POSITIVE 1% "
    INPUTo---4"-W'Ir-+--oTO LOAD
    VOLTAGE

    .,
    100
    1%

    -v

    2N3684

    MONITOR
    OUTPUT
    5V/A
    RI Rl
    VOUl:R'Z'L
    .J
    5K
    1%

    Current Monitor

    R I senses current flow of a power supply. The the output monitor voltage accurately reflects the
    JFET is used as a buffer because ID = Is. therefore power supply current flow.

    10 COMPANION CHANNEL
    FOR STEREO CIRCUIT

    r--~~--"'---""-~~--~-1'--O .ISV

    ,.
    VOLUME
    '.' OUTPUT
    '" lSDK
    50.
    LINEAR
    10.
    LINEAR
    ~
    "M ZN4149
    TAPER TAPER ":'

    Uhf

    lNPUT~
    1M
    68.

    2.2K

    1M

    L-_~~
    lOOK
    -~,p
    ______
    '" -e~~~
    l~:~H~--"M"-"",,,~.
    I
    I
    I
    I
    ,.
    _______ -e_+-~ __
    2N1565

    UK
    ~~-o_ISV

    low Cost High Level Preamp and Tone Control Circuit

    This preamp and tone control uses the JFET to its of less than .05% with a SIN ratio of over 85 dB.
    best advantage; as a low noise high input imped- The tone controls allow 18 dB of cut and boost;
    ance device. All device parameters are non-critical the amplifier has a 1 volt output for 100 mV input
    yet the circuit achieves harmonic distortion levels at maximum level.

    AN32-11
    AI
    . - - - - - - - -. . .--o+IZV

    10K
    10K
    OUTPUT

    2N3565
    v"

    INPUT o-~Pt--v

    v-

    Precision Current Source

    Schmitt Trigger
    The 2N3069 JFET and 2N2219 bipolar serve as
    voltage isolation devices between the output and
    the current sensing resistor, R I . The LM101 pro- This Schmitt trigger circuit is "emitter coupled"
    vides a large amount of loop gain to assure that the and provides a simple comparator action. The
    circuit acts as a current source. For small values of 2N3069 JFET places very little loading on the
    current, the 2N2219 and 10k resistor may be elim- measured input. The 2N3565 bipolar is a high hF E
    inated with the output appearing at the source of transistor so the circuit has fast transition action
    the 2N3069. and a distinct hysteresis loop.

    tSUPPlY

    Gos:5~homlX .

    ...--. .-....,OVOUT

    -IOV

    Low Power Regulator Reference


    High Frequency Switch

    This simple reference circuit provides a stable volt- The 2N4391 provides a low on-resistance of
    age reference almost totally free of supply voltage 30 ohms and a high off-impedance (<'2 pF) when
    hash. Typical power supply rejection exceeds off. With proper layout and an "ideal" switch, the
    100dB. performance stated above can be readily achieved.

    AN32-12
    »
    z
    February 1970 W
    w

    »
    z
    ANALOG-SIGNAL COMMUTATION
    »
    r-
    oG)
    INTRODUCTION MOS IC STRUCTURE
    I

    Telemetry and other data-acquisition systems have MOS IC's generally provide four or more channels
    en
    G)
    become very compact and efficient, particularly in a monolithic chip, but two are enough to illus-
    trate the basic construction that governs switch z
    when built with integrated circuits. To keep in
    step, small, low-power commutators are needed to operation. The cutaway view of Figure 1 shows »r-
    multiplex large numbers of analog signals. Metal- two complete MOSFET's, one of which may be on
    while the other is off. Figure 2 is the schematic. C')
    oxide·semiconductor field·effect transistors do the
    job well. o
    s:
    MOS IC's containing several MOSFET switching s:C
    channels are presently available in production
    quantities and perform excellently as low-level -t
    analog commutators if the system designer under-
    stands their limitations and exploits their advan- ~
    tages. This rep\lrt will describe the DC character- o
    istics involved in switching analog signals when the z
    signal input range varies between -lOV and +10V.
    "SUBSTRATE"OR
    "'ULK" CONNECTION
    MOSFET's size up very well against earlier switch-
    ing devices when their overall characteristics are
    considered (see Table 1 and the discussion of com-
    FIGURE 1. Cross-section of Two MOSFET's in an Inte-
    petitive devices). In addition to being fabricated
    grated Circu it.
    easily as multichannel IC's-in some cases, com-
    plete with switching-control circuitry on the
    chip-MOSFET's have several significant electrical
    advantages:

    ~
    'ULK

    .. Power dissipation is essentially zero in most


    INPUT I
    applications. No DC power is consumed in the
    control gate, and practically no signal power is GATE1~
    dissipated in the switch.
    INPUT 2 OUTPUT
    • Offset voltage is zero in a well-designed switch.
    .. Resistance is reasonably low when the channel GATEZo---I
    is conducting.
    • Resistance of an OFF channel is practically
    FIGURE 2. Schematic Diagram of Two-Channel Analog
    open-circuit (R oFF is on the order of 10 12 Switch.
    ohms and leakage currents are very small. about
    100 pAl. Both MOSFET's have a common substrate, the
    • Analog signals are well isolated from the "bulk" consisting of lightly doped N type silicon.
    switch·control signals. Thermally grown silicon oxide covers the entire
    chip surface, except where the oxide was etched
    With all of these things in their favor, MOS ana- away to allow ohmic connections of input and
    log-switching IC's will come into much wider use, output electrodes to stripes diffused with P+
    especially in large, multichannel instrument~tion dopants. These stripes are the MOSFET drain and
    and data-transmission systems. source regions. Each gate is defined by the gate
    electrode, which lies over a channel region and is
    isolated from it by the oxide (hence, MOSFET's
    N are sometimes called insulated-gate FET's or
    Mechanical a.polar Junction PMOS
    Swltl;:h TranSI$10r Photocell FET FEr IGFET's).
    "On" Rlnlslance 104n Ion I Kn JOn loon
    "Oft" Lukage IOpA l00pA IOnA l00pA 1DOpA All electrodes are etched from a thin film of
    Oflwt Voltage 10-2 V 0 0
    Commutation Rate 1 KHz 100KHz 100Hz lOMHz so MHz deposited aluminum. Each MOSFET has separate
    input and gate electrodes, but the output elec-
    trodes may be paired as shown, connected to a
    Table 1 common output pin, or connected to separate out-
    Comparison of Switches put pins on the package. The same basic MOSFET

    AN33-1
    structure can be used, whether the circuit is a
    differential switch, a multiplexer, or independent
    switches in a single package (see Figure 3).
    "
    ·rtf
    '
    T --,
    +10Y

    ~".
    DATA

    DATA INPUT SWITCH CONTROL


    tlDV SWING +IDV (OFFI
    -20V(ON)

    FIGURE 4. Biases on Single MOS Channel at Maximum


    Signal Range of ±10V.
    BULK BULK
    NOTE PI" 5 tonntcltd to cn'lnd dn.u bul. NOTE Pm 5 clnneelt!! to Cile ind d!YIU bulk
    MM450, MM550 MM451, MMSSI

    The applied biases are those that would be used at


    an analog signal range of ± lOV. At any signal
    " range, the following guidelines apply:
    1. Bulk bias V S s must equal or be more positive
    than the most positive excursion of the analog
    signal. This bias must be maintained at all
    times, so is taken from a DC supply.
    2. To turn the switch ON and make Ro N low, the
    voltage applied to the gate should be at least
    5V more negative than the most negative excur·
    sion of the analog signal (1DV is desirable). The
    actual gate voltage is VG G and the gate bias is
    NOTE. PII" 1 Ind 8 cDnnecltd 10 tnt and dlYlC. bll".
    -VGs,
    MM452,MM552
    3. To ensure that the switch turns OFF fully,
    FIGUR E 3. Connection Diagrams of Dual Differential VGG should be as positive as Vss making
    Switch, Four-Channel Switch and Quad MOS
    V GS = D.
    Transistor.

    The first rule must be followed to get good per·


    MOSFET's are, for practical purposes, bilaterally formance from the switch. With V BB most posi·
    symmetrical. The drain (or source) can be either tive, the p·n junctions are kept reverse·biased.
    the input or output. By strict definition, the drain When the channel is OFF, this condition isolates
    is the electrode to which majority-carrier current the drain from the source. When the switch is
    flows. The majority carriers are "holes" in the turned ON and the P·channel is enhanced, the
    channel of P·channel MOSFET's (N·channel drain·channel·source region is isolated by the p·n
    MOSFET's are not commonly used in MOS IC's). junction from the substrate because the substrate
    In most analog switching applications, the signal is "reverse biased" from all of these regions at all
    contains AC components, so the direction of cur· times.
    rent flow frequently alternates.
    The voltage across the switch, from drain to
    source, is caused by I R drop whether the switch is
    on or off. The MOS analog switch does not have
    SWITCHING AND ISOLATION any inherent offset Voltage. To get V au , = V ,n in a
    MOSFET switch merely requires that load resis·
    A P·channel MOSFET turns on when negative volt· tance R L be much'larger than the resistance in the
    age is applied between gate and source. The gate is conducting channel, Ro N' Since R L is generally
    biased negative with respect to the bulk. Electrons about 100 kilohms in most high·accuracy analog
    accumulate on the gate, creating positive charges commutator applications, the requirement is easily
    in the channel region. This inverts the electric met.
    charge thus creating an "enhanced" P type channel
    in the n·type semiconductor. When the gate is Figure 5 helps clarify rules (2) and (3). This curve
    several volts more negative than threshold, a con· shows how the gate·source threshold voltage
    ducting channel is formed, allowing majority changes with bulk-source bias voltage. Channel re-
    carrier current (holes) to flow freely between sistance is high and current flow at the output can
    source and drain. The channel is said to be "en· only be a few microamperes. A forward bias higher
    hanced," so these MOSFET's are called P·channel than threshold is needed to enhance the channel.
    enhancement MOSFET's. Making gate bias much more negative than VTH at
    turn·ON does this. Then, at turn·OF F, the gate
    bias becomes more positive than VTH when
    Operating voltages in a typical switching channel VGG = VBS' The channel must revert to N·type
    are illustrated in Figure 4. In most schematics, the silicon thus preventing majority carrier current
    bulk connection would not be shown. flow.

    AN33-2
    family of National Semiconductor's
    ./
    V
    MM450/MM550 MOS switching IC's). The "bi-
    • polar" family in Figure 6c shows what happens
    Q
    /
    Q when Vos is allowed to go positive_
    J
    ,: II During small excursions of Vos, the MOSFET acts
    as a voltage-variable resistor. But when Vos rises
    1
    to about +0_6V, there is an abrupt increase in
    drain current. At this point, the diode drop is
    10 15 20
    exceeded and the drain-bulk junction becomes
    YOULK TO SOURCE
    forward biased_ Minority carriers are injected into
    the n-type channel region, causing grounded-base
    pnp bipolar transistor action (note in Figure 1 that
    FIGURE 5. Variation in Switching-Threshold Voltage
    with Changes in Bulk-ta-Source Bias Voltage. a MOSFET resembles a lateral pnp transistor in the
    OFF condition)_ Output current will be c< times
    the input current_ In most MOS devices, the ampli-
    The circuit designer must use biases that prevent fication factor will be 0_5 to 0.9.
    the drain from having a positive potential when
    the switch is OFF. For example, V'" = +10V and It is absolutely mandatory that the V os ~ +0.6V
    V BB = +9V should not be allowed. Operating with be avoided. Otherwise the effective Ro F F will be
    Vos = +1 V won't harm the MOSFET, but some of poor and the channel wi II seem to have abnormally
    the signal will appear at the output. Effects of high leakage current.
    improper biasing can be seen in Figure 6. With
    the source and bulk grounded while Vos varies, Only the upper right corner of the graph in
    output currents at different gate biases are mea- Figure 6b, detailed in the third quadrant of
    sured to produce the "drain family of curves." Figure 6c, is useful in practical circuit designs. The
    The normal family looks like Figure 6b (the drain useful characteristics are to the right of -V os = -1
    and above a load line at about 10 = 0.5 mA.

    ·. ~th
    VD •
    ON AND Ol-F RESISTANCE

    Both Ro Nand Ro F F normally vary with signal


    voltage and operating temperature. A positive
    signal voltage improves channel enhancement by
    6a making the gate more negative with respect to
    drain and source.

    -. ,.... .. Ro N is minimum at the most positive signal level.


    i -10
    l.-
    -&
    -)5
    It will increase slowly with temperature, since high
    !; -'5 temperatures reduce the mobility of majority car-
    ~
    8
    -20 ~ ... riers. Neverthless, RON will have little effect on
    -Z5
    ~"... signal quality if R L is much larger. Ro N does vary
    !: -3D
    ~ -35
    -lZ ? nonlinearly, though, so we investigated its effect
    -1l.5
    ~ -40
    -4. "'"
    l--: p::P
    Vos=-15V
    upon signal quality. Figure 7 proves that the effect

    -50 Total Harmonic Distortion vs VOS


    -100 -BD -60 -40 -20 10
    VIN =-IOV
    Vos - DRAIN TO SOURCE VOLTAGE - VOLTS
    "IN =+10V /
    6b
    /
    Dynamic RON
    I 1/
    I VIN·-5~
    10
    1188=+10V "OUT" +10ifJ , I/VIN=OV -;/
    ./I ~
    Y
    VF-;t~D~ I I
    ~ ......-: ~
    ~~:::: -bZ
    IIi
    11'1') V1N =t5V
    [2_ . VGO=+C
    1M
    ,
    v
    ····i
    Vos - RMS IV)

    t2'l
    , VGO
    Vco
    -0
    '"--5
    FIGURE 7. Small-Signal Harmonic Distortion (Measured
    VGO =-1D with Only About 100 Ohms Load
    Voo 00-20 Resistance).
    10
    -1.0 -0.6 -0.2 +02 +0.6 .1.0
    t:.V 1N (V) is negligible provided that the biasing rules are
    6c observed.

    The curves of small-signal harmonic distortion in


    FIGURE 6. Drain-Current Measuring Circuit, Normal
    Drain Family of Curves, and "Bipolar" Drain Figure 7 were measured with practically no load
    Family of Curves. resistance. AC signals at various voltages were

    AN33-3
    applied to the MOSFET input and the current Worst-case RON can be expected at a -10V input.
    flow was measured at the output with the help of Figure 8 gives the change in RON of the
    a 100-ohm current-sensing resistor_ Distortion MM450/MM550 series devices when the analog
    levels less than 0_ 1% could not be measured with input is at +10V, OV and -10V. If lower imped-
    available instruments. The anomaly in the +10V ance is essential, the gate can be biased more
    curve is due to diode distortion of the type illus- negative. For instance, at V BB = +10V, VGG can
    trated in Figure Bc. The input signal's AC plus DC be made -25V or -30V instead of -20V, in-
    components exceeded the bulk voltage, creasing -VGB to -35V or -40V. Don't go over
    V BB = +10V, by more than the +O.BV diode drop. the specificed maximum bias, which is usually
    -45V, because excessive bias could reduce the
    The harmonic distortion is amply low for practical device operating life.
    applications. With a l-kilohm load, the small-signal
    distortion typically would be less than 0.5%, with Conversely, all biases can be reduced if the signal
    V;n = ±10V and Vas almost ±lV. A load of voltage range is less than ± 1OV. The gate-drive
    1 kilohm is unusually small. Small signal distortion circuit will not have to swing as far, the switch can
    would be almost unmeasurable with a 10-kilohm be operated faster, and switching transients will be
    load_ When signal accuracy must be very high, smaller. Or, the bulk bias can be reduced and the
    100 kilohms are used by some designers. gate bias maintained at the previous ON level. This

    CONDITION I: RONvSVGG Dynamic RON


    ANALOG INPUT VOLTAGE
    AT+1DVOLTS

    VBs a+l0V

    v"
    •1DV
    r
    ur v
    ou, 1.
    T VGC

    CONDITION 2: RONVSVGG Dynamic RON


    ANALOG INPUT VOL lAGE
    ATOVOLTS

    VBs +l0V

    v,.
    . v - w vou ,
    r I "'"
    ...
    T VCG
    .2'00 • •

    "L-~~~~-L-L-L~
    --111
    o --4 -8 -12 -16 -2tI
    VeG (VI

    CONDITION 3: Dynamic RON


    ANALOG INPUT VOL lAGE
    AT -10 VOLTS
    VaB-t,DV

    v"
    -1DV-WVoU,
    r ...s.
    T VC'
    -16 -17 -18 -19 -20
    1DL-L-~~~-L-L-L-L~
    -10 -0,6 -02 +02 +0.6 +1.0
    Vee tV} C.VIN IV)

    FIGURE 8. Typical RON Characteristics of MM450/MM550 MOS Devices at Most Positive, Zero and Most Negative
    Signal Voltages.

    AN33-4
    will give the effect shown in Figure 9-an improve· Channel leakage is measured with the test circuit
    ment in channel enhancement and reductions in in Figure l1a. At V in = +10V, the leakage at the
    RON at the various signal levels. output is at its maximum positive value. As V in
    goes more negative than +10V, channel leakage
    RON vs VGG
    decreases, goes through zero, and becomes negative,
    as in Figure lIb.

    +IDV IOpA
    OUTPUT LEAKAGE
    CURRENT

    -4 -8 -12
    Vee IV)

    FIGURE 9. Bulk Bias Effect on RON.


    -16 -20
    '''iij 11a
    .,0V

    .... OpA

    -8DpA

    11b
    V"

    FIGURE 11. Channel-Leakage Test Circuit and Variation


    When the gate is turned OFF, impedance between in Leakage with Signal Voltage.
    source and drain becomes very high
    (R OFF '" 10 12 ohms). A MOSFET's only signifi·
    cant DC conduction is leakage current. Total The designer of switching systems that require
    leakage in MM450/MM550 devices is typically less very high Ro F F values under all signal conditions
    than 100 pA at 25°C. It rises more rapidly than should anticipate the possibility of worst·case leak·
    age. But average leakage will generally be consider·
    RON with increasing temperature, approximately
    doubling with every 10°C rise in temperature. ably less than worst case. First, leakage currents in
    However, the MM450 devices are low·leakage types each switch are voltage-sensitive, and will be less
    that are specified for use to 125°C. At the maxi· than maximum at signal voltages less than +10V.
    Secondly, when the analog signals on some chan-
    mum temperature, leakage will usually be less than
    nels are positive and those on other channels are
    100 nA. (At very high signal frequencies, another
    negative, the negative currents will subtract from
    conduction mechanism may occur-analog signal
    the positive currents, further reducing the total
    feedthrough in the device capacitances, which can
    leakage at the output. Also, when a switch is ON,
    be prevented by making the gate·driver impedance
    it would not be contributing to the leakage.
    low when the switch is OFF.)
    Assuming signal voltages vary randomly between
    The two significant forms of DC leakage are leak· +10 and -10V, total leakage will run about half
    age from source and drain to bulk, and leakage that of worst case. Of course, leakage will be still
    through the channel from input to output. When less if the analog signal limits are less than ±10V.
    all channels in the multiplexer are OFF, and the
    outputs of each MOSFET are connected to a com· CONCLUSION
    mon package pin, total leakage will be the sum of
    the bulk and channel leakages. Integrated MOSFET switching circuits make ex-
    cellent low-level analog commutators. Power dis-
    Worst·case leakage is measured with the circuit in sipation is essentially zero, capacitance is reason-
    Figure 10. The pin at which the leakage current ably low (typically 8 pF at the analog input). the
    ROFF/RoN ratio is high, and the control signal is
    is measured is biased to -25V and all other pins
    are grounded. This is equivalent to the bulk being isolated from the input. MaS IC's with four or
    biased at +lOV, all gates at +10V, and all analog· more switching channels are readily available in
    signal inputs at +10V, with the output at -15V. production quantities.

    Conventional bipolar drive circuitry can control


    channel switching at rates in the megahertz range.
    Hybrid integrated circuits containing monolithic
    MaS multiplexers and bipolar drivers are being
    manufactured for medium-speed applications
    (i,:HQQ14 and LHOOI9). Level·changing circuits in
    these devices allow external TTL or DTL IC's to
    control the commutator at analog signal levels to
    ±10V. MaS commutator systems can be built with
    building-block circuits such as the MM454F in
    -25V
    Figure 12. This monolithic IC can commutate at
    rates to 1 MHz, depending on the range of signal
    FIGURE 10. Worst·Case Leakage Test Circuit and Typi·
    voltages. The control logic on the chip includes a
    cal Worst-Case Total Leakage of MM451 at clock·countdown chain that facilitates submulti-
    25°C. plexing.

    AN33-5
    low-level commutation: contact bounce, contact
    pitting, susceptibility to vibration, and the neces-
    sity to move a physical mass to turn the switch on
    ANALOG
    OUTPUT or off. It cannot commutate very fast and con-
    sumes more power than a solid-state switch, as a
    rule.

    Bipolar transistors make excellent digital switches,


    the fastest ever developed, but they are usually a
    poor choice for multiplexing low-level analog
    signals. Their main disadvantages are an inherent
    offset voltage and the impossibility of isolating the
    switching control signal from the analog signal
    CLOCK
    OUTPUT being switched. Furthermore, analog switching
    INPUT 4:1
    COUNTDOWN rates are slower than FET's. Their Ron is low,
    though-typically 10 ohms in analog switches
    RESET-----<l>----------' (versus milliohms in power transistors). Bipolar
    transistors fare much better in high-level switching,
    FIGURE 12. Logic Diagram of MM454F Four-Channel where DC offset is not a problem.
    MOS Multiplexer. Switches and Control
    Circuitry Are Fabricated in the Same Mono- Photocells make fairly good analog switches.
    lithic Chip.
    Because light is used as the control signal, the con-
    trol is completely isolated from the analog elec-
    MOSF ET switches are generally used to com- trical signal. However, Ro N is high and the
    mutate low-frequency analog signals. Today, the Ro F F IRa N ratio is relatively poor. Even at
    preferred device for RF-signal multiplexing is the moderate ROFF/RoN ratios, photocells cannot
    N-channel junction FET, which can handle signal commutate much faster than 100 Hz. After ex-
    frequencies in the VHF range. MOS IC's have oper- posure to intense light, a photocell made with a
    ated successfully, however, in some R F applica- semiconductor such as cadmium sulfide or cadmi-
    tion. The high-frequency capabilities of MOS IC's um selenide exhibits a long turn-off decay time.
    are being investigated by the author and will be Photocell turn-off time constants may stretch out
    the subject of a future report. for many seconds before Ro F F reaches an accept-
    able level. Faster switches can be made with com-
    Although the most outstanding feature of binations of electroluminescent diodes and photo-
    MOSFET's is the ease with which they can be fab- transistors, but these devices are still very
    ricated as multichannel monolithic IC's, their elec- expensive.
    trical characteristics compare quite favorably with
    those of other switching components. An "order Some N-channel junction F ET' s come close to
    of magnitude" comparison of MOSFET's and being ideal switches. Offset voltage is zero, and the
    other devices that could be used for low-level admittance-to-input capacitance ratio YIs/C'ss is
    analog switching is given by Table 1. Better char- the highest of any contemporary device. These
    acteristics might be obtained in each case, but two parameters govern commutation rate, which
    these values are typical. can be very high if the impedances of the signal
    source and the load are made very low. Theoreti-
    Each type of analog switch has advantages and cally, the high majority-carrier mobility in an
    limitations that must be considered for practical N-channel J-FET enables it to operate at a fre-
    use. No switch is perfect. If a switch were perfect, quency higher than any other type of FET. A
    it would have zero resistance when ON, infinite good example is the 2N4391: ROFFIRON is
    resistance when OFF, and be 100% efficient-that about 109 , Rds (on) is a maximum of 30 ohms,
    is, it would consume no power. and maximum leakage at 25°C is 100 pA. The one
    major disadvantage of N-channel J-FET's is that
    Electrically, the mechanical switch comes close to they are extremely difficult to make in the form
    thi'i ideal. It has the highest ROFFIRON ratio and of multichannel IC's. For high-frequency com-
    totally isolates the analog signal from the switch- mutation, the P-channel type of J-FET is a poor
    ing-control function. However, it has mechanical choice because its majority carrier mobility is
    drawbacks that make it noisy and unsuitable for lower than N channel J-FET's.

    AN33-6
    »z
    ,
    March 1970 to)
    -!lo

    ::z:
    o
    $.
    HOW TO BIAS THE MONOLITHIC JFET DUAL
    -!
    o
    III
    );
    (f)

    -I
    The National Semiconductor monolithic JFET gate and substrate gate brought out separately. ::z:
    dual is a unique device. Its unusual intertwined The National monolithic JFET dual could be m
    geometry results in a very good matching charac· called a "siamese tetrode". This unique configura·
    s:
    teristic and exceptional thermal tracking character·
    istic plus the fact that its drain currents may be
    t ion p resents several alternatives for proper
    biasing.
    o
    2
    biased over a broad range without seriously affect·
    ing matching and tracking. FMll00 through
    or-
    FM1111, FM1200 through FM1211, and FM3954 BIAS SCHEMES =i
    through FM3958 (similar to 2N3954 through ::z:
    2N3958) are the device numbers for the mono· If the bulk were ohmically connected to each gate,
    lithic JFET dual. all gates would be common. The dual would turn
    n
    into a differential switch, like the one in Figure 2, c..
    '"T1
    A typical National monolithic JFET dual's differ· m
    ential gate matching (t.V Gs ) is less than 10 mV -!
    and temperature drift is typically less than
    101lVtC. What drain current you use for biasing C
    C
    is not critical, so you needn't even bother biasing
    the unit to its zero T.C. drain current, as far as
    »
    r-
    t.V GS matching and tracking are concerned.
    SCALING
    ROS(on)' Yfs, and loss track better than 1% over INPUT RESISTORS OUTPUT
    the full specified temperature range (_55°C to
    +125°C). The FM1100, FM1105, FM1200, and
    FM1205 are specified at 2 mV(max) t.V GS with a
    drift of 5 IlV tC(max). There are specs available
    wh ich are less stringent than these, but many of
    the devices exceed this tough spec.

    In order to obtain this performance advantage over


    separate matched JFET die, the two JFETs must FIGURE 2. Dual Differential Analog Switch.
    be made such that there is one diffused "top" gate
    for each of the devices and a "bulk" gate which is and would not be a true dual. This switch, inciden·
    common to both of the devices. (See Figure 1.) tally, is an excellent application of the FM1100,
    Normally, single triode JFETs have the diffused FM 1200, and FM3954 series. When the gates are
    top gates internally connected to the bulk and this tied externally, the near· perfect match of the
    bulk is used as the gate connectior,. There are a JFETs assures precision in analog switching and
    few tetrode JFETs available with both the diffused mu Itiplexing.

    GATE 1 GATE Z

    ~~~,~~ __~~~~1-__ S0URCE2


    ORAIN 2

    SUBSTRATE

    FIGURE 1. Simplified Section of Monolithic JFET Dual

    AN34-1
    AGC CONTROL Figure 5. Common mode rejection is very poor
    since the bulk gate is degenerative; it could be-
    One of the most obvious uses of the bulk gate is come forward biased on positive common mode
    AGe control because it is almost completely iso- swings and cut off both channels on negative com-
    lated from the signal path_ The bulk bias voltage mon mode swings.
    affects ID' VGSloff), and Yfs ' but it does not
    significantly affect VG S matching and tracking_
    The diffused gates (G I and G2 ) could be called the
    differential mode gates and the bulk could be
    called a common mode gate.

    +v . - - - - ( ) D2 OUTPUT
    .---+----oDI

    G1o--Yt:;-r--;:::t.+----,
    D2
    .----+---0 DI OUTPUT INPUT
    Sl ..........._ .... S2

    G2~------t--------'

    INPUT B
    1-................- - 0 AGC

    G2~---------i-------------J
    FIGURE 5_ Substrate Bias, No Common-Mode Range_

    FIGURE 3_ Automatic Gain Control.


    For comparator applications, the bulk terminal
    may be connected to the comparison voltage along
    with gate 2. If the input varies over many volts (in
    excess of V GS Ioff) l. a 1 M ohm resistor in series
    with gate 1 will prevent excessive gate current in
    the positive gate source forward bias situation or
    the negative gate-bulk reachthrough breakdown
    mode. Reachthrough breakdown will be covered
    later.
    DI v+ D2
    --- --
    +V

    GI G2

    ....-----it--"'-'4t---+-o AGC

    .---~;) D2 OUTPUT
    .---+----~D1

    o INPUT
    1M

    G1

    FIGURE 4_ AGC Connections for Frequencies to 30 MHz.

    OPERATIONAL AMPLIFIER BIASING FIGURE 6_ Biasing for Comparator Applications.

    In operational amplifier applications which do not


    require any common mode rejection, biasing is For special applications where very low leakage is
    fairly simple. The most straightforward biasing desirable, drain-gate voltage should be kept as low
    method is to simply ground the bulk as shown in as possible but in excess of pinchoff and drain

    AN34-2
    current should be at 100/1A or less. Figure 7 uses +V

    the bulk to bias the monolithic JFET dual so that


    gate·source voltage is zero, thus eliminating that
    leakage component. The gates must be operated at
    or very close to ground potential; the LM101A is
    used for feedback biasing to force the source volt· Gl o---'.l~..,
    age to ground, using the bulk gate to control INPUT

    source voltage. G2o----~~-~-~~-~

    +V
    OUTPUT

    0-----002 OUTPUT
    ...- - - + - - - - 0 0 1

    FIGURE 9. Large Common Mode Range Biasing, Com-


    mon Drain.

    If the common drain amplifier configuration is


    preferred, Figure 9 shows how to bias the bulk,
    just use a resistor from each of the sources, they
    should be the same value of course.

    If large differential voltages are to be encountered


    (in excess.of VGS(off») Figure 10 shows how to
    increase gate·bulk reachthrough voltage.
    FIGURE 7. Low·Leakage Substrate Biasing Method.
    The circuit in Figure 10 has a static bias of zero
    volts from gate to bulk, regardless of drain current
    bias. The amplifiers in Figure 8 and 9 will have a
    finite static bias voltage from gate to bulk thus
    BIASING OP AMPS FOR LARGE COMMON reducing the amount of input voltage required to
    cause reachthrough voltage from gate to bulk.
    MODE RANGE
    Figure 10 shows optimum biasing for large dif·
    The simplest bias method to accommodate large ferential signals. Reachthrough breakdown is only
    common mode signals is shown in Figure 8, simply increased, not eliminated; the 10 M.I1 bias resistors
    connect the bulk to the sources for the common will prevent excessive gate to bulk current in the
    source amplifier configuration. reach through breakdown mode.

    +V
    +V

    ...- - - - 0 0 2
    OUTPUT
    . .---+-----001
    "----1------0 OUTPUT

    Gl o--e~h-r_-:::lf,L-...., ..
    Glo---.l~..,
    10M
    INPUT

    G2o------+----~ INPUT
    ~--SS~It:::~-JS2
    10M

    G2o--~---~~----J

    FIGURE 8. Large Common Mode Range Biasing, Com·


    man Source. FIGURE 10. Best Biasing for Large Input Signals.

    AN34-3
    Additional series gate resistance must be used if +10V

    gate source forward bias voltage is likely. These


    resistors will prevent excessive gate source forward
    current. -VG1S~
    r-1 Gs

    REACHTHROUGH VOLTAGE VGS(OFFI for 10:Z: 1 nA VREACHTHROUGH at IG ,,1 J.l.A

    Figure 11 is a simplified cross section of Figure 1. GATE 1 VREACHTHROUGH==!V01SIOfFJI +VGsSIFORWARDI

    If Vb. = 0 and one of the gates is biased toward


    cutoff, channel current will decrease to the pico- VGSSIFORWAADt::>! O.6V
    amp range. If the gate is driven past cutoff, the
    depletion region will reach the bulk and "reach-
    FIGURE 12. Reachthrough in One Half of Dual JFET.
    through" voltage from gate to bulk will be en-
    countered. Figure 12 shows reachthrough is
    greater than VGS(off) and varies from one unit to The circuit designer must also bear in mind reach-
    another just as VGS(off) does. Electrically, reach- through voltage when using large signal AC volt-
    through breakdown is similar to a zener diode
    ages. If instantaneous voltages from gate to bulk
    breakdown, i.e., the gate impedance will rapidly
    are too great, reach through breakdown will occur.
    change from a very high to a very low value. As
    long as the current is 0.1 mA or less, the device
    will not be damaged.

    CONCLUSION
    GATE DRA\'N SDjURCE GATE
    National Semiconductor's monolithic JFET duals
    SDU~ \ / /AIN METAL
    (FMll00 series, FM1200 series, and FM3954

    ~ ~"''''
    c ;""? m

    BULK
    series) can be used in a wide variety of appl ica-
    tions. The bulk gate can be put to advantageous
    use for reducing input gate leakage, AGe opera-
    tion, R F balanced mixer applications, or even dif-
    ferential analog switch usage. All in all, the seven
    terminal monolithic JFET dual is more flexible,
    useful, and economical than a six terminal two
    chip dual. The monolithic dual now allows per-
    FIGURE 11. Simplified erossSection of Monolithic JFET formance levels wh ich were heretofore impossible
    Dual. to achieve.

    AN34-4
    »
    z
    Ronald Stump W
    May 1970 00

    »
    "C
    "C
    !:
    (")

    ~
    o
    APPLICATIONS OF MOS z
    ANALOG SWITCHES en
    o
    ."
    ABSTRACT

    This discussion begins with some basic commuta- MOS switches do have somewhat unique driving
    $:
    tion circuits, then describes some uses in linear requirements. In order to solve this problem, o
    amplifier applications such as reset functions and National manufac.tures a hybrid integrated circuit
    en
    chopper applications. The use of MOS switches as which provides DTL-TTL drive compatibility with »
    :2
    a suppressed carrier double-sideband modulator the dual differential switch. These devices use the
    and a double-sideband demodulator is then cov- DM7801 chip with an MM450 chip for the »
    r
    ered; followed by a circuit proposal for a phase-
    locked loop AM-FM detector without tuned
    LH0014 and the OM7800 chip with an MM450
    chip for the LH0019_ The LH0014 is basically a
    oG)
    circuits. OPDT switch while the LH0019 is two SPOT
    switches in the same package. Each connection has en
    THE MOS DIFFERENTIAL SWITCH-DC TO RF its particular advantages and disadvantages. =E
    The dual differential switch is a particular switch ::::::j
    COMMUTATION CIRCUITS (")
    connection scheme which at first glance prompts
    one to say-so what? It is, however, one of those The LH0014 may be used as a two channel com-
    J:
    m
    simple circuit configurations which can find a wide
    variety of uses in electronic circuits. The dual dif-
    mutator only, because two of its four channels are en
    always on. The LH0019 may be used for systems
    ferential switch could also be called a DPDT with any number of channels since it can shut all
    switch or two SPDT switches-depending on how channels off on command.
    they are toggled_
    Figure 3 shows a six channel commutator which
    MOS switches have some unique features which may be easily expanded. Data sampling may be
    make them very useful for data switching! ,2,3: no done on any format which the user chooses. Sam-
    offset voltage, high Ro F F lRo N ratios, low leak- pling format is easily controlled by DTL or TTL
    age, fast operation, and matched "on" resistance. logic design independent of the LH0019. Since
    Within definite bounds, MOS switches exhibit each buffer-driver of the LH0019 has a dual input
    good isolation between the switching drive and gate, all channel blanking is readily achieved. If
    signal path. desired, the format shown in Figure 3 may be

    =5=:
    0--0 !
    !
    0--0 I
    I
    I

    (al MOS Configuration (b) Schematic Configuration

    FIGURE 1. MM450/MM550 MOS Dual Differential Switch

    AN38-1
    modified so as to use the LH0019 logic inputs as figuration. Demultiplexing may be accomplished
    binary gates which can reduce the command logic by using a circuit identical to the multiplexer
    complexity if the blanking function is not because the MOS device is a true bilateral switch.
    required. In hard·wired systems where the multiplex "out·
    puts" are electrically connected as in Figure 4, the
    Since the multiplexed information is in differential signal may be transmitted in either direction. For
    form, common mode noise is greatly reduced. non-hardwired systems, the modulation-demodula·
    Also, the MOS gate drive spiking is drastically tion sequence is still bilateral, but provisions must
    reduced because of the differential channel con- be made for transmit/receive function control.

    3~,----~---.------------------------------------,

    OUTPUTIN,UriNPUTINPUTINPUTOUT'UT
    1 81 AI AI B2 Z

    5 GNDlo-----------~

    '"

    ANALOG OUTPUT I Vee NC GND N.C. V",~",

    (a) LH0014

    OUTPUT INPUT INPUT


    o Vm'.o. 2 A2 BZ

    l....I-J--.......!.- ANALOG OUTPUT 1 B GNO V pl ., OUTPUT INPUT INPUT


    I AI Bl
    NOTE Alllnpull ~HIGH"

    (b) LH0019

    FIGURE 2. LH0014 and LH0019 OTL·TTL Compatible


    MOS Analog Switches

    AN38-2
    .lltH."~El
    IL.UI~G

    ~~~--------------l

    I ;. 'j CHI

    I
    I

    !}'
    _ _ _ _ _ _ _ _ ...J

    --------~}"'

    I}'
    I
    ________ J

    I
    ________ J

    FIGURE 3. Differential Signal Commutator-LH0019

    '"'I I,"'
    ",[ I,"'
    '"'I I'"
    .
    , [ I,,,

    FIGURE 4. Commutation-Modulation and Demodulation

    AN38-3
    USAGE IN LINEAR AMPLIFIER CIRCUITS LH0014 can greatly reduce component count for
    chopper stabilized amplifiers.
    The LH0014 and LH0019 devices are useful for
    switching functions in linear circuit applications
    because of high off/on resistance ratio and ease of DOUBLE SIDEBAND MODULATOR
    switching control using logic elements. Sample and
    hold circuits, integrator reset switching, and reset The LH0019 can be used as a double sideband
    stabilized amplifiers are a few examples (Figure 5). modulator. In modulator applications, the
    More detailed information on this type of circuitry LH0019 functions as a DPDT switch which alter-
    is available in National Semiconductor applications nately reverses the polarity of the modu lating
    notes ANA, AN-5, AN-20, and AN-29 4 - 7 signal at the chopper frequency. MOS switches
    work quite well at this application because of zero
    An obvious use of the LH0014 and LH0019 are in offset voltage and large signal handling ability.
    chopper stabilized amplifiers (Figure 6). One of
    the better forms of chopper stabilized amplifiers is I n order to build a double sideband balanced
    the series shunt chopper with sample and hold modulator S ,9, one of the two modulating inputs
    type of output. The LH0014 does a good job at must be applied as a balanced input. For the cir-
    this because it contains the complete set of cuit shown in Figure 7, an LM102 and LM107
    switches plus proper drive for the switches. The were used for an audio phase splitter.

    (a) Integrator (b) Reset Stabilized Amplifier

    FIGURE 5. Switching Applications With Linear Circuits

    r-- - - -- - --- -LHOOi4]


    CHOPPER
    ORIVE
    I
    I
    I
    ,------, I
    I

    :~
    INPUT
    I
    L-+-___ ~ OUTPUT

    I
    --.J

    FIGURE 6. Series-Shunt Chopper Stabilized Amplifier

    AN38-4
    Il---.------------------~---------------
    r----------, LI·---4-----.--------------~----~---------

    A~~IO I
    I
    I UOIO

    I Lj-l--I--.-'''4---<> ""'
    I
    I
    I
    ~ _ _ _ _ __ V-_ ~~E~

    FIGURE 7. Double Sideband Modulator-Demodulator

    Both point A and point B in Figure 7 are DSB the switching transients are an "in phase" or
    modulated outputs; so, technically, you could get "common mode" error.
    by with only one. The waveform at point A is
    illustrated in Figure 8a for a carrier frequency of To better illustrate the improvement by using a
    100 kHz and an audio frequency of 12.5 kHz. balanced output, the audio signal was reduced to
    Point B is equal and out of phase. zero volts and the points A, B, and A·B were mea·
    sured as shown in Figure 9. The improvement
    operating in the differential mode is oDvious.
    One type of spurious response encountered with
    MOS switching devices is output spikes caused by The circuit drive requirements for Figure 7 may be
    a charge being dumped into the channel by the simplified by using the LH0014 since it provides
    gate drive through gate·channel capacitance. By an inverting function internally. Only one phase of
    adding Cl, part of the charge can be absorbed, toggle drive to the LH0014 is required.

    Honz.10 n$/cm
    VerI. IV/em

    (al va

    FIGURE 8. Double Sideband Signal

    thus reducing the voltage amplitude of the spikes. The modulation will be distorted more due to the
    The R1Cl combination has its 3 dB point at about phase lag created by the internal inverter of the
    80 kc, so output from the phase spl itter was not LH0014. Figure lOa shows the switching perform·
    attenuated in the audio range. ance of the LH0019 while Figure lOb shows the
    switching performance of the LH0014. In applica·
    The astute observer will notice switching transients tions which do not require high carrier fre·
    on the waveform in Figure 8a. By taking the out· quencies, the LH0014 is adequate, but for carrier
    put in differential form at points A and B, these frequencies above 100 kHz, the LH0019 provides
    transients are greatly reduced because the desired improved performance because of its symmetrical
    signals are equal but of opposite polarity, while switching behavior.

    AN38-5
    Konz. SOns/em
    VIlrt.O.1V/cm

    FIGURE 9. MOS Switching Transients

    (al LH0019 50 ns/cm (bl LH0014 50 ns/cm

    FIGURE 10. Channel Switching-LH0019 vs LH0014

    (al Single Ended Output (bl Differential Output

    FIGURE 11. Demodulator Recovered Output

    DOUBLE SIDEBAND DEMODULATOR These switching transients may be filtered out


    quite easily. It is, however, instructive to compare
    The major requirement of double sideband signal the recovered audio signal with the original. The
    demodulation is proper carrier reinsertion. For modulating signal had less than 0.1% distortion at
    maximum output, the carrier must be reinserted 1 kHz. Figure 12 shows the distortion of the
    exactly in phase or exactly 1800 out of phase with recovered signal vs. signal amplitude.
    respect to the signal. Any departure from this
    optimum phase relationship will reduce the reo Carrier frequency was 100 Hz for the upper curve
    covered signal amplitude. By applying the double and 10kHz for the lower. These curves indicate
    sideband signal to a second LH0019, as shown in that most of the distortion is due to switching
    Figure 7, the original modulating waveform may transients, especially at low modulation levels.
    be recovered, along with some switching transients Output filtering will significantly reduce the reo
    (Figure 11). covered signal distortion.

    AN38-6
    Figure 13 emphasizes the affect that switch ing in·phase (amplitude modulated) and quadrature·
    transients have on harmonic distortion. At carrier phase (frequency modulated) signals plus the
    frequencies below 10 kHz, the RMS value of the feasibility of not using any inductors for tuning.
    transients is reduced to a point where distortion of
    Figure 16 shows the proposed circuit block dia·
    the MOS switches themselves can be seen.
    gram which uses a phase· locked loop for phase
    The LH0014 and LH0019 data sheet suggests a reference signal. The voltage controlled oscillator
    V plus supply value of 10 volts and a V minus (VeO) is operated at 4 fa. Flip Flop #1 provides a
    supply value of -20 volts. However, switching two phase output which is fed into FF #2 and
    transients may be reduced by using different power FF #3. The outputs of FF #2 and FF #3 are
    supply voltages. Figure 14 and Figure 15 show what exactly 900 out of phase regardless of the fre·
    happens to harmonic distortion caused by spiking quency of the veo. This kind of performance is
    versus power supply level. Figure 14 is plotted for awfully hard to achieve using tuned circuits. For a
    V minus with V plus at 10 volts. Figure 15 shows 455 kHz detector, the veo would operate at
    what happens as V plus is varied. All of the pre· 1820 kHz. TTL flip flops will operate quite nicely
    vious data was taken at V plus at 14 volts and V at that frequency and should hold phase shift
    minus at -12 volts. errors to practically zero. The LM 107 provides De
    gain to close the phase·locked loop, it forces the
    veo to a frequency and phase angle which causes
    the "FM out" port to zero volts De; this port is
    AM·FM DEMODULATOR
    then operating exactly in quadrature with the
    Although an AM·FM demodulator was not applied signal. This part of the detector is then
    physically constructed, the previously discussed insensitive to amplitude modulation and sensitive
    "double sideband demodulator" performance to frequency modulation. Since the AM detector
    impl ies that a very interesting phase detector can portion is operating exactly 900 out of phase with
    be built. The interesting features of this type of a the FM portion, its output is insensitive to FM and
    detector are large dynamic range, recovery of both sensitive to AM.

    ".
    10.0 1111
    1111111
    1111111 1111
    ..
    5.'
    11111 111111111
    . fREQAT 1.0 kHz
    z -\ SI'
    c.ARIER AT 100 kHz AND 10 kHz
    z
    0 ,11111 IIIIIIII
    ~ '.0 ~ 4.0
    s'~INAl AT lIJ&~IH!
    =
    Q '.0 IODk~ ~ 3.'
    !E
    ~
    ... i 2.'
    ~
    2.' 10kHz 10
    V
    10. 1000 10,000 100,000
    .01 0.1 I.' 10
    RMS·YOl TS (V) CARRIER FREQ (Hz)

    THERE WAS LITTLE SIGNIFICANT DIFFERENCE IN DISTORTION


    AT SIGNAL AMPLITUDES OF J.QV, I.av, a.lV, a.lv RMS.

    FIGURE 12. Recovered Signal Harmonic Distortion vs FIGURE 13. Recovered Signal Harmonic Distortion vs
    Audio Modulation Level Carrier Frequency

    L - CURVE
    1· NEG.SUPPL Y AT -20V

    ~ POSITIVE SUPPLY AT +IDY ~ '-CURVE 2 NEG.SUPPL Y AT -12V

    ~ 50 ~ 5.0

    ~
    ~
    4.'
    3.'
    2.'
    J...
    ! 4.0
    3.'
    2.'
    I.'
    I.'
    1012141611202Z 20 6.0 10.0 14.0 18.0
    NEGATIVE SUPPLY VOLTAGE IV) POS1T1VE SUPPLY VOLTAGE (VI

    FIGURE 14. Harmonic Distortion vs Negative Power FIGURE 15. Harmonic Distortion vs Positive Supply
    Supply Voltage Voltage

    AN38-7
    FIGURE 16. AM·FM Demodulator

    CONCLUSION 2. D.L. Wollesen, "Analog Signal Commutation",


    National Semiconductor AN·33, February
    The most obvious use of the LH0014 and LH0019 1970.
    is in commutator applications, and it indeed is a
    very useful device for that purpose. The use of 3. D.L. Wollesen, "Analog Switching-High Speed
    these switches in linear circuit applications is also With JFET's", EON, January 15, 1970.
    very attractive because of DTL·TTL control com·
    patibility. There are many more uses of these
    4. R.J. Widlar, "Monolithic Operational Ampli·
    switches possible than the few examples described
    fiers", National Semiconductor AN·4, April
    here.
    1968.
    The unusual application of these devices as sup·
    pressed carrier double·sideband modulators and 5. R.J. Widlar, "Integrated Voltage Follower",
    demodulators suggests applications in servo systems National Semiconductor AN·5, May 1968.
    and even communications systems due to their
    high speed operation. The final circuit suggestion, 6. W.S. Routh, "Applications Guide For Op
    a phase·locked loop AM·FM demodulator without Amps", National Semiconductor AN·20,
    tuned circuits should be very useful in communica· February 1969.
    tions systems. The LH0019 will operate quite well
    at an I F frequency of 455 kHz or less. 7. R.J. Widlar, "I.C. Op Amp Beats FET's On In-
    put Current", National Semiconductor AN-29,
    These basic capabilities of the MOS dual differen· December 1969.
    tial switch should encourage much greater usage
    of this type of device in new product designs. 8. F.E. Terman, Electronic and Radio Engineer-
    ing, McGraw-Hili, New York, 1955.
    REFERENCES
    9. M. Schwartz, Information Transmission Modu-
    1. D. Mrazek, "High Speed MOS Commutators", lation and Noise, McGraw-Hili, New York,
    National Semiconductor AN·28, January 1970. 1959.

    AN38-8
    »
    ;2
    October 1970
    ...~
    '1J
    ::c
    m
    (")
    en
    o;2
    (")
    (")
    PRECISION IC COMPARATOR o
    RUNS FROM 5V LOGIC SUPPLY s:'1J
    »
    ::c
    INTRODUCTION CIRCUIT DESCRIPTION ~
    In digital systems, it is sometimes necessary to In order to understand how to use this compar- o
    convert low level analog signals into digital ator, it is necessary to look briefly at the circuit ::c
    information. An example of this might be a configuration. Figure 1 shows a simplified sche- ::c
    detector for the illumination level of a photo- matic of the device. PNP transistors buffer the c
    diode. Another would be a zero crossing detector z
    for a magnetic transducer such as a magnetometer en
    or a shaft-position pickoff. These transducers have "T1
    low-level outputs, with currents in the low ::c
    microamperes or voltages in the low millivolts. o
    Therefore, low level circuitry is required to
    condition these signals before they can drive logic
    s:
    circuits. U1
    <
    A voltage comparator can perform many of these r-
    precision functions. A comparator is essentially a oc;,
    high-gain op amp designed for open loop opera-
    tion. The function of a comparator is to produce a (")
    logic "one" on the output with a positive signal
    between its two inputs or a logic "zero" with a en
    negative signal between the inputs. Threshold
    c
    '1J
    detection is accomplished by putting a reference '1J
    ~
    voltage on one input and the signal on the other.
    Clearly, an op amp can be used as a comparator, 3••
    except that its response time is in the tens of
    microseconds which is often too slow for many
    appl ications. GROUND

    A unique comparator design will be described here


    along with some of its applications in digital tI"50DpA
    systems. Unlike older IC comparators or op amps,
    it will operate from the same 5V supply as DTL or L-...._ _.... .-_~ ...._ _ _ _ _ v-
    TTL logic circuits. It will also operate with the
    single negative supply used with MOS logic. Hence, FIGURE 1. Simplified Schematic of the Comparator
    low level functions can be performed without the
    extra supply voltages previously required.
    differential input stage to get low input currents
    The versatility of the comparator along with the without sacrificing speed. The PNP's drive a
    minimal circuit loading and considerable precision standard NPN differential stage, Q 3 and Q4' The
    recommend it for many uses, in digital systems, output of this stage is further amplified by the
    other than the detection of low level signals. It can Q S -Q 6 pair. This feeds Q 9 which provides
    be used as an oscillator or multivibrator, in digital additional gain and drives the output stage.
    interface circuitry and even for low voltage analog Current sources are used to determine the bias
    circuitry. Some of these applications will also be currents, so that performance is not greatly
    discussed. affected by supply voltages.

    AN41-1
    by ° °
    The output transistor is 11, and it is protected
    10 and R6 which limit the peak output
    common mode range of the IC. The output will
    directly drive DTL or TTL. The exact value of the
    current. The output lead, since it is not connected pull up resistor, R s , is determined by the
    to any other point in the circuit, can either be speed required from the circuit since it must drive
    returned to the positive supply through a pull-up any capacitive loading for positive-going output
    resistor or switch loads that are connected to a signals. An optional offset-balancing circuit using
    voltage higher than the positive supply voltage. R3 and R4 is included in the schematic.
    The circuit will operate from a single supply if the
    negative supply lead is connected to ground. Figure 3 shows a connection for operating with
    However, if a negative supply is available, it can be MaS logic. This is a level detector for a
    used to increase the input common mode range. photodiode that operates off a -10V supply. The
    output changes state when the diode current
    Table 1 summarizes the performance of the reaches 1 fJ.A. Even at this low current, the error
    comparator when operating from a 5V supply. The contributed by the comparator is less than 1 %.
    circuit will work with supply voltages up to ±15V

    Table 1. Important Electrical Characteristics of the .,


    LM111 Comparator when Operating from
    2.5M
    ••
    1O.
    Single, 5V Supply {TA = 2SoCI.
    TOMOS
    LOGIC
    Limits
    Parameter Units
    Min Typ Max

    Input Offset Voltage 07 3 rnV


    Input Offset Current 4 10 nA
    I nput Bias Current 60 100 nA '--41--6-- '-·-10'
    Voltage Gain 100 V/rnV
    FIGURE 3. Level Detector for Photodiode
    Response Time 200 ns
    Common Mode Range 0.3 3.8 V
    Output Voltage Swing 50 V Higher threshold currents can be obtained by
    Output Current 50 rnA reducing R I, R2 and R3 proportionally. At the
    Fan Out (DTLlTTL) 8 switching point, the voltage across the photodiode
    Supply Current 3 5 rnA is nearly zero, so its leakage current does not cause
    an error. The output switches between ground and
    -10V, driving the data inputs of MaS logic
    directly.
    with a corresponding increase in the input voltage
    range. Other characteristics are essentially un-
    The circuit in Figure 3 can, of course, be adapted
    changed at the higher voltages.
    to work with a 5V supply. At any rate, the
    accuracy of the circuit will depend on the
    LOW LEVEL APPLICATIONS supply-voltage regulation, since the reference is
    derived from the supply. Figure 4 shows a method
    A circuit that will detect zero crossing in the
    output of a magnetic transducer within a fraction
    of a millivolt is shown in Figure 2. The magnetic .,
    u.
    r-----'\M.--. .- -.....~·5.
    r - - - - -...- . .- .....~ •• -5' ••5.
    ...
    .,
    .5
    2.
    TTL
    OUTPUT

    01
    lM113
    TO TTL 120
    .2 LOGIC
    1.

    FIGURE 4. Precision Level Detector for Photodiode

    MAGNETIC of making performance independent of supply


    PICKUP
    voltage. D 1 is a temperature-compensated refer-
    FIGURE 2. Zero Crossing Detector for Magnetic Trans- ence diode with a 1.23V breakdown Voltage. It
    ducer
    acts as a shunt regulator and delivers a stable
    pickup is connected between the two inputs of the voltage to the comparator. When the diode current
    comparator. The resistive divider, R 1 and R 2 , is large enough (about 10 fJ.A) to make the voltage
    biases the inputs 0.5V above ground, within the drop across R 3 equal to the breakdown voltage

    AN41-2
    of D I, the output will change state. R 2 has been make it insensitive to fast noise spikes. Because of
    added to make the threshold error proportional to the low error currents of the LM Ill, it is possible
    the offset current of the comparator, rather than to get input impedances even higher than the
    the bias current. It can be eliminated if the bias 300 kil obtained with the indicated resistor
    current error is not considered significant. values.

    A zero crossing detector that drives the data input The comparator can be strobed, as shown in
    of MOS logic is shown in Figure 5. Here, both a Figure 6, by the addition of 01 and Rs. With a
    logic one on the base of °
    1 , approximately
    2.5 mA is drawn out of the strobe terminal of the
    LM Ill, making the output high independent of
    the input signal.

    Sometimes it is necessary to transmit data between


    TOMOS
    LOGIC digital equipments, yet maintain a high degree of

    ., electrical isolation. Normally, this is done with a


    transformer. However, transformers have problems
    ID'
    with low·duty·cycle pulses since they do not
    preserve the dc level.

    FIGURE 5. Zero Crossing Detector Driving MOS Logic


    The circuit in Figure 7 is a more satisfactory
    method of obtaining isolation. At the transmitting
    positive supply and the -10V supply for MOS
    circuits are used. Both supplies are required for the
    circuit to work with zero common·mode voltage.
    An alternate balancing scheme is also shown in the
    schematic. It differs from the circuit in Figure 2 in
    that it raises the input·stage current by a factor of
    three. This increases the rate at which the input
    voltage follows rapidly·changing signals from
    7V /J.IS to 18V /J.IS. This increased common·mode
    slew can be obtained without the balancing
    potentiometer by shorting both balance terminals
    to the positive·supply terminal. Increased input
    bias current is the price that must be paid for the
    faster operation.
    FIGURE 7. Data Transmission System with Near-Infinite
    Ground Isolation
    DIGITAL INTERFACE CIRCUITS
    Figure 6 shows an interface between high· level
    end, a TTL gate drives a gallium·arsenide light·
    logic and DTL or TTL. The input signal, with OV emitting diode. The light output is optically
    and 30V logic states is attenuated to OV and 5V
    coupled to a silicon photodiode, and the compar·
    by R1 and R 2 • R3 and R4 set up a 2.5V threshold ator detects the photodiode output. The optical
    coupling makes possible electrical isolation in the
    . - - -....- -....- V .. ·5V thousands of megohms at potentials in the
    thousands of volts .
    •J
    82. .&

    ., ---1f-!!
    INPUT-'\M...................

    l40K
    2K

    TO TTL
    The maximum data rate of this circuit is 1 MHz.
    At lower rates ("-200 kHz) R3 and C 1 can be
    eliminated.
    lOGIC

    t1
    .,
    UK TTL
    STROBE MULTIVIBRATORS AND OSCILLATORS
    The free·running multivibrator in Figure 8 is
    another example of the versatility of the compar·
    ator. The inputs are biased within the common
    mode range by R I and R 2 . DC stability, which
    insures starting, is provided by negative feedback
    FIGURE 6. Circuit for Transmitting Data Between High·
    Level Logic and TTL
    through R 3' The negative feedback is reduced at
    high frequencies by C1. At some frequency, the
    positive feedback through R4 will be greater than
    level for the comparator so that it switches when the negative feedback; and the circuit will oscil·
    the input goes through 15V. The response time of late. For the component values shown, the circuit
    the circuit can be controlled with C 1, if desired, to delivers a 100 kHz square wave output. The

    AN41-3
    frequency can be changed by varying C I or by mu Itivibrator, except that the positive feedback is
    adjusting R I through R 4 , while keeping their obtained through a quartz crystal. The circuit
    ratios constant. oscillates when transmission through the crystal is
    at a maximum, so the crystal operates in its
    Because of the low input current of the compar- shunt-resonant mode. The high input impedance
    ator, large circuit impedances can be used. of the comparator and the isolating capacitor, C2 ,
    Therefore, low frequencies can be obtained with
    relatively-small capacitor values: it is no problem
    to get down, to 1 Hz using a 1 jJ.F capacitor. The
    speed of the comparator also permits operation at
    .,
    lOOK
    V+=5V
    ••
    z.
    frequencies above 100 kHz.

    Rl v+· ~v RS
    24K lK

    .3
    IO. .Z >~-"'-DUTPUT
    IDOK

    .3
    so.
    SQUARE
    WAVE
    OUTPUP

    FIGURE 9. Crystal-Controlled Oscillator

    -TTL Of OTl hnout of two

    FIGURE 8. Free-Running Multivibrator


    minimize loading of the crystal and contribute to
    frequency stability. As shown, the oscillator
    delivers a 100 kHz square-wave output.
    The frequency of oscillation depends almost
    entirely on the resistance and capacitor values
    because of the precision of the comparator. Fur- FREQUENCY DOUBLER
    ther, the frequency changes by only 1% for a 10% In a digital system, it is a relatively simple matter
    change in supply voltage. Waveform symmetry is to divide by any integer. However, multiplying by
    also good, but the symmetry can be varied by an integer is quite another story especially if
    changing the ratio of R I to R 2 . operation over a wide frequency range and
    waveform symmetry are required.
    A crystal-controlled oscillator that can be used to
    generate the clock in slower digital systems is A frequency doubler that satisfies the above
    shown in Figure 9. It is similar to the free running requirements is shown in Figure 10. A compar-

    "
    10K

    INPur---+---'''!

    OUTPUT

    FREQUENCY RANGE
    INPUT -5 kHr to 50 IIHI
    OUTPUT-ID kHz 10 100 IIHr

    FIG U R E 10. Frequency Doubler

    AN41-4
    ator is used to shape the input signal and feed it to 10 kn, because the 1 MHz open loop gain of the
    an integrator. The shaping is required because the comparator is about 80 dB. However, this does not
    input to the integrator must swing between the affect the de characteristics and is not a problem
    supply voltage and ground to preserve symmetry unless the input signal dwells within 200 /lV of the
    in the output waveform. An LM108 op amp, that transition level. But if the oscillation does cause
    works from the 5V logic supply, serves as the difficulties, it can be eliminated with a small
    integrator. This feeds a triangular waveform to a amount of positive feedback around the compara-
    second comparator that detects when the wave- tor to give a 1 mV hysteresis.
    form goes through a voltage equal to its average
    value. Hence, as shown in Figure 11, the output Stray coupling between the output and the bal-
    ance terminals can also cause oscillations, so an
    attempt should be made to keep these leads apart.
    FIRST CDMPARATOR rI rI It is usually advisable to tie the balance pins
    OUTPUT ----1 L.....J L together to minimize the effect of this feedback. If
    balancing is used, the same result can be accom-
    INTEGRATOR OUTPUT ~
    plished by connecting a 0.1 /IF capacitor between
    SECOND COMPARATOR - , rI I these pins.
    OUTPUT L-J L...J

    CIRCUIT QUTPUT Ln.JlJ1J Normally, individual supply bypasses on every


    device are unnecessary, although long leads be-
    tween the comparator and the bypass capacitors
    are definitely not recommended. If large current
    FIGURE 11. Waveforms for the Frequency Doubler
    spikes are injected into the supplies in switching
    the output, bypass capacitors should be included
    at these poi nts.
    of the second comparator is delayed by half the
    duration of the input pulse. The two comparator When driving the inputs from a low impedance
    outputs can then be combined through an exclu- source, a limiting resistor should be placed in series
    sive-OR gate to produce the double-frequency with the input lead to limit the peak current to
    output. something less than 100 mAo This is especially
    important when the inputs go outside a piece of
    With the component values shown, the circuit equipment where they could accidentally be
    operates at frequencies from 5 kHz to 50 kHz. connected to high voltage sources. Low impedance
    Lower frequency operation can be secured by sources do not cause a problem unless their output
    increasing both C 1 and C2 . voltage exceeds the negative supply voltage.
    However, the supplies go to zero when they are
    turned off, so the isolation is usually needed.

    APPLICATION HINTS Large capacitors on the input (greater than 0.1 j.LF)
    One of the problems encountered in using earlier should be treated as a low source impedance and
    IC comparators like the LM710 or LM106 was isolated with a resistor. A charged capacitor can
    that they were prone to erratic operation caused hold the inputs outside the supply voltage if the
    by oscillations. This was a direct result of the high supplies are abruptly shut off.
    speed of the devices, wh ich made it mandatory to
    provide good input-output isolation and low- Precautions should be taken to insure that the
    inductance bypassing on the supplies. These oscil- power suppl ies for this or any other IC never
    lations could be particularly puzzling when they become reversed-even under transient conditions.
    occurred internally, showing up at the external With reverse voltages greater than 1 V, the IC can
    terminals only as erratic de characteristics. conduct excessive current, fuzing internal alumi-
    num interconnects. This usually takes more than
    In general, the LMlll is less susceptible to spuri- 0.5A. If there is a possibility of reversal, clamp
    ous oscillations both because of its lower speed diodes with an adequate peak current rating
    (200 ns response time vs 40 ns) and because of its should be installed across the supply bus.
    better power supply rejection. Feedback between
    the output and the input is a lesser problem with a No attempt should be made to operate the circuit
    given source resistance. However, the LMlll can with the ground terminal at a voltage exceeding
    operate with source resistances that are orders of either supply voltage. Further, the 50V output-
    magnitude higher than the earlier devices, so stray voltage rating appl ies to the potential between the
    coupling between the input and output should be output and the V- terminal. Therefore, if the
    minimized. With source resistances between 1 kn comparator is operated from a negative supply, the
    and 10 kn, the impedance (both capacitive and maximum output voltage must be reduced by an
    resistive) on both inputs should be made equal, as amount equal to the voltage on the V- terminal.
    this tends to reject the signal fed back. Even so, it
    is difficult to completely eliminate oscillations in The output circuitry is protected for shorts across
    the linear region with source resistances above the load. It will not, for example, withstand a

    AN41-5
    short to a voltage more negative than the ground The comparator can also be used in many analog
    terminal. Additionally, with a sustained short, systems. It operates from standard ±15V op amp
    power dissipation can become excessive if the supplies, and its dc accuracy equals some of the
    voltage across the output transistor exceeds best op amps. It is also an order of magnitude
    about 10V. faster than op amps used as comparators.

    The input terminals can exceed the positive supply


    The new comparator is considerably more flexible
    voltage without causing damage. However, the
    than older devices. Not only will it drive RTL,
    30V maximum rating between the inputs and the
    DTL and TTL logic; but also it can interface with
    V- terminal must be observed. As mentioned
    MOS logic or deliver ±15V to FET analog
    earlier, the inputs should not be driven more
    switches. The output can switch 50V, 50 mA
    negative than the V- terminal.
    loads, making it useful as a driver for relays, lamps
    or light-emitting diodes. Further, a unique output
    CONCLUSIONS stage enables it to drive loads referred to either
    A versatile voltage comparator that can perform supply or to ground and provide ground isolation
    many of the precision functions required in digital between the comparator inputs and the load.
    systems has been produced. Unlike older compar·
    ators, the IC can operate from the same supply The LM 111 is a plug-in replacement for compar-
    voltage as the digital circuits. The comparator is ators like the LM710 and LM106 in applications
    particularly useful in circuits requiring consider· where speed is not of prime concern. Compared to
    able sensitivity and accuracy, such as threshold its predecessors in other respects, it has many
    detectors for low level sensors, data transmission improved electrical specifications, more design
    circuits or stable oscillators and multivibrators. flexibility and fewer application problems.

    AN41-6
    »
    2
    February 1971 .l=-
    N

    (')

    ."
    IC PROVIDES ON-CARD REGULATION :xl
    o
    FOR LOGIC CIRCUITS <
    C
    INTRODUCTION m
    en
    Because of the relatively high current requirements
    of digital systems, there are a number of problems
    For one, if the series pass transistor is put on the
    chip, the integrated circuit need only have three
    o
    associated with using one centrally-located regu-
    2
    terminals. Hence, an ordinary transistor power I

    lator. Heavy power busses must be used to package can be used. The practicality of this (')
    distribute the regulated voltage. With low voltages approach depends on eliminating the adjustments »
    :xl
    and currents of many amperes, voltage drops in usually required to set up the output voltage and
    connectors and conductors can cause an appre- limiting current for the particular application, as C
    ciable percentage change in the voltage delivered external adjustments require extra pins. A new :xl
    to the load. This is aggravated further with TTL solid-state reference, to be described later, has m
    logic, as it draws transient currents many times the sufficiently-tight manufacturing tolerances that C)
    steady-state current when it switches. output voltages do not always have to be C
    individually trimmed. Further, thermal overload r-
    These problems have created a considerable inter- protection can protect an IC regulator for virtually »
    -f
    est in on-card regulation, that is, to provide local any set of operating conditions, making current-
    regulation for the subsystems of the computer. limit adjustments unnecessary. o
    Rough preregulation can be used, and the power 2
    distributed without excessive concern for line Thermal protection limits the maximum junction
    drops. The local regulators then smooth out the
    voltage variations due to line drops and absorb
    temperature and protects the regulator regardless
    of input voltage, type of overload or degree of
    "o:xl
    transients. heat sinking. With an external pass transistor, there
    is no convenient way to sense junction tempera- r-
    A monolithic regulator is now available to perform ture so it is much more difficult to provide oC)
    this function. It is quite simple to use in that it thermal limiting. Thermal protection is, in itself, a
    requires no external components. The ir,tegrated very good reason for putting the pass transistor on (')
    circuit has three active leads-input, output and the chip.
    (')
    ground-and can be supplied in standard transistor
    power packages. Output currents in excess of 1 A :xl
    can be obtained. Further, no adjustments are When a regulator is protected by current limiting (')
    required to set up the output voltage, and overload alone, it is necessary to limit the output current to C
    protection is provided that makes it virtually a value substantially lower than is dictated by -f
    impossible to destroy the regulator. The simplicity dissipation under normal operating conditions to en
    of the regulator, coupled with low-cost fabrication prevent excessive heating when a fault occurs.
    and improved reliability of monolithic circuits, Thermal limiting provides virtually absolute pro-
    now makes on-card regulation quite attractive. tection for any overload condition. Hence, the
    maximum output current under normal operating
    conditions can be increased. This tends to make up
    DESIGN CONCEPTS for the fact that an IC has a lower maximum
    junction temperature than discrete transistors.
    A useful on-card regulator should include every-
    thing within one package-including the power- Additionally, the 5V regulator works with rela-
    control element, or pass transistor. The author has tively low voltage across the integrated circuit.
    previously advanced arguments against including Because of the low voltage, the internal circuitry
    the pass transistor in an integrated circuit regu- can be operated at comparatively high currents
    lator.' First, there are no standard mUlti-lead without causing excessive dissipation. Both the
    power packages. Second, integrated circuits neces- low voltage and the larger internal currents permit
    sarily have a lower maximum operating tempera- higher junction temperatures. This can also reduce
    ture, because they contain low-level circuitry. This the heat sinking required-especially for com-
    means that an IC regulator needs a more massive mercial-temperature-range parts.
    heat sink. Third, the gross variations in chip
    temperature due to dissipation in the pass transis- Lastly, the variations in chip temperature caused
    tors worsen load and line regulation. However, for by dissipation in the pass transistor do not cause
    a logic·card regulator, these arguments can be serious problems for a logic-card regulator. The
    answered effectively. tolerance in output voltage is loose enough that it

    AN42-1
    is relatively easy to design an internal reference Conditions for temperature compensation can be
    that is much more stable than required, even for derived starting with the equation for the emitter·
    temperature variations as large as 150°C. base voltage of a transistor which is2

    CIRCUIT DESCRIPTION
    The internal voltage reference for this logic·card
    regulator is probably the most significant depar· (1)
    ture from standard design techniques. Tempera· nkT To kT Ie
    ture·compensated zener diodes are normally used +-Iog -+-Iog -
    q 'T q 'leo'
    for the reference. However, these have breakdown
    voltages between 7V and 9V which puts a lower
    Where VgO is the extrapolated energy-band-gap
    limit on the input voltage to the regulator. For low
    voltage for the semiconductor material at absolute
    voltage operation, a different kind of reference is
    zero, q is the charge of an electron, n is a constant
    needed.
    which depends on how the transistor is made
    (approximately 1.5 for double·diffused, NPN
    The reference in the LM 109 does not use a zener
    transistors), k .is Boltzmann's constant, T is
    diode. Instead, it is developed from the highly·
    absolute temperature, Ie is collector current and
    predictable emitter·base voltage of the transistors.
    V BEO is the emitter-base voltage at To and leo.
    In its simplest form, the reference developed is
    equal to the energy·band·gap voltage of the
    semiconductor material. For silicon, this is The emitter-base voltage differential between two
    1.205V, so the reference need not impose mini· transistors operated at different current densities is .
    given by 3
    mum input voltage limitations on the regulator.
    An added advantage of this reference is that the
    output voltage is well determined in a production kT J,
    Ll VB E = - log, - , (2)
    environment so that individual adjustment of the q J2
    regulators is frequently unnecessary.
    where J is current density.
    A simpl ified version of this reference is shown in
    Figure 1. In this circuit, 0, is operated at a Referring to Equation (1), the last two terms are
    quite small and are made even smaller by making
    Ie vary as absolute temperature. At any rate, they
    v' can be ignored for now because they are of the
    same order as errors caused by nontheoretical
    behavior of the transistors that must be deter·
    mined empirically.

    If the reference is composed of VB E plus a voltage


    proportional to Ll VB E, the output voltage is
    obtained by adding (1) in its simplified form to
    (2):

    """'-"'--"'--4"" GROUND

    Figure 1. The Low Voltage Reference in One of Its Simpler Differentiating with respect to temperature yields
    Forms.
    a Vr,f VgO V BEO
    - - = - - + - - +-Iog. - .
    k J,
    (4)
    relatively high current density. The current density aT To To q J2
    of O 2 is about ten times lower, and the
    emitter·base voltage differential (Ll VBE) between
    the two devices appears across R3 . If the For zero temperature drift, this quantity should
    transistors have high current gains, the voltage equal zero, giving
    across R2 will also be proportional to LlV BE . 0 3 is
    a gain stage that will regulate the output at a kTo J,
    VgO = V BEO + - log, - . (5)
    voltage equal to its emitter base voltage plus the q J2
    drop across R2 . The emitter base voltage of 0 3 has
    a negative temperature coefficient while the LlV BE The first term on the right is the initial emitter·base
    component across R2 has a positive temperature voltage while the second is the component
    coefficient. It will be shown that the output proportional to emitter-base voltage differential.
    voltage will be temperature compensated when the Hence, if the sum of the two are equal to the
    sum of the two voltages is equal to the energy· energy·band·gap voltage of the semiconductor, the
    band·gap voltage. reference will be temperature·compensated.

    AN42-2
    A simplified schematic for a 5V regulator is given the output voltage is developed across Ra by the
    in Figure 2. The circuitry produces an output collector current of 0 7 , The emitter·base voltage
    voltage that is approximately four times the basic differential is produced by operating 0 4 and 0 5 at
    reference voltage. The emitter·base voltage of 0 3 , high current densities while operating 0 6 and 0 7
    0 4 , 0 5 and Oa provide the negative·temperature· at much lower current levels. The extra transistors
    coefficient component of the output voltage. The improve tolerances by making the emitter·base
    voltage dropped across R3 provides the positive· voltage differential larger. R3 serves to compensate
    temperature·coefficient component. 0 6 is oper· the transconductance 4 of 0 5 , so that the Ll V BE
    ated at a considerably higher current density than component is not affected by changes in the
    0 7 , producing a voltage drop across R4 that is regulator output voltage or the absolute value of
    proportional to the emitter·base voltage differ· components.
    ential of the two transistors. Assuming large
    current gain in the transistors, the voltage drop The voltage gain for the regulating loop is provided
    across R3 will be proportional to this differential, by a, 0, with Og buffering its input and 0" its
    so a temperature·compensated·output voltage can output. The emitter base voltage of 0 9 and 0, a is
    be obtained. added to that of 0'2 and 0'3 and the drop across
    Ra to give a temperature·compensated, 5V output.
    An emitter·base·junction capacitor, C" frequency
    compensates the circuit so that it is stable even
    without a bypass capacitor on the output .
    .----&----o----IH'UT
    The active collector load for the error amplifier is
    '~ 0 17 , It is a multiple-collector lateral PNP4. The
    output current is essentially equal to the collector
    ~-O-YoJ'\00-4>-~)-OUTPUT current of O 2, with current being supplied to the
    zener diode controlling the thermal shutdown, D2 ,
    by an auxiliary collector. a, is a collector FET4
    that, along with R" insures starting of the
    regulator under worst·case conditions.

    The output current of the regulator is limited


    when the voltage across R'4 becomes large enough
    to turn on 0,4' This insures that the output
    current cannot get high enough to cause the pass
    transistor to go into secondary breakdown or
    damage the aluminum conductors on the chip.
    Further, when the voltage across the pass transis·
    tor exceeds 7V, current through R'5 and D3
    reduces the limiting current, again to minimize the

    L - -....--C~--. .---GROUIllD ,---t'----t---.,---.,--t-'NPUT

    Figure 2. Schematic Showing Essential Details of The 5V


    Regulator.

    !J------t'--1--+---t- OUTPUT
    In this circuit, Oa is the gain stage providing
    regulation. Its effective gain is increased by using a
    vertical PNP, 0 9 , as a buffer driving the active
    collector load represented by the current source.
    0 9 drives a modified Darlington output stage (0, D.
    and O2 ) which acts as the series pass element. With 6lV

    this circuit, the minimum input voltage is not


    limited by the voltage needed to supply the
    reference. Instead, it is determined by the output
    voltage and the saturation voltage of the Darling·
    ton output stage. L---<~~_""'--+-~-""'-""-~GROUNO

    Figure 3 shows a complete schematic of the


    LM109, 5V regulator. The LlV BE component of Figure 3. Detailed Schematic of The Regulator.

    AN42-3
    chance of secondary breakdown. The performance protect the load from damage. The regulator is
    of this protection circuitry is illustrated in also designed so that it is not damaged in the event
    Figure 4. the unregulated input is shorted to ground when
    there is a large capacitor on the output_ Further, if
    the input voltage tries to reverse, D, will clamp
    this for currents up to 1A_
    • It- t'--...
    ~5°~_ The internal frequency compensation of the
    os , regulator permits it to operate with or without a
    Ii t'--... T.=25°C
    ~ bypass capacitor on the output. However, an
    ""i--..
    I z
    r-..
    output capacitor does improve the transient
    response and reduce the high frequency output
    ~ 1
    NilS"''::
    .,....... impedance_ A plot of the output impedance in
    '-TO-'
    I Figure 5 shows that it remains low out to 10 kHz
    VOUT = 4.5V
    I even without a capacitor. The ripple rejection also
    0
    , ZO Z5 30 35 remains high out to 10 kHz, as shown in Figure 6.
    " IS
    INPUT VOL TACE tV) The irregularities in this curve around 100 Hz are
    caused by thermal feedback from the pass transis-
    Figure 4. Current·Limiting Characteristics. tor to the reference circuitry. Although an output
    capacitor is not required, it is necessary to bypass
    the input of the regulator with at least a O.22I1F
    capacitor to prevent oscillations under all con-
    Even though the current is limited, excessive ditions.
    dissipation can cause the chip to overheat. In fact,
    the dominant failure mechanism of solid state
    regulators is excessive heating of the semicon-
    ductors, particularly the pass transistor. Thermal
    protection attacks the problem directly by putting
    a temperature regulator on the IC chip. Normally,
    this regulator is biased below its activation
    threshold; so it does not affect circuit operation.
    However, if the chip approaches its maximum
    operating temperature, for any reason, the temper-
    ature regulator turns on and reduces internal
    1~' L-~ __~__-L__~--J
    dissipation to prevent any further increase in chip 10 100 til IDle lOOk 1M
    temperature. fREOUENCY IHtl

    The thermal protection circuitry develops its Figure 5. Plot of Output Impedance As A Function of
    reference voltage with a conventional zener diode, Frequency.
    D2 . 0 '6 is a buffer that feeds a voltage divider,
    delivering about 300 mV to the base of Q'5 at
    175°C. The emitter-base voltage, 0 ,5 , is the actual 100
    temperature sensor because, with a constant /N\ I
    voltage applied across the junction, the collector lii. -4'\..l.....+..,T,.."·C
    TJ.25~ ~
    current rises rapidly with increasing temperature.

    Although some form of thermal protection can be ;.


    '"
    T.-151ft ' \ . ~

    \~
    ~ ..
    incorporated in a discrete regulator, IC's have a \.
    distinct advantage: the temperature sensing device IL=2DOmA
    V1N"'DV
    detects increases in junction temperature within 6V 1N =3V IOP
    ZDL.~"":..J. __..L__.L.......J
    milliseconds. Schemes that sense case or heat-sink 10 100 IK 10K lOOK 1M
    temperature take several seconds, or longer. With FREQUENCY IHd
    the longer response times, the pass transistor
    usually blows out before thermal limiting comes Figure 6. Ripple Rejection of The Regulator.
    into effect.

    Another protective feature of the regulator is the


    crowbar clamp on the output. If the output Figure 7 is a photomicrograph of the regulator
    voltage tries to rise for some reason, D4 will break chip. It can be seen that the pass transistors, which
    down and limit the voltage to a safe value. If this must handle more than 1A, occupy most of the
    rise is caused by failure of the pass transistor such chip area. The output transistor is actually broken
    that the current is not Iimited, the aluminum into segments. Uniform current distribution is
    conductors on the chip will fuse, disconnecting the insured by also breaking the current limit resistor
    load. Although this destroys the regulator, it does into segments and using them to equalize the

    AN42-4
    currents. The overall electrical performance of this Although the LM 109 is designed as a fixed 5V
    Ie is summarized in Table 1. regulator, it is also possible to use it as an
    adjustable regulator for higher output voltages.
    One circuit for doing this is shown in Figure 9.

    OUTPUT

    Figure 9. Using The LM109 As An Adjustable·Output


    Regulator.

    The regulated output voltage is impressed across


    R1 , developing a reference current. The quiescent
    current of the regulator, coming out of the ground
    terminal, is added to this. These combined
    Figure 7. Photomicrograph of The Regulator Shows That currents produce a voltage drop across R2 which
    High Current Pass Transistor (Right) Takes More raises the output voltage. Hence, any voltage above
    Area Than Control Circuitry (Left). 5V can be obtained as long as the voltage across
    the integrated circuit is kept within ratings.
    PARAMETER CONDITIONS TVP
    The LM109 was designed so that its quiescent
    Output Voltage 5.0V current is not greatly affected by variations in
    Output Current 1.5A input voltage, load 9r temperature. However, it is
    not completely insensitive, as shown in Figures 10
    Output Resistance 0.03f!
    and 11, so the changes do affect regulation
    Line Regulation 7.0V$. V 1N ~35V O.OO5%1V
    somewhat. This tendency is minimized by making
    Temperature Drift _55°C S T A S 125°C o.o2%lC the reference current through R 1 larger than the
    Minimum Input Voltage lOUT'" lA 6.5V quiescent current. Even so, it is difficult to get the
    Output NOise Voltage 10 Hz ~ f ~ 100 kHz 40~V regulation tighter than a couple percent.
    Thermal Resistance
    Junction to Case
    LM109H (TO·51
    LM109K (TO·31
    15°CIW
    3°C/W
    . I 'L = 200 mA

    1
    - T,I.,,!.
    Table 1. Typical Characteristics of The Logic-Card Regu-

    I
    lator: TA = 2SoC. S.S
    '.=_55°C
    I--T'
    ~
    z
    ~ SA iJ I
    APPLICATIONS
    Because it was designed for virtually foolproof
    operation and because it has a singular purpose,
    ~
    •.S
    - l - f- T!.150°C
    ~ T
    -
    10 15 20 25
    the LM109 does not require a lot of application INPUT VOLTAGE (V)
    information, as do most other linear circuits. Only
    one precaution must be observed: it is necessary to
    Figure 10. Variation of Quiescent Current With Input
    bypass the unregulated supply with a 0.22 !.IF Voltage At Various Temperatures.
    capacitor, as shown in Figure 8, to prevent
    S.D

    OUTPUT
    I VIN = 10V

    !
    =
    =
    ~
    z S.S "l. H--
    ..... ,.... ~~
    ~

    ~ I IL=I~~
    50
    i1i
    ~ I ~
    Figure 8. Fixed 5V Regulator

    oscillations that can cause erratic operation. This,


    . -15-50-250
    I
    2550 7510D12515O
    JUNCTION TEMPERATURE (OCI
    of course, is only necessary if the regulator is
    located an appreciable distance from the filter Figure 11. Variation of Quiescent Current With Tempera-
    capacitors on the output of the dc supply. ture For Various Load Currents.

    AN42-5
    The LM 109 can also be used as a current regulator bypassing the non·inverting input to ground. A
    as is shown in Figure 12. The regulated output 100 pF capacitor should also be included between
    voltage is impressed across R" which determines the output and the inverting input to prevent
    the output current. The quiescent current is added frequency instability. Temperature drift can be
    to the current through R,. and this puts a lower reduced by adjusting R 4 , which determines the
    limit of about 10 mA on the available output zener current, for minimum drift. For best
    current. performance, remote sensing directly to the load
    terminals, as shown in the diagram, should be
    used.
    INPUT
    CONCLUSIONS
    ., The LM 109 performs a complete regulation
    '---+-OUTPUT function on a single silicon chip, requiring no
    external components. It makes use of some unique
    advantages of monol ithic construction to achieve
    Figure 12. Current Regulator. performance advantages that cannot be obtained
    in discrete-component circuits. Further, the low
    cost of the device suggests its use in applications
    The increased failure resistance brought about by where single'point regulation could not be justified
    thermal overload protection make the LM 1 09 previously.
    attractive as the pass transistor in other regulator
    circuits. A precision regulator that employs the IC Thermal overload protection significantly im-
    thusly is shown in Figure 13. An operational proves the reliability of an IC regulator. It even
    ampl ifier compares the output voltage with the protects the regulator for unforseen fault condi-
    output voltage of a reference zener. The op amp tions that may occur in field operation. Although
    controls the LM 109 by driving the ground this can be accomplished easily in a monolithic
    terminal through an FET. regulator, it is usually not completely effective in a
    discrete or hybrid device.

    The internal reference developed for the LM 109


    also advances the state of the art for regulators.
    Not only does it provide a low voltage, tempera-
    ture-compensated reference for the first time, but
    also it can be expected to have better long term
    stability than conventional zeners. Noise is in-
    herently much lower, and it can be manufactured
    to tighter tolerances.

    REFERENCES
    1. R.J. Widlar, "Designing Positive Voltage Regu-
    lators," EEE, Vol. 17, No.6, pp.90-97,
    June 1969.

    2. J.S. Brugler, "Silicon Transistor Biasing for


    Linear Collector Current Temperature Depen-
    dence," IEEE Journal of Solid State Circuits,
    pp. 57-58, June, 1967.

    3. R.J.Widlar, "Some Circuit Design Techniques


    Figure 13. High Stability Regulator. for Linear Integrated Circuits," IEEE Trans. on
    Circuit Theory, Vol. Xll, pp.586-590,
    December, 1965.
    The load and line regulation of this circuit is better
    than 0.001 %. Noise, drift and long term stability 4. R.J. Widlar, "Design of Monolithic Linear
    are determined by the reference zener, 0,. Noise Circuits," Handbook of Semiconductor Elec-
    can be reduced by inserting 100 H2, 1% resistors tronics, Chapter X, pp 10.1-10.32, L.P. Hunter,
    in series with both inputs of the op amp and ed., McGraw-Hili Inc., New York, 1970.

    AN42-6
    Thomas B. Mills
    June 1971

    -I
    :t:
    m
    "tI
    :t:
    THE PHASE LOCKED LOOP I C AS A »
    en
    COMMUNICATION SYSTEM BUILDING BLOCK m
    .-o
    INTRODUCTION
    (')
    The phase locked loop has been found to be a
    useful element in many types of communication
    systems. It is used in two fundamentally different
    The output of the VCO is related to its input
    control voltage by "
    m
    C
    ways: (1) as a demodulator, where it is used to
    follow phase or frequency modulation and (2) to
    (4) .-o
    track a carrier or synchronizing signal which may for ef = 0, let 02 = wO, then o
    vary in frequency with time. "tI
    (5)
    When operating as a demodulator, the phase locked (')
    loop may be thought of as a matched filter oper-
    ating as a coherent detector. When used to track a
    It can be seen that the action of the VCO is that
    of an integrator in the feedback loop when the
    »en
    carrier, it may be thought of as a narrow-band phase locked loop is considered in servo theory.
    filter for removing noise from a signal.
    A better understanding of the operation of the
    »
    (')
    Recently, a phase locked loop has been built on a loop may be obtained by considering that initially,
    o
    monolithic integrated circuit, incorporating the
    basic elements necessary for operation: a double
    the loop is not in lock, but that the frequency of
    the input signal ej and VCO eo are very close in s:
    balanced phase detector and a highly linear voltage
    controlled oscillator, the frequency of which can
    frequency. Under these conditions ed will be a
    beat note, the frequency of which is equal to the
    s:c
    be varied with either a resistor or capacitor. frequency difference of eo and ej. This signal is z
    also applied to the VCO input, since it is low (')
    BASIC PHASE LOCK LOOP OPERATION enough to pass through the filter. The instantan- »
    Figure 1 shows the basic blocks of a phase locked
    eous frequency of the VCO is therefore changing
    ~
    ioop. The input signal ej is a sinusoid of arbitrary
    and at some point in time, if the VCO frequency
    o
    frequency, while the VCO output signal, eo, is a
    equals the input frequency, lock will result. At
    this instant, ef will assume a level sufficient to
    z
    sinsuoid of the same frequency as the input but of hold the VCO frequency in lock with the input en
    arbitrary phase. If frequency. If the tuning of the VCO is changed -<
    en
    (such as by varying the value of the tuning capa-
    ej =.,f2 Ej [sinwot+Ol(t)] (1) -I
    citor) the frequency output of the VCO will m
    eo =.,f2 Eo [sin wot+ 02(t)] (2) attempt to change; however, this will result in an
    instantaneous change in phase angle between ej and
    s:
    eo, resulting in a change in the dc level of ed which a:J
    the output of the multiplier (phase detector) is C
    will act to maintain frequency lock: no average
    ed = ej . eo = 2E jEo sin [wot + 0l(t)] frequency change will result. .-C
    cos [wot + 02(t)] Similarly, if ej changes frequency, an instantaneous Z
    = EjE o sin [alIt) - 02(t)]
    change will result in a phase change between ej and Q
    + sin [2 wot + ° (t) + 02(tl]
    1 (3)
    eo and hence a dc level change in ed. This level
    shift will change the frequency of the VCO to
    .-a:J
    the low pass filter of the loop removes the ac
    maintain lock.
    o(')
    components of the multiplier output; the dc term The amount of phase error resulting from a given
    is seen to be a function of the phase angle between
    the VCO and the input signal.
    frequency shift can be found by knowing the
    "dc" loop gain of the system. Considering the
    phase detector to have a transfer fu nction:
    "
    INPUT

    and the voltage controlled oscillator to have a


    transfer function:

    FIGURE 1. Basic Phase Locked Loop (6)

    AN46-1
    or taking the Laplace transform scribed above, but the "ac" or transient perform-
    ance which is governed by the components of the
    loop filter pi aced between the phase detector and
    (7) the voltage controlled oscillator. In fact, it is this
    loop filter that makes the phase locked loop so
    the phase of the VCO output will be propor- powerful: only a resistor and capacitor are all that
    tional to the integral of the control voltage. is needed to produce an arbitrarily narrow band-
    width at any selected center frequency.
    Combining these equations:
    The simplest filter is a single capacitor, Figure 2,
    KoKd F(s) and is used for wide bandwidth applications, such
    (8)
    s + KoKo F(s) as where wideband data modulation must be
    followed. The transfer function of the filter is
    8 ds) - 8 2 (s) simply:
    (9)
    8, (s) s + KoKo F(s)
    (13)
    Application of the final value theorem of Laplace
    transforms yields
    substitution into (8) results in

    (10) (14)

    With a step change in phase of the input 118" the


    Laplace transform of the input is 7, = R,C,

    118, In terms of servo theory, the damping factor and


    0, (s) = -s- which gives !:Ie(s) = 0, (s) - 02(S)
    natural frequencies are
    5118,
    lim !:Ie(t) = lim s + KoKo F(s) = 0 (11)
    t-)ooo s-+o KOKO] '/2
    [ (15)
    R,C,
    the loop will eventually track out any change of
    input phase, and there will be no phase error in
    the steady state solution. 1 ] '/2
    [ (16)
    2 (R,C, KoKo)
    If the input is a step in frequency, of magnitude
    11w, the change in input phase will be a ramp:

    0, (s) = 11w/s2

    substitution of this value 0, into (10) results in

    11w 11w
    lim 0e(t) = lim s + KoKo F(s) KoKo F(o) (12)
    t-+ oo 5-+0

    this result shows the resulting phase error is


    dependent on the magnitude of the frequency
    step and the "dc" loop gain KoKo, which is also
    called the velocity error coefficient Kv' It should
    be noted that the dimensions of KoKo are 1Isec. z
    This can also be seen by considering Ko = volts/ Ii
    radian, while Ko = radians/sec/volt. The product is

    volts radians/sec
    radian x volt sec

    this can be thought of as the "dc" loop gain. (Note


    FIGURE 2. Phase Locked Loop with Simple Filter
    that additional dc gain between the phase detector
    and the voltage controlled oscillator will increase
    the loop gain and hence reduce the steady state
    phase error resulting from a change in frequency From this it can be seen that large time constants
    of the input.) for R,C, or high loop gain will reduce the damping
    factor and hence decrease stability. Therefore, if a
    THE LOOP FILTER narrow bandwidth is desired, the damping factor
    will become very small and instability will result.
    In working with phase locked loops, it is necessary It is not possible to adjust bandwidth, loop gain,
    to consider not only the "dc" performance de- and damping independently with this simple filter.

    AN46-2
    With the addition of a damping resistor R2 as
    shown in Figure 3, it is possible to choose band·
    width, damping factor and loop gain independently;
    the transfer function of this filter is

    (17)

    the loop transfer function becomes:

    FIGURE 4. Filter Time Constant vs Natural Frequency

    (18)

    the loop natural frequency is

    (19)

    while the damping factor becomes

    (20)
    FIGURE 5. Damping Time Constant vs
    Natural Frequency
    (21)

    DESIGN CONSIDERATIONS

    Considering the above discussion, there are really


    two primary considerations in designing a phase
    locked loop. The use to which the loop is to be put
    will affect the design criterion of the loop com·
    ponents. The two primary factors to consider are:
    T1- R1C1 Tz"RZCI
    1. Loop gain. As pointed out previously, this
    affects the phase error between the input signal
    and the voltage controlled oscillator for a given
    frequency shift of the input signal. It also deter·
    mines the "hold in range" of the loop providing
    no components of the loop go into limiting or
    saturation. This is because the loop will remain
    in lock as long as the phase difference between
    the input and the VCO is less than ±90°. The
    higher the loop gain, the further the input can
    change in frequency before the 900 phase error
    is reached. The hold in range is

    (22)
    FIGURE 3. Phase Locked Loop with Damping
    Resistor Added
    (providing saturation or limiting does not
    occur).

    In practice, for a fixed loop gain KoKo, the natural 2. Natural Frequency. The bandwidth of the loop
    frequency of the loop may be chosen and will be is determined by the filter components R" R,
    dependent mainly on 7" since 72 « 7 , in most and C, and the loop gain. Since the loop gain
    cases. Then, according to (21), damping may be is normally selected by the criterion in 1. above,
    determined by 72 and for all practical purposes, the filter components are used to select the
    will be an independent adjustment. These equa· bandwidth. The selection of loop bandwidth
    tions are plotted in Figures 4 and 5 and may be may be governed by several things: noise band·
    used for design purposes. width, modulation rates if the loop is to be

    AN46-3
    used as an FM demodulator, pull-in time and
    D.1
    \"=0.3
    hold-in range_ There are two conflicting require- "'<
    t ~ U.5
    ments that will have an affect on loop band-
    width: ~~
    , 0
    D.'

    D.3
    "'" !\-t=
    ~
    r,;
    0.701

    N
    (a) Loop bandwidth must be as narrow as
    possible to minimize output phase jitter
    =
    = ., r=5.D
    ~ "2.0

    t"l.0
    due to external noise_ -0.1
    /
    (b) The loop bandwidth should be made as -0.3
    large as possible to minimize transient error D 1 2 3
    wo'
    ••• 1 8

    due to signal modulation, output jitter due


    to internal oscillator (VeO) noise, and to
    obtain best tracking and acquisition pro- FIGURE 7. Transient Phase Error lie(d Due to a Step
    perties_ in Frequency b.w. ISteady-State Velocity
    Error, b.w/K v, Neglected.1
    These two principles are in direct opposition and,
    depending on what it is that the loop is to accom-
    plish, an optimum solution will lie somewhere There is some frequency-step limit below which
    between the two extremes_ the loop does not skip cycles, but remains in
    lock, called the "pull-out frequency" wpo' Viterbi
    If the phase locked loop is to be used to demodu-
    has analyzed this and his results are shown in
    late frequency modulation, the design should pro-
    Figure 8, which plots normalized pullout fre-
    ceed with the criterion of b above_ It is necessary
    quency for various damping factors for high gain
    to provide sufficient loop bandwidth to accom-
    second order loops. Peak phase errors for other
    modate the expected modulation_ It must be
    types of input signals are shown in Figures 8 and 9_
    remembered that at all times, the loop must remain
    in lock, (peak phase error less than 90°), even
    under extremes of modulation, such as peaks or
    step changes in frequency_ I.' K~=o.J
    1.2~lft",o.!i
    For the case of sinusoidal frequency modulation, I.D
    the peak phase error as a function of frequency
    deviation and damping factor is shown in Figure 6_
    ;;~ '8 ",.D7"--
    '·2.D _ _
    D.'
    =
    =
    1.' D.2 -.ll':;;> ~,·'.D
    1.4 f-ti'"
    D
    1.2
    ~ .. 0.5
    o , 2 3 4 5 6 1 a
    1.'
    -~ ,.
    .~

    .
    D.'
    r-O.101

    FIGURE 8. Transient Phase Error liehl Due to a Ramp


    in Frequency ~w. (Steady-State Accelera-
    f"Z.O
    '.2 • =5.0 tion Error, ~wlwn2, included. Velocity
    D Error, b.WtlK v, Neglected
    '.1 0.20.30.50.71.0 2 3 1D
    w",/W n "
    FIGURE 6_ Steady-State Peak Phase Error Due to
    D.'
    Sinusoidal FM (High-Gain, Second-
    Order Loop.1 D.1

    D.'
    ;;I~
    D.3
    It can be seen that the maximum phase error occurs =
    0
    D.1
    when the modulating frequency wm equals the ~1k!'2.0
    loop natural frequency W n ; if the loop has been -0.1
    "LOr- 1=
    , ••. D~~ r.o·~F
    designed with a damping factor of .707, the peak
    phase error (in radians) will be .71 b.w/w n (b.w ~
    -0.3

    .... o
    t=O.!i
    ~= 0.3 1=
    1 2 3 4 5 6 1 8
    frequency deviation). From this plot, it is possible
    to choose wn for a given deviation and modulation
    frequency.
    FIGURE 9_ Phase Error lieW Due to a Step in PhaseM
    If the loop is to demodulate frequency shift keying
    (FSK), it must follow step changes in frequency.
    The filter components must then be chosen in In designing loops to track a carrier or synchroniz-
    accordance with the transient phase error shown ing signal, it is desirable to make the loop band-
    in Figure 7. It must be remembered that the loop width narrow so that phase error due to external
    filter must be wide enough so the loop will not noise will be small. However, it is necessary to
    lose lock when a step change in frequency occurs: make the loop bandwidth wide enough so that
    the greater the frequency step, the wider the loop any frequency jitter on the input signal will be
    filter must be to maintain lock. followed.

    AN46-4
    NOISE PERFORMANCE
    Z
    ::I 500
    Since one of the main uses of phase locked loops o
    2DO
    is to demodulate or track signals in noise, it is ~
    i= 100
    1/
    helpful to look at how noise affects the operation :i 50

    of the phase locked loop. ~ 20

    ~ 111
    1/
    The phase locked loop, as mentioned earlier, may
    be thought of as a filter with a fixed, adjustable ~,
    bandwidth. We have seen how to calculate the loop
    natural frequency Wn (15), (19), and the damping
    1 1.0 I.' 2.0
    LtJOP SIGNAl·TQ·NOISE RAllO
    factor I (16), (20). Without going through a deriva-
    tion, the loop noise bandwidth BL may be shown
    to be FIGURE 11. Unlock Behavior of High-Gain, Second-
    Order LooP,1 ~ 0.707

    BL ~J[: (jw) [2 df ~ ~n [I ;1] + Hz (23)


    When designing the loop filter components, enough
    bandwidth in the loop must be allowed for instan-
    for a high gain, second order loop. This equation is taneous phase change due to input noise. In the
    plotted in Figure 10. It should be noted that the previous section, the filter was selected on the
    dimensions of noise bandwidth are cycles per basis that the peak error due to modulation would
    second while the dimensions of wn are radians be less than 900 (so the loop would not loose lock).
    per second. However, if noise is present, the peak phase error
    will increase due to the noise. So if the loop is not
    to lose lock on these noise peaks, the peak allow-
    ,.. able error due to modulation must be reduced to
    ~ 3.0 i,.,:,.":,,
    w" something less, on the order of 400 to 50°.
    ~ 2.5

    ~ 2.0 LOCKING
    §
    ~ 1.5
    ./
    V Initially, a loop is unlocked and the veo is running
    ~1.11 at some frequency_ If a signal is applied to the
    a
    zos \ VV
    input, locking mayor "Tlay not occur depending on
    several things.
    o 0.51.01.52.0 2.5 3.0 3.5
    DAMPING FACTOR - r If the signal is within the bandwidth of the loop
    filter, locking will occur without a beat note being
    FIGURE 10. Loop-Noise Bandwidth (For High-Gain, generated or any cycles being skipped. This fre-
    Second-Order Loop) quency is given by

    Noise threshold is a difficult thing to analyze in a


    phase locked loop, since we are talking about a
    statistical quantity. Noise will show up in the input
    If the frequency of the input signal is further
    signal as both amplitude and phase modulation. It
    away from the veo frequency, locking may still
    can be shown that near optimum performance of a
    occur, with a beat note being generated. The great-
    phase locked loop can be obtained if a limiter is
    est frequency that can be pulled in is called the
    used ahead of the phase detector, or if the phase
    "pUll in frequency" and is found from the approxi-
    detector is allowed to operate in limiting. With the
    use of a limiter, amplitude modulation of the input mation
    signal by noise is removed, and the noise appears
    as phase modulation. As the input signal to noise
    ratio decreases, the phase jitter of the input signal
    due to noise increases, and the probability of losing which works well for moderate and high gain loops
    lock due to instantaneous phase excersions will (wn/KoKo < .4).
    increase. In practice it is nearly impossible to
    acquire lock if the signal to noise ratio in the loop An approximate expression for pull in time (the
    (SNR)L ~ 0 dB. In general, (SNR)L of +6 dB is time required to achieve lock from some frequency
    needed for acquisition. If modulation or transient offset Llw) is given by:
    phase error is present, a higher signal to noise ratio
    is needed to acquire and hold lock.

    A computer simulation performed by Sanneman


    and Rowbotham has shown the probability of A MONOLITHIC PHASE LOCKED LOOP
    skipping cycles for various loop signal to noise
    ratios for high gain, second order loops. Their A complete phase locked loop has been built on a
    data is shown in Figure 11. monolithic integrated circuit. It features a very

    AN46-5
    linear voltage controlled oscillator and a double All of the current supplied by Q 2 is diverted
    balanced phase detector. through 0, and Q3, which sets up an equal cur-
    rent in Q4. This current is supplied by the charged
    A simplified schematic of this voltage controlled capacitor C (which now discharges linearly), caus-
    oscillator is shown in Figure 12. Q 2 is a voltage ing the voltage across it to decrease. This continues
    controlled current source whose collector current until a lower trip point is reached and Q 7 turns
    is a linear function of the control voltage ef. Initial· OFF and the cycle repeats. Due to the matching of
    Iy Q 5 is OFF and the collector current of Q 2 passes Q 3 and Q4, the charge current of C is equal to the
    through O2 and changes C in a linear fashion. The discharge current and therefore the duty cycle is
    voltage across C is therefore a ramp, and con· very nearly 50%. Figure 13 shows the wave forms
    tinues to increase until Q 7 is turned ON; this turns at (1) and (2).
    OFF Qs, causing Q 9 and Q" to turn ON. This in
    turn turns ON Q5. With Q 5 ON, the anode of 0, Figure 14 shows the double balanced phase detec-
    is clamped close to -Vee and O2 stops conducting, tor and amplifier used in the microcircuit. Transis-
    since its cathode is more positive than its anode. tors Q, through Q 4 are switched with the output

    FIGURE 12. Simplifieo Voltage Controlled Oscillator

    _Dfi:f-----if--+-+---

    FIGURE 13. VCO Waveforms

    FIGURE 14. Phase Detector and Amplifier

    AN46-6
    of the veo, while the input signal is applied to Ra serves as the resistive portion of the loop filter,
    the bases of Q 5 and Q6. The output current in and additional resistance and capacitance may be
    resistors R3 and R4 is then proportional to the added here to fix the loop bandwidth. For use as
    difference in phase between the veo output and an FM demodulator, the voltage at pin 7 will be
    the input; the ac component of this current will the demodulated output; since the dc level here
    be at twice the frequency of the veo due to the is fairly high, a reference voltage has been pro·
    full wave switching action transistors Q 1 through vided so that an operational amplifier with differ·
    Q4. The waveforms of Figure 15 illustrate how ential input can be used for additional gain and
    the phase detector works. Diodes Dl and D2 serve level shifting.
    to limit the peak to peak amplitude of the collector
    voltage. The output of the phase detector is further
    amplified by QlO and Qll, and is taken as a volt· The complete microcircuit, called the LM565, is
    age at pin 7. shown in Figure 16.

    FIGURE 15. Phase Detector Waveforms, Showing Limit Cases for Phase Shift Between Input and VCO Signals

    ,."'

    FIGURE 16. LM565 Phase Locked Loop

    AN46-7
    USING THE LM565 tion regardless of center frequency. IRIG channel
    13 has been selected as an example of demon-
    Some of the important operating characteristics of strate the usefulness of the LM565 as an FM
    the LM565 are shown in the table below. (Vee demodulator.
    ±6V, T A = 25°C).

    Phase Detector
    IRIG Channel 13
    Input Impedance 5 k" Center Frequency 14.5 kHz
    Input Level for Limiting 10mV Max Deviation ±7.5%
    Output Resistance 36kQ
    Output Common Mode Voltage 4.5V Frequency Response 220 Hz
    Offset Voltage (Between pinS 6 and 71 10DmV Deviation Ratio 5
    SensitIVity Ko 5V/rad
    Voltage Controlled Oscillator
    Stabllltv Since with a deviation of ±10%, the LM565 will
    Temperature 200 ppml'C produce approximately 300 mV peak to peak
    Supply Voltage 200 ppm/%
    Square Wave Output Pm 4 5.4 V pp output, with a deviation of 7.5%, we can expect
    Triangle Wave Output Pin 9 2.4 V pp an output of 225 mV. It is desirable to amplify
    Maximum Operating Frequency 500kHz
    Sensitivity Ko 4.5 fa rad/seeN and level shift this signal to ground so that plus
    (fa: osc. freq in Hz) and minus output voltages can be obtained for
    Closed Loop Performance
    frequency shi"fts above and below center frequency_
    Loop Gain KoKo 2.8 folsec
    Dernod. Output, ±10% Deviation 300 mV
    (A .001 ,uF capacitor IS needed between pinS 7 and 8 to stop An LM 1 07 can be used to provide the necessary
    parasitic oscillations).
    additional gain and the level shift. In Figure 17,
    R4 is used to set the output at zero volts with no
    To best illustrate how the LM565 is used, several input signal. The frequency of the VCO can be
    applications are covered in detail, and should pro- adjusted with R3 to provide zero output voltage
    vide insight into the selection of external com- when an input signal is present.
    ponents for use with the LM565.
    The design of the filter network proceeds as
    IRIG CHANNEL DEMODULATOR follows:

    In the field of missile telemetry, it is necessary to It is necessary to choose wn such that the peak
    send many channels of relatively narrow band data phase error in the loop is less than 90° for all
    via a radio link. It has been found convenient to conditions of modulation. Allowing for noise mod-
    frequency modulate this information on a set of ulation at low levels of signal to noise, a desirable
    subcarriers with center frequencies in the range of peak phase error might be 1 radian or 57 degrees,
    400 Hz to 200 kHz. Standardization of these fre- leaving a 33 degree margin for noise. Assuming
    quencies was undertaken by the Inter-Range Instru- sinusoidal modulation, Figure 6 can be used to
    mentation Group (I RIG) and has resulted in several estimate the peak normalized phase error. It
    sets of subcarrier channels, some based on devia- will be necessary to make several sample cal-
    tions that are a fixed percentage of center fre- culations, since the normalized phase error is a
    quency and other sets that have a constant devia- function of wn.

    . - - - -___-------4II---+--o.,v

    OUTPUT

    L-________________________________ +-____-t__ ~~v

    R4
    25DK

    FIGURE 17_ IRIG Channal13 Demodulator

    AN46-8
    Selecting a worst case of wn/w m ; 1, wn ; 2rrX of approximately +6 dB because of the bandwidths
    220 Hz; selecting a damping factor of .707, involved. The above number of -8.4 dB signal to
    noise for threshold was obtained with a noise
    o
    - - - ; .702
    spectrum 100 kHz wide. The noise power in the
    /::,wlw n loop will be reduced by the ratio of loop noise
    bandwidth to input noise bandwidth
    or
    BLOOP 1890 Hz
    /::'w 2rr X 1088 Hz B,NPuT = 100 kHz; .02 or -17 dB
    ee; .702 Wn ; .702 2rr X 220 Hz
    the equivalent signal to noise in the loop is -8.4 dB
    ; 3.45 radians +17 dB ; +8.6 dB which is close to the above·
    mentioned limit of +6 dB. It should also be noted
    this is unacceptable, since it would throw the loop that loss of lock was noted with full modulation
    out of lock, so it is necessary to try a higher value of the signal which will degrade threshold some·
    of W n . Let Wn ; 2rrx 500 Hz, then wm/w n ; .44, what (although the measurement is more realistic) .
    • ,ld

    2rr X 1088 lOOK . . . - - - - - - - - ,


    = .44 X 2 rr X 500 = .95 radians

    ~
    10K

    this should be a good choice, since it is close to 1K


    radian. Operating at 14.5 kHz, the LM565 has a :i
    loop gain Ko KD of 100

    10
    2.28 x 14.5 x 103 ; 33 x 103 sec w2-- 25DD I
    w-+
    1
    1 10 100 tOOK
    the value of the loop filter capacitor, C" can be lK 10K

    found from Figure 4:


    FIGURE 18. Bode Plot for Circuit of Figure 17
    7, + 72 ; 3.5 x 10- 3 sec

    from Figure 5, the value of T2 can be found (for


    a damping factor of .707) FSK DEMODULATOR

    ;
    4.4 X 10- 4 sec Frequency shift keying (FSK) is widely used for
    T2
    the transmission of Teletype information, both in
    T, ;
    (35 - 4.4) X 10-4 sec ;
    31.4 X 10- 4 sec the computer peripheral and communications field.
    T, Standards have evolved over the years, and the
    C1 ;
    R ; 31.4 X 10- 4 sec ;
    1 pF commonly used frequencies are as follows:
    4.4 X 10- 4 sec
    R2 ; ;
    440n a) mark 2125 Hz
    1 X 10- 6 pF 2975 Hz
    space
    b) mark 1070 Hz
    Looking at Figure 10, the noise bandwidth BL can
    space 1270 Hz
    be esti mated to be
    c) mark 2025 Hz
    space 2225 Hz
    BL ; .6 Wn ; .6 X 3150 rad/sec
    ; 1890 Hz a) is commonly used as subcarrier tones for radio
    Teletype, while b) and c) are used as carriers for
    the complete circuit is shown in Figure 17. Mea· data transmission over telephone and land lines.
    sured performance of the circuit is summarized
    below with a fully modulated signal as described As a design example, a demodulator for the 2025
    above and an input level of 40 mVrms: Hz and 2225 Hz mark the space frequencies will
    be discussed.
    f 3 dB 200
    r Q8 Since this is an FM system employing square wave
    modulation, the natural frequency of the loop
    Output Level 770 mVrms
    Distortion 0.4% must be chosen again so that peak phase errors
    Signal to Noise at verge of loss of lock do not exceed 900 under all conditions. Figure 7
    (bandwidth of noise; 100 kHz) -8.4 dB shows peak phase error for a step in frequency;
    if a damping factor of .707 is selected, the peak
    It will be noted that the loop is capable of de· phase error is
    modulating signals lower in level than the noise;
    this is not in disagreement with earlier statements ee
    that loss of lock occurs at signal to noise ratios D.w/w n = .45

    AN46-9
    FIGURE 19. FSK Demodulator 12025-2225 cps)

    FIGURE 20. FSK Demodulator with DC Restoration

    or values calculated above caused too much roll off


    /:'w of a square wave modulation signal of 150 Hz. The
    II. .45
    Wn two 10k resistors and .02 f.1F capacitors at the
    input to the LM111 comparator provide further
    /:'w filtering of the carrier, and hence smoother opera·
    Wn = .45 Be tion of the circuit.

    in our case, /:'w 2 1TX 200 Hz = 1250, if lie = 1 A problem encountered with this simple demodu·
    radian, lator is that of dc drift. The frequency must be
    adjusted to provide zero volts to the input of the
    1250 rad/sec comparator so that with modulation, switching
    .45 500 rad/sec occurs. Since the deviation of the signal is small
    1 radian
    (approximately 10%), the peak to peak demodu·
    fn = 80 Hz lated output is only 150 mV. It should be apparent
    that any drift in frequency of the VCO will cause
    The final circuit is shown in Figure 19. The values a dc change and hence may lock the comparator
    of the loop filter components (C, = 2.2 f.1F and in one state or the other. A circuit to overcome
    R, = 700n) were changed to accommodate a this problem is shown in Figure 20. While using
    keying rate of 300 bauds (150 Hz), since the the same basic demodulator configuration, an

    AN46-10
    INPUTfRQM
    ''''IRleOROIR

    FIGURE 21. Block Diagram of Weather Satellite Demodulator

    VIOIO
    OUUUT

    .o£l
    yt'"
    HIIRrl
    SYNC

    FIGURE 22. Weather Satellite Picture Demodulator

    LM 111 is used as an accurate peak detector to lated on a 2.4 kHz subcarrier which is frequency
    provide a dc bias for one input to the comparator. modulated on a 137.5 MHz RF carrier. Upon
    When a "space" frequency is transmitted, and the reception, the output from the receiver FM detec-
    output at pin 8 of the LM565 goes negative tor will be the 2.4 kHz tone containing AM video
    and switching occurs. the detected and filtered information. It is common practice to record the
    voltage of pin 3 to the comparator will not follow tone on an audio quality tape recorder for subse-
    the change. This is a form of "dc restorer" circuit: quent demodulation and display. The 2.4 kHz
    it will track changes in drift. making the compara- subcarrier frequency may be divided by 600 to
    tor self compensating for changes in frequency, etc. obtain the horizontal sync frequency of 4 Hz.

    WEATHER SATELLITE PICTURE


    DEMODULATOR Due to flutter in the tape recorder, noise during
    reception, etc., it is desirable to reproduce the
    As a last example of how a phase locked loop can 2.4 kHz subcarrier with a phase locked loop, which
    be used in communications systems, a weather will track any flutter and instability in the recorder,
    satellite picture demodulator is shown. Weather and effectively filter out noise, in addition to pro-
    sate II ites of the Nimbus, ESSA,. and ITOS series viding a signal large enough for the digital fre-
    continually photograph the earth from orbits of quency divider. In addition, an in phase component
    100 to 800 miles. The pictures are stored imme- of the veo signal may be used to drive a synchro-
    diately after exposure in an electrostatic storage nous demodulator to detect the video information_
    vidicon, and read out during a succeeding 200 A block diagram of the system is shown in Fig-
    second period. The video information is AM modu- ure 21, and a complete schematic in Figure 22.

    AN46-11
    The design of the loop parameters was based on A vertical sweep circu it is shown using an LM308
    the following objectives low input current op amp as a Miller rundown
    circuit. The values are chosen to produce an output
    fn 10Hz, Wn ; 75 radlsec voltage ramp of -4.5V 1220 sec, although this may
    be adjusted by means of the 22 meg. charging
    BL 40 Hz (from Figure 10) resistor. If an oscilloscope is used as a readout,
    the horizontal sync can be supplied to the trigger
    the complete loop filter, calculated from Figures input with the sweep set to provide a total sweep
    4 and 5, is shown in Figure 22. When the loop is time of something less than 250 ms. A camera is
    in lock and the free running frequency of the VCO used to photograph the 200 second picture.
    is 2.4 kHz, the VCO square wave at pin 4 of the
    565 will be in quadrature (900 ) from the input
    SUMMARY AND CONCLUSIONS
    signal; however, the zero crossings of the triangle
    wave across the ti ming capacitor will be in phase, A brief review of phase lock techniques has been
    and if their signal is applied to a double balanced presented and several useful design tools have been
    demodulator, such as an LM 1596, switching will presented that may be useful in predicting the
    occur in the demodulator in phase with the 2.4 performance of phase locked loops.
    kHz subcarrier. The double balanced demodulator
    will produce an output proportional to the ampli· A phase locked loop integrated circu it has been
    tude of the subcarrier applied to its signal input. described and several applications have been given
    An emitter follower, Q1, is used to buffer the to illustrate the use of the circu it and the design
    triangle wave across the timing capacitor so exces· techniques presented.
    sive loading does not occur.

    The demodulated video signal from the LM1596


    is taken across a 25k potentiometer and filtered to
    a bandwidth of 1.4 kHz, the bandwidth of the
    transmitted video. Depending on the type of dis· REFERENCES
    play to be used (oscilloscope, slow scan TV moni· 1. Floyd M. Gardner, "Phaselock Techniques",
    tor, of facsimile reproducer), it may be necessary John Wiley and Sons, 1966.
    to further buffer or amplify the signal obtained.
    If desired, another load resistor may be used 2. Elliot L. Greenberg, "Handbook of Telemetry
    between pin 6 and VCO to obtain a differential and Remote ContrOl", McGraw-Hili, 1967.
    output; an operational amp could then be used to 3. Andrew Viterbi, "Principles of Coherent Com-
    provide more gain, level shift, etc. munication", McGraw-Hili, 1966.

    AN46-12
    »
    z
    Barry Siegel and Leonard Van Der Gaag ~
    August 1971 00

    »
    -a
    -a
    APPLICATIONS FOR A NEW ULTRA-HIGH SPEED BUFFER r
    (')
    INTRODUCTION »-I
    Voltage followers have gained in popularity in
    applications such as sample and hold circuits,
    from the output, 0 1 and O2 will drift at different
    rates. A circuit which overcomes offset voltage
    o
    Z
    general purpose buffers, and active filters since drift is used in a new high speed buffer amplifier, en
    the introduction of IC operational amplifiers. Since the LH0033. Initial offset is typically 5 mV and
    they were not specifically designed as followers, offset drift is 20 /lV/oC. Resistor R2 is used to "T1
    o

    'q:
    these early IC's had limited usage due to low band- establish the drain current of curren1:-source tran-
    width, low slew rate and high input current. Usage sistor, O2 at 10 mAo
    :c
    of voltage followers was expanded in 1967 with
    the introduction of the LM 102, the first IC de-
    »
    signed specifically as a voltage follower. With the 2
    LM102, engineers were able to obtain an order of
    magnitude improvement in performance and ex-
    '.
    flo

    ~
    OUTPUT
    ~
    tend usage into medium speed applications. The
    LM 11 0, an improved LM 102, was introduced in
    m
    c
    late 1969. However, even higher speeds and lower !:i
    :c
    input currents were needed for very fast sample ~

    and holds, A to D and D to A converters, coax FIGURE 1. Simple Voltage Follower Schematic
    »I
    cable drivers, and other video applications. ::I:
    The solution to this application problem was The same drain current flows through 0 1 causing G)
    attained by combining technologies into a single a voltage at the source of approximately 1.1 V. ::I:
    The 10 mA flowing through Rl plus 03'S VBE of
    package. The result, the LH0033 high speed buffer,
    0.6V causes the output to sit at zero volts for
    en
    utilizes J F ET and bipolar technology to produce -a
    a ultra-fast voltage follower and buffer whose zero volts in. 0 3 and 0 4 eliminate loading the m
    propagation delay closely approaches speed-of- input stage (except for base current) and CR 1 and m
    light delay across its package, while not com- CR 2 establish the output stage collector current. C
    promising input impedance or drive characteristics. O:J
    Table I compares various voltage followers and C
    illustrates the superiority of the LH0033 in both "T1
    "T1
    low input current or high speed video applications. m
    :c
    CIRCUIT CONSIDERATIONS

    The junction FET makes a nearly ideal input device


    for a voltage follower, reducing input bias current
    to the picoamp range. However, FET's exhibit
    moderate voltage offsets and offset drifts which
    tend to be difficult to compensate. The simple
    voltage follower of Figure 1 eliminates initial
    offset and offset drift if 0 1 and O2 are identically
    .~

    .
    OFFsnl'

    matched transistors. Since the gate to source


    voltage of O2 equals zero volts, then 01'S gate to
    source voltage equals zero volts. Furthermore as FIGURE 2. LH0033 Schematic
    Vp1 changes with temperature (approximately
    2.2 mV/oCI. V P2 will change by a correspond- If 0 1 and ~ are matched, the resulting drift is
    ing amount. However, as load current is drawn reduced to a few /lV/oC.

    TABLE I COMPARISON OF VOLTAGE FOLLOWERS

    CONVENTIONAL FIRST GENERATION SECOND GENERATION SPECIALLY DESIGNED


    PARAMETER MONOLITHIC OP AMP VOLTAGE FOLLOWER VOLTAGE FOLLOWER VOLTAGE FOLLOWER
    LM741 LM102 LM110 LHOOlJ

    INPUT BIAS CURRENT 200nA JOnA 1 DnA OOSnA

    SLEW RATE 05V1~s 10V/~s 30V/lJs 1500V/jJs

    BANDWIDTH 10MHz IOMHz 20MHz l00MHz

    PROP DELAY TIME 350n5 35"5 18ns 12n5

    OUTPUT CURRENT CAPABILITY :t.5mA :t2mA :t2mA :t.,OOmA

    AN48-1
    PERFORMANCE OF THE LH0033
    FAST VOLTAGE FOLLOWER/BUFFER

    The major electrical characteristics of the LH0033 IStICS. Other typical performance curves are illus-
    are summarized in Table II. All the virtues of a trated in Figures 4 through 10. Of particular
    ultra-high speed buffer have been incorporated. interest is Figure B. which demonstrates the per-
    Figure 3 is a plot of input bias current vs tempera- formance of the LH0033 in video applications
    ture and shows the typical FET input character- to over 100 MHz.

    TABLE \I

    PARAMETER CONDITIONS VALUE PARAMETER CONDITIONS VALUE

    Output Of~et Voltage Rs=l00kfl SmV Output Current Capability :±l00mA peak

    Input Bias Current 50pA


    Slew Rate Rs= 50n, RI." lk 1500V/$lS
    Input Impedance V IN " 1,OV(ms
    AI. = lk. t= 1 kHz P(opagatlonDelay 12n5

    Voltage Gain V1N "'0Vrms 098 Bandwidth l00MHz


    • VIN'" 1 OVrms
    AI.: lk, f '" 1 kHz, Rs = lOOk Rs= 50n, A L " lk

    Output Voltage SWing Vs = ±15V, Rs = 1DOIe: ±13V


    RI." Ik

    "D '.0
    "
    . /
    Vs ·±15.GV
    Vs=±2OV
    ~ As·,OOk
    ;>
    " r-r R,I.""
    14
    Rs=IODkn
    TA·+25~C
    ./ / ~
    0.100
    ~ 4' " "
    ~

    V
    Vs·±15V_
    " i 10

    .10
    "7
    i"":::-.'O,
    Vs =±10V
    i ,. ...... r-,.

    ~ /
    /'

    .001
    I o
    /
    o 25 50 75 100 125 zo
    TEMPERATURE rei
    -SO
    "
    TEMPERATURE (OCI
    100 ISO
    " IS
    SUPPLY VOLTAGE (tV)

    FIGURE 3. Input Bias Current FIGURE 4. Output Offset Voltage FIGURE 5. Output Voltage vs
    vs Temperature vs Temperature Supply Voltage

    Vs·±t!iV I .- Vll.= ±1!iV


    r-
    Vs=:t15V
    ..
    35
    i Rs=SDn
    I :. 11 --RL""kn.Rs=5Gn Rs=5D.O:

    ~ ...
    -. RL =1kO
    TA =+25"&
    I
    I
    "
    TA =+25 G C

    T T
    RL ",son
    V.,.. '" 1.OVrms

    -::I
    30
    ;
    ~ INPUT~ i INPUT- \
    I
    '.0
    D.'
    A.
    Z5
    ~
    ~ .
    ~ -6 j:;:=OUTl'UT
    ~
    OUTPUT
    zo
    :; \\ U f 15
    E
    :;;
    ~
    \\
    l§:
    ~
    -10
    _IZ ! \i
    OA

    u
    ./
    A " l!!

    10 20 3D 40 50 68 10 2D 3D 40 50 60 '.0 '.0 ,. 10.0 20.0


    " 100
    TIME (lIS) TIME (lIS) FREDUENCY (MHt)

    FIGURE 6. Negative Pulse Respons. FIGURE 7. Positive Pulse Response FIGURE 8. Frequency Response

    Z1
    , /~
    /' ~
    1 zo
    IA h
    ""
    1 19
    /' IA
    / ./.: "\ TA "-55·C

    I 18 /I' TA =+25G C

    '/ TA -+125·C

    OLJLJLJ---'---'---'---'-'
    " " 15
    " -50
    " '00 '50
    SupplyValta.l(tV) TEMPERATURE ("'C)

    AGURE 9. Supply Current v. FIGURE 10. Rise and Fall Time


    Supply Voltage vs Temperature

    A(\J4B-2
    APPLICATIONS FOR ULTRA-
    FAST FOLLOWERS ..
    The LH0033's high input impedance (10 11 n,
    shunted by 2 pF} and high slew rate assure minimal
    .n
    loading and high fidelity in following high speed
    pulses and signals_ As shown below, the LH0033
    is used as a buffer between MOS logic and a high
    speed dual limit comparator_ The device's high
    FIGURE 13.
    input impedance prevents loading of the MOS
    logic signal (even a conventional scope probe will Another application that utilizes the low input
    distort high output impedance MOSL The LH0033 current, high speed and high capacitance drive
    adds about a 1.5 ns to the total delay of the com- capabilities of the LH0033 is a shield or line
    parator. Adjustment of voltage divider R1,R 2 driver for high speed automatic test equipment_
    allows interface to TTL, DTL and other high In this example, the LH0033 is mounted close to
    speed logic forms_ the device under test and drives the cable shield
    thus allowing higher speed operation since the
    device under test does not have to charge the cable_

    FIGURE 14. Instrumentation Shield/Line Driver

    v•.,.
    The LH0033's high input impedance and low
    input bias current may be utilized in medium
    speed circuits such as Sample and Hold, and D to
    FIGURE 11_ High Speed Dual Limit Comparator for A converters. Figure 15 shows an LH0033 used
    MOS Logic as a buffer in medium speed D to A converter.

    The LH0033 was designed to drive long cables, Offset null is accomplished by connecting a lOOn
    shielded cables, coaxial cables and other generally pot between pin 7 and V-. It is generally a good
    stringent line driving requirements_ It will typically idea to insert 20n in series with the pot to prevent
    drive 200 p F with no degradation in slew rate and excessive power dissipation in the LH0033 when
    several thousand pF at a reduced rate_ In order to the pot is shorted out. In non-critical or AC
    prevent oscillations with large capacitive loads, coupled applications, pin 6 should be shorted
    provision has been made to insert damping resistors to pin 7. The resulting output offset is typically
    between V+ and pin 1, and V- and pin 9_ Values 5 mV at 25°C.
    between 47 and lOOn work well for C L > 1000 P F.
    For non-reactive loads, pin 12 should be shorted to
    pin 1 and pin 10 shorted to pin 9. A coaxial driver
    is shown in Figure 13. Pin 6 is shorted to pin 7,
    obtaining an initial offset of 5.0 mV, and the 43n
    coupled with the LH0033's output impedance
    (about 6n} match the coaxial cable's characteris-
    tic impedance. C1 is adjusted as a function of
    cable length to optimize rise and fall time. Rise
    time for the circuit as shown in Figure 12, is
    10 ns.
    FIGURE 15.

    The high output current capability and slew rate


    of the LH0033 are utilized in the sample and hold
    circuit of Figure 16. Amplifier, A 1 is used to
    buffer high speed analog signals. With the config-
    uration shown, acquisition time is limited by the
    time constant of the switch "ON" resistance and
    sampling capacitor, and is typically 200 or 300 ns.
    A2's low input bias current, results in drifts in
    hold mode of 50 mV at 25°C and ~ at 125°C
    sec sec·
    The LH0033 may be utilized in AC applications
    such as video amplifiers and active filters. The
    FIGURE 12. LH0033 Pulse Response into 10 Foot circuit of Figure 17 utilizes boot strapping to
    Open Ended Coaxial Cable achieve input impedances in excess of 10 Mn_

    AN48-3
    where: Av = No load voltage gail), typically 0.99.
    V+ = Positive Supply Voltage.
    V- = Negative Supply Voltage.

    For the foregoing application, 6. Va would be


    -100 mV. This apparent "offset" may be adjusted
    to zero as outlined above.
    Figure 19 shows a high Q, notch filter which takes
    advantage of the LH0033's wide bandwidth. For
    LOGIC the values shown, the center hequency is 4.5 MHz.
    IN'UT

    FIGURE 16. High Speed Sample & Hold


    ,
    lo·Z"R1C1
    Rl·ZRt

    cl·T
    FIGURE 19. 4.5 MHz Notch Filter
    aol~F

    INPUT 0---1 The LH0033 can also be used in conju nction with
    an operational ampl ifier as current booster as
    shown in Figure 20. Output currents in excess of
    100 mA may be obtained. Inclusion of 150n
    resistors between pins 1 and 12, and 9 and 10
    provide short circuit protection, while decoupling
    pins 1 and 9 with 1000 pF capacitors allow near
    FIGURE 17. High Input Impedance AC Coupled full output swing.
    Amplifier
    The value for the short circuit current is given by:
    A single supply, AC coupled amplifier is shown
    in Figure 18. Input impedance is approximately
    500k and output swing is in excess of 8V peak-
    to-peak with a 12V supply.

    VCC'IZGV
    where: Isc ~ 100 mAo

    OII,.F
    IN,UT 0---1

    FIGURE 18. Single Supply AC Amplifier


    lou,;· 100 mA
    ,n
    1$O'ii00:,'OOmA
    The LH0033 may be readily used in applications
    where symmetrical supplies are unavailable or may
    FIGURE 20. Using LH0033 as an Output Buffer
    not be desirable. A typical application might be
    an interface to an MOS shift register where V+ =
    5.0V and V- = -25V. In this case, an apparent SUMMARY
    output offset occurs. In reality, the output voltage
    is due to the LH0033's voltage gain of less than The advantages of a FET input buffer have been
    unity. The output voltage shift due to asymmetri- demonstrated. The LH0033 combines very high
    cal supplies may be predicted by: input impedance, wide bandwidth, very high slew
    rate, high output capability, and design flexibility,
    making it an ideal buffer for applications ranging
    from DC to in excess of 100 MHz.

    AN48-4
    Barry Siegel
    August 1971

    "C
    2
    o
    o
    o
    m
    o
    ::D
    PIN DIODE DRIVERS <
    m
    ::D
    en

    INTRODUCTION

    The DH0035/DH0035C is a TTL/DTL compatible, There are essentially two considerations of interest
    DC coupled, high speed PIN diode driver. It is in the "ON" condition. First, the amount of
    capable of delivering peak currents in excess of "ON" control current must be sufficient such that
    one ampere at speeds up to 10 MHz. This article R F signal current will not significantly modulate
    demonstrates how the DH0035 may be applied to the "ON" impedance of the diode. Secondly, the
    driving PIN diodes and comparable loads which time required to achieve the "ON" condition must
    require high peak currents at high repetition rates. be minimized.
    The salient characteristics of the device are sum-
    marized in Table I.

    RfI.<f1C~ )'H~RF.UT
    G~ ,.'
    PARAMETER
    Differential Supply
    Voltage (V+ - V-I
    Output Current
    CONDITIONS VALUE
    30V Max.

    1000 rnA
    . jl-.-.-,-_._-----'
    Maximum Power 1.5W
    FIGURE 1. Simplified PIN Diode Switch
    PRF = 5.0 MHz 10 ns
    V+ - V- = 20V 15 ns
    10% to 90%
    V+ - V- = 20V
    The charge control model of a diode 1 :2 leads to
    10 ns
    the charge continuity equation given in equa-
    90% to 10%
    tion (1).

    dQ Q
    Table I DH0035 Characteristics i= dt + T (1)

    where: Q = charge due excess minority carriers


    T = mean life time of the minority carriers
    PIN DIODE SWITCHING REQUIREMENTS
    Equation (1) implies a circuit model shown in Fig-
    Figure 1 shows a simplified schematic of a PI N .. dQ
    ure 2. Under steady condItIons Cit = 0, hence:
    diode switch. Typically, the PIN diode is used in
    R F through microwave frequency modulators and
    switches. Since the diode is in shunt with the RF Q
    loc = Tor Q = loc T (2)
    path, the R F signal is attenuated when the diode
    is forward biased ("ON"), and is passed unattenu-
    ated when the diode is reversed biased ("OFF"). where: I = steady state "ON" current.

    AN49-1
    The time response of the charge, hence the time
    for the diode to achieve the "ON" state could be
    shortened by applying a current spike, Ipk, to the
    I,. TOTAL CURRENT diode and then dropping the current to the steady
    IDC = SS CONTROL CURRENT state value, loc, as shown in Figure 3b. The
    'RF = RF SIGNAL CURRENT
    optimum response would be dictated by:

    (ipk) (t) = 7'l oc (5)

    FIGURE 2. Circuit Model for PIN Switch

    The conductance is proportional to the current, I;


    ' '--l
    IDe - - '-------
    hence, in order to minimize modulation due to the
    RF signal, loc » iRF . Typical values for loc
    range from 50 mA to 200 mA depending on PIN
    diode type, and the amount of modulation that
    can be tolerated. n I
    I
    The time response of the excess charge, 0, may be I
    evaluated by taking the Laplace transform of 'oc'
    I

    ~
    equation (1) and solving for 0:

    O(s) =~
    1 + S7
    (3)

    Solving equation (3) for O(t) yields:

    O(t) = L-1 [O(s)] = 17(1 _ €-tlT) (4) FIGURE 3b.

    The time response of a is shown in Figure 3a. As


    can be seen, several carrier lifetimes are required
    to achieve the steady state "ON" condition (0 = The turn off requirements for the PI N diode are
    loc· 7). quite similar to the turn on, except that in the
    "OFF" condition, the steady current drops to the
    diode's reverse leakage current.

    A charge, loc'7, was stored in the diode in the


    "ON" condition and in order to achieve the "OFF"
    state this charge must be removed. Again, in order
    to remove the charge rapidly, a large peak current
    (in the opposite direction) must be applied to the
    PIN diode:
    'oc --,.------- a (6)
    -lpk»"T

    It is interesting to note an implication of equation


    (5). If the peak turn on current were maintained
    for a period of time, say equal to 7, then the diode

    . ./ i
    n I would acquire an excess charge equal to Ipk·T.
    I This same charge must be removed at turn off,

    ~.!
    instead of a charge loc'7, resulting in a consider-
    ably slower turn off. Accordingly, control of the
    width of turn on current peak is critical in achiev-
    ing rapid turn off.

    V i
    .. 5r
    APPLICATION OF THE DH0035 AS A
    PIN DIODE DRIVER
    The DH0035 is specifically designed to provide
    both the current levels and timing intervals re-
    FIGURE 30. quired to optimally drive PIN diode switches. Its

    AN49-2
    v'

    RJ
    SODH

    CRI 11

    Rl OUTPUT
    25011

    12
    A
    "

    R,
    lkll

    I ••

    5 GND

    v-

    FIGURE 4. DH0035 Schematic Diagram

    V' = lOV

    I
    r---,L_-, I...L i
    --2r----~.~ 1-
    , I Q zoo",l '"
    I , I I
    I , I
    LOGIC
    , Ii! Jl
    INPUT >0----;":,:...--.....-----=-;,-1
    I zo"~
    IL
    ---J---~
    lf2 DM7BJDfDM88JO! 4

    -1--- OHDOJ5

    56n
    R. Ch
    120llF ":"

    V-=-10.0V

    FIGURE 5. Anode Grounded Design

    schematic is shown in Figure 4. The device utilizes ANODE GROUND DESIGN


    a complementary TTL input buffer such as the
    Selection of power supply voltages is the first con-
    DM7830/DM8830 or DM5440/DM7440 for its
    sideration. Table I reveals that the DH0035 can
    input signals.
    withstand a total of 30V differentially. The supply
    Two configurations of PI N diode switch are pos- voltage may be divided symmetrically at ±15V, for
    sible: cathode grounded and anode grounded. The example. Or asymmetrically at +20V and -10V.
    design procedures for the two configurations will The PIN diode driver shown in Figure 5, uses ±10V
    be considered separately. supplies~

    AN49-3
    When the a output of the DM8830 goes high a where: D.C. = Duty Cycle =
    transient current of approximately 50 mA is applied
    to the emitter of a, and in turn to the base of as. ("ON" time)
    ("ON" time + "OFF" time)
    as has an hfe = 20, and the collector current is
    hfe X 50 or 1000 mAo This peak current, for the Pmax = 1.5W
    most part, is delivered to the PIN diode turning it
    "ON" (RF is "OFF"). In terms of IDC:

    Ipk flows until C2 is nearly charged. This time is


    given by:
    (12a)
    CUN
    t = !Pi< (7)
    For the circuit of Figure 5 and a 50% duty cycle,
    P diss = 0.5W.
    where: b. V = the change in voltage across C2 .
    Prior to Os's turn on, C2 was charged to the minus Turn-off of the PI N diode begins when the a out-
    supply voltage of -10V. C2 's voltage will rise to put of the DM8830 returns to logic "0" and the
    Q output goes to logic "1". O2 turns "ON", and
    within two diode drops plus a Vsat of ground:
    in turn, causes 0 3 to saturate. Simultaneously, a,
    V = Iv-I- Vf(PIN Diode) - Vf cR , - Vsatos (8) is turned "OF F" stopping the base drive to as.
    0 3 absorbs the stored base charge of as facilitat-
    for V- = -10V, b.V = 8V. ing its rapid turn·off. As Os's collector begins to
    rise, 0 4 turns "ON". At this instant, the PIN
    Once C2 is charged, the current will drop to the diode is still in conduction and the emitter of 0 4
    steady state value, IDC, which is given by: is held at approximately -0.7V. The instantaneous
    current available to clear stored charge out of the
    PIN diode is:
    (9)

    where: Vcc = 5.0V


    R, = 250n
    R3 = 500n (13)
    . R (R3) (b.V) (R,) (9a)
    •• M = R, V+ + IDCR3R, + Vcc R3
    where:
    For the driver of Figure 5, and IDC = 100 mA, RM hfe + 1 = current gain of ~ = 20
    is 56 ohms (nearest standard value). VeE 04 = base·emitter drop of 0 4 = 0.7V
    Returning to equation (7) and combining it with Vf(PIN) = forward drop of the PIN
    equation (5) we obtain: diode = 0.7V

    For typical values given, Ipk = 400 mAo Increasing


    (10) V+ above 10V will improve turn-off time of the
    diode, but at the expense of power dissipation in
    the DH0035. Once turn-off of the diode has been
    Solving equation (10) for C2 gives: achieved, the DH0035 output current drops to the
    reverse leakage of the PI N diode. The attendant
    power dissipation is reduced to about 35 mW.
    (11)
    CATHODE GROUND DESIGN
    For 7 = 10 ns, C2 = 120 pF. Figure 6 shows the DH0035 driving a cathode
    grounded PIN diode switch. The peak turn-on
    One last consideration should be made with the current is given by:
    diode in the "ON" state. The power dissipated by
    the DH0035 is limited to 1.5W (see Table I). The (V+ - V-I (h fe + 1)
    DH0035 dissipates the maximum power with 0 5 Ipk ~ R3 (14)
    "ON". With 0 5 "OFF", neglible power is dissi-
    pated by the device. Power dissipation is given by: = 800 mA for the values shown.

    The steady state current, IDC, is set by Rp and is


    given by:

    (15)

    x (D.C.):5:P max (12)

    AN 49-4
    V'

    ",
    62!!
    5.tlV

    r ___ l,~ __ -,
    , I
    I I.
    I I
    I I
    I :>0....-1,...:°'--_---.....--=+-1 r- - ...,
    IN
    I I II D;~~E I
    I
    I I 2DPF~ .1
    ,l swITCH
    IL--...J
    I
    • 112 D."" I DHOO35

    ~--1---~ -1--~ =
    = b '~I~
    -lOV=V-

    FIGURE 6. Cathode Grounded Driver

    where: 2V BE = forward drop of 0 4 base emitter Again, the power dissipated by the DH0035 must
    junction plusVtof the PIN diode = l.4V. be considered. In the "OFF" state, the power
    dissipation is given by:
    In terms of Rp, equation (15) becomes:

    (20)

    where: D.C. = duty cycle =


    For the circuit of Figure 6, and I DC = 100 mA,
    Rp is 62 ohms (nearest standard value). "OFF" time
    It now remains to select the value of C1 . To do "OFF" time + "ON" time
    this, the change in voltage across C1 must be
    evaluated. In the "ON" state, the voltage across The "ON" power dissipation is given by:
    C1 , Vc, is given by:

    loc X (VC)ON ] (1 - D.C.)


    (16)
    (21)
    For the values indicated above, (Vc)ON = 3.8V.
    where: (VC)ON is defined by equation (16).
    In the "OFF" state, Vc is given by:
    Total power dissipated by the DH0035 is simply
    PON + POFF ' For a 50% duty cycle and the cir-
    (17) cuit of Figure 6, P diss = 616 mW.

    The peak turn-off current is, as indicated earlier,


    = 8.0V for the circuit of Figure 6. equal to 50 mA x h te which is about 1000 mAo
    Once the excess stored charge is removed, the
    Hence, the change in voltage across C 1 is: current through 0 5 drops to the diodes leakage

    V (VC)OFF - (VC)ON (18)


    current. Reverse bias across the diode = V- - Vsat
    -10V for the circuit of Figure 6.
    =
    8.0 - 3.8
    REPETITION RATE CONSIDERATIONS
    4.2V
    Although ignored until now, the PRF, in particular,
    The value of C1 is given, as before, by equation the "OFF" time of the PIN diode is important in
    (11): selection of C2 , R M , and C 1 , Rp. The capacitors
    must recharge completely during the diode "OFF"
    C1 -- locT (19) time. In short:
    V-
    (22a)
    For a diode with T = 10 ns and loc = 100 mA,
    C1 = 250 pF. 4 RpC 1 .,;: tOFF (22b)

    AN49-5
    FIGURE 7. RF Turn-On (10 no/em) FIGURE 8. RF Turn-Off (10 no/em)

    CONCLUSION

    The circuit of Figure 6 was breadboarded and has been demonstrated which enable the designer
    tested in conjunction with a Hewlett-Packard to tailor the DH0035 driver to the PI N diode
    33622A PIN diode. application.

    loc was set at 100 mA, V+ = 10.0V, V- = 10V.


    Input signal to the DM8830 was a 5V peak, REFERENCES
    100 kHz, 5 J.Ls wide pulse train. R F turn-on was
    accomplished in 10-12 ns while turn-off took 1. "Pulse, Digital, & Switching Waveforms", Jacob
    approximately 5 ns, as shown in Figures 7 and 8. Millman & Herbert Taub, McGraw-Hili Book
    Company, Inc., New York, N.Y.
    In practice, adjustment C2 (C,) may be required 2. "Models of Transistors and Diodes", John G.
    to accommodate the particular PIN diode minority Linvill, McGraw-Hili Book Company, Inc., New
    carrier life time. York, N.Y.
    3. National Semiconductor AN-T8, Bert Mitchell,
    SUMMARY March 1969.
    A unique circuit utilized in the driving of PIN 4. Hewlett-Packard Application Note 914, January
    diodes has been presented. Further a technique 1967.

    AN49-6
    l>
    zI
    Todd Smathers
    September 1971 ....
    C1I

    l>
    c:
    z
    A UNIQUE MONOLITHIC is
    AGC/SQUELCH AMPLIFIER c:
    m
    s:
    o
    z
    or-
    :::j
    :::t
    INTRODUCTION C')
    As complexity and usage of communication transients onto the signal during periods of rapid
    systems increases, there is a growing use of a gain changing. Two mechanisms may be defined l>
    G')
    special class of circuitry, designed to make the for these elements; either effective resistance or C')
    system more convenient to the user, as well as effective transconductance is varied by the DC .......
    allowing it to adapt to changes in the transmission control voltage. Because the variation is accom· en
    channel. The most common function is voltage· plished by changing quiescent operating points, p
    variable gain, used in volume compression and DC decoupling is required at the output, and only c:
    expansion, and a specialized case, squelch, in AC signals may be handled. DC decoupling, m
    which gain remains either in its maximum or
    r-
    however, still allows rapid changes in DC operating C')
    minimum state. point to be transmitted as switching transients. :::t
    While linearity is claimed for F ET and the lamp·
    The main problem in such circuitry is finding a photocell schemes, such linearity is still only part l>
    suitable nonlinear element to do the job. Conven· of a large·signal nonlinear characteristic. With any s:"tJ
    tional elements, appearing in Table 1, share of the elements, quasi·linearity is obtained by
    common problems of distortion, cost, limited traversing a small segment of the overall element !:
    signal handling capability, sometimes limited gain range; hence, variable gain elements must precede "T1
    reduction range, and usually insert unwanted any system voltage gain. m
    :::a

    TABLE 1. Conventional Gain Control EleIllents

    CONTROL/ LARGE
    CONTROL
    ELEMENT MECHANISM OUTPUT SIGNAL COMMENTS
    RANGE
    ISOLATION HANDLING
    P-N Junction Forward Resistance Good Poor Poor Simple, predictable
    Bipolar Transistor Saturation Resistance Fair Poor Fair Beta Dependent
    FET Channel Resistance Good Poor Fair Unpredictable gate
    control voltage
    requirements; for
    driving fairly high
    impedance loads
    Photocell-Lamp Photocell Resistance Good Good Good Requires power to
    drive lamp; cell must
    be shielded from
    ambient light
    FET Transconductance Fair Poor Poor Unpredictable gate
    control voltage
    requirements; for
    driving fairly high
    impedance loads
    Bipolar Transistor Transconductance Fair Poor Poor Commonly used in
    AM·IF applications

    Tetrode Vacuum Tube Transconductance Fair Poor Good Filament Power

    AN51-1
    A MONOLITHIC APPROACH A feedback circuit senses common-mode output
    from the emitter followers, and compares it with
    Because of the inexpensive complexity possible
    the DC control voltage, to reliably set attenuation
    with monolithic construction, techniques may be
    characteristics. For max imum gain, 0 3 and 0 6
    used which circumvent many of the shortcomings
    behave as ordinary emitter followers. As the con-
    of discrete gain control circuits. The balanced
    trol voltage rises, 0 4 and 0 5 begin to conduct,
    diode attenuator of Figure 1 allows variable series-
    effectively "robbing" 0 3 and 0 6 of available DC
    emitter current. Consequently, dynamic emitter
    resistances of 0 3 and 0 6 , in series with the signal,
    increase, while those of 0 4 and 0 5 decrease,
    shunting across the signal. In the limit, 0 3 and 0 6
    are completely cut off, and the shunt pair fully
    conducting.

    FIGURE 1. Balanced Diode Attenuator

    shunt attenuation, and if used in a differential cir-


    cuit, with monolithic matching, can cancel all
    spurious control-signal effects at the output. Fig-
    ure 2 gives a subsystem block diagram, for effec-
    tively controlling the balanced arrangement of
    Figure 1. An input differential amplifier provides
    differential diode drive even if only single ended
    inputs are available, and keeps the common-mode
    DC level to 0 3 and 0 6 at a constant level. Notice
    FIGURE 2. System Block Diagram
    that emitter followers have been substituted for
    simple diodes, giving higher input impedance, and
    superior gain reduction range. The input diff.-amp. Emitter follower output is fed into a differential
    also prevents gain changes from affecting the input input, single-ended output amplifier, where com-
    impedance. Since the control elements are quasi- mon-mode changes resu Iting from the gain control
    linear only for small signal voltages, the input diff.- voltage are rejected, and the signal is amplified to
    amp. has unity gain, with all circuit gain being usable levels. Thus, the system is a variable gain
    performed after the variable elements. DC amplifier.

    ...-+--+....-0'"

    FIGURE 3. LM170 Schematic

    AN51-2
    MONOLITHIC REALIZATION control feedback amplifier; 0 22 and 0 23 are
    matched constant current sources, whose opera-
    A practical version of Figure 2's block diagram, tion is stabilized by the same circuit that regulates
    National's LM170 appears as a schematic in Fig-
    the input stage. Rather than obtain a common-
    ure 3_ Despite its apparent complexity, and its use mode feedback voltage with resistors as in Figure
    of 34 junction devices and 20 resistors, the entire 2,010 and 011 are used, saving chip space reducing
    circuit has been compressed onto a 39 x 42 mil emitter follower loading, and giving a fixed voltage
    monolithic chip, Figure 4, smaller than most drop at the summing point. Two emitter followers,
    operational amplifiers_ 0 24 and 0 32 are available as gain control inputs,
    allowing considerable control versatility, and may
    be used as peak detectors, as well. Control input
    overvoltage protection is provided by zener diodes
    (reverse base-emitter junctions), 0 33 and 0 34,
    while feedback amplifier excursion is limited by
    another zener, 03S' Bias levels are set so that AGC
    action begins when the applied control voltage
    equals three forward diode drops, about +2.1 V_ As
    control voltage is further increased, gain is reduced
    by progressively shunting current from 0 3 and 0 6
    into 0 4 and Os; the "transition width" of the
    system is about 400 mV, so that above approxi-
    mately +2.SV, minimum gain is obtained. These
    control levels were chosen to be compatible with
    tuned gain control amplifiers, such as the LM 171
    RF/IF amplifier, elsewhere in the system, and to
    allow the circuit to be driven, in switched-gain
    applications, by standard monolithic SV logic,
    such as TTL, DTL, or RTL.
    FIGURE 4_ LM170 Chip

    Examining first the input circuit, Figure S, one


    may notice that the configuration is essentially
    that of the highly successful LM10l operational
    amplifier_ Emitter followers, 0 1 and O 2, combine
    with an unusual lateral PNP configuration, 0 12
    and 0 13, to allow large common-mode input range
    (up to and including the positive supply voltage),
    low input offset voltage, and the ability to with-
    stand large differential input overvoltages without
    damage_ Common-mode feedback to a differential
    current source, 0 14 and 01S, along with a stable,
    diode determined reference, automatically biases
    the differential input configuration to give constant
    and predictable DC common-mode output voltage,
    despite variations in the relatively unpredictable
    lateral PNP "beta" _ The input circu it draws con- fRO~Q'9-------_...J
    stant power supply current regardless of power
    FIGURE 6. LM170 AGe Section
    supply voltage, and consequently exhibits predict-
    able input impedance and bias currents. To increase usable dynamic input range, and de-
    crease distortion, R2, R3, R4 and Rs are added
    to the differential gain control section. These
    resistors have little effect on other circuit param-
    eters, but help to "linearize" the transfer charac-
    teristic throughout the gain control region.

    The output stage, Figure 7, provides large common-


    mode rejection, and a single-ended output, which
    ""
    l~U~ ,
    has a quiescent value halfway between ground and
    the positive supply_ Output stage voltage gain is a
    """ function of supply voltage, being approximately
    100 (40 dB) at Vee = 12V_ Thus, except for its
    lower gain, the LM 170 has the same configuration
    and essential characteristics as an operational am-
    plifier.
    FIGURE 5. LM170 Input Differential Amplifier

    The gain control circuit, Figure 6, operates as out- Output impedance is intentionally high (SOOO
    lined in Figure 2; 02S, 0 26 and 0 27 form the ohms). and short-circuit resistant. Thus, any num-

    ANSl-3
    charge of the time constant capacitor, so that
    effective fast-attack, slow-release squelch occurs.
    Since 0 21 is part of a Darlington, and has a base
    current limiting resistor, R20' it will neither satu-
    rate nor damage itself when large electrolytic
    capacitors are used; however, it will draw suffici-
    ently large currents to bring the capacitor below
    the 2.1V gain control threshOld, and then taper
    off in discharge rate.

    GENERAL APPLICATION CONSIDERATIONS

    FIGURE 7. LM170 Output Stage


    As with any device capable of producing gain,
    when using the LM 170, consideration must be
    ber of LM170's may be directly tied together at given to proper layout of the device and its exter-
    their outputs, for multi-channel mixing or switch- nal circuitry to prevent any undesirable feedback
    ing applications. that may cause oscillation. Since the inputs may
    be biased either directly from Vee or indirectly
    For AGC systems, output signal voltage is usually through a divider network, effective power supply
    peak-detected, and fed back to the gain control bypassing is essential. To guarantee effective by-
    input, maintaining essentially constant output volt- passing at ail frequencies, multiple bypassing should
    age with widely varying input signals. In the case be used. A large capacitor, 10 J.lF or greater, shOUld
    of squelch, however, the output is normally com- be used to absorb all low frequency power supply
    pletely off, in the absence of input signals; thus, variations and a smailer capacitor, approximately
    control voltage for squelch operation cannot be .01 J.lF, to prevent any high frequency feedback
    derived from the output, but must be sampled through Vee. These should be located as physically
    before the gain-reduction stage. Figure 8 shows the close to the device as possible.
    built-in squelch amplifier and detector. Lateral

    '~"
    J$
    PNP transistors 0 12 and 0 13 are constructed with
    two collectors each, so that differential signals
    drive the gain control stage, across R 13 and R 14,
    and separately, from the second pair of collectors, lM:10
    drive 0 20 , 0 36 , and 0 21 . The quiescent current lK 1 5

    from the extra collectors is regulated by the same


    feedback circuit that controls operation of the 10'1' ':" ""'1 ..,
    input stage. If an external resistor (or potenti-
    FIGURE 9. Input Biasing FIGURE 10. Input BiaSing
    ometer) is connected from Pin 7 to ground, it will
    serve as collector load for 0 12 , and can be user and Decoupling Network and Decoupling Network
    adjusted so that 0 20 , normally saturated, turns off
    Additional DC input stability may be necessary.
    for peak signal voltages exceeding any desired
    This is most easily accomplished by a series RC
    value. When this happens, 0 36 and 0 21 turn on,
    roll-off from Vee to the inputs to ground. If the
    discharging an external capacitor, and bringing the
    inputs are to be biased directly from Vee, the
    voltage at Pin 6 below the threshOld required to
    network shOUld be connected as in Figure 9.
    turn the amplifier fully on. Since the collector
    Values of 1k ohms and 10 J.lF give a rOil-off that
    load for 0 20 is a current source, in parallel with a
    is 3 dB down, at approximately 17 Hz. Since the
    high impedance Darlington pair, 0 36 and 0 21 , the
    input bias current is typically around 8.0 J.lA, the
    VOltage gain of the squelch detector is very high,
    voltage drop across the 1k ohm resistor will be
    and abrupt action occurs with even smail incoming
    negligible. If the inputs are biased at some common
    signals.
    mode voltage less than Vee, then the addition of a
    single capacitor from the common mode input
    point to ground accomplishes the same thing (see
    Figure 10). Again, a value of approximately 10J.lF
    will give effective roll-off.

    The input stage exhibits the same high tolerance to


    abuse as does the LM 101; large currents forced into
    either input (when input VOltage exceeds the posi-
    tive supply by more than O. 7V, for example)
    shOUld be avoided. If such transients normally
    occur in the system, as frequently is the case
    during turn on or turn off, protect the inputs with
    FIGURE 8. LM170 Squelch Detector series input resistance.

    The external capacitor and large charging resistor An inspection of the self-balancing action within
    can be chosen for time constants up to several sec- the LM 170 explains how large gain changes can be
    onds, for releasing the squelch; the geometry of achieved, without appreciable DC output shift.
    0 21 , however, is large, allowing a very fast dis- ObviOUSly, if all components in the circuit are

    AN51-4
    exactly matched, this will work perfectly. There AGC APPLICATIONS
    are two possible sources of DC output shift in the
    LM170. The first is an unavoidable small VBE mis· AGC Using Built in Detectors
    match between critical components, causing small
    differential shifts to appear ahead of the output In most systems, the LM170 will be followed by
    gain stage, along with the usual large common· further voltage amplification. This may be advan·
    mode shifts. Units are selected, to various specifi· tageous, as it can provide increased forward gain in
    cations, at the factory, for low output shift. The the AGC loop, resulting in tighter output regula·
    second source of DC shift is externally induced in· tion. In systems having widely varying load imped·
    ances, AGC derived from the system output can
    put offset voltage. As with any operational· type
    amplifier, a certain bias current must flow into each automatically compensate for additional output
    loading. Connected as in Figure 11, the emitter
    input, in the microampere range, to operate the
    input transistors. While input offset current (the follower at Pin 4 is used as a high impedance
    detector, with detector smoothing performed by a
    difference between the two input currents) is very
    low, use of unequal source resistances will cause capacitor at Pin 2. DC threshold for the detector is
    set at any desired level by a potentiometer, deter·
    different voltage drops across each input resistor
    or a net input offset voltage. For critical applica· mining the positive peak output voltage which
    tions, then, especially if large input resistance is initiates gain regulation.
    used, it is recommended that equal input resistors
    be used. Conversely, if the least expensive graded
    units are used, and minimum output shift is still of
    importance, input offset voltage may be individual-

    ' ' '":1


    ly trimmed for each unit, to give nearly ideal
    Av'SUU UUTPUT
    characteristics, as observed on an oscilloscope.

    Another serious source of offset can occur when a


    large capacitor is used to couple to the input of the
    001 .. F
    LM 170. This may cause brief periods of positive
    feedback during a portion of the input waveform
    cycle, during which the device may oscillate. This FIGURE 11. LM170 AGe Using Internal Peak Detector
    and Additional System Gain
    may be easily prevented, however, by connecting a
    capacitor of approximately the same value as the A word of caution is necessary here. When oper·
    input capacitor from the unused input terminal ating the LM 170 with an external gain stage to
    to ground. provide very high AGC loop gains (on the order of
    Gain control inputs, Pins 3 and 4, are shunted by several hundred), proper layout is essential. As
    6.SV zener diodes. If control voltage is anticipated with any high gain circuitry, good power supply
    to go above +6.SV, and if the driving source is regulation is a necessity. Multiple bypass capacitors
    capable of providing more than about 10 mA are used (Figure 11) to give effective wide band
    under these conditions, it is advisable to protect filtering. This should prevent any undesirable rip-
    the zeners with a series resistance at each gain ples or transient spikes from being transferred from
    control input. one device to another through Vee.

    While the large geometry squelch output transistor, Depending on the amount of external loop gain
    0 21 , is capable of sinking large instantaneous desired, several other steps may be necessary. As
    discharge currents from electrolytic capacitors, it with many other AGC circu its, there is a DC shift
    is not advisable to attempt sinking large (more in output voltage associated with the change in
    than SO or 100 mAl continuous currents from applied AGC control voltage. If this shift is fast
    "stiff" voltage sources, which may cause large enough and of sufficient magnitude, it may be
    dissipation on the chip. coupled from the output of the LM 170 to the
    following gain stage. This may cause severe spiking
    The LM170's ability to accept common·mode in the output of the LM 170 which may swing the
    input voltage equal to the positive supply can be a gain stage into limiting causing extreme distortion.
    great convenience to the circuit designer, and saves This can be prevented by providing a given amount
    several components, in such applications as direct of offset in a given direction to the input of the
    dynamic microphone drive. It should be realized, LM170. If an increase in AGC voltage at the AGe
    however, that this system works only with the threshold causes a positive shift in output voltage,
    small (under 100 mV) input signals for which the it may be fed back through the system to cause
    circuit was intended. While input transistors 0 1 a further increase in AGe control voltage. If,
    and O2 still are effective as emitter followers with however, an increase in AGe voltage causes a
    zero, and even less than zero volts collector·to· negative shift in output voltage, when this shift
    base, large positive base voltages (more than about is fed back it will tend to decrease AGe voltage
    400 mV above the positive supply, will allow 0 1 which should help to prevent the spike from
    and O2 to saturate, degrading amplifier gain, input occurring. I n normal application, the LM 170 inputs
    impedance, bandwidth, and input bias current. are biased with approximately 2 kn resistors. If a
    Normal operation should nevllr see more than resistor on the order of S Mn is tied from the
    about SO mV of input signal, sb that this is not a inverting input (Pin 1) to ground, it will provide
    problem. enough offset to control both the direction and

    ANS1-S
    magnitude of the output shift. A potentiometer
    may be substituted to trim the offset to any
    desired value.

    The other problem that may occur can result from


    too large an AC swing at the AGC control point.
    Pins 3 and 4 are protected from positive over
    voltages by a 6.3V zener. If the AC swing is so
    large that it swings negative below .7V, the zener
    will be forward biased. If this occurs, a parasitic FIGURE 13. Internal Full Wave AGC Detection
    NPN transistor can be formed causing an undesired
    transistor action. To prevent this, two solutions are output of the LM170 or of following gain stages if
    available. In the first a germanium diode can be they are used. If driven directly from the output of
    used to shunt all negative swings from the AGC the LM 170, a primary impedance greater than
    pin to ground. It is tied directly from the AGC pin SO H2 is acceptable. Figure 14 shows that AGC
    (Pin 3 or Pin 4) to ground, being forward biased if voltage inputs greater than approximately 2.SV will
    the AC signal tries to swing negative. The alternate provide maximum available gain reduction. There·
    method, as shown in Figure 11 is a silicon diode in
    series with the AGC pin. It is forward biased for all <4' r-
    positive voltages so DC bias is provided and all posi· ." 1\
    tive going AC swings provide proper AGC action.
    All negative swing are promptly cut off at +0.7V.

    Care should be taken to avoid exposing the circuit -ID


    \
    to any RF radiation or 60 Hz power line fields as -20
    they may get into the high gain loop and cause -3D
    erratic AGC action. Coupling capacitors should -4, '-1--
    be selected to give proper operation over the 1.9 2.0 2.1 2.2 2.3 2.4 2,5 2.6
    VAGC CONTROL (V)
    desired range of frequencies. In Figure 11, the low
    frequency limiting factor is the .01 AGC feedback FIGURE 14. Typical Voltage Gain vs AGC Control
    capacitor which gives a roll off near 160 Hz. Voltage (Pin 3 or Pin 4)
    Increasing its size would proportionally lower the
    low frequency cutoff. fore if the transformer output provides a voltage
    swing of approximately 3V peak, it will be more
    . Figure 12 shows the output regulation resulting than adequate to operate the LM 1 70 over its
    from this system with an added 46 dB of voltage entire AGC range.
    gain following the LM170.
    AGC CIRCUIT WITH TRANSISTOR DETECTOR
    In Figure 15, an external PNP transistor acts as a
    negative peak detector, with threshold set by a
    potentiometer. In its quiescent state, the PNP tran-
    sistor is off; negative going signal peaks, AC
    coupled to the detector, cause momentary conduc-
    tion, which turns on the high impedance gain
    control input, Pin 4. Pin 2 is bypassed by a rela-
    tively large capacitor which will charge, and
    maintain a sufficient DC voltage to operate the
    amplifier's gain at the correct level. This level, set
    by the threshold potentiometer, is the point at
    which negative peaks marginally turn on the PNP
    transistor. Thus, as input signal level increases, the
    circuit automatically lowers gain, to maintain a
    constant peak-to·peak output level. Since the capa-
    FIGURE 12. AGC Transfer Characteristics, Internal citor at Pin 2 cannot follow instantaneous audio
    Detector, For Varying Inputs

    Vert. = output, 10 mV/cm


    Hori •. = input, 10 mV/cm

    Both available AGC inputs may be used, as in


    Figure 13, to provide full·wave output detection,
    which responds to both positive and negative
    output peak voltages.

    If a transformer is used to provide fu II wave AGC


    detection as shown in Figure 13, it must be chosen
    to meet two criteria. First, it must have a high
    enough input impedance to avoid loading down the FIGURE 15. AGC Circuit with External Peak Detector

    ANSl-6
    vanatlons, audio frequency linearity is not dis- of an unused transmission channel must be reo
    turbed, although charging from the low impedance moved, until useful information is received. The
    of Pin 2 and discharging through a much higher squelch circuit of Figure 17 includes a number of
    resistance, causes fast attack, slow release AGC refinements, which make it smooth·acting, and
    action. easy on the ear of the listener.

    In this example, common·mode input bias is ob· The threshold potentiometer at Pin 7 is manually
    tained directly from Vee, through equal resistors, set to cut in at any desired input level. The large
    to minimize offsets resulting from input bias capacitor at Pin 6, and its associated charging
    current. resistor, may be chosen to give squelch release
    times of as much as several seconds, while the
    The family of transfer characteristics, Figure 16, large current sinking capability into Pin 6 assures
    shows that some output increase occurs as the fast attack, so that first speech syllables are not
    input increases, but by only a small percentage. lost.

    A portion of the voltage at Pin 6 is fed back to


    the threshold potentiometer; since there are two
    stable voltage states at Pin 6, this creates a con·
    trolled amount of hysteresis in the squelch circuit.
    Thus, there exists a "dead band" of squelch
    sensitivity, which greatly enhances the circuit's
    immunity to rapid transmission channel fading, or
    erratic speech patterns. Combined with the slow·
    release characteristic, hysteresis gives a very well·
    behaved squelch system. A typical threshold con·
    trol setting might be one at which amplification
    begins above a 20 mV p.p input. With the feedback
    values shown, the input level must consistently
    stay below 12 mV p.p before gain is cut off. The
    small feedback resistor may be eliminated if hys·
    teresis is not required.
    FIGURE 16. AGe Transfer Characteristics Transistor
    Detector, For Varying Inputs
    While squelch attack is abrupt, release follows the
    Vert. = output, 10mV/cm slow charging contour of the time constant capaci·
    Hariz. = input, 10mV/cm tor, through the logarithmic gain control region.
    Thus, gain "fades out" following cessation of
    When using an external peak detector, proper speech, rather than the less ear·pleasing effect of
    layout and biasing are essential to prevent the conventional squelch circuits, in which a rush of
    transistor from oscillating. As always multiple background noise may be heard, followed by an
    bypassing of the power supply should be used. In abrup,t and often percussive cutoff.
    addition, a capacitor of approximately .01 j.tF
    should be connected from the base of the PNP to The time constant capacitor is charged by a volt·
    the collector and from the base to Vee. These age divider, rather than a single resistor, so that its
    prevent any positive feedback from causing the quiescent charged voltage is about +3V, with the
    external peak detector to oscillate. values shown, from a +12V supply. There is no
    need to charge the capacitor much above this
    point, because gain has already been completely
    SQUELCH APPLICATIONS
    cut off, and further charging only makes more
    Squelch Preamplifier with Hysteresis work for the large geometry transistor at Pin 6, in
    performing its rapid discharge function. In any
    Audio squelch is useful in noisy acoustic environ· event, if a single charging resistor is used, the
    ments, to suppress background microphone noises, timing capacitor cannot charge above about+6.5V,
    and in receiving systems, where the constant clatter because both Pins 3 and 4 are shunted internally
    by protective zener diodes.

    In Figure 17, the LM170 appears in another of its


    lOOK many possible input configurations. It is directly
    CHARIi'PO/i
    IIISISTDII driven by a low resistance dynamic or controlled·
    magnetic microphone, with no other input biasing
    components required. The amplifier is compact
    SQUELCH
    enough to fit inside even the smallest commercial

    1 microphone cases; its low current drain from sup·


    THRUHDLD

    lOOI! c~~~~ 50
    "F
    plies between +4.5 and +6.0V would permit inclu·
    (SHDR'TOGROUNOTO
    O(F(ATHYST£AUISI
    sion of batteries within the same case.

    Figure 18 illustrates how a large number of such


    FIGURE 17. Squelched Preamplifier with Hysteresis microphones could be directly connected to a

    AN51-7
    OSCILLATORS

    Wien-Bridge Oscillator Using the LM170


    The classic Wien-Bridge Oscillator is still a popular
    choice for many designs.

    A brief review of the principle of this form of


    oscillator will show how ideally su ited is the
    I
    I LM170 to this configuration.
    I
    M'CR~i~~~ES Figure 20 shows the general configuration of the
    FIGURE 18. Random Access Microphone System Wien-Bridge oscillator.

    common bus, at their outputs, to give a random


    access, automatic break·in public address or paging
    system, which might be useful, for example, at a
    large conference table, or in a courtroom. While
    background noises at each microphone location
    would be suppressed, close talking would immedi·
    ately allow one or more speakers to be heard. Be· FIGURE 20. General Wien-Bridge Oscillator Configuration
    cause squelch switching levels are compatible with
    TTL logic, a priority logic system could be devised, The components R 1 C l and R2C2 form a positive
    which would not only give certain speakers "break- feedback network whose transfer, it can be shown,
    in" priority, but allow them to automatically cut is a maximum when the lead produced by R1 Cl
    off certain other speakers at the same time. . and the lag afforded by R2C2 have the same value.
    At this condition the "gain" of the network's is
    TRANSMITTER OR TAPE RECORDER VOX 1
    Av = (1 + R l /R 2 +C 2/C l )
    In addition to squelching its own gain, the LM 170
    can become a voice-operated-relay control, or and the frequency is given by the expression:
    VOX, to switch high powered electronic or electro-
    mechanical devices. Automatic transmit-receive f =
    operation is possible in two way communication 211yRl R2 C1 C2
    systems, or tape recorder motors may be switched R3 and R4 form a negative feedback loop and
    on at the first syllable of infrequent speech, such control the gain of the amplifier. For sustained
    as in dictation, conserving tape. oscillation, the loop gain of the system must equal
    unity (in practice slightly greater), therefore the
    To handle large amounts of power, all that is condition for oscillation is
    needed is a small PNP power transistor, driving a
    relay, which can have multiple poles. Action is R3 + R4 = 1 + Rl + C2
    essentially the same as in squelch operation, except
    R4 R2 C,
    that the capacitor discharged by Pin 6 is charged or
    by the relay driving circuitry. The amplifier may R3 Rl + C2
    simultaneously be used as a continuous-running R4 R2 Cl
    preamplifier, may be squelched along with the
    Amplitude control of an oscillator assists in stabi-
    relay, or may even operate with an independent lizing its frequency as well as amplitude since it
    AGC signal, into Pin 3 or 4.
    prevents the poles from wandering about on their
    root locus plot with gain changes and ensures
    starting.

    Practically, one of the negative feedback resistors


    is often made voltage sensitive to ensure reliable
    starting and to control the output amplitude. If R3
    is chosen to be voltage sensitive, its characteristic
    has to be negative (such as a thermistor) or more
    usually R4 is the control element, using, very
    often, a light bulb which has a positive voltage-
    FIGURE 19. VOX Preamp resistance characteristic.

    A reed relay is shown in the schematic of F ig- The simple elements such as the thermistor and
    ure 19, but any fast acting relay may be used. The light bulb rely for their action on their thermal
    relay coil is shunted by a diode, to protect the characteristics. The response time for these devices
    PNP transistor. If power supply impedance is high limits their usefulness.
    the circuit may tend to oscillate; bypassing the
    supply with a fairly large capacitor will eliminate Alternatively the. gain of the amplifier itself may
    the problem. be varied to afford amplitude stability.
    It can now be seen how the LM170 dovetails Decade Tunable Oscillator
    nicely with the Wien-Bridge Oscillator configura-
    By using a modified twin-tee feedback network,
    tion_ It has gain, plus and minus inputs and an
    the LM170 will produce a sine wave oscillation,
    auxiliary control of gain via its "AGC Control
    tunable over one decade in frequency_The tech-
    inputs"_
    nique used is shown in Figure 23 where wideband
    positive feedback is applied to the non-inverting
    Figure 21 shows a suitable low-frequency oscillator
    input by the capacitive divider C1 & C2 - Capacitor
    design embodying the principles just discussed_
    C1 also decouples the input from supply noise_

    "'
    11IK

    ""
    J9DK

    .'.""
    tl,C2'1,F-8H,
    Cl.CZ"I'"F-IIH,

    FIGURE 21_ Wien-Bridge Oscillator ..."


    FIGURE 23_ Decade Tunable Oscillator
    The positive feedback loop from Pin 8, the output, Negative feedback occurs through the twin T at all
    to Pin lOuses R = 200k and C = _1 for 8 Hz_ The frequencies except the null frequency of the T
    R of the lag arm is formed from two resistors network, allowing the circuit to oscillate there_
    which provide bias for Pin 10, they are of course The nominal low frequency of oscillation for the
    in parallel with regard to signal. The bias for Pin 1 circuit is approximately 320 Hz with the assym-
    is provided in the same manner. The 820k resistor metric parallel T shown_ At this frequency and 1 V
    together with the bias resistors provides a maxi- rms out, the total harmonic distortion is under
    mum loop gain of about 4, the system needs a gain 0.25%_ At the upper frequency limit, 3300 Hz the
    of three for oscillation since the attenuation of output has dropped less than 1_5 dB and the
    the positive feedback loop at resonance is 3_ distortion is 0.45%_

    The resulting output is peak detected at constant A Modulated 455 kHz Signal Generator
    Pin 4 of the device which is the base of an emitter
    An inexpensive, high "Q", 455 kHz ceramic filter
    follower biased by the external adjustable potenti-
    may be substituted for the twin-tee feedback net-
    ometer chain, the amplitude adjustment_ Detector
    smoothing is provided by the 1000 p.F capacitor
    connected to Pin 2, the em itter of the detector
    emitter follower_ The large value is dictated in
    th is particu lar design by the desire to ach ieve
    regulation at about 10 Hz_

    The frequency may be changed by changing only


    the capacitors up to a few kHz, beyond that it is
    desirable to reduce the bridge resistor values so
    that the input current offset characteristics of
    the LM 170 do not limit the performance_ Oscil-
    lators up to a few MHz m"y then be fabricated_
    FIGURE 24_ 455 kHz Modulated Constant Output
    Oscillator

    \
    r-.. F=8H~
    i-'
    F=80Hz

    100 2DD 400 600 BOD 1000


    DUTPUT AMPLITUDE (mV,ms)

    FIGURE 22. Oscillator Distortion vs Output Level

    Figure 22 shows the distortion versus output


    amplitude of the circuit shown in Figure 3 for
    8 Hz and 80 Hz versions of the oscillator. FIGURE 25_ 455 kHz Modulated by 100 Hz

    AN51-9
    work of the previous example, to create a regu- circuitry, shown in Figure 27 connects one of the
    lated-output AM IF al ignment generator, Figure AGC control pins, Pin 4, to the collector of a
    24. If the AGC threshold voltage, which determines saturating switch, 0 21 , at Pin 6. With no signal,
    stabilized output, is varied at a low (audio) rate, 0 20 is saturated and 0 21 is off, and Pin 6 sits at
    the output amplitude will be forced to track the the voltage determined by the supply and resistive
    audio modulation, as in Figure 25. dividing network, or by the internal zener.

    The input configuration shown in Figure 19 may


    be used when two power supplies are available
    elsewhere in the system, as it allows the inputs and
    output of the LM 170 to be referred to ground. Of
    course, any other suitable input biasing scheme
    may be used instead, for the 455 kHz signal
    generator.

    Simultaneous Squelch & AGC Using the LM170


    An interesting application of the LM 170 involves
    simultaneously obtaining AGC and a fast attack, FIGURE 27. Normal Squelch Circuit
    slow release squelch. It has been contributed by
    B. Chandler Shaw of Bendix Electrodynamics, Note that no capacitor is connected to Pin 2. When
    North Hollywood, California. the combination of peak decreasing signal currents
    and low enough shunt-values of Squelch Threshold
    control are such that the base drive for 0 20 no
    longer causes saturation, 0 36 and 0 21 immediately
    turn 'on, rapidly discharging the capacitor at Pin 6,
    lowering the voltage at Pins 4 and 2, and bringing
    I
    the amplifier quickly up to full gain. Upon cessa-
    I tion of the signal, 0 20 saturates again turning
    L~ 0 36 and 0 21 off, and the voltage at Pin 4 rises
    ."
    INPUT
    according to the RC time constant of the network,
    giving some delay, and finally a smooth turn-off
    FIGURE 26. Internal AGe Control Circuitry of the amplifier.

    In normal AGC operation, a filter capacitor is If a filter capacitor were connected from Pin 2 to
    required on Pin 2 to store the peak AGC control ground, it would not be possible to lower quickly
    signal. The circuitry involved, shown in Figure 26, the voltage at Pin 2 to obtain a fast attack squelch.
    uses the emitter follower 0 24 as a buffer and peak However, if the capacitor C 1 is connected to Pin 6,
    detector. Obviously, the voltage on the filter capa- as shown in Figure 28, Pin 2 is drawn down
    citor can be rapidly increased (lowering the gain) rapidly when unsquelching and the low imped-
    by the current available through the emitter fol- ance path through 0 21 provides the ground for the
    lower but decreases slowly by discharging through filtering action required for AGC with signal and
    the 50k resistor (increasing the gain). This is exact- threshold level applied at Pin 3. With no signal,
    ly opposite of what we require. The normal squelch 0 21 turns off and the voltage at Pin 4 rises nor-

    TOAGC
    Vee ARRAY

    DC
    FEEDBACK

    r---'
    v" I
    I
    I lOOK

    C2
    r25~F
    O - - - - - n - - - - - " ' . - A U O I O FEEDBACK
    ___ L~O_~_ ..J
    SQUELCH
    THRESHOLD L---"VIIIr---_oI_OCTHRESHOlO
    15K

    100

    FIGURE 28. Simultaneous Squelch and AGe

    AN51-1O
    mally, slowly squelching the amplifier. Note that
    C, becomes reverse biased with no signal. Since
    the voltage between Pin 4 and 2 is only one diode
    drop, this is insufficient to forward bias the capa·
    citor and no deforming occurs. Hysteresis is pro·
    vided by the positive feedback to the bottom end
    of the threshold control through the 33k resistor.

    Temperature Compensating Techniques


    FIGURE 30. Temperature Compensating Circuitry
    The LM 170 AGC control circuit is designed for a
    "transition width" of approximately 400 mV, to trol voltage going to Pin 3 or Pin 4 of the LM 170
    go from full gain to practically zero output swing. to give the desired gain. To adjust this circuit, the
    Due to this narrow control voltage width and to amount of thermal compensation needed is deter-
    the AGC control stage being biased essentially mined from the curves as before. The temperature
    from a three diode chain, the gain of the LM170 is shift over the desired operating range and the
    subject to large variation with temperature. (See amount of gain needed are also known. Therefore,
    data sheet for curves of Av vs Control Voltage at the amount of DC shift in AGC control voltage is
    different temperatures.) With approximately a 2 also known by taking it straight from the Av vs
    mV per degree C shift per diode the three diode Control Voltage curves. This gives the number of
    chain bias voltage can vary by 600 mV over a 6T mV per degree C required. Potentiometers R, and
    of 100°C. As a worst case, at a given control volt· R2 are then set to give proper operation. An ex-
    age of 2.4V at room temperature, the gain may ample is shown below:
    vary from +40 dB at _55°C to -30 dB at +125°C.
    This necessitates the use of an external voltage Gain Required 30 dB
    compensation circuit that can stabilize gain varia· Operating Temperature
    tions over any temperature range from _55°C to Range: -55°C to +125°C
    +125°C.
    Change in AGC Control
    Two circuits were found to be quite effective in Voltage (from Av vs
    reducing voltage gain drift. The first has less com- Control Voltage Curves
    ponents but is less flexible, while the second is in data sheet) 1.9V to 2.7V = 800 mV
    slightly more difficult to adjust but gives a wide
    degree of compensation over the guaranteed tem- This means 800 mV 4.4 mVtC
    1800C or
    perature operating range.
    Potentiometer R, shunts T, thereby reducing the
    The first circuit is shown in Figures 29A and 29B. compensation from a maximum of 6 mV/oC. The
    Figure 29A has only two diodes and is used only value of R, was chosen to be approximately 10k
    where a maximum shift of 4 mVtC in AGC con- ohms to prevent an unnecessary waste of current
    trol voltage is required. This will be effective at from Vee.
    gain levels only slightly below maximum. From the
    curves it can be seen that at lower gain levels, more Let R, = 10 kQ
    than 4 mVtC of compensation is required so the
    three diode chain shown in Figure 29B is used. To set for a T.C. of 4.4 mV, set R, to 4.4/6.0 or
    Adjustment is simple. Once the amount of com- 74% of its total value or 7400 ohms.
    pensation needed is found from the curves and
    the correct circuit is chosen, potentiometer R, is Now potentiometer R2 is used to set the AGC
    adjusted to give the desired gain. control voltage to give a gain of 30 dB.

    The relative displacement of the three temperature


    curves on the Av vs Control voltage plot clearly
    AI R2
    UK 10K shows that the relation between control voltage
    and temperature is not linear. Therefore, since
    "'
    UK UK
    both of the compensating techniques described
    above are approximately linear, some gain change
    with temperature is to be expected. This shift is
    minimized however, by either of these simple,
    easily adjusted, circuits so that total variations in
    FIGURE 29A. Temperature FIGURE 29B. Temperature gain less than ±3 dB over the entire operating
    Compensating Circuitry Compensating Circuitry range is possible.

    If a more flexible circuit is desired, the one shown Conclusion


    in Figure 30 can be used. Transistor T, biased by
    R4 and 2R4 provides a maximum of 6 mVtC The LM 170 is an extremely versatile system com-
    thermal coefficient. Potentiometer R, shunting T" ponent, allowing squelch and AGC in inexpensive
    is adjusted to provide the amount of compensation communication systems. As a general purpose vari-
    needed. Potentiometer R2 then sets the AGC con- able gain element, the device opens up many new

    AN51-11
    areas of circuit design, in which closed loop gain
    feedback may be used to control other parameters,
    heretofore never considered as convenient vari·
    abies. Its compatibility with ordinary monolithic
    logic creates possibilities in digital·communication
    system interfacing. The applications discussed in
    this report should stimulate fresh thinking, in
    finding new and useful services for a unique vari·
    able circuit element made possible only by mono·
    lithic technology.

    APPENDIX

    Squelch Release Timing


    The timing capacitor from Pin 6 to ground in
    FIGURE 31. 5 "F Capacitor Timings
    Figure 17 is charged by an external resistor (nomi·
    nally 100 kn), to determine the delay between
    cessation of speech and tu rnoff of the LM 170.
    Figures 31, 32 and 33 show timings available from
    5, 10 and 25 /IF capacitors. The upper trace is the
    input, 15 20 mV/cm. Notice that the input does
    not have to be completely shut off, but must only
    remain below the externally set squelch threshold
    long enough for the timing capacitor to charge to
    the gain control region. Both traces are shown at
    200 ms per division.

    The lower trace is the amplifier's output. At first,


    since input level is below the squelch threshold,
    output is zero. An abrupt increase in input level
    above the threshold causes almost immediate turn·
    on of the amplifier. When input level is decreased
    to its original value, amplifier output follows FIGURE 32. 10 "F Capacitor Timings
    linearly, because gain is still at its maximum value.
    A delay period follows, during which the timing
    capacitor charges from the low voltage (less than
    lV) previously forced by the squelch output, Pin 6,
    up to the gain control region, which begins at
    about +2.1V. The capacitor is still charging along
    an exponential RC curve while it passes through
    the gain control region, so that a gradual turnoff
    is observed, rather than the less pleasant abrupt
    turnoff of conventional squelch systems.

    As an alternative to choosing different timing


    capacitor.values for different release times, a single
    value may be used along with a potentiometer
    which would replace the lOOk charging resistor.
    This would allow a front panel variable delay
    control, accessible by the system user. FIGURE 33. 25 "F Capacitor Timings

    AN51-12
    September 1971

    HIGH SPEED ANALOG SWITCHES

    SUMMARY

    In the past, many factors combined to make The telephone companies are probably the most
    precision, high speed analog switching circuits com- adept at signal mUltiplexing, but other applications
    plex and expensive, if not impossible. A unique are beginning to appear. Modern aircraft are using
    monolithic J-FET family opens new analog switch- multiplexing to reduce weight in wire harnesses.
    ing applications which require high toggle rates, Any applications requiring long multiconductor
    high frequency signal handling ability, and high cable runs are prime targets for economic use of
    level analog signals with broad dynamic range_ analog signal multiplexing.
    Called the AM 1ODD, AM 1001 and AM 1002 analog
    switches, these devices were developed specifically TIME DOMAIN MULTIPLEXING
    for high speed analog switching applications. The
    AM 1000 series overcomes the problem of slow
    There are two basic types of multiplexing: fre-
    switching speed normally associated with junction
    quency domain multiplexing and time domain
    FET analog switches. While MOS analog switches
    are noted for their high speed, they have the mUltiplexing. Frequency domain multiplexing is
    common in RF communications, it uses a number
    peculiar problem of their ON resistance being
    modulated by the analog signal level. The AM 1000 of subcarriers on a data channel, each subcarrier
    series eliminates this problem too. being modulated in some manner. An example
    would be FM radio standard broadcast which has
    National's AM 1000 series analog switches are home stereo multiplex information (a suppressed
    simple N-channel monolithic integrated circuit carrier double sideband subcarrier) and the SCA
    J-FETs. They are packaged in TO- 72 (4-pin TO-18) commercial "background music" multiplex in-
    headers to reduce circuit board space and yet formation (an FM modulated subcarrier). When
    retain the advantages of a hermetically sealed the number of data channels becomes great, fre-
    package. quency domain multiplexing becomes difficult to
    implement.
    WHAT IS AN ANALOG SIGNAL?
    In time domain multiplexing, a certain time slot
    An analog signal is an electrical voltage (or is allowed for sampling of a particu lar data line.
    current) whose level is an analog of certain in- Thus, if you sample some analog information
    formation. This information can be an electrical during a 10 /.Is time slot at a 10 kHz rate, you
    level itself, a voice signal, an electrical analog have time "left over" to sample nine other signals
    of a pressure, temperature, position, etc., or any at 10 /.Is intervals at a 10 kHz rate. If you can
    other data source. The analog information may improve the analog switch device to execute a
    also be preconditioned by logarithm ic compres- suitable sample in only 1 /.Is, you have made a
    sion or expansion, or other desired "distortion." tenfold improvement and you have the choice of
    If the analog information does not vary quickly increasing system channel capability to 100 chan-
    with time and if many analog signals have to nels (with no change in analog signal bandwidth),
    be handled in a system, the analog information increasing analog signal frequency bandwidth by
    may be sampled periodically rather than monitored 10 times (with no increase in channels), or a com-
    continuously. Sampled data systems can dramati- promise between increasing signal bandwidth and
    cally reduce cost and weight by proper utilization increasing the number of data channels. This is
    of available information channel bandwidth where what the AM 1000 family of analog switches is
    the cost of additional data channels becomes all about; they allow shorter sampling times for a
    expensive. given signal accuracy.

    AN53-1
    WHAT MAKES A GOOD ANALOG SWITCH? There is at least -1 OV from gate to sou rce of 0 1
    so it is pinched off and leakage from input to
    There are five principle parameters which deter-
    output is in the pA range. O 2 has -10V from gate
    mine how good an analog switch is:
    to source so it is also pinched off and its current
    which shunts the input signal is in the pA range.
    ON resistance
    ON resistance modulation
    OFF resistance
    Offset voltage
    Commutation rate

    There are other considerations which may also be


    significant for special cases, but these five will
    almost always have significant bearing on a system
    design. For most applications, there are two de- FIGURE 2. AM1000 Circuit
    vices which are the most popular-MaS switches
    and J-FET switches. Relays normally would be
    a good choice but they won't toggle very fast.
    In general, the MaS switches have had a speed ad-
    vantage, and ease of fabrication advantage, where-
    as the J-FET switches have an advantage of lower
    ON resistance, no ON resistance modulation, higher
    voltage capability.4.5,6 The AM 1 000 family of
    analog switches have all of the advantages of the
    J-FET plus high speed wh:ch makes it superior to
    any MaS switch in a precision system.
    FIGURE 3. AM1000 Turned Off
    WHAT MAKES THE AM1000 FAST?
    Figure 1 shows a typical J-FET circuit used in
    analog switching. Diode Dl allows the gate drive 0 3 is operated at OV gate-source so it draws satura-
    signal to drive the gate negative thus turning off tion current, loss. The bias supply for Dl must be
    the J-FET switch. When the gate drive signal goes 10V more positive than the negative drive signal.
    positive, diode Dl decouples the drive from the During turn-on, the drive signal ideally makes a
    gate and resistor Rg discharges the gate-source step function change from -20V to +10V thus
    capacitance. Rg must be large so it doesn't load turning D2 off. The gates of 0 1 , O2 and 0 3 are
    the analog signal, typical values for Rg are 100 kQ then driven positive by the saturation current of
    and up; thus the gate capacitance-R g time con- 0 3 through diode D 1 . The rate that this voltage
    stant is large which precludes high switching rates. slews is dependent on gate capacitance and loss
    If Ciss of the J-FET is 15 pF nominal and Rg is of 0 3 , Cissloff) of the AM 1000 is about 10 pF so
    100 kQ, the time constant is 1.5 !J.s thus making the voltage slews at:
    megacycle toggle rates impossible.
    dv loss 5 X 10-3
    dt ; Ciss ; 5 X 108 V/sec
    10-11

    """'~
    ..,
    SIG~Al .....

    -= ':"
    R, 111 R,
    Within 5V of rise (about 10 ns), O2 begins to turn
    on and Dl turns off. The remainder of the gate
    " capacitance charge is discharged into the input
    s,DE~~ ::::""1IL (or source) of 0 1 via the ON resistance of O2 and
    0 3 , During this time interval the average series
    resistance of O2 and 0 3 is about 2 kQ and the
    FIGURE 1_ Typical J-FET Analog Switch gate capacitance is changing from about 10 pF
    to about 25 pF. The approximate RC time con-
    stant is 20 pF and 2 kQ, or 40 ns, depending on
    the level of the analog signal. Total turn on time
    The AM 1000 consists of three J-FETs. One large
    is therefore about 50 ns. For a +10V analog
    and two small ones. The large one acts as the
    signal, the correct analysis is a little more complex,
    analog signal pass transistor. The two smaller
    but the AM 1000 will turn on in about 70 ns for
    FETs act as a turn-on circuit which reduces
    this circuit condition. The reason that the turn-on
    switching transients.
    transient at R L is drastically reduced is that the
    The pinchoff voltage of all these FETs are al- discharge path of gate capacitance does not flow
    most identical and are all less than 10V. In Fig- through R L . The small transient that may appear
    ure 3 (ignoring diode drops), the gates of all three at RL is due to the time that Dl is on during
    FETs are at -20V and the AM 1000 is turned off. turn-on.

    AN53-2
    The capacitance of the AM 1000 is about twice that
    of the MOS switch but the system load resistance
    is 25 times lower thus giving the AM 1000 a toggle
    rate advantage of about 12 times over the MOS
    "high speed" analog switch. In order to graphically
    illustrate the superiority of the AM 1000, two
    simple series switches were constructed; one with
    O-;*"I-+-~_...J L~+*-o DRI~E the MOS switch and one with an AM 1000. The
    MOS analog switch was set up to sample a +10V
    DC signal, after being switched off, the output
    FIGURE 4. AM1000 Turning On returns to ground level. The AM1000 was set up
    to sample a portion of the turn off transient of
    So, the AM1000 achieves its high switching speed the MOS analog switch, each switch with a 0.5%
    because its Rg (see Figure 1) is very low during system accuracy! Figure 5 shows the circuit used
    turn on, yet its Rg during the OFF state is in the to obtain the oscillograph shown in Figure 6A.
    G ohm range and thus doesn't load the signal.

    TOGGLE RATE
    The toggle rate (how fast the switch can be turned
    on and off) of an analog switch is not a simple
    straightforward parameter for a real system design.
    The reason is 'that most analog switches are speci-
    fied at a ridiculously low impedance level; this is
    done in order to show the highest speed that the
    device can possibly go. This speed is not normally
    realistic for most systems designs. In order to
    demonstrate a realistic comparison, the AM1000
    will be pitted against an MOS analog switch for a
    system with a ± 1OV analog signal swing.

    TABLE 1: AM1000 - MOS Parameter Comparison


    FIGURE 5. Analog Switch Comparison Circuit

    MOS
    PARAMETER AM1000
    ANALOG SWITCH
    ROSlon) (Max) 3011 40011 A National LH0033 high speed buffer was used
    to sense the analog voltage at the load resistor of
    ROSlon) (Min) 2011 15011
    the MOS switch and drive the analog input of the
    ROSien) (Nom) 2511 27511
    AM1000. Figure 6A shows the oscillogram; the
    C,~ INoml 15 pF 7 pF upper trace is the MOS switch turning off; its load
    Breakdown Volts 40V 35V voltage heading toward ground; the lower trace
    (oscilloscope vertical gain reduced slightlY for
    photo clarity) shows the AM 1000 sampling this
    ROSlan) and Ciss indicate the basic speed capability
    switching transient. Figure 68 shows the timing
    of the devices assuming low source and load
    pulses, the upper trace being the MOS drive timing
    impedance, here the AM 1000 has a speed advantage
    and the lower is the AM1000 drive timing (posi-
    of about 5: lover the MOS switch.
    tive indicating off for both devices). It is interesting
    The parameter that affects toggle rate the most, to note that the turn-on delay or "aperture time"
    however is ROSlan) variation with analog signal of the AM1000 is primarily caused by the DH0034
    level. At an analog signal of +10V, the MOS translator. Maximum specified turn on time is
    switch has an ROSlan) of 150n and for a -10V 100 ns and turn off time is specified at 100 ns for
    analog signal it has an on resistance of 400n. This the AM 1000. Figure 6 shows absolute superiority
    variation of ON resistance is caused by the bu Ik of the AM1000 in switching ability for a given
    gate to channel voltage modulating the ON re- system accuracy.
    sistance of the MOS switch. 5 Thus, the MOS
    switch has a design on resistance characteristic of AM1000 DRIVE CIRCUITS
    275n ±125n. The AM1000 has an ROSlon) of 25n
    Normally, analog switches will be selected by some
    ±5n and its resistance does not vary with analog
    digital control means wh ich will usually mean OV
    signal level.
    add +5V power supply levels. The AM 1 000 needs
    For a system of a given accuracy, the load imped- a driver capable of handling the full analog voltage
    ance is determined by the variations expected in swing, plus 10V. Therefore a circuit known as an
    channel resistance. Assuming a system accuracy of analog switch translator is normally requried. There
    ±0.5%, the AM1000 load resistance could be as are several types available. All of the following
    low as 1 kn; the MOS switch load resistance would circuits feature "break before make" action which
    have to be 25 kn (±125n being 0.5% of 25 kn). is desirable for mUltiplexing.

    AN53-3
    +1DV

    +BV

    > +BV

    ~
    ~ "IV
    ~
    ~>
    +2V

    HORIZONTAL - 200 ",/OIV

    FIGURE 6A. AM1000 Sampling the Switching Transient of an MOS Analog Switch

    OFF

    MOS
    ANALOG
    SWITCH

    ON

    OFF

    AM1000

    ON

    FIGURE 6B. Analog Switch Drive Timing

    Analog switch translator·drivers fall into two basic which the AM 1000 must charge. Usually this
    categories. Those with pullups and those without. additional capacitance is not excessive.
    If the translator·driver has a pullup, such as the
    National DM7800, then a switching diode must be
    used to decouple the driver from the AM 1000
    when the driver goes positive.
    on
    m
    r~pull

    FIGURE 8. Translator·Driver without Pullup


    m
    rNI'IlTS
    In some systems, the cost of monolithic or hybrid
    drivers is not worth the space they save. Figure 9
    shows a four channel driver using low cost discrete
    components. The ON channel is selected by binary
    FIGURE 7. Translator·Driver with Voltage Pullup
    coding and is DTL·TTL compatible. If A and B
    are "high" then drive is removed from as allowing
    The AM 1000 does not requ ire a driver with a pull· channell AM100l to pull up and turn on. 0 6 , 0 7
    up. Figure 8 shows the circuit for this configura· and as have drive applied which pull down on
    tion. Note that the driver decoupling diode is not CH2, 3 and 4 thus turning them off. The voltages
    required. This configuration eliminates one power and devices indicated in Figure 9 allow ±15V
    supply but adds the capacitance of the driver analog signals to be handled.

    AN 53-4
    FIGURE 9. Binary Controlled Four Channel Multiplexer

    CURRENT MODE MULTIPLEXING The 10 k02 feedback resistor shown results in 10V
    output for 1 mA input. Thus the scaling resistor at
    So far, the discussion of mUltiplexing circuits has
    the input is selected for 1 mA for 100V input, or
    been confined to sampling various analog input
    10 IlAN. A 1000V analog signal would use a
    voltages. Voltage mode analog switching allows
    1 M02 scaling resistor. For lower voltage signals,
    maximum toggle rates but limited voltage range
    the Ron of the AM1000 would have to be con-
    (±10V for AM1000, AM1002 and ±15V for
    sidered for precision systems. The bound limit
    AM100l).
    diodes connected to +10V and -10V prevents
    If large analog voltages must be handled, current excessive voltage from appearing at the AM 1000.
    mode multiplexing must be used; toggle rate is Input impedance to the current to voltage con-
    reduced because accurate current-voltage conver- verter is Rf divided by the open loop op amp gain
    ters are not as fast as non-inverting voltage ampli- (5000 for the LH0032); the input impedance
    fiers. Analog signal loading can also be a problem. would be 202 in Figure 10.
    Nevertheless current mode multiplexing allows
    sampling of very high analog voltages. This is OTHER APPLICATIONS
    accomplished by using scaling resistors and bound
    Analog computer circuits can make good use of
    limit diodes at the input of the analog switch.
    analog switches. A few examples are sample and
    Also, in this case the current to voltage converter
    hold circuits, reset stabilized circuits, integrator
    should be the lowest impedance point in the
    reset switches, and chopper stabilized amplifiers. 4
    system. so the AM 1000 must be "turned around",
    so its analog "output" is used for the signal input Video signal switching can be done with a mini-
    and vice versa. mum of switching transients. More unusual appli-
    cations such as double sideband suppressed carrier
    modulators can be constructed plus double side-
    band suppressed carrier demodulation and FM
    quadrature demodulators. 5

    CONCLUSION
    Where precision, high speed analog switching is
    required, the AM1000 series of analog switches
    "rewrites the book."
    Time domain multiplexing can be dramatically
    FIGURE 10. Current Mode Multiplexing improved in channel capability and/or analog signal
    bandwidth capability. Sample and hold circuits can
    The system sensitivity in Figure lOis determined be improved, chopper stabilized amplifiers can be
    by Rf in the cu rrent to voltage converter op amp. improved and virtually any other circuit which
    The LH0032 J-FET input op amp is selected requires precision, high level, high speed analog
    because of its high slew rate and low input current. switching can be improved.

    AN53-5
    BIBLIOGRAPHY 4. Cohen, Joel M. "Sample and Hold Circuits Using
    1. Mrazek, Dale "High Speed MOS Commutators" FET Analog Gates" EEE, January 1971.
    National Sem iconductor AN-28. 5. Stump, Ronald and Wollesen, Donald, "MOS
    2. Wollesen, Donald L. "Analog Signal Commuta- Analog Switches" National Semiconductor AN-
    tion" National Semiconductor AN-33. 38.
    3. Wollesen, Donald L. "Analog Switching - High 6. Gordon, Bernard, "Digital Sampling and Re-
    Speed with J-FETS" EON, January 15, 1970. covery of Analog Signals" EEE, May 1970.

    AN53-6
    »
    :2
    I
    Todd Smathers c.n
    April 1972 ~

    »
    o
    o
    A COMPLETE MONOLITHIC
    $:
    "tI
    AM/FM/SSB IF STRIP r-
    m
    -I
    m
    CIRCUIT DESCRIPTION
    s:
    General o
    :2
    The LM273 and LM274 families of multi-mode
    IF amplifier/detectors have been designed for AM,
    for the TO-5 style package, those for the dual-in-
    line package are indicated in parentheses_
    or-
    FM, SSB, CW and video applications in the com- :::j
    munications market. They are able to perform SECTION ONE
    J:
    these diverse functions and others by virtue of a The first section consists of two gain blocks sep-
    flexible organization with accessible general pur- arated by a wide range AGC network_ Each gain o
    pose functional blocks_ As shown in Figure 1, they block functions as a linear amplifier for low level
    »
    are divided into two separate sections, which share
    a common power supply. Pin numbers are shown
    AM, SSB or video, or as a symmetric emitter
    coupled limiter for FM. s:
    ......
    ."
    s:
    ......
    en
    15T5EC110111 1ST SECTION
    OUTPUT
    en
    INPUT g:!

    ."
    --o'~ 10(14)
    en
    AGCCONTRDLI
    QUAD CAPACnOASWITCH r-Q
    -= sm
    GN.
    SUBSTRATE/CASEI
    -I
    ::D
    "tI
    2N05fCTlDN
    INPUT

    DC fEEDBACK
    BYPASS

    PIN NUMBERSIIliPARENTHESESARE
    FDRMGlDEDDUALINLINEPACKACES

    1(10)

    FM DUADRATURE PHASEI DUTPUTfROMOUAD PEAK


    SSBBFO/AMUNBALAIliCE DETECTOR/AMPLIFIER/ DETECTOR
    INPUT PRODUCT DETECTOR OUTPUT

    FIGURE 1. LM273 and LM274 Block Diagram

    1ST SECTION ISTSECTIDN


    INPUT OUTPUT

    AGCCONTROtl
    DUAD CAPACITOR SWITCH

    FIGURE 2. First Section Block Diagram

    AN54-1
    About 10 dB of voltage gain is taken ahead of the The LM273/LM373 and LM274/LM374 differ in
    AGe block to improve AM or SSB signal to noise their second stage of the first section, as shown in
    ratio with AGe and still provide reasonable signal Figure 5. In the LM273/LM373, a low impedance
    handling characteristics. The input will accept output emitter follower is used to drive low-Z
    100 mVrms signals without objectionable distor· loads such as mechanical or ceramic filters. Its
    tion, due to the emitter degenerating resistors, output impedance is about 70n at 455 kHz and
    R. in the input stage shown in Figure 3. climbs to about 200n at 30 MHz, and a simple
    series resistor, Rs , may be used to match this
    value to the filter input impedance. The additional
    insertion loss caused by this resistor, compared to
    1ST SECTION transformer matching, is approximately 20 10glO
    INPUT
    ""Ra/R IN , where Ro is the output resistance of
    Pin 9 and RIN is the filter input resistance. Although
    external active circuitry may be connected to
    Pin 9, no more than 200llA of De current should
    be drawn from there.
    The LM274/LM374 has a high impedance current
    source output, excellent for driving high-Z loads
    such as Le, crystal and some ceramic filters. To
    prevent saturation of 0 7 , the maximum magni·
    FIGURE 3. Input Stage tude of the load impedance driven by Pin 9 should
    be no greater than (Vee-Ia RL -4.5V)/l pk-l a ),
    The input impedance is approximately that of the where 10 and Ipk are the peak and quiescent out·
    lk input bias resistor, making it relatively indepen· put currents at Pin 9 respectively and RL is the
    dant of h f ., which can vary over a 4: 1 range below effective De resistance between Pin 9 and Vce.
    f~. The differential output current of the first stage
    The quiescent output current is 0.5 mA to 1.0 mA
    is applied to the half·balanced attenuator shown at room temperature and, for FM, the peak current
    in Figure 4. is very close to twice 10 , Then for RL small and a
    12V supply, IZlmax ~ 7.5V/l.0 mA = 7.5k.
    v' AM or SSB operation requires only about a
    5 mVrms input to Pin 4, the second section input,
    I - - - - - - v "..
    and therefore in theory the swing on Pin 9 need
    only be 5 mV times the filter insertion loss, and
    the filter Z can be much higher than for FM.
    v'

    AGCCDNTROLI
    OUADCAPACITOR 1
    SWITCH

    1ST SECTION
    OUTPUT

    FIGURE 4. Attenuator Circuitry

    As Pin 1 becomes more positive than the tempera,


    ture compensated reference voltage, V REF (about
    3.75V), both parts of 0'0 steal signal current away
    from 0 9 and 0", and from the latters' load reo la) LM213/lMJ7J
    sistances. Therefore, the differential output voltage
    decreases, i.e., the gain is reduced. As current is
    shunted away from Og and a" by the AGe action v'

    there also occurs a common mode voltage shift


    in their collector output voltage. This is signifi-
    cantly reduced by the emitter resistor in the fol-
    lower connected to VB lAS and a feedback loop
    which adjusts the value of 10 ,

    Also connected to Pin 1 is the input to the


    quadrature capacitor switch. Since AGe is not de-
    sired for FM, grounding the AGe control input
    enables the switch which connects the capacitor
    to the Pin 6 input of the product/quadrature
    detector. This switch stays enabled until V, be-
    comes greater than about 3V. The value of R is (b) lM2741LM314
    greater than 20k, and the current into Pin 1, with
    5V applied is less than 100llA at room temperature. FIGURE 5_ 1st Section Output Stages

    AN54-2
    In general, the power delivered to the load will be inverting input of the first stage of section two,
    greater if an LM274/LM374 is used for loads and should be bypassed for I F frequencies with a
    greater than 1 k, and LM273/LM373 for loads less disc capacitor and for the low frequency feedback
    than 1 k. compensation with an electrolytic.

    SECTION TWO

    The second section of both the LM273/LM373


    and the LM274/LM374 consists of two gain blocks,
    a quadrature capacitor and switch, a product/
    quadrature detector, and a DC feedback amplifier.
    The gain blocks amplify linearly at low levels for
    AM, SSB, CW or video, and limit symmetrically
    at high levels for FM.

    FM Detection

    When Pin 1 is grounded, as described in the discus- FIGURE 6. Second Section


    sion on the first section, the quadrature capacitor is
    closed connecting a 6 pF junction capacitor from
    the output of the first stage to the Pin 6 input
    of the quadrature detector. A simple phase shift
    network, a.c. coupled from Pin 6 to ground,
    can be designed to give about 90° difference in F.
    IF
    phase (), between the two inputs to the quadrature
    detector at center frequency, and a rapid I'!.()/I'!.f
    around center. At high levels, the quadrature
    detector can be looked at as a pair of switches
    controlled by the two detector inputs, as shown
    in Figure 7. When the phase shift network pro·
    duces a 90° phase difference between the two
    switches, the capacitor is being charged from the
    current source and discharged through the resistors
    for equal time intervals. This is shown in the first
    timing diagram and is the condition defining f = fo .

    Note that the charge and discharge rate is twice


    the IF frequency. In the second timing diagram, f = fa
    the phase shift is less than 90° and the charge time
    0" 10" 180'
    is considerably greater than the discharge time. I I I
    Therefore the average voltage across the capacitor
    in this condition will be greater than in the 90°
    case at f = f o.
    :~ I I I

    In the LM273/LM373 and LM274/LM374, the ': ~ r---I


    switching described above is implemented by a 'rl ; L-J L
    I
    double balanced mixer (similar to the LM1596)
    shown in Figure 8. The lower input to the quad· C I CHARGE~
    CHARGE
    DIS. I
    rature detector 034'S base, is driven by an emitter
    I I I
    follower, 0 22 , directly from the first stage out·
    put load. (Devices 0 34 and 0 35 form the first
    switch Sl, in the analogy but in a balanced arrange·
    ment.) The other input, the bases of 0 28 and 0 29 ,
    is driven by the voltage developed across the D" 90" 180'

    quadrature network connected to Pin 6. For de· I I I

    tector switch ing action, about 100 m Vrms of sig·


    nal are required there and this places a lower limit
    on the impedance seen from Pin 6 in some FM
    :---:--t-rL-
    I I
    applications. The four devices, 0 27 -0 30, form the : ~
    S2 switch in balanced fashion with the capacitor f-1; ; L-.Jr---IL -
    discharge path through the 1 k load resistor. I I

    An active balance network, indicated in Figure 6,


    looks at the average voltage at the base of 0 34,
    ~
    compares it to the bias voltage V at 035'S base,
    and feeds a correction signal back to Pin 3, the DC FIGURE 7. Quadrature Detector Analog and
    Feedback Bypass Pin. This pin is actually the Timing Diagrams

    AN54-3
    matched to the following AM peak detector.
    Therefore, when Pin 6 is pulled down to unbalance
    the product detector, a switch is activated which
    transfers the DC feedback comparison to Pin 7 and
    appropriate reference voltage. As a result, the AM
    performance is optimized under all conditions of
    temperature, supply variations, etc.
    AM Active Peak Detector
    The final block in the LM273/LM373 and LM274/
    LM374 is an active positive peak detector. Basically,
    it is a video amplifier with a power detector on
    its output, and close control over the DC output
    voltage. The quiescent voltage at Pin 8 matches
    the AGC stage .reference voltage, Vref in Figure 4,
    FIGURE 8. Simplified Equivalent Circuit of with respect to both magnitude and temperature
    Quadrature Detector coefficient. As a result, the AM output changes less
    than ± 1 dB over temperature.
    On positive going signals, 0 46 rapidly charges
    capacitor C to the peak value of the voltage and
    then as the voltage decreases its base emitter
    becomes reverse biased and the capacitor discharges
    slowly through the 50 p.A current source. The
    value of C should be chosen large enough to hold
    ripple below values which will cause undesired
    AGC voltage modulation, yet small enough to be
    J
    IIU"UT'RUMIIUAU
    OEleCTOAIAIII'lIFl~RI able to follow downward going envelope changes.
    PAODUCTDElHTOR

    y'

    OUTPUT fROM QUAD


    DETECTOR/AMPLlfIERI 7
    PRODUCT DETECTOR

    FIGURE 9. Product Detector Circuitry ! PEAKDETECTDRQUT

    SSB Detection
    The double balanced detector, used in switching
    mode for FM, becomes a product detector for
    SSB when the lower pair is operated at lower levels FIGURE 10. Positive Peak Detector
    in its Iinear mode.
    Under these conditions the circuit functions as a Since Pin 7, the input to the detector, is available,
    form of analog multiplier, producing outputs at a simple shu'nt filter connected at this point should
    the sum and difference of the BFa and IF fre· be used to improve SIN performance by eliminating
    quencies. The desired one of these is chosen by any broadband noise generated in the second
    the filter on Pin 7, which for the difference (audio) section of the IC. Since this is a fairly low impe-
    frequency is a roll-off capacitor. dance point, about 1 k, a low LlC ratio is required.
    Since AGC is used for SSB, Pin 1 is no longer
    grounded and the quadrature capacitor switch is TYPICAL APPLICATIONS
    opened. Nevertheless, the impedance to ground at
    Pin 6 for the IF should ,be kept low, especially AM Operation
    at high frequencies, to avoid any oscillator pulling. In Figure 11, the LM273 functions as an AM IF
    strip operating at 455 kHz. AM operation is
    AM Detection achieved by connecting R2 from Pin 6 to ground to
    offset the product detector, as previously described,
    Since the product detector/quadrature detector
    is not requ ired for AM, the upper port is switched and by connecting R 1 from the AM detector out·
    out by means of a resistor from Pin 6 to ground. put at Pin 8 to the AGC input, Pin 1. The value of
    This can be envisioned as applying a minus DC R 1 may be modified to obtain different trade·
    input to one port of the multiplier so that it simply off's between output voltage and AGC range. This
    becomes an inverting amplifier. results from the AGC current flowing in RIde·
    creasing the AGC voltage at Pin 1, therefore having
    It is no longer as important that the offset between a degenerative effect on loop gain and causing the
    0 34 and 0 35 bases be minimized, and it is more AC and DC output at Pin 8 to be higher for a
    desirable that the DC output voltage at Pin 7 be given AGC voltage.

    AN54-4
    1-----------------------------------------,
    I ,--------1 I
    I I I
    I I
    I
    I I
    I
    I I
    I I I
    o-_ _L_--+<!P-2~' -. -----~
    '~2VC 1-
    ~~

    FIGURE 11. AM IF Strip

    The filter shown from Pin 7 to ground is used to The larger 0 is, the more rapid is the phase change
    shape the bandwidth of the passband to the active versus frequency shift and therefore, the greater
    peak detector. The AC coupled tank passes the the detected output. If the phase nonlinearity
    desired signal while shunting all wideband noise produced by this network is considered predomin-
    to ground, preventing undesirable AGCing on noise ately that due to the cubic term in the arctan ex-
    spikes. The interstage filter shown from Pin 9 to pansion, then the relative harmonic distortion (HO)
    Pin 4 may also be used to provide additional band- expressed in percent will be approximately
    pass shaping. It may be an L·C, ceramic, crystal
    or any other type of filter that is desired. (See
    section on "Application Hints").
    HD(%) ~ 33.3
    [ OL1
    L W
    W
    r
    (2 + b.ww\)J1 3
    FM Operation
    The quadrature network can be implemented in
    many fashions. Of these, the simplest is the paral·
    lei resonant tank AC coupled to Pin 6, as shown in

    ~33.3 C~w) 3

    Note that the distortion that will be produced


    FIGURE 12. AC Equivalent of Simple is proportional to 0 3 while phase shift (and there-
    Quadrature Network fore, output) is proportional to 0, for a given b.w
    and w r• For example, for ±75 kHz deviation
    Figure 8. The AC equivalent circuit is shown in at 10.7 MHz, the 0 of the network must be 66.7
    Figure 12. Rp is the parallel equivalent resistance or less for 3.3"10 distortion.
    of the coil, and in the expressions, l/G T is Rp ll3k.

    SSB Operation
    2 Cs
    S C+Cs Typical single sideband operation is shown in
    2 GT 1 Figure 13. This mode of operation is basically
    S + S C + Cs + L(C + Cs ) the same as AM with the exception that the
    balanced mixer is now used for a product detector
    instead of as a simple gain stage. The local oscil-
    () lator is fed into Pin 6 with the optimum level of
    (W/_W 2 ) switching signal to the upper port being approxi-
    mately 60 mVrms. The AGC operates in the same
    _
    11 O(w 2_".,2) +_1 [O(W 2_W2)] 3 +
    r r
    manner as for AM with the feedback resistor from
    - 2" - WWr 3 WrW ... Pin 8 to Pin 1 determining output level and AGC
    figure of merit. The audio output is taken from
    Pin 7 so it should have all RF shunted to ground
    for 45 0 < () < 135 0
    through a capacitor filter. The impedance looking
    into Pin 7 is well defined at approximately 1 kn so
    w,2 ~ l/[L(C + Cs )] this facilitates making a simple RC roll off with a
    b.w ~ Iw r - W I well defined cutoff frequency_ Additional AGC
    filtering may be added by a capacitor from Pi n 8
    o ~ [w,(C + Cs )] /G T to ground if desired.

    AN54-5
    1----------------------------,
    I 1----- 1 I
    I ' I
    >-~~ I
    I I
    I I
    I I
    o - - -----+L
    .~f~c
    -P-P.'
    i -,
    ~~gl

    MANUAL
    toJllRDl
    ..,
    SSUUDIG

    FIGURE 13. Single Sideband IF Strip

    '-----------~~~~~~~~~~--------------------l

    . ."
    I I I
    ~
    I I
    I
    ItIP':'::~
    I I

    I
    II II
    o-
    __ <p-~~.
    L_-.... - , _____ -.1
    .~~O 1.
    -:f!:

    FIGURE 14. Synchronous AM Detector

    Synchronous AM Detector as in the AM configuration by connecting a 5k


    resistor in parallel with an .01 f.LF capacitor from
    The LM273, LM274 series lends itself well to Pin 6 to ground and serves only as an additional
    synchronous AM detection by virtue of its doubly gain stage. An "S" cu rve network is now connected
    balanced mixer requiring no external component& to Pin 7 which is the input to the AM peak detec-
    for operation. A typical connection diagram is tor. Frequency deviations are now converted to
    shown in Figure 14. The circuit is very similar to amplitude variations by the "S" curve network and
    the previous AM I F setup with the exception that are then converted to audio by the peak detector
    detection now takes place in the product detector with the output now being taken at Pin 8. Pin 1 is
    rather than the peak detector. For correct syn· grounded since no AGe is desired in the limiting
    chronous detection the signal level at Pin 6 should mode for FM. Here the LM274 shows superiority
    be sufficient to drive the upper port into a full to the LM273. Additional gain can be obtained
    switching mode. A level near 60 mVrms is optimum. from the first gain block in add ition to bandpass
    If enough signal is not available at the input of filtering by using a high Q tank as a collector load
    the LM273 or LM274 to develop this large a sig· at Pin 9. For example, at 10.7 MHz, a coil of 2 f.LH
    nal swing at Pin 6, then an additional gain stage with an unloaded Q approaching one hundred, in
    may be inserted from Pin 9 to Pin 6. National's parallel with approximately 100 pF. connected
    LM703L works very nicely here to provide suffi· from Pin 9 to Vee greatly improves not only
    cient gain to swing Pin 6 into full switching with wideband noise and unwanted signal rejection but
    input levels as low as several microvolts. The audio also lowers the FM limiting threshold to 300 f.LVrms,
    output is taken at Pin 7 and again add itional AGC By using the peak detector, the useable audio out·
    filtering may be added at Pin 8 if desired. The put can be increased to 150 mVrms or greater.
    interstage filter is optional and only needs to
    be used if receiver bandwid'th requirements necessi· Double Conversion I F Strip
    tate its use.
    An interesting approach to a monolithic double
    FM Slope Detector conversion I F strip is possible with the LM273 and
    LM274 by using what is normally the AGC
    An alternate method for using the LM273/LM274 block, as a balanced mixer. A possible schematic
    for FM detection is shown in Figure 15. The quad· is shown in Figure 16. The incoming signal is fed
    rature detector is no longer used. It is unbalanced into Pin 2 and after passing through one gain

    AN54·6
    r-------------------------------,
    I r------, I
    I I
    I
    I
    I
    . ~
    I

    'l,'!'" 0.01111 '~llln".lO ... ttG." .... , ... ""''',,''. Tlll., ... "",,,,

    FIGURE 15. 10.7 MHz FM Slope Detector IF Strip

    '------------~-~~~~~~~~--------------------l

    I I I
    i :
    I
    I
    I
    J1 ~::,~.''" ...
    1M. DUHIOR

    .~l.o-Q---';

    FIGURE 16. Double Conversion IF Strip

    stage is converted down in frequency the first If the strip is to be used for AM then the active
    time by inserting the first local oscillator signal peak detector can be used and the audio can be
    into Pin 1. A bandpass network from Pin 9 to taken at Pin 8. A series RC roll·off must be added,
    Pin 4 selects the desired frequency and passes it however, to derive the DC voltage needed for AGC
    to successive gain stages. The second frequency action if the internal AM detector is used.
    conversion occurs in the balanced mixer with the
    second local oscillator injected into Pin 6. Addi· Coherent Phase Locked Receiver
    tional filtering is connected at Pin 7 to shunt all A phase-locked receiver for detecting FM or FSK
    but the desired signal from the succeeding stage. signals using the LM273 or LM274 is shown in
    Simultaneous AGC is available by feeding back a Figure 18. The design is similar to the double con-
    DC voltage, derived from Pin 8, to Pin 1. Frequency version I F strip mentioned previously, with the
    conversion with the AGC block requires a local addition that the first local oscillator is a voltage
    oscillator signal level on the order of 800 m Vrms controlled oscillator whose control voltage is de-
    while the signal level into Pin 6 can be somewhat rived from the audio output. A gain stage has
    less, on the order of 60 mVrms. Figure 17 shows been inserted from the audio out/control voltage
    the typical conversion gain performance versus point to the input to the VCO to provide higher
    L.O. frequency in the AGC block using 800 mVrms loop gain.
    for local oscillator input level.
    LM273. LM274 Typical Application Breadboard

    30 Figure 19 shows a printed circuit board that has


    Ac (dB)
    ~ 2S
    been laid out for using the LM273 or LM274 in
    either AM, FM, or SSB modes. It was designed for
    ~ 20 t±: ,
    wide band coupling between Pins 9 and 4 which
    ~ 15
    I may necessitate slight component layout alteration
    if bandpass filtering is desired. Provision has been
    made for a 50>2 input terminator resistor if needed.
    VlO • B~Drllvrm5
    'r;"lkH'l I For AM, Pin 6 is used to unbalance the balanced
    mixer; for FM Pin 6 is connected to the phase shift
    510152025303540455055
    INPUT FREQUENCY (MH,J
    network; and for SSB Pin 6 becomes the local
    oscillator input. Pin 7 is used for noise filtering in
    AM while it is the audio out for FM and SSB.
    FIGURE 17. AGC Block Frequencv Conversion
    Voltage Gain vs Input Frequency
    Observe that short leads, close AC bypassing, and
    overall coverage by the ground plane give optimum
    and very stable operation.

    AN54-7
    i------------~-~~~~~~~~---------------~----l
    I I I
    , I I
    ",;;o-j I
    I
    I
    I
    I
    •J
    .:,,1>0----+

    FIGURE lB. Phase Locked Receiver IF Strip

    LM273
    LM274
    • •
    GNU

    TO PIN 10

    TO PIN 1

    AM/FM
    AUOIO
    li'
    IN

    •
    • •

    FIGURE 19. Printed Circuit Board for AM, FM, or SSB

    LM273 application hints AGC figure of merit or sensitivity low


    1. Very high loss in Pin 1 and Pin 4 coupling
    AM Detector Mode network or fi Iter.
    Problem: 2. Bandpass network at Pin 7 too wide or too
    low Q.
    No signal; voltage check reveals DC voltage >4.0
    3. Input impedance match to Pin 2 off.
    volts at Pin 8.
    FM Detector Mode
    Possible Cause: Noisy, distorted det. signal out or low FM limiting
    1. LM273 oscillating due to remote bypassing of range
    Pins 3 or 10. 1. Poor shielding allowing RF coupling between
    2. LM273 oscillating due to long leads, allowing interstage coupling networks.
    feedback from Pins 8 to 7, 7 to 4, 7 to 2, or a 2. Phase shift network shifted from I F frequency
    combination thereof. and detection taking place on outside slope of
    3. Very wide bandwidth coupling between stages detector curve.
    and at Pin 7, allowing AGC action on detected 3. Interstage coupling circuit and phase shift
    noise. network not aligned to each other.
    4. Shunt bandpass filter not connected to Pin 7, 4. No, or insufficient RF bypass and audio de-
    or too broad. emphasis at Pin 7.
    Detected audio level low or distortion high 5. Phase shift network has wrong bandwidth for
    proper detection in the band desired.
    1. Load impedance on Pin 8 too low, or capaci-
    SSB Mode
    tance too high.
    Low figure of merit range and/or low level, noisy
    2. Feedback AGC resistor too low or high.
    3. Impedance of bandpass network on Pin 7 too det. audio.
    low. 1. Pre inserted carrier level low.
    4. Audio decoupling cap. at Pin 1 insufficient, 2. Insufficient cap. on Pin 8 to have audio peak
    allowing audio to modulate it. detection.
    5. Low frequency bypass at Pin 3 insufficient. 3. See 'AM detector' problems.

    AN54-8
    l>
    Z
    I
    Robert C. Dobkin U'I
    December 1971 0)

    ...
    N
    <
    o
    r-
    1.2 volt reference -I
    ::u
    m
    'T1
    m
    INTRODUCTION ::u
    Temperature compensated zener diodes are the be proportional to b,V sE . 0 3 is a gain stage that
    m
    Z
    most easily used voltage reference. However, the will regulate the output at a voltage equal to its
    o
    lowest voltage temperature-compensated zener is emitter base voltage plus the drop across R2. The m
    6_2 volts_ This makes it inconvenient to obtain emitter base voltage of 0 3 has a negative tempera-
    a zero temperature-coefficient reference when the ture coefficient while the b,V BE component across
    operating supply voltage is 6 volts or lower_ With R2 has a positive temperature coefficient. It will
    the availability of the LMl13, this problem no be shown that the ouput voltage will be tempera-
    longer exists_ ture compensated when the sum of the two voltages
    The LM 113 is a 1_2V temperature compensated is equal to the energy-band-gap voltage.
    shunt regulator diode. The reference is synthesized Conditions for temperature compensation can be
    using transistors and resistors rather than a break- derived starting with the equation for the emitter-
    down mechanism. It provides extremely tight regu- base voltage of a transistor which is2
    lation over a wide range of operating currents in
    addition to unusually low breakdown voltage and
    low temperature coefficient.

    DESIGN CONCEPTS
    The reference in the LM 113 is developed from the
    highly-predictable emitter-base voltage of inte-
    grated transistors. In its simplest form, the voltage where V gO is the extrapolated energy-band-gap
    voltage for the semiconductor material at absolute
    is equal to the energy-band-gap voltage of the
    zero, q is the charge of an electron, n is a constant
    semiconductor material. For silicon, this is 1.205V.
    which depends on how the transistor is made
    Further, the output voltage is well determined in a
    (approximately 1.5 for double-diffused, NPN tran-
    production environment.
    sistors), k is Boltzmann's constant, T is absolute
    A simplified version of this reference 1 is shown in temperature, Ie is collector current and V BEO is
    Figure 1. In this circuit, 0 1 is operated at a rela- the emitter-base voltage at To and leo.
    tively high current density. The current density
    The emitter-base voltage differential between two
    of O2 is about ten times lower. and the emitter-
    transistors operated at different current densities
    base voltage differential (LW SE ) between the two
    devices appears across R 3 . If the transistors have is given by
    high current gains, the voltage across R2 will also kT J1
    q log. J; (2)

    v' where J is current density.


    Referring to Equation (1), the last two terms are
    quite small and are made even smaller by making
    Ie vary as absolute temperature. At any rate, they
    can be ignored for now because they are of the
    same order as errors caused by nontheoretical be-
    havior of the transistors that must be determined
    empirically. /
    '.
    If the reference is composed of V BE plus a voltage
    proportional to b,V BE , the output voltage is ob-
    tained by adding (1) in its simplified form to (2):
    L-.!-...._ _.:-.....~GROUND
    V,.f = VgO (1 - ~)+ VBEO(~)
    kT :!!
    FIGURE 1. The low Voltage Reference in One of Its
    Simpler Forms.
    + q log. J 2 ' (3)

    AN56-1
    Differentiating with respect to temperature yields Figure 4 shows the output voltage change with
    operating current. From 0.5 mA to 20 mA there
    aV,.f _ ~ + VB EO + ~ :!.! (4) is only about 6 mV of change. A good portion of
    aT - - T o T o q log. J 2 '
    the output change is due to the resistance of the
    For zero temperature drift, this quantity should aluminum bonding wires and the Kovar leads on
    equal zero, giving the package. At currents below about 0.3 mA the
    diode ·no longer regulates. This is because there
    kTo J,
    VgO = VSEO + -q- log. J;' (5) is insufficient current to bias the internal tran-
    sistors into their active region. Figure 5 illustrates
    The first term on the right is the initial emitter-base the breakdown characteristic of the diode.
    voltage while the second is the component propor-
    tional to emitter-base voltage differential. Hence,
    if the sum of the two are equal to the energy-band-
    gap voltage of the semiconductor, the reference
    will be temperature-compensated.
    2: 1.230 f-f-f-f-f-f-f-f-H
    Figure 2 shows the actual circuit of the LMl13. ~
    0, and O2 provide the !:NSE term and 0 4 provides !; 1.220 f-t-~-±... -+--+-++-+-..t
    the VSE term as in the simplified circuit. The
    additional transistors are used to decrease the
    ~~ 1.210 I-I-I-I-I-I-I-I-H
    dynamic resistance, improving the regulation of
    the reference against current changes. 0 3 in con- 12DD_SL,__,L,__,L,...J,L-,L,-.L,-.L,-:.L,...."=,-:',,.,
    junction with current inverter, 0 5 and 0 6 , provide TEMPERATURE ("C)
    a current source load for 0 4 to achieve high gain.
    FIGURE 3. Output Voltage Change with Temperature

    '""'

    _, ~LUllL~-LLU~ __L...J
    0.' " 30
    REVERSE CURRENT (mAl

    FIGURE 4. Output Voltage Change with Current

    FIGURE 2. Schematic of the LMl13

    0 7 and Og buffer 0 4 against changes in operating


    current and give the reference a very low output
    resistance. 0 8 sets the minimum operating current D.Z 0.4 0.6 0.8 1.0 1.2 1.4

    of 0 7 and absorbs any leakage from Og. Capacitors REVERSE VOLTAGE (V)

    C" C2 and resistors Rg and RlO frequency com-


    pensate the regulator diode. FIGURE 5. Reverse Breakdown Characteristics

    PERFORMANCE
    The most important features of the regulator diode
    APPLICATIONS
    are its good temperature stability and low dynamic
    resistance. Figure 3 shows the typical change in The applications for zener diodes are so numerous
    output voltage over a _55°C to +125°C temperature that no attempt to delineate them wi II be made.
    range. The reference voltage changes less than However, the low breakdown voltage and the fact
    0.5% with temperature, and the temperature coef- that the breakdown voltage is equal to a physical
    ficient is relatively independent of operating property of silicon - the energy band gap voltage-
    current. makes it useful in several interesting applications.

    AN56-2
    Also the low temperature coefficient makes it use-
    ful in regulator applications - especially in battery
    powered systems where the input voltage is less
    than 6V_

    Figure 6 shows a 2V voltage regulator which will


    operate on input voltages of only 3V_ An LMl13
    is the voltage reference and is driven by a FET
    current source, 01' An operational amplifier com-
    pares a fraction of the output voltage with the
    reference. Drive is supplied to output transistor 02
    through the V+ power lead of the operational
    amplifier. Pin 6 of the op amp is connected to the
    LMl13 rather than the output since this allows
    a lower minimum input voltage. The dynamic FIGURE 7. Amplifier Biasing for Constant Gain with
    Temperature
    resistance of the LM 113 is so low that current
    changes from the output of the operational ampli-
    fier do not appreciably affect regulation. Frequency As shown, the gain will change less than two per
    compensation is accomplished with both the 50 pF cent over a -55°C to +125°C temperature range.
    and the 1 f.1F output capacitor. Using the LMl14A monolithic transistor and low
    drift metal film resistors, the amplifier will have
    less than 2 f.1V fc voltage drift. Even lower drift
    may be obtained by unbalancing the collector
    load resistors to null out the initial offset. Drift
    under nulled condition will be typically less than
    0.5 f.1vtc_
    The differential amplifier may be used as a pre-
    amplifier for a low-cost operational amplifier such
    as an LM 101 A to improve its voltage drift charac-
    teristics. Since the gain of the operational amplifier
    '"
    21<2905
    is increased by a factor of 100, the frequency
    compensation capacitor must also be increased
    from 30 pF to 3000 pF for unity gain operation.
    To realize low voltage drift, case must be taken
    to minimize thermoelectric potentials due to
    temperature gradients. For example, the thermo-
    electric potential of some resistors may be more
    .....IM.-+-'---+-VOUT ·2V
    "
    n, than 30 f.1vtc, so a 1°C temperature gradient
    "
    UlK
    across the resistor on a circuit board will cause
    " "
    'Sohdl •• I,lum
    much larger errors than the amplifier drift alone.
    Wirewou nd resistors such as Evenohm are a good
    choice for low thermoelectric potential.
    Figure 8 illustrates an electronic thermometer
    FIGURE 6. Low Voltage Regulator Circuit using an inexpensive silicon transistor as the tem-
    perature sensor. It can provide better than 1°C

    It is important to use an operational amplifier with


    low quiescent current such as an LM108. The
    quiescent current flows through R2 and tends to
    turn on 02' However, the value shown is low
    enough to insure that O2 can be turned off at
    '""
    worst case condition of no load and 125°C
    operation.
    Figure 7 shows a differential amplifier with the
    current source biased by an LM 113. Since the
    LMl13 supplies a reference voltage equal to the
    energy band gap of silicon, the output current of
    the 2N2222 will vary as absolute temperature. This
    compensates the temperature sensitivity of the '"" 'AdI""lorDV"Ot
    transconductance of the differential amplifier 'Adl",II •• 100 ",VI C

    making the gain temperature stable. Further, the


    operating current is regulated against supply varia-
    tions keeping the gain stable over a wide supply FIGURE 8. Electronic Thermometer
    range.

    AN56-3
    accuracy over a 100°C range. The emitter-base has one hundred times better reverse characteris-
    turn-on voltage of silicon transistors is linear with tics than breakdown diodes. Additionally, wide-
    temperature. If the operating current of the sensing band noise and long term stability are good since
    transistor is made proportional to absolute tem· no breakdown mechanism is involved.
    perature the nonlinearily of emitter-base voltage
    can be minimized. Over a _55°C to 125°C tempera· The low temperature coefficient and low regulation
    ture range the nonlinearily is less than 2 mV or the voltage make it especially suitable for a low voltage
    equivalent of 1°C temperature change. regulator or battery operated equipment. Circuit
    design is eased by the fact that the output voltage
    An LMl13 diode regulates the input voltage to and temperature coefficient are largely indepen-
    1.2V. The 1.2V is applied through Rz to set the op- dent of operating current. Since the reference vol·
    erati ng cu rrent of the temperatu re-sensi ng transisto r. tage is equal to the extrapolated energy-band·gap
    of silicon, the device is useful in many temperature
    Resistor R4 biases the output of the amplifier compensation and temperature measurement appli-
    for zero output at O°C. Feedback resistor R5 is cations.
    then used to calibrate the output scale factor to
    100 mV tC. Once the output is zeroed, adjusting REFERENCES
    the scale factor does not change the zero.
    1. R.J. Widlar, "On Card Regulator for Logic
    CONCLUSION Circuits," National Semiconductor AN·42, Feb-
    ruary, 1971.
    A new two terminal low voltage shunt regulator
    has been described. It is electrically equivalent 2. J.S. Brugler, "Silicon Transistor Biasing for
    to a temperature-stable 1.2V breakdown diode. Linear Collector Current Temperature Depen-
    Over a -55°C to 125°C temperature range and dence," IEEE Journal of Solid State Circuits,
    operating currents of 0.5 mA to 20 mA the LM 113 pp. 57-58, June, 1967.

    AN56-4
    l>
    :2
    I
    Robert K. Underwood en
    March 1972 w

    :2
    m
    :E
    C
    m
    en
    NEW DESIGN TECHNIQUES G')
    FOR FET OP AMPS :2
    -t
    m
    (")
    :z:
    :2
    Introduction
    The LH0052, LH0042 and LH0022 series opera· lowest possible cost. The amplifiers are internally
    oc::
    tional amplifiers are "monobrid" integrated circuits compensated to be unity gain stable and require m
    consisting of a monolithic dual junction field no external parts for operation with the exception en
    effect transistor followed by a special Iinear inte- of feedback and input impedances as dictated by
    the application. Amplifiers are available in TO-99, ."
    grated circuit amplifier chip. Each device features
    very closely matched input characteristics, very (TO-5 metal can), TO-91 (10-lead 1/4" x 1/4" o
    high input impedance, and ultra low input currents flat pack) or TO-116 (14-lead cavity dual in-line ::JJ
    with no compromise in noise, common mode package) and are specified either for the full ."
    rejection ratio, open loop gain or slew rate. The military temperature range of _55°C to +125°C or m
    LH0052 is internally laser nulled and features offset for an expanded commercial temperature range of -t
    current of 100 femtoamps max at 25°C (100 pA
    at +125°Cl. offset voltage of 200 microvolts max
    _25°C to +85°C. Operation is specified for power
    supply voltages between 10 volts (±5 volts) and
    o
    ."
    and offset drift of 5 IlV 1°C max. Unlike most 44 volts (±22 volts). Table I below, and Typical Per-
    modu Ie F ET op amps, th is series of op amps does formance Characteristics (/ast page) give a summary l>
    not require "grading" of electrical performance
    at final test_ Different die types are used in each
    of other major parameters illustrating similarities
    and differences of members of the series. See
    s:
    ."
    member of the family to assure availability and individual data sheets for complete specifications. en

    TABLE 1. Porformanco Comparison of LH0052/LH0022/LH0042 FET Op Amp Family.

    PARAMETER (TA = 25°C) LH0052 LHOO22 LH0042 UNITS


    Offset Voltage (Max) 0.2 4 20 mV
    Offset Voltage Drift IMax) 5 10 20 INtC
    Offset Current (Max) 0.1 2.0 5.0 pA
    Bias Current (Max) 1.0 10 25 pA
    Open Loop Gain (Min) 100 100 50 V/mV
    Bandwidth (Typ) 1 1 1 MHz
    Slew Rate (Typ) 3 3 3 V/lls
    Output Current Drive (M in) ±10 ±10 ±10 rnA
    Min Supply Voltage ±5 ±5 1:5 V
    Max Supply Voltage ±22 ±22 ±22 V
    Input Voltage Range (Min) ±12 ±12 ±12 V
    CMRR (Min) 80 80 70 dB
    Compensation Components 0 0 0
    Output Current Limit Yes Yes Yes
    Simple Offset Null Yes Yes Yes
    Package Types TO-5 DIP, TO-5 DIP, TO-5
    FP FP

    AN63-1
    Why FETs?

    The virtue of super gain bipolar transistors as 1500


    the input stage to operational amplifiers is well
    known 1,2 and widely used in such amplifiers as
    the LM 1DB, LM 112, and LM216, These amplifiers
    attain very low input bias currents by special
    processing that allows the first stage to ru n at very
    low emitter currents while achieving current gains
    of 1500. This results in relatively constant bias and
    offset currents with temperature tend ing to increase
    at low temperatures where transistor gain is lowest. 1K lore lOOK 1M lDM
    (Figure 1) SOURCE RESISTANCE fi!sI

    FIGURE 2. Total Equivalent Input Noise Voltage

    A useful noise model applicable to operational


    amplifiers in general is shown in Figure 3. It con·
    sists of an ideal noiseless amplifier preceded by a
    number of noise sources. Amplifier voltage noise,
    EN, appears directly in series with one of the
    10-15 LJLJ---1--1.--1.--L.....J........J...-' inputs. Current noise from the amplifier develops
    _60_110_2002040 &080100120
    an additional noise voltage across the source reo
    TEMPERATURE ( C)
    sistance. The RMS value of thermal noise from the
    source resistances can be calculated from the
    FIGURE 1. Typicallb vs. Temperature for Several
    Op Amps equation Ers = V4kT(BW)Rs which simplifies to
    Ers = 4VRs nV /VHz for room temperature calcula·
    tions and resistor values in kilohms.

    The low emitter current available in the typical The total spot noise present at the input to the
    super gain amplifier severely limits the slew rate ideal amplifier may be found by summing the RMS
    attainable, the devices that have input currents in values of the three noise voltage sources as follows:
    the same area as the LH0052 family normally have
    slew rates in the neighborhood of a few tenths of a
    volt per microsecond. As long as a FET is operated
    in its normal linear region, its input current is not
    materially affected by the channel current. The
    LH0052 family, therefore, runs more input stage EN comes directly from data of the type plotted in
    current and thus attains a typical slew rate of the figure by looking at the flat portion of the curve
    three volts per microsecond. A soon·to·be an·
    nounced device (LH0062) has demonstrated slew
    rates greater than 50 volts per microsecond with
    the same input characteristics as the LH0052
    family.

    Rs

    FET's Feature Superior Noise at High Source


    Resistances Rs

    Figure 2 is a plot of total amplifier noise at 100 Hz


    (1 Hz bandwidth) vs source resistance for the
    LH0052 family of FET amplifiers and the LM10B,
    representative of the best super·gain bipolar ampli·
    fiers. Thermal noise contributed by the source
    resistance is also plotted. Note that at low source
    resistances the LM10B is lower noise; at high
    source resistance the LH0052 series is superior. FIGURE 3. Noise Model of an Operational Amplifier

    AN63·2
    below 10k and assuming that the current noise is at first glance that this would necessarily result in a
    insignificant in th is area. For the LH0052 and cheaper, more reliable product. At the present state
    LM10B EN, at 100 Hz, 1 Hz bandwidth, is of the art, severe compromises are necessary to
    70 nV/v'Hz and 35 nV/yHz respectively. IN may both the FET and bipolar devices so constructed as
    be computed from a total noise measurement at exemplified by the 740 and 536 with the net
    high source resistance by using a calculated value of result that specifications must be relaxed and lor
    E" and the previously measured value of EN' a yield loss suffered. The two chip "monobrid"
    approach taken with the LH0052 family maxi·
    mizes performance while allowing lowest cost.

    Circuit Description
    For the LH0052 family and the LM lOB, IN is
    10 fA/v'Hz and 100 fA/yHz respectively.
    Figure 4 is a simplified schematic typical of all of
    the amplifiers in the family. The input FET (0 "
    O2 ) is a monolithic dual similar in construction to
    One way to illustrate the importance of noise the discrete FMll00 series device. The stage is
    current in deciding which of two amplifier types operated as a source follower with V+ applied
    will be better in a given situation is to set the total directly to the drains for the maximum possible
    noise equal for the two cases and solve for the value common mode range.
    of Rs at which this occurs. The amplifier with the
    lower noise voltage will be superior at source resis·
    tances lower than this value; the one with lower
    current noise will be better at higher resistances. A differential common base PNP stage (03, 0 4 )
    Note that this is merely calculating the intersection serves as the load for the input FETs. The bases
    of the curves of Figure 2. The intersection will of this stage form the bias point for the backside
    normally lie near 150k when comparing the gate of the monolithic input FET3. To obtain
    LH0052 family with the best of the presently high voltage gain from the PNP common base stage,
    available bipolar amplifiers. the output resistances of 0 5 and 0 6 are used as
    loads, giving effective values of about 2 megohms
    while at the same time converting the differential
    current signal into a single ended Voltage. The
    Low Offset Voltage is no Problem with Modern operating drain current for the input stage is
    JFETs determined by the bias network composed of the
    current source 0 '0 and the diodes 0'1 and 0 ,2 ;
    target current is 40 m icroamps per side.
    FETs have a reputation for poor control of voltage
    matching characteristics that developed from be·
    havior of the early matched dual discrete devices.
    These were invariably a pair of separate FET chips
    mounted on the same header tested for gate to A Darlington driver (0 ,6 , 0 17 ) is used to avoid
    source voltage match at some specified current at loading the first stage output. The output stage
    room temperature. Devices constructed in this uses a conventional complementary symmetry
    design with a bias current of about 60 microamps
    manner tracked rather poorly over temperature due
    through 0 '4 and 0 20 to minimize crossover dis·
    to Gis mismatch and temperature gradients across
    the header. tortion. Output current is limited to about ±25 mA
    at 25°C ambient decreasing to about ±17 mA at
    +125°C. The output characteristics are similar to
    those of conventional ampl ifiers.
    The monolithic dual FETs of the FMll00 series
    interweave the channels of the two halves of the
    device and achieve a match not only of Vgs but of
    all other parameters. Further, the Vgs match is pre·
    served over a wide range of drain currents, drain to Simple Offset Voltage Adjustment does not De-
    source voltage, and temperature. The voltage drift grade Drift or CMRR
    attainable with this technique is exceeded only
    by the very best bipolar devices.
    These amplifiers use the same internal offset
    nulling technique as the LM741 and others, that is,
    a single 10k pot connected between the offset
    nulling pins and V- as shown in Figure 5. Adjust·
    It is possible to fabricate FETs and bipolar transis· ment of this pot will always produce offset null.
    tors on the same wafer at the same time. Why not With the premium devices of the series, it may be
    build a single monolithic FET/bipolar amplifier desirable to restrict the range of adjustment to in·
    utilizing each where it is best suited? It would seem crease the precision of the null. This may be done

    AN63·3
    OUTPUT

    ,n
    'OK

    OFFSET 10K POT IEXTERNAL) OFFSET


    NULL NULL

    FIGURE 4. Internal Schematic

    A2

    A2

    Al

    At

    Al

    Al

    L...-4~_v-
    '---e---v-
    *Al and I or A4 installed at calibration

    FIGURE 5. Trimpot Offset Trim FIGURE 6. Fixed Resistor Offset Trim

    by inserting a resistor of about lOOk in series with Careful PC Board Layout Must be Observed
    the wiper of the pot. This technique provides a
    In order to realize the full low input current
    method of externally nu II ing offset voltage of the
    capabilities of these amplifiers, considerable care
    amplifiers to zero with virtually no effect on offset
    must be exercised in the design of the input cir-
    voltage drift or CMRR.
    cu itry and in the selection of materials contacting
    the input conductors. A leakage impedance of
    By definition, offset voltage is that voltage which even 10 12 ohms to 15 volts produces a leakage
    must be applied between the input terminals to current of 15 pA, much higher than amplifier
    obtain zero output voltage. Th is suggests a straight- input current. This level of leakage may be inad-
    forward and practical "universal,,4 system to null vertently produced by socket leakage, poor quality
    the offset in an operating circuit. Figure 7 illus· or imperfectly cleaned' printed circu it boards, or
    trates one way that an adjustable voltage in the improperly cured protective coatings. Sockets are
    millivolt range may be connected in series with the to be avoided if possible; they can not only degrade
    input signal to subtract the amplifier offset. If this leakage current, but may cause other unsuspected
    technique of offset nulling at the inputs of the erratic behavior when used in severe environments.
    amplifier is used, the TO-5 devices of the series (If absolutely unavoidable, they should be high
    will bepin compatible with virtually all of the 8 Pin quality, preferably Teflon.) Printed circuit board
    TO-5 amplifiers on the market today, bipolar or material should be judged both on initial resis-
    FET. tivity and on the likelihood of degradation by

    AN63-4
    outside influences. Teflon and polycarbonate are GND
    particularly recommended; glass epoxy may be
    used if it is protected with a silicone or epoxy coat·
    ing to prevent moisture absorption. If operation at D----V·
    high humidities is required, this coating will be
    desirable anyway to control surface leakage. All
    residues of previous operations, such as soldering
    flux, inks, and resists, must of course be thoroughly
    removed before coating.

    R2

    Rl
    FIGURE 8. DIP Non-Inverting Amplifier PC Layout

    Rl
    r-~::<H::~>----~---GND

    R'
    R3
    v-
    v'
    v-·
    _..!:~== __ -===ft~::J<>--INPUT
    c:=-_=~f---V'
    20n A6
    2SK
    RS
    ':' 2DK

    ru·~+M r
    OUTPUT
    ADJUSTMENT RANGE" [IV+I - (V-I] (~) (Rl ~IRj)
    VOLTAGE GAIN =;{ FIGURE 9. Flat Pack Inverting Amplifier PC Layout

    FIGURE 7. Universal Offset Trim

    l'
    Another approach which has been successfully used
    with the TO-5 amplifiers is to term inate all critical
    connections on Teflon standoff insu lators. These
    may be interconnected as required with Teflon 4
    insulated wire, keeping connections as short as sO
    possible to minimize noise pick-up. A short length 6o---DUTPUT
    of Teflon tubing slipped over the wire from the 1
    amplifier prevents contact with the oversize hole
    in the mounting board. The remainder of the ampli-
    GUARD
    o ~
    r
    1

    fier connections may be terminated conventionally, v'


    either to printed circuit lands or to other standoff
    insu lators. FIGURE 10. TO-S - 10 Pin Pattern PC Layout

    Input Guarding Improves System Performance


    Even with properly cleaned and coated printed
    circuit boards, leakage currents can limit the circuit
    performance under severe environmental condi-
    tions. In most cases with the LH0052 family
    devices, leakagewill be primarly to V- as the inputs
    are between the offset null pin (wh ich in normal
    operation runs at a voltage very near V-) and the
    V- pin itself. This would seem to predict that
    leakage into the inverting and non-inverting inputs
    should at least be of the same polarity, but the
    effects are too unpredictable to make much use of
    the cancellation which should occur.
    FIGURE 11. TO-S - 8 Lead Pattern
    These currents may be intercepted before they
    reach the ampl ifier inputs by a guard conductor
    in the leakage path operating at the same potential The flat pack and dual-in-line packages have an
    asthe inputs. Resistance between the inputs and the unconnected pin on either side of the inputs. These
    guard will cause little current to flow because of may be used as shown, both to continue the guard
    the premise that the guard voltage equals the input into the package and as a convenient method of
    voltage. Suggested board layouts for the various surrounding the inputs with a guard conductor
    package types are shown in Figures 8 through 11. without running a line between device pins. The

    AN63-5
    eight lead TO-5 package has only one spare pin, so
    the leads must either be formed into a 10 lead
    circle with two gaps, or the pin circle expanded
    sufficiently to allow a conductor to pass between GUARD
    device pins. If the board is double sided or multi-
    layer, the guard pattern should be repeated on all
    conductor planes.
    Av =+1
    Figures 12 through 15 show how the guard is com· v-
    m itted on the more common op amp circu its. With R1 =RSOURCE
    an integrator or inverting amplifier, where the in-
    puts are close to ground potential, the guard is FIGURE 13. Guarded Voltage Follower

    Rl R2 junction of the feedback resistors. Low impedance


    1M 100M
    INPUT--'lNIr--4.....----'lNIr---..., in this context means that expected leakage cur-
    rents should not be capable of generating dele-
    terious error voltages. A resistor, R3 , may be
    added to balance the source resistance and thus
    cancel the effect of bias current.

    Rl R2
    loon 9.9K

    v'
    -R2
    AV =R'1=-100 GUARD

    R3 = RSOURCE

    FIGURE 12. Guarded Inverting Amplifier lNPUT-------fT~

    v-
    AV=l+M-=+1DD
    simply grounded. With the voltage follower, the
    guard is bootstrapped to the output. If it is de-
    FIGURE 14. Guarded Non-Inverting Amplifier
    sirable to put a resistor in the inverting input to
    compensate for the source resistance, it is con-
    nected as shown in Figure 13.
    The general case of a full differential configura-
    Guarding a non-inverting amplifier is a little more tion may require the use of a guard driver ampli-
    complicated. A low impedance point must be fier A2 as shown in Figure 15. Resistors Rs and R6
    created by using relatively low value feedback re- develop the proper voltage for the guard at their
    sistors to determine the gain (R l and R2 in junction, but it will normally be impractical to
    Figure 14). The guard is then connected to 'the make them low enough resistance due to source

    R2
    100M

    Rl· RJ
    R2· R4
    R1 = R5 + R6

    ~=Av
    Av '" ~ = 10

    FIGURE 15. Guarded Full Differential Amplifier

    AN63-6
    loading. R7 is included to balance the effect of Rs Precision Integrator
    plus R6 and thus not degrade the closed loop The low input bias currents attainable with ampli-
    common mode rejection. fiers of this series make them a natural choice for
    integrator applications requiring long time con-
    Voltage Followers stants. Figure 18 illustrates a typical practical
    circuit, Rl should be selected so that the total
    The excellent common mode rejection and range
    of the amplifiers in th is series suggest their use as
    unity gain voltage follower amplifiers. They per· TTL Ilr---- AHD'n - - - - - ,
    form well in this function with the one precaution """"""sn~
    COHTAGL

    • :
    I
    I
    - - - --,

    shown on the circuit of Figure 16. The straight-


    forward circuit with a direct feedback connection

    Rs
    Rl
    lOOK
    I

    ~ 10
    ":"
    -- -~lf-~-
    •
    '

    R4
    ''''
    11
    1

    11
    I

    RI t1

    IN'~~ o-"'.."""...._.-'f '-'


    -= Av '" +1

    \Iou,·~f-\I,···v,
    FIGURE 16. Unity Gain Voltage Follower

    FIGURE lB. Precision Integrator


    and no resistors will function, but if a low impe-
    dance signal having a slew rate faster than the
    amplifier can follow is applied to the input, a leakage current at the summing node is smaller
    differential input voltage might be developed in than the signal current (V l /R l ) by a margin suffi-
    excess of the absolute maximum. R 1 limits the ciant to insure the required accuracy, i.e.
    current under these conditions to a safe value of V l /R l » Ibl . C l should be chosen for low
    200 }lA. R2 is included to cancel the error voltage leakage, stability, accuracy, and low voltage coef·
    due to bias current and should in general be equal ficient. Polystyrene or polycarbonate dielectric is
    to the source resistance plus R l' the best choice for capacitances up to about one
    microfarad, Teflon is good for the lower values.
    For applications requ iring voltage gain as well as
    high input impedance, a voltage divider may be in- R2 is included to protect the input circuit during
    cluded in the feedback path as in Figure 17. The the reset transient, although many low speed appli·
    voltage gain of this circuit is approximately cations will not require it at all. If the resistance
    1 + R2/R3 (neglecting amplifier open loop gain). of the reset switch is 100 ohms, the maximum
    current that could flow in C l is 10V 1100 ~ 0.1 amp.
    In reality this may well be limited to a lower value
    RS Rl by loss, if the reset switch is an FET. Then the
    10M 100'
    rate of change of voltage cannot exceed 0.1 ampl
    1 }IF ~ 0.1 V/}ls which is well within the slew rate
    capabilities of the amplifier. R3 , used to balance
    the resistance in the inputs, should be made equal
    to the sum of R2 and the reset switch resistance.
    Av'" R2 ;JRl

    =+100
    Sample/Hold Amplifiers
    R4 - RS RJ
    1. The LH0052 fam ily of amplifiers is well su ited
    for use as a buffer amplifier in long hold-time
    sample/hold circuits. They may be used in any of
    FIGURE 17. Non·lnverting Amplifier the common configurations where improved hold
    performance is required. Figure 19A illustrates
    one circuit taking advantage of the low bias currents
    R4 is included as a convenient variable to equalize attainable. R 1 serves to bootstrap the connection
    resistances in the two amplifier inputs: R4 in series between analog switch Sl and S2 so that there is
    with the parallel combination of R2 and R3 should essentially no voltage across Sl in the hold mode.
    be set equal to the source resistance plus Rl . Note When Sl and S2 are closed to enter the sample
    that all of these resistors may not be necessary mode, the effect of Rl is slight as it is much higher
    depending on the required voltage gain, source resistance than the switches. After a long enough
    impedance, accuracy requ irement, temperature time, C l will charge to the input voltage, the
    range, and ampl ifier selected. amplifier will buffer it to the output, and both

    AN63-7
    ends of R, will be at the input potential so it input of the system. This causes C, to charge to a
    will have no effect at all after the transient. level proportional to the system DC offset. When
    Figure 19B illustrates an alternate circu it configura· the re·zero line is deactivated, the amplifier be·
    tion with input buffer amplifier. haves Iike a conventional inverting stage, sub·
    tracting off the system offset and giving a true
    ground referenced output.
    Re·Zeroing Amplifier
    If the total worst case leakage at the capacitor node
    Figure 20 illustrates a technique which may be is 1 nA, and if C, = 0.01 JlF, then the drift rate is
    useful in situations where a signal has an unknown 10-9/0.01' 10-6 = 0.1 Vis. Fora 10voltfull scale
    and variable DC offset, such ,as in telemetry. In system requiring an accuracy of 0.1% (10 mV),
    operation, the re·zero command line is enabled the amplifier would need a re·zeroing reference
    while a ground reference signal is applied to the every 100 m s.

    .,
    10K

    GUARD

    ANI~~~~o-_~ _______,

    TTL SAM~~E~~~~~ o-.-t--" 6 ANALOG


    OUTPUT

    _ _ ...!H~ ___ ..J C1


    L.
    T O.01"F
    POLYSTYRENE

    FIGURE 19A. Low Drift Sample/Hold

    ANALOG
    I OUTPUT
    INPUT
    I
    r---...I I I
    SAMPLE/HOLD ~9 .J
    '0 I
    ":" L _ _ !!!!l'~ _ _ ...I *Polystyrene dielectric

    FIGURE 19B. Precision Sample and Hold

    R2
    100M

    Rl
    10M
    INPUT o------4~---I\I\,..,.---_4I...,:..j

    r- OUTPUT

    I
    I I
    TTL~.J
    REZERQ COMMAND~

    L _ '~HO.!!! _ .J
    Cl-0.0l"f POLYSTYRENE v'

    FIGURE 20. Re·Zeroing Amplifier

    AN63·8
    Precision Current Sink Figure 22, the input currents remain low and
    constant. This is an adequate signal range for
    Figure 21 illustrates a variation on a common
    many applications, especially in view of the offset
    technique for generating a precisely regulated cir-
    voltage performance available in the top of the line
    rent. This circuit could be used in conjunction
    amplifiers. If wider signal range is required,
    with another FET input amplifier connected as a
    resistors R, and R2 should be included to limit
    the input current to a safe value. Internal zener
    junctions will limit the differential input voltage
    R2 to a safe value if the input current is limited
    12K '15
    200/lA.
    ~ lOUT = 1 nA
    The output clamp circu it shown in Figure 22 will
    01 drive 3 standard TTL loads or 30 National low
    2N4117A
    power TTL loads. Considerable power may be
    01 saved by increasing R3 if full fan·out is not reo
    LMllJ quired. If only 2 low power loads are to be driven
    the required low state output current is 360 /lA:
    R3 so R3 = 10V /360 /lA = 27k.
    1000 Meg

    Rl
    Rl
    v'
    1.8K
    10K
    .,v
    L-_ _ _ _ _ _...._ _ _ _ _ 15
    INPUT 01
    IN914
    TTL
    R' OUTPUT
    FIGURE 21. Precision Current Sink 10K
    REFERENCE

    ':"
    v-
    high input impedance follower to form an ohm-
    meter for accurately measuring very high resis-
    tances. R " R2 and 0 , form bias and reference FIGURE 22. Precision Voltage Comparator
    voltages near, but within, the common mode and
    output voltage limits of the amplifier. 0, is selected
    for very low gate leakage so that the current in its
    source will be nearly identical to the feedback True Instrumentation Amplifier
    current in its drain. In operation, the amplifier
    Figure 23A illustrates an instrumentation ampli·
    output will cause the gate of 0, to be cut off
    fier that features high differential and common
    however much is necessary to keep the voltage
    mode input resistance (10 '2 ohms), ± 10V common
    across R3 equal to 1.220 volts, the breakdown
    mode and differential mode input range, .01%
    voltage of 0 " The LMl13 diode is available to an
    gain accuracy at Av = 1000, and 110 dB CMRR
    initial voltage accuracy of 1% (12.2 mV) and is
    with 1 kQ imbalance in bridge source resistance.
    guaranteed to drift less than 15 m V over the
    Input current is less than 1 pA and offset drift is
    temperature range, thus by specifying the LH0052
    less than 5/lV/"C. R, provides a simple means of
    amplifier and a 1% resistor, a current sink can be
    adjusting gain over a wide range without degrading
    designed for a worst case initial accuracy near 2%
    CMRR. R2 is an initial trim used to maximize
    and a drift over the temperature range of less than
    CMRR without using super precision matched
    2%. The technique may be applied over a wide
    resistors. Input common voltage is sensed via R3 and
    range of currents by properly scal ing R3 and its
    R4 and the LM 110 provides low impedance VeM
    balancing resistor R4 ; a mirror image current
    drive to input cable shields to reduce leakage and
    source is possible using a P channel F ET for 0" coupling to inputs. If the input current of the
    LH0052 (1 pA max) is not low enough, additional
    Precision Comparator circuitry as shown in figure 238 may be added to
    provide "Zero" input bias current.
    FET amplifiers have a significant advantage over
    bipolar in precision voltage comparator applica-
    tions: the input current is nearly independent of Ultra Low Level Transconductance or Charge
    input Voltage. With a bipolar input stage, input Amplifier
    current is 1/~ of the emitter current, but the
    A picoamp amplifier for pH meters, medical
    emitter current can vary from zero when the stage
    electronics and radiation detectors is illustrated
    is cut off to twice the nominal value when fully
    in Figure 24. A high quality glass sealed feedback
    conducting. Furthermore, the inputs are often
    resistor such as Victoreen type RX-1 should be
    internally clamped to a diode drop for protection
    employed as well as guard shielding as discussed
    of the emitter base junctions.
    earl ier. Optionally C, may be added to convert
    As long as the input and reference signals are the circuit to a charge amplifier with RL used to
    no more than 4 volts apart in the circu it of provide OC stability.

    AN63-9
    SHIELD

    500K

    10K
    O~""
    INPUTS OUTPUT
    10K
    05'0

    CMRR
    AOJR2 lOOK

    SHIELD

    FIGURE 23A. True Instrumentation Amplifier

    R6& 7
    INPUTCURRENTIERD
    IOTURN
    lOOK

    10K

    -15V

    FIGURE 23B. Zero Input Bias Current

    circuit shown in Figure 25 performs this function


    simply and accurately. Initially, S1 and 52 are
    closed and 53 open with the logic input in the
    TTL "1" state. This allows capacitor C1 to charge
    to the same voltage as the e'N 1 input signal. When
    I" the logic input is taken to TT L "0", 51 and 52 open
    PROBE'::--=~:::j~!:::B-"" and 53 closes, causing the difference between the
    OUTPUT
    stored value of e'N1 and the present value of e'N2
    to appear at the non-inverting input of the LH0022.

    ·VI~toreen type RX·1


    crequtvalent
    -=
    ' - _....._V·=_15V The low leakage and high input impedance of the
    HDpllOnaltOlllake
    chargeamphfler LH0022 allows the use of a reasonable size hold
    capacitor wh ile at the same time provid ing gain
    FIGURE 24. Picoamp Amplifier
    for scaling, if needed. Note that the two analog
    inputs, e'N1 and e'N2 may be connected together
    Precision Subtractor for Automatic Test Gear to take the voltage difference on a single line at
    It is often necessary in testing linear circuits to take two different times. The disable input is used to
    the difference between two voltage readings occur- open all switches, for example, to ignore a transient.
    ing at different times. The specialized sample/hold If not needed, the disable input should be grounded.

    AN63-10
    Sensitive Low Cost "VTVM" and significantly lower cost. What's the difference
    Figure 26 illustrates a modern approach to con· between modules and these integrated circuit
    structing VTVM's and VOM's. The LH0042 re- amplifiers? In most cases the answer is nothing
    places all active circuitry. Optionally the circuit but two .01 pF power supply decoupling capacitors.
    may be run off of 8 flashlight batteries and only To make your own module merely build a small
    draws 20 mW of power. The clever designer would 1·114 x 1·1/4 printed circuit board that adapts the
    add some more switching to allow operation of the pin·out of the LH0052 to your module require·
    FET op amp in transconductance mode as shown ment. No need to pot the assembly in epoxy, the
    in Figure 24, thus combining both voltage and LH0052 family is completely heremetic and does
    current measuring capability into the same circuit. not absorb moisture. Some modules specify higher
    output current capability than the ±10 mA of the
    How to Build a FET Op Amp "Module" LH0052. To build a ±100 mA output "module"
    The LH0052 series when compared spec for spec F ET op amp, simply add a LH0002 buffer as shown
    with modules usually offers superior performance in Figure 27.

    r,;-----, ".
    ' ' !;Jj I Tt-F-eo-JlJV'v-....e-JV\"-"E~-.!f
    .INz~l .. I
    lOUT
    I I IL.. _____ _

    DISABLE

    lOGIC
    IN
    dM!I

    I
    L _______
    I
    I ,--------

    .!H!!.4~ __
    ":'" lD-13pF

    FIGURE 25. Precision Subtractor for Automatic Test Gear

    99'
    INPUT 0-"'--", +15V

    g.
    10/,

    OUTPUT
    IV
    9001(
    1%

    IOV

    JU'
    1%

    -15V
    10'
    1%

    FIGURE 26. Sensitive Low Cost "VTVM"

    r----------------,
    I , . . - - - -.....- ...- ....-;--V·
    INV
    I
    INPUT

    >=--i--t--OUTPUl
    NON INV t--""*-GROUND
    INPUT

    L....._ _~~....._ ...._-i--'V·


    _____________ J
    SMALL PC BOARD
    ZEROADJ

    FIGURE 27. 100 mA Output FET Op Amp "Module"

    AN63·11
    Typical Performance Characteristics

    I nput Offset Current Input Bias Current vs Offset Error (Without


    vs Temperature Temperature Vas Nulll
    100 Il10D 1000
    ~Vs "ISV
    VIN ~ 0 ~~~N .~5V

    .
    ~ 10

    lHOO42
    ! 100
    FLHOO42

    V
    ~ ~LHOO22 10
    /' VLHOO22 10 ,*illJIllLCLWJlIIL-1

    < lHOO52 1==


    LH~ ~
    /' -
    -
    01
    25 45 65 85 105 125 25 45 65 65 105 125 1M 10M 100M 1000M

    TEMPERATURE ( C~ TEMPERATURE I C) INPUT SOURCE RESISTANCE (!l)

    Offset Error (Without Total Input Noise Voltage"" Total Input Noise Voltage*
    Vas Nulll vs Source Resistance vs Frequency
    400
    I~ Vs ~ ·15V :i 500
    I Vs= "5V

    ~
    350

    300
    T,
    '" I i Rs= 10M T,
    '"
    400
    < 111111
    "0
    I > 300
    111111

    -~
    > zoo
    'o=10Hz
    ~ 150 ~ zoo
    IIIIIIIII 1111111

    -
    100
    10 ' 1 KH~l.lllIr" I - 100
    I
    50 R, -IOO!,

    ~
    <
    tI1Tlllml
    10k lOOk 1M 10M 10 100 1k 10k lOOk
    INPUT SOURCE RESISTANCE (il) SOURCEAESISTANCE(!2j FREQUENCY (Hlj
    *NOIseVoltage Includ€sCont'lbullOn from Source Re;Istance *NolseVoltage Includes ContJlbutlOn from Sou fee ReSIStor

    Connection Diagrams
    Dual-tn-Line Package Flat Package Metal Can Package

    Ta-5

    Conclusion
    The practical advantages of the LH0052 series of filters and instrumentation_ The low input offset
    FET input operational amplifiers has been demon- voltage and drift, high open loop gain, and excellent
    strated_ The extremely low input bias and offset common mode rejection combine to make the
    current make members of the family ideal choices devices equally well suited for general purpose
    for critical applications in hold amplifiers, active appl ications includ ing summers, su btractors, and
    osc ilIato rs.

    References
    1. R.J. Wldler "Ie Op Amps Equal Discretes" 4. R.C. Dobkin "Universal Balancing Techniques"
    National Semiconductor TP·9, December 1968 National Semiconductor LB·9, August 1969

    2. R.J. Widler "IC Op Amp Beats FETs on Input 5. W.S. Routh "An Applications Guide for Opera·
    Current" National Semiconductor AN-29, De· tional Amplifiers" National Sem Iconductor
    cember 1969 AN·20, February 1969
    3. D.L. Wollesen "How to Bias the Monolithic 6. National Semiconductor Linear Applications
    JFET Dual" National Semiconductor AN·34, Handbook
    Murch 1970

    AN63-12
    »
    z
    Joe E. Byerly and Ernest L. Long
    May 1972

    ,...
    s:w
    00
    -'
    LM381 LOW NOISE DUAL PREAMPLIFIER ,...
    o
    INTRODUCTION
    ~
    z
    The LM381 is a dual preamplifier expressly de· Attempts have been made to fill this function with o
    signed to meet the requirements of amplifying selected operational amplifiers. However, due to rJ)
    low level signals in low noise applications. Total the many special requirements of this application, m
    equivalent input noise is typically 0.5 flV rms these recharacterizations have not adequately met
    (Rs ~ 600r2, 10-10,000 Hz). the need. o
    c
    Each of the two amplifiers is completely inde·
    pendent, with an internal power supply decoupler·
    With the low output level of magnetic tape heads
    and phonograph cartridges, amplifier noise becomes
    »
    ,...
    regulator, providing 120 dB supply rejection and critical in achieving an acceptable signal·to·noise
    60 dB channel separation. Other outstanding fea· ratio. This is a major deficiency of the op amp in "tI
    :tI
    tures include high gain (112 dB), large output this application. Other inadequacies of the op
    m
    voltage swing (Vee -2V) p-p, and wide power amp are insufficient power supply rejection, limited
    »
    bandwidth (75 kHz, 20 VpiJ ), The LM381 operates
    from a single supply across the wide range of 9 to
    small'signal and power bandwidths, and excessive
    external components. s:
    40V. The amplifier is internally compensated and ,...
    "tI
    short·circuit protected.
    ."

    TABLE 1. TA = 25°C, Vee = 14V, unless otherwise stated.


    m
    :tI

    PARAMETER CONDITIONS MIN TYP MAX UNITS

    Voltage Gain Open Loop (Differential Input) 160.000 V/V


    Open Loop (Single Ended Input) 320.000 V/V
    Supply Current Vee 9 to 40V, RL = 00 10 rnA

    Input Resistance
    (POSitive Input) 100 kD
    (Negative Input) 200 kD

    Input Current
    (Positive Input) 0.2 pA
    (NegatIVe Input) 0.5 pA

    Output Resistance Open Loop 150 D

    Output Current Source B rnA


    Sink 2 rnA

    Output Voltage Swing Peak-ta-peak Vee -2 V


    Small Signal Bandwidth 15 MHz

    Power Bandwidth 20V p -p (Vee = 24Vl 75 kHz

    Maximum Input Voltage Linear Operation 300 mVrms

    Supply Rejection Ratio f"" 1 kHz 120 dB

    Channel Separation f == 1 kHz 60 dB

    Total Harmonic DIstortion 75 dB Gain, f = 1 kHz 0.1% %

    Total Equivalent Input NOise Rs = 600n, 10-10, 000 Hz (Single Ended Input) 0.55 J..lVrms

    Noise Figure 50 kD. 10-10. 000 HZ} 1.0 dB


    10 kn, 10-10,000 Hz (Single Ended Input) 1.3 dB
    5 kD. 10-10. 000 Hz 1.6 dB

    AN64-1
    CIRCUIT DESCRIPTION The· voltage gain of the single ended input stage
    is given by:
    To achieve low noise performance, special consider-
    ation must be taken in the design ~f the input
    stage_ First, the input should be capable of being
    RL 200k
    AV(AC) 160 (1)
    re 1.25k
    operated single ended; since both transistors con-
    tribu-te noise in a differential stage degrading input
    Where:
    noise by the factor .J2. Secondly, both the load
    and biasing elements must be resistive; since active
    components would each contribute as much noise
    KT
    re
    as me input device_ ~
    The voltage gain of the differential input stage is:

    + The schematic diagram of the LM381, Figure 2, is


    divided into separate groups by function; first and
    second voltage gain stages, third current gain stage,
    R,
    10K
    and the bias regulator.
    The second stage is a common-emitter amplifier
    (0 5 ) with a current source load (Os). The Darling-
    FIGURE 1. Input Stage ton emitter-follower 0 3 , C4 provides level shifting
    and current gain to the common-emitter stage (05 )
    and the output current sink (07 ), The voltage
    The basic input stage, Figure 1, can operate as a gain of the second stage is approximately 2000
    differential or single ended amplifier. For optimum making the total gain of the ampl ifier typically
    noise performance O2 is turned OFF and feedback 160,000 in the differential input configuration.
    is brought to the emitter of OI-
    The preamplifier is internally compensated with the
    I n applications where noise is less critical, 0 1 and pole-splitting capacitor, C 1• This compensates to
    O2 can be used in the differential configuration. unity gain at 15 MHz. The compensation is ade-
    This has the advantage of higher impedance at quate to preserve stability to a closed loop gain
    the feedback summing point, allowing the use of of 10. Compensation for unity gain closure may be
    larger resistors and smaller capacitors in the tone provided with the addition of an external capacitor
    control and equ ilization networks. in parallel with C 1 between Pins 5 and 6, 10 and 11.

    ,-.-----
    v"
    (OJ

    ----,I
    R1
    I
    01
    I
    I
    I
    I
    "I
    Z1 ' - - - - -.....-t-0 17••J

    I
    I
    _ _ _ _ _ .L ____ ~
    I

    FIGURE 2. Schematic Diagram

    AN'64-2
    Three basic compensation schemes are possible
    for this amplifier: first stage pole, second stage
    pole and pole·splitting. First stage compensation
    will cause an increase in high frequency noise
    because the first stage gain is reduced, allowing
    the second stage to contribute noise. Second stage
    compensation causes poor slew rate (power band·
    width) because the capacitor must swing the full
    output voltage. Pole·splitting overcomes both these
    deficiencies and has the advantage that a small R4
    monolithic compensation capacitor can be used. 22
    +0--4-....-1
    The output stage is a Darlington emitter·follower
    (Qa, Og) with an active current sink (Q7)' Tran·
    sistor Ql0 provides short·circuit protection by "'
    lim iting the output to 12 mAo

    The biasing reference is a zener diode (Z2) driven


    from a constant current source (Qll)' Supply de· FIGURE 4. Differential Input Biasing
    coupling is the ratio of the current source imped·
    ance to the zener impedance. To achieve the high
    current source impedance necessary for 120 dB For bias stability, the current through R5 is made
    supply rejection, a cascode configuration is used ten times the input current of Q2 (""0.5 f.lA). Then,
    (Qll and Q12)' The reference voltage is used to for the differential input, resistors R5 and R4 are:
    power the first stages of the ampl ifier through
    emitter·followers Q14 and Q15' Resistor Rl and 1.2
    zener Zl provide the starting mechanism for the 240 kQ MAXIMUM
    5 x 10-6
    regulator. After starting, zero volts appears across
    (3)
    0 1 taking it out of conduction.

    Vee \
    ( 2.4 - 1) R5 · (4)

    Biasing

    Figure 3 shows an AC equivalent circuit of the


    LM381. The non· inverting input, Ql, is referenced
    to a voltage source two V BE above ground. The
    output quiescent point is established by negative
    DC feedback through the external divider R4/R5
    (Figure 4).

    R4
    Z2

    +0--4-....-1

    "'

    22
    +0--4-....-1
    FIGURE 5. Single Ended Input Biasing

    When using the single ended input, Q 2 is turned


    OFF and DC feedback is brought to the emitter
    of Q1 (Figure 5). The impedance of the feedback
    summing point is now two orders of magnitude
    lower than the base of Q2 (""10 kQ). Therefore,
    FIGURE 3. AC Equivalent Circuit to preserve bias stability, the impedance of the

    AN64·3
    feedback network must be decreased. In keeping Capacitor C 2 sets the low frequency 3 dB corner
    with reasonable resistance values, the impedance where X C2 = Rs ,
    of the feedback voltage source can be 1/5 the
    summing point impedance.
    (9)
    The feedback current is <100 p.A worst case.
    Therefore, for single ended input, resistors R5
    The small'signal bandwidth of the LM381 is 15
    and R4 are:
    MHz making the preamp suitable for wide-band
    instrumentation applications. However, in narrow-
    R -.~~ 0.6
    1200n MAXIMUM band applications it is desirable to limit the ampli-
    5 - 5 I FB 5 x 10-4 fier bandwidth and thus eliminate high frequency
    (5) noise. Capacitor C3 accomplishes this by shunting
    the internal pole-splitting capacitor (C,), limiting
    the bandwidth of the amplifier. Thus, the high
    (6)
    frequency 3 dB corner is set by C3 according to
    equation 10.

    C3 =----A- -4 X 10-'2 (10)

    11,8) 21Tf3 re 1020


    f3 high frequency 3 dB corner
    •• re first stage small-si'gnal emitter resistance
    "'2.6 kn
    .5 A = mid-band gain in dB

    J" -::-
    For music applications, response shaping is re-
    quired to provide the NAB standard tape playback
    equalization. Figure 8 shows the NAB equalization
    FIGURE 6. AC Open Loop characteristic .

    The circuits of Figures 4 and 5 have an AC and


    .. f,=SOr
    35 t"
    DC gain equal to the ratio R4/R5' To open the
    AC gain, capacitor C 2 is used to shunt R5 (Fig-
    3D - J
    ure 6). The AC gain now approaches open loop.
    ! 25
    7-112& 151PS
    !:! 20
    The low frequency 3 dB corner, fo, is given by:
    \.~
    ~ 15

    Ao '0 1-7/8 &H/4,J


    21TC 2 R4 where: Ao = open loop gain (7) II
    Od.'11"
    ,,':,;:oj ~
    ,
    REF ERENCE GAIN ~:Li0
    10 Hz 100 Hz 1 kHz 10 kHz 100 kHz

    Tape Playback Preamplifier


    FIGURE 8. NAB Equilization Characteristic
    Figure 7 shows the LM381 in a flat response tape
    playback configuration. The mid-band gain is set The NAB response is achieved with the circuit of
    by resistor ratio Figure 9. Resistors R4 and R5 set the DC bias and
    are chosen according to equations 3 and 4 for
    (8)

    (1,BI

    II
    .6

    II .6
    .5

    .5
    FIGURE 9. NAB Tape Preamp.

    differential input operation and equations 5 and 6


    FIGURE 7. Flat Response Tape Amplifier for the single ended input. The reference gain of

    AN64-4
    the preamp, above corner frequency f2 (Figure 8), Equation (11)
    is set by the ratio:
    o dB Reference Gain 355
    o dB reference gain (11)
    R7
    Rs = 355-1
    The corner frequency f2 (Figure 8) is determined
    where X C4 = R7 and is given by: Rs ~ 180n.
    7. For low frequency corner fo = 40 Hz,
    (12)
    equation (14)
    1 _ .5
    Corner frequency f, is determined where XC4 = R4 :
    C2 = 21T foRs = 6.28x40x180 -2.21xl0
    1
    f, = 21TC4 R4 ' (13)
    C2 "" 201lF.

    The low frequency 3 dB roll·off point, fo, is set 24V

    where XC2 = Rs:

    (14) >="-....-0 5Vrms

    Example: Design a NAB equalized preamp for a


    tape player requ iring 0.5V rms output from a head
    sensitivity of 800 IlV at 1 kHz, 3·3/4 IPS. The
    II
    power supply ·voltage is 24V and the differential 240K

    input configuration is used. ~ZOjJF

    1. From equation (3) let R5 = 240 kn.


    FIGURE 10. Typical Tape Playback Amplifier

    e
    2. Equation (4) R4 = (VCC
    - - -1 ) R5
    2.4
    This circuit is shown in Figure 10 and requires
    R4 4 -1
    2.4 2.4 x 105 approximately 5 seconds to turn·ON for the gain
    )
    and supply voltage chosen in the example. Turn·
    R4 2.16 X 10 5 ~2.2 Mn ON time can closely be approximated by:

    3. For a corner frequency, f, equal to 50 Hz,


    equation (13) is used. (15)
    1
    (13) C4 = 21Tf,R 4 6.28x50x2.2xl0s As seen by equation (15), increasing the supply
    voltage decreases turn·ON time. Decreasing the
    = 1.44xlO· g amplifier gain also decreases turn·ON time by
    reducing the R~C2 product.
    C4 ~ 1500 pF.
    Where the turn·ON time of the circuit of Figure 9
    4. From Figure 8, the corner frequency f2 = 1770 is too long, the time may be shortened by using
    Hz at 3-3/4 IPS. Resistor R7 is found from the circuit of Figure 11. The addition of resistor
    equation (12). RD forms a voltage divider with Rs'. This divider is
    chosen so that zero DC voltage appears across

    .-----4t------~ v"
    R7= - - - - - - -
    6.28xl770x 1.5x 10.g

    R7 ~ 62 kn.

    5. The required voltage gain at 1 kHz is:

    0.5V rms _ 2_
    II
    Av = 800llV rms - 6.25xl0 V/V - 56 dB. .5

    6. From Figure 8 we see the reference frequency


    gain, above f2' is 5 dB down from the 1 kHz
    value or 51 dB (355 V/V). FIGURE 11. Fast Turn·On NAB Tape Preamp.

    AN64·5
    C2. The parallel resistance of Rs' and RD is made The turn-ON. time becomes:
    equal to the value of Rs found by equation (11). In
    most cases the shunting effect of R D is negligible tON'" -2-/R 4 C2 In ( 1- ~).
    Vee
    (19)
    and Rs' '" Rs.
    For differential input, R D is given by: Example: Design an NAB equalized preamp with
    the fast turn-ON circuit of Figure 12 for the same
    (Vee -1.2) Rs' requirements as the previous example.
    RD = 1.2 (16)
    1. From equation (3A) let R5 = 24 kn.

    (~~~
    For single ended input:
    2. Equation (4) R4 = - 1) R5
    (Vee - 0.6) Rs'
    RD = 0.6 (17)
    = (:.! - 1) 24x 103
    I n cases where power supply ripple is excessive, the
    R4 = 2.16x 105 ", 220kn.
    circuit of Figure 11 cannot be used since the ripple
    is coupled into the input of the preamplifier 3. From the previous example the reference fre-
    through the divider. quency gain, above f2' was found to be 51 dB or
    The circuit of Figure 12 provides fast turn-ON 355VIV.
    while preserving the 120 dB power supply rejection. R7 + Rs
    Equation (11) ~ = 355.
    The DC operating point is still established by R4/
    R 5. However, equations (3) and (5) are modified by
    4. The corner frequency f2 is 1770 Hz for 3-3/4
    a factor of 10 to preserve DC bias stability.
    IPS.
    1
    Equation (12) C4 = 271f2 R7
    rI~~ LM381 >llo":LII_ _ +-o 5. The corner frequency f, is 50 Hz and is given
    by equation (18).
    1Z,1lDR.,._I2_V--'IIi
    Ai/I' ,....---i(~ (18)
    1

    II . .. C4 = -2-71-f'-R-s-'[""(-:-R-4":"';-s-Rs-):-2---1-;"]

    AS
    6. Solving equations (11), (12), and (18) simultane-
    ously gives:

    R4 (1, + -/f,2 + f, f2 (Ref. Gain)


    Rs = f2 (Ref. Gain) (20)
    FIGURE 12. Two-Pole Fast Turn-On NAB Tape Preamp.

    2.2x 105 (50 + -/2500+50x 1770x355)


    For differential input, equation (3) is modified as: Rs = 1770x355

    2 V Be 1.2 = 1.98 x 103


    (3A) R5 = 1001 02 = -50-x-l-0-.a
    Rs '" 2 kn.
    = 24 kn MAXIMUM. 7. From equation (11) R7 = 354 Rs= 708xl03
    R7 '" 680 kn.
    For single ended input:
    1
    V Be
    0.6 8. Equation (12) C4 = 271f2 R7
    Equation (5A) R5 = 50 IFB = - - -
    5Ox10'"
    = 120n MAXIMUM. 6. 28x 1770x680x 103
    Equations (11), (12) and (14) describe the high
    C4 = 1.32xl0-'0", 120 pF.
    frequency gain and corner frequencies f2 and fo as
    before. Frequency f, now occurs where X C4 equals 1
    the composite impedance of the R4, Rs, C2 net- 9. Equation (14) C2 = 271foRs
    work as given by equation (18).

    1
    (18) 6.28x40x2xl03
    C4 = - - - " ' [ - " - - - - - - , ] ' "
    271f, Rs (R4;S Rs ) 2 - 1

    AN64-6
    This circuit is shown in Figure 13 and requires only Curve B shows the required preamplifier response
    0.1 seconds to turn·ON. to make the composite, A + B, provide the NAB
    recording characteristic. This response is obtained
    with the circuit of Figure 16. Resistors R4 and R5

    I.,...,
    TO R(~ORDIN(;
    r-'H(AO

    II

    FIGURE 16. Tape Recording Preamp.


    FIGURE 13

    set the DC bias as before using equations (31 and


    TAPE RECORD PREAMPLIFIER (41 for the differential input and equations (51 and
    (61 for the single ended input. Resistor R6 and
    capacitor C2 set the mid·band gain as before (equa·
    When recording, the frequency response is the tions (81 and (911. Capacitor C 5 sets the high
    complement of the NAB playback equalization,
    frequency 3 dB point, f3' (Figure 151 as:
    making the composite record and playback reo
    sponse flat. Figure 14 shows the record character·
    istic superimposed on the NAB playback response. (21)

    The preamp gain increases at 6 dBfoctave above


    40 f3 until Rg = X e5 .
    J5 IIIJ~~-
    REcoRD'---.
    3D
    Rg (221
    ~ 25
    20
    \
    z f4 =desired high frequency cutoff
    0

    15 NAB
    ~
    ~hAYBACK
    10 Resistor Rg is chosen to provide the proper record·
    I, IIllI{ II" ing head current.
    .il IIIII tAl _ _ _v_o_ __
    10Hz 100 H2 1 kHz 10kHz
    Rg = (231
    iRECORD HEAD

    FIGURE 14. NAB Record & Playback Equilization L, and C6 form a parallel resonant bias trap to
    present a high impedance to the recording bias
    frequency and prevent intermodulation distortion.
    Curve A of Figure 15 shows the response char· Example: A recorder having a 24V power supply
    acteristics of a typical laminated core, quarter· uses recording heads requiring 30 J1A AC drive
    track head. current. A microphone of 10 mV peak output is
    used. Single ended input is desired for optimum
    noise performance.
    40
    J5 11111 III 1. From equation (51 let R5 = 1200Q.

    H:-~) lUolRll
    (~~~
    30

    25 -r AD RESPoT~ 2. Equation (61 R4 -1) R5


    ~ 20
    15

    10 W-
    I II
    tJ ; ~ lR'AMP V
    ( 1~~ - 1) 1 200.

    10 Hz
    It 100 Hz
    ~;~Ij,
    1 kHz
    ~J>
    10 kHz 100kHz
    R4 = 2.28xl04 ", 22 kQ.

    3. The maximum output of the LM381 is (Vee


    -2Vl p_p ' For a 24V power supply, the maxi·
    FIGURE 15. Recording Head & Preamp. Response for mum output is 22Vp.p or 7.8V rms. Therefore,
    NAB Equilization an output swing of 6V rms is reasonable.

    AN64·7
    _ _ _v....2..-_ __
    From equation (23) Rg
    iRECORO HEAD

    6V
    Rg = 30J1A = 200 kn. 0,
    l,.., TORECDMWG
    rv HEAD

    4. Let the high frequency cutoff f~ = 16 kHz (Fig-


    ure 15). The recording head frequency response
    begins falling off at approximately 4 kHz.
    Therefore, the preamp gain must increase at
    this frequency to obtain the proper composite
    characteristic. The slope is 6 dB/octave for the FIGURE 17. Typical Tape Recording Amplifier
    two octaves between f3 (4 kHz) and the cutoff
    frequency f4 (16 kHz). Therefore, the mid-band
    gain lies 12 dB below the peak gain.
    PHONO PREAMPLIFIER
    We are allowing 6V rms output voltage swing.
    . 6V
    Therefore, the peak gaIn = 10m\! = 600 or Crystal and ceramic phono cartridges provide out-
    55.6 dB. put levels of 100 mV to 2V and therefore do not
    require preamplification_ Magnetic cartridges, how-
    The mid-band gain = 43.6 dB or 150.
    ever, provide much lower outputs as shown in
    Table 2.
    5. From equation (B) the mid-band gain =
    TABLE 2.
    R4:S R6 = 150.
    MANUFACTURER MODEL OUTPUT AT 5 cmlsec

    R _ R4 _ 22 x 10 3 _ Empire SCientific 999 5 mV


    6 - 149 - 149 - 147.7 BBB B mV
    Shure V-15 3.5 mV
    M91 5 mV
    Pickering V-15 AT3 5 mV

    6. Equation (9) C2 Output voltage is specified for a given modulation


    velocity. The magnetic pickup is a velocity device,
    therefore, output is proportional to velocity. For
    6. 2Bx 50x 1 50 example, a cartridge producing 5 m V at 5 cm/sec
    will produce 1 mV at 1 cm/sec and is specified as
    2.12x10· 5 having a sensitivity of 1 mV /cm/sec.

    I n order to transform cartridge sensitivity into


    useful preamp design information, we need to
    know typical and maximum modulation velocity
    7. Equation (21) C5 limits of stereo records.

    The RIAA recording characteristic establishes a


    maximum recording velocity of 25 centimeters
    6. 2Bx4x 103x 150
    per second in the range of BOO to 2500 Hz.
    2.66x10· 7 Typically, good qual ity records are recorded at a
    velocity of 3 to 5 cm/sec.
    C5 "" 0.27J1F.
    Figure 1B shows the RIAA playback equalization.
    This response is obtained with the circuit of
    8. Equation (22) Rs Figure 19.

    Resistors R4 and R5 set the DC bias (equations (3)


    and (4), or (5) and (6)). The 0 dB reference gain
    6. 28x 16x 1 03x 2. 7x 10. 7
    is set by the ratio:
    36.B
    (24)
    Rs"" 33n.

    AN64-B
    1. From equation (3) let R5 ~ 100 k.l1.
    30

    ~ (~~~ -
    f,
    20 2. Equation (4) R4 1) R5
    10

    ~(~-1)105
    f,
    0
    - f, 2.4
    10

    R4 ~ 11.Sx10 5 ~ 1.2 M.I1.


    20

    30 LL~~-UW-~~~UW

    10Hl 100Hz 1 kHz 10kHz 100kHz


    3. Equation (2S) C7 ~

    FIGURE 18. RIAA Playback Equilization

    6.28xSOx1.2x 10 s
    ~ 2.6Sx 10·g
    The corner frequency, fl' (Figure 18) is established
    where XC7 ~ R4 or: C 7 ~ .003f.1F.

    (25) 1
    4. Equation (26) C7 ~
    211f2 RlO ;

    - - - -1- - - -
    MAGNETIUI~~
    RlO ~
    6. 28x 500x 3x 10·g
    141 + LM'" >(:::;'.':..)--<)--0
    CARTRIDGE /2, 13 ~ ~
    1.03x105
    OR 3,12) _

    -= -= R4
    RIO ~ 100 k.l1.

    5. The maximum cartridge output at 25cm/sec is:


    R5
    (.5 mV/cm/scc) x (25 em/sec) ~ 12.5 mV. The
    required mid-band gain is therefore:

    SV rms
    1-=2.""5'-m-"VC:-r-m-s ~ 400.
    "7

    FIGURE 19. RIAA Phono Preamp.

    6. Equation (24)
    Likewise, frequency, f2 occurs where XC7 ~ RIO or:
    RlO + R6
    o dB Ref. Gain ~ -R-;;- ~ 400;
    (26)
    100k
    R6 ~ 399 ~ 251 ~ 240.11

    The third corner frequency, f3, is determined Rz ~ 10 Rs ~ 2400.11.


    where Xes ~ RlO:

    (27) 7. Equation (9)

    1 1
    1.7x10·5
    C2 ~ 211foR6
    ~ ~

    6.28x40x 240
    Resistor R z is used to insert a zero in the feedback
    loop since the LM381 is not compensated for C2 ~ 20f.1F.
    unity gain. Either R z is required to provide a zero
    at or above a gain of 20 dB (R z ~ 10 Rs), or ex-
    ternal compensation is provided for unity gain B. Equation (27)
    stability according to equation (10).
    1 1
    Cs ~ ~

    211f3RIO 6.28x2200x6.8x 104


    Example: Design a phonograph preamp operating
    from a 30 volt supply, with a cartridge of O.S mV/ ~
    7.23 X 10-10
    em/sec sensitivity. to drive a power amplifier of
    SV rms input overload limit. Cs ~ 0.001 f.1F.

    AN64-9
    The completed design is shown in Figure 20 where "cut". For example, if 20 dB of "boost" and "cut"
    a 47 k.l1 input resistor has been included to pro- is desired, the ratio R,,1R'2 and R'2/R,3 is 20 dB
    vide the R IAA standard cartridge load. or 10:1. The low frequency control point, f"
    (Figure 22) is set where XCg= R'2 and Xc,o= R".

    3DV
    (28)
    \~1

    rr
    +
    ,t"F (7,BI
    4l.
    ";:" ";:" 12.131_ (29)

    laOH
    lOOK
    20
    I"- F~lll~os~
    IIIII
    10
    i'\ "iiIIOST ~
    ~lL
    FIGURE 20. Typical Magnetic Phono Preamp.
    ~I[
    10
    ~
    Vw r-~ 1/2 CUT
    II I I
    20
    IFI~tl fur
    TONE CONTROLS
    10 Hz 100 Hz 1kHz 10 kHz 100 kHz

    Most tape and phonograph applications require


    bass and treble tone controls. Due to the insertion FIGURE 22. Bass & Treble Tone Control Response for
    loss of the tone control, (equal to the available 20 dB Boost & Attenuation
    boost), it has been normal to use two preamplifiers
    with the control placed between them. However,
    due to the excellent gain and large output capa- The treble control is the analogue of the bass
    bility of the LM381, only a single preamp is re- control with the resistor and capacitor dividers
    quired. reversed. The ratio of reactance of C"/C'2 is set
    equal to the amount of "boost" and "cut". The
    high frequency control point, f2' is established
    where XC'2 = R'3.
    INPUT INPUT

    '12
    1 C12
    C'2 (30)
    co 2rrf2 R'3·
    '14

    OUTPUT OUTPUT
    '13 '13
    R'4 (31)
    2rrf 2 C'2 .
    '"
    '" (32)
    ";:" 1 C11 R'5 2rrf2C"

    Figure 23 shows one channel of a practical pre-


    FIGURE 21. Bass & Treble Controls
    amplifier for a stereo phonograph. The preamp
    is complete with R IAA equalization, bass and
    treble tone control, balance control and volume
    Figure 21 shows the bass and treble tone controls. control.
    The potentiometers, R'3, are audio taper; i.e., at
    the center of shaft rotation the wiper is at the
    90%-10% point of the total resistance. Both con- AUDio MIXER
    trols are simple AC dividers, with the flat response
    position where the signal is attenuated from the In many audio applications it is desirable to pro-
    "fu II boost". vide a mixer to combined or select several inputs.
    Such applications include public address systems
    where more than one microphone is used; tape
    In the bass control the ratio of resistors R"/R,2 recorders, high fidelity phonographs, guitar ampli-
    and R'2/R,3 determine the degree of "boost" and fiers, etc.

    AN64-10
    [F
    30V

    + .002
    1" (7,8)
    41K

    -= -= (2,131 TREBLE
    82K

    1.2M
    10K
    24DOn ;;>.~--~-JW'lr-..... -------<r---,>,< SDK
    8.ZK
    24011
    lOOK VOLUME
    50K
    ........a TO POWER
    BALANCE
    AMP '1'.02
    10llK

    TO CH 2
    1
    FIGURE 23. Single Channel of Complete Phono Preamp.

    Figure 24 shows the LM381 in a mixer configura·


    tion. Inputs at A, B, C, -N can be selected and (7,8)
    combined (summed) with potentiometers R A , R B ,
    R c , -RN' Resistors R4 and R5 establish the DC
    quiescent point in accordance with equations (3A)
    R4
    and (4). (Only the differential input configuration
    is used in the mixer application since the high
    source impedance of the input potentiometers
    would negate any advantage of the single ended I
    I' RN I R5
    input.) Input bias current is supplied through No---If--~-~
    resistor R F, Therefore, an upper limit of RF
    should be established to avoid output offset volt·
    "
    age problems. A safe upper limit is to let:
    FIGURE 25.

    (33)
    The voltage gain of the mixer is now:

    RF
    1Av l = R R (35)
    A. B. C + SA,B,C

    Ao---1l----W~~ .Since resistor R F is no longer required to supply


    the input bias current, it does not have the upper
    Bo---1~~ limit as in the previous circuit. Therefore, the open
    ~ . .J R,
    R, loop gain of the LM381 can be realized, Capacitor
    c ~ ~-r--+--'VV'v---t C" shunts the AC feedback of the R4 - R5 net·
    I
    R5 work and is found by:
    No--~?-~_J
    "

    FIGURE 24. Audio Mixer


    C,

    The voltage gain of the mixer is: amplifier open loop gain in dB

    R4RF + R4R5 + R5 R F fo = low frequency 3 dB corner


    1Av A,B,C I (34)
    R 5 (R A • B,C + RSA,B,C)

    Example: Design a microphone mixer for use with


    Where the values of R F and the source impedance, 600Q dynamic microphones with an output level
    Rs , are such that the gain of the circuit of Figure of 10 mY. The mixer should operate from a 24V
    24 is inadequate, the configuration of Figure 25 supply and deliver 5 volts output. A dynamic range
    may be used. of 80 dB is desired.

    AN64·11
    1. From equation (3A) R5 = 24 k!1 At maximum attenuation:

    2. Equation (4)

    R4 = (VCC_
    2.4
    1) R5
    RA • B.C = 5.99 X 106 "" 5M!1

    R4 = (3i-
    2.4
    1) 24 x 103

    R4 = 2.16x 105 "" 220 k!1

    3. For 5V output:

    5V
    Gain = 10 mV = 500

    4. For BO dB dynamic range:

    500
    Attenuation = = 5 X 10.2
    BOdB

    5. Equation (34)
    R4 RF + R4R5 + R5 RF
    1Avl =
    R5 (R A ,B,C + Rs)

    FIGURE 26.

    CONCLUSION:
    At maximum volume: R A , B,C, = 0, Gain = 500

    The applications presented in this note are by no


    RF = 500 x 2.4 X 104 (0 -t; 600) - (2.2 x 10 5 )(2.4 X 104 )
    means exhaustive. The LM3Bl is a widely versatile
    2.2 X 10 5 + 2.4 X 104 low noise, high gain, wide band gain block and, as
    such has many applications outside the audio
    RF = 7.B7k "" B.2k spectrum.

    AN64·12
    l>
    Z
    I
    Joe E. Byerly & Marvin Vander Kooi
    December 1972
    en
    CD

    r-
    s:w
    00
    o
    LM380 POWER AUDIO AMPLIFIER "tI
    o
    INTRODUCTION
    :E
    m
    The LM3BO is a power audio amplifier intended driving a PNP differential pair with a slave current- :0
    for consumer applications. It features an internally source load. The PNP input is chosen to reference l>
    fixed gain of 50 (34 dB) and an output which
    automatically centers itself at one-half of the
    the input to ground, thus enabling the input trans·
    ducer to be directly coupled.
    c
    C
    supply voltage. A unique input stage allows inputs
    to be ground referenced or AC coupled as required. The output is biased to half the supply voltage by o
    The output stage of the LM3BO is protected with resistor ratio R,/R 2. Negative DC feedback, l>
    both short circuit current limiting and thermal
    shutdown circuitry. All of these internally pro-
    through resistor R2, balances the differential stage
    with the output at half supply, since R, = 2 R2
    s:"tI
    vided features result in a minimum external parts (Figure 1).
    count integrated circuit for audio applications.
    r-
    ."
    The second stage is a common emitter voltage gain
    amplifier with a current-source load. Internal com-
    m
    This paper describes the circuit operation of the :0
    LM3BO, its power handling capability, methods of pensation is provided by the pole-splitting capacitor
    volume and tone control, distortion, and various C'. Pole-splitting compensation is used to preserve
    application circuits such as a bridge amplifier, a wide power bandwidth (100 kHz at 2W, Bn). The
    power supply splitter, and a high input impedance output is a quasi-complementary pair emitter-
    audio amplifier. follower.

    The amplifier gain is internally fixed to 34 dB or


    CIRCUIT DESCRIPTION 50. This is accomplished by the internal feedback
    network R2-R 3 . The gain is twice that of the
    Figure 1 shows a simplified circuit schematic of the ratio R2/R3 due to the slave current-source which
    LM3BO. The input stage is a PNP em itter-follower provides the full differential gain of the input stage.

    TABLE 1. Electrical Characteristics INote 1)

    PARAMETER CONDITIONS MIN TYP MAX UNITS

    Power Output (rms) an load, 3% T.H.D. (Notes 3, 4) 2.5 Wrms


    Gain 40 50 60 VN
    Output Voltage Swing an load 14 Vpop

    Input Resistance 150k n


    Total Harmonic Distortion Po =2.5W. INotes 4 & 51 0.2 %

    Power Supply Rejection Cbvpass = 5pF, f = 120 Hz 38 dB


    INote 21
    Supply Voltage Range a 22 V
    Bandwidth Po = 2W, RL =an lOOk Hz

    Quiescent Output Voltage a 9 10 V


    Quiescent Supply Current 7 25 rnA

    Short Circuit Current 1.3 A

    Note 1: Vs = 18V; T A = 25°C unless otherWise specified.


    Note 2: RejectIOn ratio referred to output
    Note 3: With device PinS 3, 4, 5, 10, 11. 12 soldered Into a 1/16" epoxy glass board with 2 ounce copper fOil with a minimum
    surface of SI)( square mches.
    Note 4: If OSCillation eXists under some load conditions, add a 2.7n resistor and 01 j.lF series network from Pin 8 to ground.
    Note5: Cbvpass "'0.47/olF on Pin 1.
    Note 6: Pins 3, 4, 5. 10, 11,12 at 50"C derates 25"C/W abo . . e 50°C case.

    AN69-1
    ,..-__________. . ,.___....,.--0 Vs (141

    R6

    25. 1 r-_ _ ~"':.'".----+_---+-01-<l~~TPUT


    8VPAt~o-----.. HI ;~

    25.

    -IN

    '"
    (3,4,5,10,11,12)
    mGND GND

    FIGURE 1.

    3.5
    3%OIST.
    GENERAL OPERATING CHARACTERISTICS LEVEL
    3.0

    S
    ;;. 2.5
    "..
    " /
    The output current of the LM380 is rated at 1.3A
    peak. The 14 pin dual-in-line package is rated at
    z
    c

    ~
    2.0

    1.5
    v,

    ::>---, ;.-" /
    // 1B-
    10%
    ....
    ~-
    50°CIW when soldered into a printed circuit board ~ OiST.
    ~-
    lOV"- EVEL
    with 6 square inches of 2 ounce copper foil (F ig- 1.0
    'V
    >i
    ure 2). Since the device junction temperature is ~ 0.5 ;1-
    limited to 150°C via the thermal shutdown cir-
    cuitry, the package will support 2 watts dissipa- o 051.01.52.0 2.53.03.54.0
    tion at 50°C ambient or 2.5 watts at 25°C ambient. OUTPUT POWER (WAnS)

    Fig1Jre 2 shows the maximum package dissipation FIGURE 3A. Device Dissipation vs Output Power -
    versus ambient temperature for various amounts of 4n Load
    heat sinking.
    3.5

    6.0 3.0
    .....
    S 5.0 i
    z
    2.5
    V,/
    ~
    ~ ..... r- ~
    ~
    z 4.0
    c

    ~
    2.0
    :: /' ')1- -
    c 1.5 1B
    --
    i
    rift-
    ia
    3.0 Q
    1.0
    16V
    14V
    1-10.-
    ~ 3%riIST.
    ~ u 12V,..1"""
    ~
    2.0 10%
    u 0.' 0I8T.

    ~ 1.0
    LEVEL

    o 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
    OUTPUT POWER (WAnS)
    o 10 20 30 40 50 60 70 80 90 100
    Til, - AMBIENT TEMPERATURE (DC)

    FIGURE 38. Device Dissipation vs Output Power-


    FIGURE 2. Device Dissipation vs Maximum Ambiant an Load
    Temperature

    3.0

    Figures 3A, B, and C show device dissipation versus II


    ..~
    2.'
    3% DlST.
    output power for various supply voltages and LEVEL
    ;;. 2.0
    loads.
    ..... - ~n
    z V,
    c

    ~ 1., 22
    - ..... ::---
    The maximum device dissipation is obtained from
    Figure 2 for the heat sink and ambient temperature
    ia
    Q 1.0
    20 ;..-
    8 ..... ~ ;;t:,I!,
    conditions under which the device will be operat-
    6V
    ~.- LEVEL

    ~ 0.'
    ing. With this maximum allowed dissipation, Fig-
    ures 3A, Band C show the maximum power supply II
    o 0.51.0 1.52.02.53.03.54.04.55.0
    allowed (to stay within dissipation limits) and the
    OUTPUT POWER (WATTS)
    output power delivered into 4,8 or 16 ohm loads.
    The three percent total-harmonic-distortion line is FIGURE 3e. Device Dissipation vs Output Power-
    approximately the on·set of clipping. 16n Load

    AN69-2
    BIASING

    The simplified schematic of Figure 1 shows that


    2.0 r--.-rrr-r---rTTr--r--,
    1.8 t--H-H-t-t-t-tt~BV'" 811
    the LM380 is internally biased with the 150 kQ
    I.' t--t-H-t--t--t--H-t--t----j resistance to ground. This enables input transducers
    1.4t--t-H-t--t--t--H-t--t----j which are referenced to ground to be direct·coupled
    1.2 t--t-H-t--t--t--H-t--t----j to either the inverting or non· inverting inputs of
    1.0 t--t-H-t--t--t--H-t--t----j the amplifier. The unused input may be either:
    d.• t--t-H-t--t--t--H-t--t----j 1) left floating, 2) returned to ground through a
    resistor or capacitor or 3) shorted to ground. In
    ::: :,1jj:t-IL
    most applications where the non·inverting input
    0.2 ~:tttt:!::rfi~~""~
    L 1W' is used, the inverting input is left floating. When
    too ZOO 500 1k 2k 5. 10k 10k the inverting input is used and the non·inverting
    FREQUENCY (Hz) input is left floating, the amplifier may be found
    to be sensitive to board layout since stray coupling
    FIGURE 4. Total Harmonic Distortion vs frequency to the floating input is positive feedback. This can
    be avoided by employing one of three alternatives:
    1) AC grounding the unused input with a small
    capacitor. This is preferred when using high source
    Figure 4 shows total harmonic distortion versus impedance transducers. 2) Returning the unused
    frequency for various output levels, while Figure 5 input to ground through a resistor. This is pre·
    shows the power bandwidth of the LM380. ferred when using moderate to low DC source
    impedance transducers and when output offset
    from half supply voltage is critical. The resistor
    40 is made equal to the resistance of the input
    1 Vee'" 1BV transducer, thus maintaining balance in the input
    ;;; 3D
    " 0'
    differential amplifier and minimizing output offset.
    3) Shorting the unused input to ground. This is
    '"z~ 25 J, ~ J 60'
    used with low DC source impedance transducers
    III
    2D PHASE 120~
    or when output offset voltage is non·critical.
    c
    IIJl
    ~ 18D"~
    15
    RL :8n I
    10 240 0
    POUT =ZW
    3000
    0 IIIIII 360 0 OSCILLATION
    10 100 1k 10k lOOk 1M 10M
    FREQUENCY (Hz)
    The normal power supply decoupling precautions
    FIGURE 5. Output Voltage Gain vs Frequency
    should be taken when installing the LM380. If
    Vs is more than 2" to 3" from the power supply
    filter capacitor it should be decoupled with a
    O.lJ.lF disc ceramic capacitor at the Vs terminal
    Power supply decoupling is achieved through the of the IC.
    AC divider formed by R, (Figure 1) and an exter·
    The Rc and Cc shown as dotted line components
    nal bypass capacitor. Resistor R, is split into two
    ~n Figure 7 and throughout this paper suppresses a

    SOdB r-rnillJ"TITT.-rjrrnmr--,rmnn

    V'N~_r--O--::-;:~~A
    Wl1 j
    ~_ 4DdB t-H-5j;;j"f!'1tt.;.,!!J..i9:TIttttI7'!-tttttttl
    2~F

    §3UdB r1--7''Ii;I'fflft-rj-tTttlI1I-t-tttttttl
    ; 20dB rt-"''--t-tttttfft7't!-1-tT°''tJj'IttI"'-t-tttttttl
    I: llllHL
    ~ 10dB F:: _ N O BW~llAPACIH~

    ~wt11llllLl=1:t1lllllllL~"fl.1fj:WJj~ "'OR STABILITY WITH


    HIGH CURRENT LOADS
    - O.l"'"~l:" ~
    '"..":.'" ":"
    10Hz 100Hz 1kHz 10kHz
    FREOUENCY
    FIGURE 7. Minimum Component Configuration

    FIGURE 6. Supply Decoupling vs Frequency


    5 to 10 MHz small amplitude oscillation which
    can occur during the negative swing into a load
    which draws high current. The oscillation is of
    25 kQ halves providing a high source impedance course at too high of a frequency to pass through
    for the integrator. Figure 6 shows supply decoupl· a speaker, but it should be guarded against when
    ing versus frequency for various bypass capacitors. operating in an RF sensitive environment.

    AN69·3
    APPLICATIONS This circu it has a distinct advantage over the cir-
    cuit of Figure 7 when transducers of high source
    With the internal baising and compensation of the impedance are used, in that, the full input imped·
    LM380, the simplest and most basic circuit con- ance of the amplifier is realized. It also has an
    figuration requires only an output coupling capaci- advantage with transducers of low source imped-
    tor as seen in Figure 7. ance since the signal attenuation of the input
    voltage divider is eliminated. The transfer function
    An application of this basic configuration is the
    of the circuit of Figure 10 is given by:
    phonograph amplifier where the addition of volume
    and tone controls is required. Figure 8 shows the
    LM380 with a voltage divider volume control and
    high frequency roll·off tone control.

    v,

    C,
    5(10~F
    Figure 11 shows the response of the circuit of

    .'~ R,'
    2.7n
    Figure 10.

    o.fC'~f ,"T'...
    5O~~mfI
    - -
    811
    -~- "mil
    'FOFl STABILlTV WITH
    HIGH CURRENT LOADS 40 H-Ilttlllll-+llttlH~-ttllj

    " f-tJIttllllI-+lIttIIIIHIHIIIIH
    3D H--lttlllll-+llttIIIIl-+I\III'!~
    FIGURE 8. Phono Amp
    ~ Z5 H--IttllllI-+IHtIIII-+IMH
    20 1+1ltIIIIH-1ltIIIIH--IlIIl1.f
    When maximum input impedance is required or the 15
    signal attenuation of the voltage divider volume 10
    control is undesirable, a "common mode" volume
    control may be used as seen in Figure 9.
    1Hz 10Hz 100Hz 1kHz 10kHz 100kHz

    FREo.UENCY

    FIGURE 11. Tone Control Response

    Most phonograph applications require frequency


    response shaping to provide the R IAA equalization
    *FOASTABllITYWITH
    characteristic. When recording, the low frequencies
    HIGHCURR£NTLOAOS
    are attenuated to prevent large undulations from
    destroying the record groove walls. (8ass tones
    FIGURE 9. "Common Mode" Volume Control
    have higher energy content than high frequency
    tones.) Conversely, the high frequencies are em-
    With this volume control the source loading imped· phasized to ach ieve greater signal-to-noise ratio.
    ance is only the input impedance of the amplifier Therefore, when played back the phono amplifier
    when in the full·volume position. This reduces to should have the inverse frequency response as
    one-half the amplifier input impedance at the zero shown in Figure 12.
    volume position. Equation 1 describes the output
    voltage as a function of the potentiometer setting.

    20 ~~~4-~~~~4-~
    150x 103 )
    (
    1- k1 R v+ 150x 103
    0<; k, <; 1
    (1)
    !
    ~
    10 r1-rHT~rHri-r~~~
    r1~~-f'\JHt~---+f,

    f, H-+ll---l'.;a.ftl-H-t+
    10 r1-H~+-Ht~~l~+-Ht

    30 ~-u~~~~-u~~~

    10Hz 100Hz 1kHz 10kHz 100kHz

    FREnUENCY

    'FOASTABILITYWITH
    HIGH CURRENT LOADS
    "AUDIO Tt\PE POTENTIOMETER FIGURE 12. RIA Playback Equalization
    (,O%QF RT AT 50% ROTATION)

    FIGURE 10. "Common Mode" Volume and Tone


    Control This response is achieved with the circuit of
    Figure 13.

    This "common mode" volume control can be The mid-band gain, between frequencies f2 and f3,
    combined with a "common mode" tone control Figure 12, is established by the ratio of R, to the
    as seen in Figure 10. input resistance of the amplifier (150 kSl.).

    AN69·4
    R,+150kll power capability by a factor of four over the
    Mid-band Gain (3) single amplifier_ However, in most cases the pack-
    150 kll
    age dissipation will be the first parameter limiting
    t18V power delivered to the load_ When this is the case,
    the power capability of the bridge will be only

    5 4.0 " " " - , , , - , , , , , - , - ,

    ~ 3.5

    ~ J 0 f--cf->'!ITII7'9H~~'
    :: 2 5 f--cY,~Io-'9H""'HI":1Hc--i
    ~

    R,=15M
    ~ 1.0 H7'5;i"'f-t~~F~H
    " ;::~ 117r.lc::J~~~n--jH
    'FOR STABILITY WITH
    HIGH CURRENT LOADS 220pF 1.5
    ~ 1.0 HIo-'9Hbl$'l"'cPf
    FIGURE 13. RIAA Phono Amplifier ~ .5 I-f--'RI-Hr--cr"
    ~ 1.0 2.0 J.U 4.0 5.0
    Capacitor C, sets the corner frequency f2 where OUTPUT POWER (WATTS)
    R, = Xc,.
    FIGURE 15A, an Load

    (4)
    twice that of the single amplifier. Figures 15A and
    B show output power versus device package dissipa-
    Capacitor C 2 establishes the corner frequency f3 tion for both 8 and 1611 loads in the bridge con-
    where XC2 equals the impedance of the inverting
    input. This is normally 150 kll. However, in the
    circu it of Figure 13 negative feedback reduces
    the impedance at the inverting input as:

    Z (5)

    Where:
    Zo = impedance at node 6 without external feed-
    back (150 kll)
    J 4 5 6 7
    OUTPUT POWER (WATTS) 16S! LOAD
    Ao gain without external feedback (50)
    FIGURE 15B, 16n Load
    Ao- A
    /3 feedback transfer function /3 = AoA
    figuration. The 3% and 10% harmonic distortion
    contours double back due to the thermal limiting
    A = closed loop gain with external feedback. of the LM380. Different amounts 01 heat sinking
    will change the point at which the distortion
    Therefore: contours bend.
    C2 = 1 The quiescent output voltage of the LM380 is
    2rr 13 ( 1 +z~o ~) specified at 9 ± 1 volts with an 18 volt supply.
    Therefore, under the worst case condition, it is
    possible to have two volts DC across the load.
    BRIDGE AMPLIFIER

    Where more power is desired than can be provided


    with one amplifier, two amps may be used in the
    bridge configuration shown in Figure 14.

    "FORSTABllITYWLTK
    IIIGHCURRENTLOADS

    FIGURE 16. Quiescent Balance Control

    With an 811 speaker this is 0.25A which may be


    excessive. Three alternatives are available; 1) care
    FIGURE 14_ Bridge Configuration can be taken to match the quiescent voltages, 2)
    a non-polar capacitor may be placed in series with
    This provides twice the voltage swing across the the load, 3) the offset balance control of Figure 16
    load for a given supply, thereby, increasing the may be used.

    AN69-5
    The circuits of Figures 14 and 16 employ the circuit does not require a high standby current
    "common mode" volume control as shown before. and power dissipation to maintain regulation.
    However, any of the various input connection
    schemes discussed previously may be used. Fig· With a 20 volt input voltage (±10 volt output) the
    ure 17 shows the bridge configuration with the circuit exhibits a change in output voltage of
    voltage divider input. As discussed in the "Biasing" approximately 2% per 100 mA of unbalanced load
    change. Any balanced load change will reflect only
    v, v. the regulation of the source voltage V IN .
    ---,
    I
    ~ The theoretical plus and minus output tracking
    ability is 100% since the device will provide an
    output voltage at one-half of the instantaneous
    supply voltage in the absence of a capacitor on the
    bypass terminal. The actual error in tracking will
    °FORSTAlILITYWrTH be directly proportional to the unbalance in the
    HIGH CURR~NT LOADS
    quiescent output voltage. An optional potentio-
    FIGURE 17_ Voltage Divider Input meter may be placed at pin 1 as shown in Figure 19
    to null output offset. The unbalanced current
    section the undriven input may be AC or DC output for the circuit of Figure 18 is limited by
    grounded. If Vs is an appreciable distance from the power dissipation of the package.
    the power supply (>3") filter capacitor it should
    be decoupled with a lJ.1F tantaulum capacitor. In the case of sustained unbalanced excess loads,
    the device will go into thermal limiting as the
    INTERCOM temperature sensing circuit begins to function. For
    instantaneous high current loads or short circuits
    The circuit of Figure 18 provides a minimum the device limits the output current to approxi-
    component intercom. With switch 5, in the talk mately 1.3 amperes until thermal shut-down takes
    position, the speaker of the master station acts over or until the fault is removed.
    as the microphone with the aid of step-up trans-
    former T , .

    HIGH INPUT IMPEDANCE CIRCUIT

    The junction FET isolation circuit shown in Fig·

    !""".~
    ure 20 raises the input impedance to 22 Mn for
    low frequency input signals. The gate to drain

    'FOR
    :
    STA.llITYWl~
    -: !
    - - - - - - - - - - - - - - - - - - - - - - - ___ oJ
    v,

    ~'D'
    HlllHCURAlNTlOADS

    FIGURE 18_ Intercom


    o
    A turns ratio of 25 and a device gain df 50 allows
    a maximum loop gain of 1250 .. Rli provides a
    "common mode" volume control. Switching 5,
    -'...
    v,. 0---"-+1_ S
    KE4221 v,

    to the listen position reverses the role of the


    master and remote speakers. A'
    22M
    Al
    2DK
    VOUT

    LOW COST DUAL SUPPLY


    The circuit shown in Figure 19 demonstrates a
    minimum parts count method of symmetrically

    I FIGURE 20,

    t A'~
    1M;'
    I
    I
    I
    I
    I capacitance (2 pF maximum for the K E4221

    l
    shown) of the FET limits the input impedance
    I as frequency increases.
    II
    I
    At 20 k Hz the reactance of th is capacitor is
    approximately -j4 Mn giving a net input imped-
    FIGURE 19. Dual SupplV ance magnitude of 3.9 Mn. The values chosen for
    R R2 and C, provide an overall circuit gain of
    "
    splitting a supply voltage. Unlike the normal R, at least 45 for the complete range of parameters
    C, and power zener diode technique the LM380 specified for the KE4221.

    AN69-6
    When using another F ET device the relevant design positive feedback around the LM380 for closed
    equations are as follows: loop gains of up to 300. Figure 21 shows a
    practical example of an LM380 in a gain of 200
    circuit.
    Av
    (~)
    R, + -
    gm
    (50) (7)
    The equation describing the closed loop gain is:

    -Av(w)
    AVCL ~ (12)
    1 _ Av(w)
    gm (8) R,
    1+-
    R2
    (9)
    where AV(w) is complex at high frequencies but is
    nominally the 40 to 60 specified on the data sheet
    IDS ~ IDss ( 1-
    VGS )2 (10) for the pass band of the amplifier. If 1 + R,/R2
    Vp approaches the value of Av(w), the denominator
    of equation 12 approaches zero, the closed loop
    The maximum value of R2 is determined by the gain increases toward infinity, and the circuit
    product of the gate reverse leakage IGSS and R2 . oscillates. This is the reason for limiting the closed
    This voltage should be 10 to 100 times smaller loop gain values to 300 or less. Figure 22 shows
    than V p • The output impedance of the FET the loaded and unloaded bode plot for the circuit
    source follower is: shown in Figure 21.

    250
    Ra ~ (11)
    gm 200 RI =loJ
    , :::r::::.L

    ,\
    AL'"an""\.
    150
    so that the determining resistance for the inter·
    stage RC time constant is the input resistance of
    '"~
    100
    J
    the LM380.

    " II
    /
    BOOSTED GAIN USING POSITIVE FEEDBACK
    10 lDD lk 10k lOOk 1M 10M
    For applications requiring gains higher than the FREOUENCY (Hz) .....
    internally set gain of 50, it is possible to apply
    FIGURE 22. Boosted Gain Bode Plot

    Vs=+IBV
    The 24 pF capacitor C2 shown on Figure 21 was
    added to give an overdamped square wave response
    v, under full load conditions. It causes a high fre-
    quency roll-off of:
    R,
    C2
    24pF '" (13)

    The circuit of Figure 21 will have a very long


    (1000 sec) turn on time if RL is not present,
    FIGURE 21. Boosted Gain of 200 Using Positive but only a 0.01 second turn on time with an 8n
    Feedback load.

    AN69-7
    »
    z
    Joe E. Byerly
    ~
    August 1972 o

    r-
    3:
    w
    LM381A DUAL PREAMPLIFIER FOR
    ULTRA-LOW NOISE APPLICATIONS ...»
    00

    INTRODUCTION c
    c
    The LM381A is a dual preamplifier expressly de- Figures 2A and 2B show the wide-band (10 Hz-
    10 kHz) input noise voltage and input noise cur-
    »
    r-
    signed to meet the requirements of amplifying low
    level signals in noise critical applications. Such rent versus collector current for the single ended '"tI
    applications include hydrophones, scientific and ::D
    instrumentation recorders, low level wideband gain 6
    m
    blocks, tape recorders, studio sound equipment, 5 »
    etc.
    4
    3:
    '"tI
    The LM381A can be externally biased for optimum ~ r-
    :;'"
    3
    noise performance in ultra-low noise appl ications.
    When this is done the LM381A provides a wide band, , ."
    high gain amplifier with noise performance that m
    exceeds that of todays best transistors.
    1
    ::D
    0
    The amplifier can be operated in either the differ- ."
    ential or single ended input configuration. How-
    ZD 60 100 140
    Ie (/.lAI
    180 220
    o
    ever, for optimum noise performance, the input ::D
    must be operated single ended, since both transis- FIGURE 2A. Wideband Equivalent Input Noise Voltage
    vs Collector Current C
    tors contribute noise in a differential stage, de- r-
    grading input noise by the factor 0. A second -I
    1.'
    consideration is the design of the input bias cir- ::D
    cuitry. Both the load and biasing elements must 1.0
    (10Hz-10kHz)

    ./
    »I
    be resistive, since active components would each 0.8 r-
    contribute additional noise equal to that of the ~ f..- .... o
    input device. Thirdly, the current density of the
    input device should be optimized for the source
    '":! 0.6

    0.4
    f..- .......... :E
    resistance of the input transducer. z
    Figure 1 shows the schematic diagram of one
    D.' o
    0 C/)
    channel of LM381A (a detailed explanation of the 180 2ZD
    circuit operation is given in application note
    ZD 60 100 140
    m
    Ie tuAI
    AN-64). To operate the input single ended, tran-
    sistor O 2 is turned OFF by returning the base of FIGURE 2B. Wideband Equivalent Input Noise Current
    »'"tI
    O2 (Pins 2, 13) to ground. vs Collector Current '"tI
    r-
    (')
    »
    .,
    ;., -I
    o
    ~13D., '" Z
    D1 I ~ --.l i'
    1
    ~
    J"i:...
    II

    (6~DI
    1\
    ~"
    Io.,j

    04 t'"
    -,
    Q1~ ? " 17,8)
    C/)

    ....0'
    (5,11) Io.,jOS ~

    (4)

    FIGURE 1. LM381A Schematic Diagram

    AN70-1
    input configuration of the LM381A. Total input v,
    noise of the amplifier is found by:
    .,

    Where:

    en = amplifier noise voltage/y'RZ

    in = amplifier noise current/y'RZ

    Rs = source resistance n
    k = Boltzmann's constant = 1.38 x 10.23
    J/oK

    T = source resistance temperature °K .,


    B.W. = noise bandwidth

    Figure 3 shows a plot of input transistor (a,) col-


    lector current versus source resistance for optimum
    ., R4

    noise performance of the LM381A. For source


    impedances less than 3 kn the noise voltage term
    (en) dominates and the input is biased at 170 f.J.A
    which is optimum for noise voltage. In the region FIGURE 4. LM38'A with Biasing Components for
    between 3 kn and 15 kn, both the en and inRs Increasing 01 Current Density
    terms contribute and the input shou Id be biased
    as indicated by Figure 3. Above 15 kn, the inRs
    term is dominant and the amp Iifier is operated Since resistors R, and R2 are biased from the
    without additional external biasing. power supply, the decoupling capacitor, C" is
    required to preserve supply rejection. The value
    of C, is given by:
    200 ,-...,...,..,rrrlTll"-.,-rrrn-m
    180 e" DOMINANT,+tt_+-t+tt+fH P.S.R.
    160 l"- 10 20
    t 140
    C, = 2rrfsR,A, (3)
    '2 120 f-++lf¥tttt-+-t+tt+fH
    ~ 100 f-++H-Id-Ht-+-t-+tttttl
    80 f-++H+~-+-t-+tttfH
    60 f-++H+~-+-t-+tttfH Where:
    P.S.R. = Supply rejection in dB referred to
    :: NORMAL SINGLE l\!n Rs DOMINANT
    input
    o CE~N~D~ED~8~IA~S~lE~V~El~~LLLllill
    HI Jk 5k 10k 2Dk 4Dk 100k fs = Frequency of supply ripple
    Rs(H)-..
    A, = Voltage gain of first stage

    FIGURE 3. Collector Current vs Source Resistance As R, becomes smaller capacitor C, increases for
    for Optimum Noise Performance
    a given power supply rejection ratio. Conversely,
    as R2 becomes smaller the gain of the input stage
    decreases, adversely affecting noise performance.
    Figure 4 shows the input stage of the LM381A with For the range of collector currents over which the
    the external components added to increase the LM381A is operating. a reasonable compromise is
    current density of transistor a,.
    Resistors R, and obtained with:
    R2 supply the additional current (1 2 ) to the exist·
    ing collector current (I,) which is approximately (4)
    18f.J.A.

    The sum of resistors R, & R2 is given by: The gain of the input stage is:

    (R, +R2 ) = - -Vs" -


    - 2.1
    --- (2)
    (2 X 105 ) R2
    le- 18x 10-6 R2 + 2 X 105
    A, = 026 1 (5)
    For DC considerations, only the sum (R, + R2 ) is -'- + -:---':---:--
    important. When considering the AC effects, how- Ie ~+....!..+....!..
    ever, the values of R, and R2 become significant. 104 R3 R4

    AN70·2
    Resistor divider R,/R 3 provides negative DC feed-
    A
    -4 X 10-'2 (11)
    back around the amplifier establishing the quies-
    cent operating point_ R f is found by: 2rrf, ( -_026) 102ci
    Ie

    Where:
    f, = high frequency 3 dB corner
    Ie = 0, collector current
    (6) A = mid band gain dB

    Example: Design an ultra-low noise preamplifier


    For DC stability let: with a gain of 1.000 operating from a 24 volt
    supply and a 600Q source impedance_ Bandwidth
    R3 = 1 kQ Maximum (7) of interest is 20 Hz to 10 kHz_

    1_ From Figure 3 the optimum collector cur-


    Rf can then be found from:
    rent for 600Q source resistance is 170 J1.A.

    2_ From equation (2).


    1 [
    R -- Vs X 107 ]
    -910 (8)
    ,- 2 6_05 X 103 + Ie x 107
    Vs - 2_1
    R, + R2 =
    Ie - 18 x 10-6
    Where:
    Vs = Supply Voltage = _-=-24-'---.=2:..:-1__

    Ie = 0, Collector Current (170 - 18) x 10-6

    R, + R2 = 1.44 X 105 _
    The AC closed loop gain is set by the ratio:

    3_ From equation (4).


    (9)
    1.44 x 105
    = 1.08 X 105
    Capacitor C2 sets the low frequency 3 dB corner 1.333
    where:
    R2 '" 100 kQ.
    (10)
    R, = 36 x 103 ", 39 kQ.

    4. From equation (7) let Rs = 1 kQ.


    v,
    5. From equation (8).
    01
    1 [ Vs X 10 7 ]
    02
    Rf = - -910
    2 6.05 x 103 + Ie x 107

    .t,~: T"
    f l~~I5.111 -:- 1 [ 24 X 107 ]
    R, = '2 -910
    {1,8} 6.05 x 103 + 1.7 x 103
    V1N 'V >'''4~<> V,
    W-LMJ81A
    (3,12)
    - (2,IJ) Rf = 2_67 X 104 ", 27 kQ_
    0,

    6. For a gain of 1.000; equation (9).


    (R f + R4 )
    OJ 04
    Amplifier Gain = ~ = 1.000

    = 27ft

    FIGURE 5. Single Ended Input Configuration with


    7. For a low corner frequency. fa. of 20 Hz;
    External Biasing Components
    equation (10).
    1 1
    Figure 5 shows the LM381A in the single ended C2 = 2rrfoR4 = 6.28 x 20 x 27_
    input configuration with the add itional biasing
    components_ Capacitor C3 may be added to limit
    the ampl ifier bandwidth to the frequency range of = 2.95 x 104
    interest. thus eliminating excess noise outside the
    pertinent bandwidth_

    AN70-3
    Z4V
    8. From equation (5) the gain of the input
    stage is:

    (2 X 105 ) R2 R2
    .,
    39K

    A, = .026
    R2

    -
    104
    +2 X
    ,

    +-+-
    105

    Ic + """:---..:...,':----:-1-
    R3 R4
    r-
    "
    VIN ""'
    I.*~" f'~
    !f+~ >":(""1.'::'1)t-J>-O
    lj.lLMJ81A
    1't:"
    v,
    _ (l~_ (4) RI
    2 X 105 X 105 - ~.1~ VK

    105 + 2 X 105
    A'=-.702~6~----1~--
    ---- + ------ •J ••
    1.7 X 10. 4 _1_ +_1_ +2- lK 2m
    104 103 27
    -::-C2
    ~3DDI'F
    A, = 372.

    FIGURE 6. Typical Application with Increased Current


    9. For 100 dB supply rejection at 120 Hz. Density of Input Stage
    Equation (3),
    Total Wideband = 4.37 X 1O- 7 V.
    P.S.R. 'DO Noise Voltage
    1020 _ _
    10"20 = _ _---'...:.....c.C-.
    C, =
    21ffR,A, 21fx 120 x 39 x 103 x 372
    Wideband
    Noise Figure
    105
    C, = ---'-'---- = 9.1 x 10-6
    1.09x 10'0 = 10 log 9.94 x 10-'8 + 9.0 X 10-'8 + 1.86 x 10-'9

    9.94 x 10-'8
    C, "" 101lF.
    = 10 log 1.92 = 2.83 dB.
    10. For a high frequency corner, f,. of 10 kHz;
    equation (11).
    CONCLUSION
    C3 = (.026) A -4 X 10·'2 In applications requiring a wide band, high gain
    21ff, T 1020 preamplifier where noise performance is critical,
    the LM381A is unsurpassed. In addition to ultra
    low noise performance, the LM381A offers two
    C3 = _ _ _ _ _.:..1_ _ _ _ _ -4 x 10·'2 completely independent amplifiers, each with an
    6.28 x 104 x 1.53 X 102 x 104 internal power supply decoupler·regulator provid·
    ing 120 dB supply rejection and 60 dB channel
    C3 = 6.4 X 10·'2"" 6.8 pF. separation.
    Other outstanding features include, high gain
    The noise performance of the circuit of Figure 6
    (112 dB) large output voltage swing (V s - 2V)
    can be found with the aid of Figures 2A and 2B
    peak to peak, wide supply operating range (9 -
    and equation (1). From Figures 2A and 2B the
    40V). wide power bandwidth (75 kHz, 20 V p . p ),
    noise voltage (en) and noise current (in) at 170 IlA
    internal frequency compensation, and short·circuit
    Ie are: en = 3.0 nV/v'HZ, in =.72 pA/v'H'l. From
    equation (1) protection

    REFERENCE
    J.E. Byerly and E.L. Long - "LM381 Low Noise
    Dual Preamplifier" National Semiconductor Cor·
    poration AN·64, May 1972.

    AN70-4
    »
    z
    Marvin K. Vander Kooi and George Cleveland
    July 1972

    s:
    (')
    ::D
    o
    MICROPOWER CIRCUITS USING THE LM4250 '"tI
    PROGRAMMABLE OP AMP
    o
    ~
    m
    ::D
    INTRODUCTION
    (')
    The LM4250 is a highly versatile monolithic opera· R, and R2 provide emitter degeneration for greater
    tional amplifier. A single external programming stability at high bias currents. 0 3 and 0 4 are used ::D
    (')
    resistor determines the quiescent power dissipa· as active loads for a, and O 2 to provide high gain
    tion, input offset and bias currents, slew rate, and also form a current inverter to provide the C
    gain·bandwidth product, and input noise character· maximum drive for the single ended output into -I
    istics of the amplifier. Since the device is in effect 0 5 . 0 5 is an emitter follower which prevents load· en
    a different op amp for each externally programmed ing of the input stage by the succeeding amplifier
    stage.
    C
    set current, it is possible to use a single stock item
    for a variety of circuit functions in a system.
    en
    This paper describes the circuit operation of the One advantage of this lateral PNP input stage is a
    z
    G)
    LM4250, various methods of biasing the device, common mode swing to within 200 mV of the
    frequency response considerations, and some cir- negative supply. This feature is especially useful -I
    cuit applications exercising the unique character· in single supply operation with signals referred to ::t
    istics of the LM4250. ground. Another advantage is the almost constant m
    input bias current over a wide temperature range. r-
    CIRCUIT DESCRIPTION LM4250 The input resistance RIN is approximately equal
    to 2~ (R E + re) where ~ is the current gain, re is
    s:
    .j::o
    The LM4250 has two special features when com-
    the emitter resistance of one of the input lateral I\)
    pared with other monolithic operational amplifiers. U1
    PNPs, and RE is the resistance of one of the 10
    One is the ability to externally set the bias current
    kQ emitter resistor. Using a DC beta of 100 and o
    levels of the amplifiers, and the other is the use of
    the normal temperature dependent expression for '"tI
    PNP transistors as the differential input pair.
    regives: ::D
    kT
    o
    G)
    r------~-------<>' ,. RIN "" 2 MQ + 2 qls· (1)
    ,".. ...'" ::D
    »
    where Is is input bias current. At room tempera· :s:
    ture this formula becomes:
    s
    RIN "" 2 MQ +
    52 mV
    (2) »
    03
    r-
    m
    .00

    50
    o
    '"tI
    20 »
    ~
    ;;
    z
    <ii
    '0 s:'"tI

    1.0 .0 .00
    ISET tlJA)

    FIGURE 1. LM4250 Schematic Diagram FIGURE 2. Input Resistance vs ISET

    Referring to Figure 1, a,
    and O 2 are high current Figure 2 gives a typical plot of RIN vs lset derived
    gain lateral PNPs connected as a differential pair. from the above equation.

    AN71·1
    Continuing with the circuit description, 0 6 level lO PIN !! lOPIN 8

    ·,--1
    shifts downward to the base of 0 8 which is the
    second stage amplifier. 0 8 is run as a common
    emitter amplifier with a current source load (0'2) VSVYITCH

    to provide maximum gain. The output of 0 8 drives

    J
    R", C1

    the class B complementary output stage com· R, 1OOO


    posed of 0'5 and 0,8' "

    The bias current levels in the LM4250 are set by


    the amount of current (I se,) drawn out of Pin 8. V-OR v- OR
    GROUND GROUND
    The constant current sources 0 10, 0", and 0'2 J, Jb
    are controlled by the amount of I,e' current
    through the diode connected transistor Og and rOPINS TOPINB
    resistor Rg. The constant collector current from
    010 biases the differential input stage. Therefore,
    the level 010 is set at will control such amplifier
    v, RUMIT

    characteristics as input bias current, input resist·


    ance, and amplifier slew rate. Current source 0" R"

    biases 0 5 and 0 6 , The current ratio between 0 5 -v,


    and 0 6 is controlled by constant current sink 0 7 ,
    Current source 0'2 sets the currents in diodes 0'3
    and 0'4 which bias the output stage to the verge V-OR v- DR
    GROUND GROUNO
    of conduction thereby eliminating the dead zone
    J, 3d
    in the class B output. 0'2 also acts as the load for
    0 8 and limits the drive current to 0,5' FIGURE 3. Biasing Schemes

    The output current limiting is provided by 0'6 and


    017 and their associated resistors R'6 and R 17 ·
    O 2 acts as an emitter follower current sink whose
    When enough current is drawn from the output,
    value depends on the control voltage Vc on the
    0'6 turns on and limits the base drive of 0,5'
    base. This circuit provides a method of varying
    Similarly 017 turns on when the LM4250 attempts
    the amplifier's characteristics over a limited range
    to sink too much current, limiting the base drive
    while the amplifier is in operation. The FET
    of 0'8 and therefore output current. Frequency
    circuit shown in Figure 3d covers the full range of
    compensation is provided by the 30 pF capacitor
    set currents in response to as little as a 0.5V gate
    across the second stage amplifier, 0 8 , of the
    potential change on a low pinch·off voltage FET
    LM4250. This provides a 6 dB per octave roll off of
    such as the 2N3687. The limit resistor prevents
    the open loop gain.
    excessive current flow out of the LM4250 when
    the FET is fully turned on.
    BIAS CURRENT SETTING PROCEDURE
    FREOUENCY RESPONSE OF A
    The single set resistor shown in Figure 3a offers PROGRAMMABLE OP AMP
    the most straightforward method of biasing the
    LM4250. When the set resistor is connected from This section provides a method of determining the
    Pin 8 to ground the resistance value for a given sine and step voltage response of a programmable
    set current is: op amp. Both the sine and step voltage responses
    of an amplifier are modified when the rate of
    v+ -0.5
    change of the output voltage reaches the slew rate
    RSET = ISET .
    (3)
    limit of the amplifier. The following analysis
    The 0.5 volts shown in Equation 3 is the voltage develops the Bode plot as well as the small signal
    drop of the master bias current diode connected and slew rate limited responses of an amplifier
    transistor on the integrated circuit chip. In appli· to these two basic categories of waveforms.
    cations where the regulation of the V+ supply
    with respect to the V- supply (as in the case of Small Signal Sine Wave Response
    tracking regulators) is better than the V+ supply The key to constructing the Bode plot for a
    with respect to ground the set resistor should be programmable op amp is to find the gain band·
    connected from Pin 8 to V-. RSET is then: width product, GBWP, for a given set current.
    V+ + IV-I-0.5 Ouiescent power drain, input bias current, or
    RSET = (4) slew rate considerations usually dictate the desired
    ISET set current. The data sheet curve relating GBWP to
    The transistor and resistor scheme shown in Fig· set current provides the value of G BWP which
    ure 3b allows one to switch the amplifier off with· when divided by one yields the unity gain cross·
    out disturbing the main V+ and V- power supply over of f u' Assum ing a set current of 6 IlA gives a
    connections. Attaching C, across the circuit pre· GBWP of 200,000 Hz and therefore an fu of
    vents any switching transient from appearing at the 200 kHz for the example shown in Figure 4.
    amplifier output. The dual scheme shown in Fig· Since the device has a single dominant pole, the
    ure 3c has a constant set current flowing through rolloff slope is -20 dB of gain per decade of
    Rs, and a variable current through RS2 ' Transistor frequency (-6 dB loctave). The dotted Iine shown

    AN71·2
    where:

    va = output voltage
    Vp = peak output voltage
    d Vo
    S, = maximum F

    The maximum sine wave frequency an amplifier


    with a given slew rate will sustain without causing
    the output to take on a triangular shape is there·
    FREQUENCV fore a function of the peak amplitude of the
    output and is expressed as:
    FIGURE 4. Bode Plot
    (10)
    on Figure 4 has this slope and passes through the
    200 kHz fu point. Arbitrarily choosing an inverting Figure 5 shows a quick reference graphical pre·
    amplifier with a closed loop gain magnitude of sentation of this formula with the area below any
    50 determines the height of the 34 dB horizontal V peak line representing an undistorted small signal
    line shown in Figure 4. Graphically finding the sine wave response for a given frequency and
    intersection of the sloped line and the horizontal amplifier slew rate and the area above the V peak
    line or mathematically dividing GBWP by 50 line representing a distorted sinewave response due
    determines the 3 dB down frequency of 4 kHz to slew rate limiting for a sine wave with the
    for the closed loop response of this amplifier con· given V peak.
    figuration. Therefore, the amplifier will now apply
    a gain of -50 to all small signal sine waves at tOOk rrnrrrnrrrm-rrr'lTl"'l/[!r.l

    frequencies up to 4 kHz. For frequencies above


    4 kHz, the gain will be as shown on the sloped
    portion of the Bode plot.

    Small Signal Step Input Response


    The amplifier's response to a positive step voltage
    change at the input will be an exponentially rising
    waveform whose rise time is a function of the
    closed loop 3 dB down bandwidth of the amplifier.
    The amplifier may be modeled as a single pole low
    REQUIRED MAXIMUM SLEW RATE "S," (V/jJs)
    pass filter followed by a gain of 50 wideband
    ampl ifier. F rom basic filter theory', the 10% to FIGURE 5. F,equency vs Slew Rate Limit vs Peak Output
    90% rise time of a single pole low pass filter is: Voltage
    0.35 Large signal step voltage changes at the output
    t, = f3 dB
    (5)
    will have a rise time as shown in equation 5 until
    a signal with a rate of output voltage change equal
    For the example shown in Figure 4 the 4 kHz
    to the slew rate of the amplifier occurs. At this
    3 dB down frequency would give a rise time of
    point the output will become a ramp function with
    87.5/Ls.
    a slope equal to S,. This action occurs when:
    Slew Rate Limited Large Signal Response V step
    The final consideration, which determines the S, :<::;: (11)
    t,
    upper speed limitation on the previous two types
    to
    of signal responses, is the amplifier slew rate. The LOW PASS
    FILTER RESPONSE
    slew rate of an amplifier is the maximum rate of
    change of the output signal which the amplifier is
    capable of delivering. In the case of sinosoidal
    . -"
    ~
    t.O I-+ttPk'kPlt'lN'l",.J.-oOf'VSTEP =32V
    rVSTEP=16V
    VSTEP =av
    4V
    VSTl:P'=
    signals, the maximum rate of change occurs at the
    zero crossing and may be derived as follows: : 0.1 VSTEP =2V
    VSTEP =IV

    (6)
    ~ .Ot
    Vo = Vp sin 211f t
    SLEW RATE
    LIMITING
    d Va .00t
    = 211 f V p cos 211 f t (7) .t 1.0 to tOO tODD to.OOO
    crt t, (j.I sttl10% TO 90%

    ~I
    FIGURE 6. Slew Rate vs Rise Time vs Step Voltage
    = 211 f Vp (8)
    d t ,= 0
    Figure 6 graphically expresses this formula and
    shows the maximum ampl itude of undistorted
    S, = 211 f MAx Vp (9) step voltage for a given slew rate and rise time.

    *See reference.

    AN71·3
    The area above each step voltage line represents the
    undistorted low pass filter type response mode of
    the amplifier. If the intersection of the rise time l30K
    and slew rate values of a particular amplifier con- v.. o-"""'I.-<~
    figuration falls below the expected step voltage v,
    amplitude line, the rise time will be determined
    by the slew rate of the amplifier. The rise time will
    then be equal to the amplitude of the step divided
    R3
    by the slew rate S,_ 300K

    Full Power Bandwidth -uv

    The full power bandwidth often found on ampli- FIGURE 7_ 500 nW x 10 Amplifier
    fier specification sheets is the range of frequencies
    from zero to the frequency found at the inter- increases the power dissipation to approximately
    section on Figure 5 of the maximum rated output 1 /lW per battery, a power drain of 15 /lW or less
    voltage and the slew rate S, of the amplifier_ will not affect the shelf life of a mercury cell.
    Mathematically this is:
    S, MICRO-POWER MONITOR WITH HIGH
    = (12)
    ffullpower 21TVrated CURRENT SWITCH
    The full power bandwidth of a programmable Figure B shows the combination of a micro-power
    amplifier such as the LM4250 varies with the comparator and a high current switch run from a
    master bias set current. separate supply. This circuit provides a method of
    continuously monitoring an input voltage while
    The above analysis of sine wave and step voltage dissipating only 100/lW of power and still being
    amplifier responses applies for all single dominant capable of switching a 500 mA load if the input
    pole op amps such as the LM101A, LM107, exceeds a given value. The reference voltage can be
    LM1OBA, LM112, LM11B, and LM741 as well as any value between +8.5V and -B.5V. With a
    the LM4250 programmable op amp_ minimum gain of approximately 100,000 the com-
    parator can resolve input voltage differences down
    500 NANO-WATT X10 AMPLIFIER into the 0_2 mV region.
    The X10 inverting amplifier shown in Figure 7
    demonstrates the low power capabil ity of the V'

    LM4250 at extremely low values of supply volt-


    age and set current_ The circuit draws 260 nA
    from the +1_0V supply of which 50 nA flows
    through the 12 M.Q set resistor_ The current into
    the -1.0V supply is only 210 nA since the set
    resistor is tied to ground rather than V-_ Total
    quiescent power dissipation is:

    Po = (260 nA) (1V) + (210 nA) (1V) (13)

    (14) FIGURE S_ /l-Power Compa,ato, with High Current


    Po = 470 nW Switch

    The slew rate determined from the data sheet The bias current for the LM4250 shown in FigureB
    typical performance curve is 1 VIms for a _05 /lA is set at 0.44/lA by the 22 M.Q Rse, resistor. This
    set current_ Samples of actual values observed were results in a total comparator power drain of
    1.2 V/ms for the negative slew rate and 0.B5 V/ms 100/lW and a slew rate of approximately 11 V/ms
    for the positive slew rate. This difference occurs in the positive direction and 12.B V Ims in the
    due to the non-symmetry in the current sources negative direction. Potentiometer Rl provides in-
    used for charging and discharging the internal put offset nulling capability for high accuracy
    30 pF compensation capacitor. applications. When the input voltage is less than
    the reference voltage, the output of the LM4250
    The 3dB down (gain of -7_07) frequency observed is at approximately -9.5V causing diode Dl to
    for this configuration was approximately 300 Hz conduct. The gate of 0 1 is held at -B.BV by the
    which agrees fairly closely with the 3.5 kHz
    voltage developed across R3 . With a large negative
    GBWP divided by 10 taken from an extrapolation voltage on the gate of 0 1 it turns off and removes
    of the data sheet typical GBWP versus set current
    the base drive from O2 - This results in a high volt-
    curve.
    age or open switch condition at the collector of
    Peak-to-peak output voltage swing into a 100 k.Q O 2 , When the input voltage exceeds the reference
    load is 0.7V or ±0.35V peak. An increase in supply voltage, the LM4250 output goes to +9.5V causing
    voltage to ±1.35V such as delivered by a pair of Dl to be reverse biased. 0 1 turns on as does O 2 ,
    mercury cells directly increases the output swing and the collector of O 2 drops to approximately 1V
    by ±0.35V to 1.4V peak-to-pe'ak. Although this while sinking the 500 mA of load current.

    AN71-4
    The load denoted as ZL can be resistor, relay coil, R,

    or indicator lamp as required; but the load current


    tUV
    should not exceed 500 mAo For V+ values of less I.
    ~
    than 15V and IL values of less than 25 mA both
    O 2 and R2 may be omitted. With only the 2N4860 v.
    INI14
    JFET as an output device the circuit is still capable
    of driving most common types of indicator lamps.
    R,
    IC METER AMPLIFIER RUNS ON
    TWO FLASHLIGHT BATTERIES
    Meter amplifiers normally require one or two
    +15V~
    9V transistor batteries. Due to the heavy current
    drain on these supplies, the meters must be switch- BI':"'ISV

    ed to the OFF position when not in use. The meter


    circuit described here operates on two 1.5V flash·
    r-f
    -=- u-=- 15V
    POWER
    SUPPLY

    light batteries and has a quiescent power drain so .TSVo----J

    low that no ON·OFF switch is needed. A pair of


    FI~URE 10. Complete Meter Amplifier
    Eveready No. 950 "D" cells will serve for a
    minimum of one year without replacement. As a
    DC ammeter, the circuit will provide current
    Resistance Values for
    ranges as low as 100 nA full·scale. DC Nano and Micro Ammeter

    The basic meter amplifier circuit shown in Figure I FULL SCALE Rf[nl Rj[nI
    9 is a current·to·voltage converter. Negative feed- 100 nA 1.5M l.5M
    back around the amplifier insures that currents 500 nA 300k 300k
    liN and If are always equal, and the high gain of the lilA 300k 0
    op amp insures that the input voltage between 51lA 60k 0
    lOIlA 30k 0
    Pins 2 and 3 is in the microvolt region. Output
    50llA 6k 0
    lOOIlA 3k 0

    since a resistance of this value contributes an


    error of less than 0.1% in output voltage. Potenti·
    ometer R2 provides an electrical meter zero by
    forcing the input offset voltage Vas to zero. Full
    scale meter deflection is set by R,. Both R, and
    R2 only need to be set once for each op amp and
    meter combination. For a 50 microamp 2 kn
    meter movement, R, should. be about 4 kn to
    give full scale meter deflection in response to a
    FIGURE 9. Basic Meter Amplifier
    300 mV output voltage. Diodes D, and D2 pro-
    vide full input protection for overcurrents up to
    voltage Va is therefore equal to -lfR f. Consider· 75 mAo
    ing the ±1.5V sources (±1.2V end·of·life) a practi·
    With an Rf resistor value of 1.5M the circuit in
    cal value of Va for full scale meter deflection is
    Figure 10 becomes a nanommeter with a full
    300 mV. With the master bias-current setting
    scale reading capability of 100 nA. Reducing Rf
    resistor (R,) set at 10 Mn, the total quiescent
    to 3 kn in steps, as shown in Figure 10 increases
    current drain of the circuit is 0.6 /lA for a total
    power supply drain of 1.8 /lW. The input bias cur- the full scale deflection to 100 /lA, the maximum
    for this circuit configuration. The voltage drop
    rent, required by the amplifier at this low level of
    across the two input terminals is equal to the
    quiescent current, is in the range of 600 pA.
    output voltage Va divided by the open loop gain.
    Assuming an open loop gain of 10,000 gives an
    The Complete Nanoammeter
    input voltage drop of 30 /lV or less.
    The complete meter amplifier shown in Figure 10
    is a differential current·to·voltage converter with
    Circuit for Higher Current Readings
    input protection, zeroing and full scale adjust
    provisions, and input resistor balancing for mini· For DC current readings higher than 100 /lA, the
    mum offset voltage. Resistor R'f (equal in value inverting amplifier configuration shown in Fig·
    to Rf for measurements of less than 1 /lA) insures ure 11 provides the required gain. Resistor RA
    that the input bias currents for the two input develops a voltage drop in response to input
    terminals of the amplifier do not contribute signifi· current IA. This voltage is amplified by a factor
    cantly to an output error voltage. The output volt· equal to the ratio of Rf/R B. RB must be sufficient·
    age Va for the differential current·to·voltage con· Iy larger than RA, so as not to load the input
    verter is equal to -2l f Rf since the floating input signal. Figure 11 also shows the proper values of
    current liN must flow through Rf and R'f. R'f RA, RB and Rf for full scale meter deflections of
    may be omitted for Rf values of 500 kn or less, from 1 mA to lOA.

    AN71·5
    LOW FREQUENCY PULSE GENERATOR
    USING A SINGLE +5V SUPPLY
    The variable frequency pulse generator shown in
    Figure 13 provides an example of the LM4250
    R. operated from a single supply. The circuit is a
    buffered output free running multivibrator with
    a constant width output pulse occurring with a
    frequency determined by potentiometer R2.

    FIGURE 11. Ammeter

    Resistance Values for


    DC Ammeter

    I FULL SCALE RA Inl Ralnl Rflnl


    lmA 3.0 3k 300k
    lOrnA
    100mA
    .3
    .3
    3k
    30k
    300k
    300k
    ..'M
    lA .03 30k 300k
    lOA .03 30k 30k
    FIGURE 13. Pulse Generator

    A 10 mV to 100V Full-Scale Voltmeter


    The LM4250 acts as a comparator for the voltages
    A resistor inserted in series with one of the input found at the upper plate of capacitor C, and at the
    leads of the basic meter am pi ifier converts it to a reference point denoted as Vr on Figure 13.
    wide range voltmeter circuit, as shown in Fig· Capacitor C, charges and discharges with a peak·to·
    ure 12. This inverting amplifier has a gain varying peak amplitude of approximately 1V determined
    from -30 for the 10 mV full scale range to by the shift in reference voltage Vr at Pin 3 of the
    -0.003 for the 100V full scale range. Figure 12 op amp. The charge path of C, is from the ampli·
    also lists the proper values of Rv, Rt , and R' t for fier output, which is at its maximum positive
    each range. Diodes D 1 and D2 provide complete voltage V H1GH (approximately V+ -0.5V), through
    R, and through the potentiometer R2. Diode D, is
    R, reverse biased during the charge period. When C,
    charges to the Vr value determined by the net
    result of V H1GH through resistor Rs and V+
    through the voltage divider made up of resistors
    " R3 and R4 the amplifier swings to its lower limit
    of approximately 0.5V causing C, to begin dis·
    charging. The discharge path is through the forward
    R;
    biased diode D 1 , .through resistor R" and into
    Pin 6 of the op amp. Since the impedance in the
    -15V
    '::" ":" discharge path does not vary for R2 settings of
    VOLTMETER from 3 kn to 5 Mn, the output pulse maintains
    a constant pulse width of 41 fJ.S ±1.5 fJ.S over this
    FIGURE 12. Voltmeter range of potentiometer settings. Figure 14 shows
    the output pulse frequency variation from 6 kHz
    down to 360 Hz as R2 places from 100 kn
    Resistance Values for a up to 5 Mn of additional resistance in the charge
    DC Voltmeter path of Ct. Setting R2 to zero ohms will short out
    diode D, and cause a symmetrical square wave
    V FULL SCALE Rv Inl Rflnl Ri[nl output at a frequency of 10 kHz. Increasing the
    10mV lOOk 1.5M 1.5M value of C, will lower the range of frequencies
    100mV 1M 1.5M 1.5M available in response to the R2 variation shown on
    IV 10M 1.5M 1.5M
    Figure 14. Electrolytic capacitors may be used for
    lOV 10M 300k 0
    100V 10M 30k 0
    the larger values of C, since it has only positive
    voltages applied to it.
    The output buffer a, presents a constant load to
    amplifier protection for input overvoltages as high the op amp output thereby preventing frequency
    as 500V on the 10 mV range, but if overvoltages variations caused by V H1GH and V LOW voltages
    of this magnitude are expected under continuous changing as a function of load current. The output
    operation, the power ratingof Rv should be adjust· of a, will interface directly with a standard TTL
    ed accordingly. or DTL logic device. Rev"ersing diode D, will invert

    AN71·6
    10,ODO The entire circuit can run from two 1.5V batteries
    connected directly (no power switch) to the V+
    and V- terminals. With a total current drain of
    g 2.8 /lA the quiescent power dissipation of the
    > circuit is 8.4 /lW. This is low enough to have no
    ~ 1,ODO
    r::-...
    significant effect on the shelf life of most batteries.
    ~ Potentiometer R" provides a means for matching
    the gains of A, and A2 to achieve maximum DC
    common mode rejection ratio CMRR. With R"
    '00 adjusted to its null point for DC common mode
    100k 5M
    rejection the small AC CM R R trimmer capacitor
    C, will normally give an additional 10 to 20 dB
    FIGURE 14. Pulse Frequency vs R2 of CM R R over the operating frequency range.
    Since C, actually balances wiring capacitance
    rather than amplifier frequency characteristics, it
    the polarity of the generator output providing a may be necessary to attach it to Pin 2 of either A,
    series of negative going pulses dropping from +5V or A2 as required. Figure 16 shows the variation of
    to the saturation voltage of Q,. CMRR (referred to the input) with frequency for
    The change in output frequency as a function of
    supply voltage is less than ±4% for a V+ change of '00
    from 4 V to 1OV. This stability of frequency versus
    80 11111111
    supply voltage is due to the fact that the reference
    ; I'CMRR
    voltage Vr and the drive voltage for the capacitor
    60
    are both direct functions of V+.
    The power dissipation of the free running multi-
    '"'"
    ~
    c
    z 40
    It
    "
    vibrator is 300 /lW and the power dissipation of
    the buffer circuit is approximately 5.8 mW.
    .l
    20 "
    Xl00 INSTRUMENTATION AMPLIFIER
    '0 '00 '.000 '0.000
    The instrumentation amplifier circuit shown in FREQUENCY (Hz)
    Figure 15 has a full differential input center
    FIGURE 16. AV and CMRR vs Frequency
    tapped to ground. With the bias current set at
    approximately 0.1 /lA, the impedance looking
    into either V 1N , or V1N2 is 100 MS1 with respect this configuration. Since the circuit applies a gain
    to ground, and the input bias current at either of 100 or 40 dB to an input signal, the actual
    terminal is 0.2 nA. The two non-inverting input observed rejection ratio is the difference between
    the CM R R curve and Av curve. For example, a
    60 Hz common mode signal will be attenuated by
    67 dB minus 40 dB or 27 dB for an actual rejec-
    ' .. tion ratio of VINIVO equal to 22.4.
    The maximum peak-to-peak output signal into a
    100 kS1 load resistor is approximately 1.8V. With
    """ no input signal, the noise seen at the output is
    approximately 0.8 mV RMS or 8 /lV RMS referred to
    the input. When doing power dissipation measure-
    ments on this circuit, it should be kept in mind
    that even a 1 MS1 oscilloscope probe placed be-
    tween +1.5V and -1.5V will more than double
    the power drawn from the batteries.

    5V REGULATOR FOR CMOS LOGIC CIRCUITS


    The ideal regulator for low power CMOS logic
    Naill Q","".nl'D·la~w
    "QIIZR2,Rl,A',RS,A&,.ndAl"'I%,p".", elements should dissipate essentially no power
    NQuJ Rll.ndCl."f.'IIC.ndACu .... o..... d.", .. bonod,"'un •• 1I
    when the CMOS devices are running at low fre-
    quencies, but be capable of delivering full output
    FIGURE 15. X 100 Instrumentation Amplifier
    power on demand when the CMOS devices are
    running in the 0.1 MHz to 10 MHz region. With a
    stages A, and A2 apply a gain of 10 to the input 10V input voltage, the regulator shown in Fig-
    signal, and the differential output stage applies an ure 17 will dissipate 350 /lW in the stand-by mode
    additional gain of -10 for a net amplifier gain of but will deliver up to 50 mA of continuous load
    -100: current when required.
    The circuit is basically a boosted output voltage-
    (15)
    follower referenced to a low current zener diode.

    AN71-7
    The voltage divider consisting of R2 and R3 pro· reverse breakdown voltage. A National Semicon·
    vides a 5V tap voltage from the 6.5V reference ductor process 25 small signal NPN transistor
    diode to determine the regulator output. Since a sorted to a 2N registration such as 2N3252 has a
    standard 6.5V zener diode does not exhibit good BV EBo at 10 fJ.A specified as 5.5V minimum,
    regulation in the 2 fJ.A to 60 fJ.A reverse current 6.5V typical, and 7.0V maximum. Using a diode
    region, O 2 must be a special device. An NPN connected 2N3252 as a reference, the regulator
    output voltage changed 78 mV in response to an
    8V to 36V change in the input voltage. This test
    :,:-<>"_'_.-___.....-\ZN~~'I O"MEATSINK
    ."
    dO ....
    was done under both no load and full load condi·
    tions and represents a line regulation of better
    ~ U than 1.6%.

    " A load change from 10 fJ.A to 50 mA caused a

    ~
    1 mV change in output voltage giving a load regu-
    "
    510K lation value of .05%. When operating the regulator
    at load currents of less than 25 mA, no heat sink
    ,e" is required for 0,. For load currents in excess of
    50 mA, 0, should be replaced by a Darlington
    '., pair with the 2N3019 acting as a driver for a higher
    '"" - ......- ......'"- - - - 4 -......-0
    ,.. <>-<>---...... power device such as a 2N3054.

    FIGURE 17.350 fJ.W Quiescent Drain 5 Volt Regulator


    REFERENCES
    transistor with its collector and base terminals Millman, J. and Hawkias, C.C.: "Electronic De-
    grounded and its emitter tied to the junction of vice and Circuits," pp. 465-466, McGraw-Hili Book
    R, and R2 exhibits a well-controlled base emitter Company, New York, 1967.

    AN71-8
    l>
    2
    T.M. Frederiksen, W.M. Howard, R.S. Sleeth ~
    September 1972 N

    -I
    :::t
    m
    THE LM3900 - A NEW CURRENT-DIFFERENCING
    r-
    QUAD OF ± INPUT AMPLIFIERS s:
    W
    PREFACE CD
    o
    With all the existing literature on "how to apply op amps" why should another application note be o
    produced on this subject? There are two answers to this question; 1) the LM3900 operates in quite I
    an unusual manner (compared to a conventional op amp) and therefore needs some explanation to l>
    familiarize a new user with this product. and 2} the standard op amp applications assume a split power
    2
    supply (±.15 Voc ) is available and our emphasis here is directed toward circuits for lower cost single m
    power supply control systems. Some of these circuits are simply "re-biased" versions of conventional
    handbook circuits but many are new approaches which are made possible by some of the unique ~
    features of the LM3900. C')
    C
    TABLE OF CONTENTS ::J:I
    ::J:I
    m
    SUBJECT PAGE
    2
    SECTION -I
    ,
    1.0 An Introduction to the New "Norton" Amplifier ............................... AN72·1 c
    ~
    1.1 Basic Gain Stage .................................................... AN72·1 ~
    1.2 Obtaining a Non-inverting Input Function ............................. AN72·2 m
    1.3 The Complete Single-supply Amplifier ............................... AN72·2 ::J:I
    m
    2.0 Introduction to Applications of the LM3900 ................................... AN 72-4 2
    C')
    3.0 Designing AC Amplifiers .................................................... AN72·6 Z
    C)
    3.1 Single Power Supply Biasing ......................................... AN72-6
    3.2 A Non-inverting Amplifier ............................................ AN72·6 oc
    3.3 "N VBE ' Biasing ...................................................... AN72-7
    3.4 Biasing Using a Negative Supply ..................................... AN72-7 »
    3.5 Obtaining High Input Impedance and High Gain ...................... AN72-7 c
    3.6 An Amplifier with a DC Gain Control ................................. AN72-7
    3.7 A Line-receiver Amplifier ............................................. AN72·8 o
    ~

    4.0 Designing DC Amplifiers .................................................... AN72·8 1+


    4.1 Using Common-mode Biasing for V1N = 0 Voc ......................... AN72-8 Z
    4.2 Adding an Output Diode for Vo = 0 Voc .............................. AN72-9 "tI
    4.3 A DC Coupled Power Amplifier {IL:::3 Amps} ......................... AN72·9 C
    4.4 Ground Referencing a Differential Voltage ............................ AN72-9 -I
    4.5 A Unity Gain Buffer Amplifier ........................................ AN72·10
    l>
    5.0 Designing Voltage Regulators ............................................... AN72·10 :s:"tI
    r-
    5.1 Reducing the Input-output Voltage ................................... AN72·11
    ~
    5.2 Providing High Input Voltage Protection .............................. AN72·11
    5.3 High Input Voltage Protection and Low (VIN - VOUT ) . . . • • . . . . . . . . . . . . . AN72·12 m
    5.4 Reducing Input Voltage Dependence and Adding ::J:I
    CJ)
    Short-circuit Protection .............................................. AN72·12

    6.0 Designing RC Active Filters ................................................. AN72-13

    6.1 Biasing the Amplifiers ............................................... AN72·13


    6.2 A High Pass Active Filter ............................................. AN72·14
    6.3 A Low Pass Active Filter ............................................. AN72·14
    6.4 A Single-amplifier Bandpass Active Filter ............................. AN72·15
    6.5 A Two-amplifier Bandpass Active Filter ............................... AN72·16

    AN72·i
    TABLE OF CONTENTS (Con't)
    SECTION SUBJECT PAGE

    6.0 Designing RC Active Filters (continued)

    6.6 A Three-amplifier Bandpass Active Filter ............................ AN72-17


    6.7 Conclusions ....................................................... AN72-18

    7.0 Designing Waveform Generators ........................................... AN72·18

    7.1 Sinewave Oscillator ................................................ AN72-19


    7.2 Squarewave Generator ............................................. AN72·19
    7.3 Pulse Generator ................................................... AN72·20
    7.4 Triangle Waveform Generator ...................................... AN72·21
    7.5 Sawtooth Waveform Generator ..................................... AN72·22
    7.5.1 Generating a Very Slow Sawtooth Waveform ................... AN72·22
    7.6 Staircase Waveform Generators .................................... AN72·23
    7.7 A Pulse Counter and a Voltage Variable Pulse Counter .............. AN72·23
    7.8 An Up-down Staircase Waveform Generator ........................ AN72·24

    B.O Designing Phase-locked Loops and Voltage


    Controlled Oscillators ..................................................... AN72·24

    8.1 Voltage Controlled Oscillators (VCO) ............................... AN72·24


    8.2 Phase Comparator ................................................. AN72·25
    8.3 A Complete Phase-locked Loop .................................... AN72-26
    8.4 Conclusions ....................................................... AN72-26

    9.0 Designing Digital and Switching Circuits ............... , ................... AN72-26

    9.1 An "OR" Gate........................................................ AN72.26


    9.2 An "AND" Gate ................•................................... AN72-27
    9.3 A Bi-stable Multivibrator ........................................... AN72.27
    9.4 Trigger Flip Flops ................................................. AN72-27
    9.5 Monostable Multivibrators (One-shots) ............................. AN72.27
    9.5.1 A Two-amplifier One-shot ..................................... AN72-28
    9.5.2 A Combination One-shot/Comparator Circuit ................... AN72-28
    9.5.3 A One-amplifier One-shot (Positive Pulse) ...................... AN72-28
    9.5.4 A One-amplifier One-shot (Negative Pulse) ..................... AN72-29
    9.6 Comparators ...................................................... AN72-29
    9.6.1 A Comparator for Positive Input Voltages ....................... AN72-29
    9.6.2 A Comparator for Negative Input Voltages ...................... AN72-29
    9.6.3 A Power Comparator .......................................... AN72.29
    9.6.4 A More Precise Comparator ................................... AN72.29
    9.7 Schmitt-Triggers .................................................. AN72.30

    10.0 Some Special Circuit Applications ......................................... AN72·30

    10.1 Current Sources and Sinks ........................................ AN72-30


    10.1.1 A Fixed Current Source ....................................... AN72-30
    10.1.2 A Voltage Variable Current Source ............................. AN72·31
    10.1.3 A Fixed Current Sink .......................................... AN72·31
    10.1.4 A Voltage Variable Current Sink ............................... AN72·31
    10.2 Operation From ±15 VocPower Supplies ............................ AN72·31
    10.2.1 An AC Amplifier Operating with±15 VocPower
    Supplies ...................................................... AN72-32
    10.2.2 A DC Amplifier Operating with ±15 VocPower
    Supplies ...................................................... AN72-32
    10.3 Tachometers ...................................................... AN72-32
    10.3.1 A Basic Tachometer ........................................... AN72-32
    10.3.2 Extending VOUT (Minimum) to Ground ......................... AN72·33
    10.3.3 A Frequency Doubling Tachometer ............................ AN72·33
    10.4 A Squaring Amplifier .............................................. AN72·33
    10.5 A Differentiator .................................................... AN72-34
    10.6 A Difference Integrator ............................................ AN72-34

    AN72·JJ
    TABLE OF CONTENTS (Can't)
    SECTION SUBJECT PAGE
    10.0 Some Special Circuit Applications (continued)
    10.7 A Low Drift Sample and Hold Circuit ............................... AN72·34
    10.7.1 Reducing the "Effective" Input Biasing Current ................. AN72·34
    10.7.2 A Low Drift Ramp and Hold ................................... AN72·34
    10.7.3 Sample-hold and Compare with New +VIN ..................... AN72·35
    10.8 Audio Mixer or Channel Selector ................................... AN72·35
    10.9 A Low Frequency Mixer ........................................... AN72·35
    10.10 A Peak Detector ................................................... AN72·36
    10.11 Power Circuits .................................................... AN72·36
    10.11.1 Lamp and/or Relay Drivers (S30 mAl .......................... AN72·36
    10.11.2 Lamp and/or Relay Drivers (S300 mAl ......................... AN72·36
    10.11.3 Positive Feedback Oscillators ................................. AN72·37
    10.12 High Voltage Operation ........................................... AN72·37
    10.12.1 A High Voltage Inverting Amplifier ............................ AN72·37
    10.12.2 A High Voltage Non-inverting Amplifier ....................... AN72·37
    10.12.3 A Line Operated Audio Amplifier ............................. AN72·38
    10.13 A Dual-channel Class-A Driver for Auto Radios .................... AN72.38
    10.14 Temperature Sensing ............................................. AN72.38
    10.15 A "Programmable Unijunction" .................................... AN72.39
    10.16 Adding a Differential Input Stage .................................. AN72.39

    LIST OF ILLUSTRATIONS
    FIGURE
    NUMBER TITLE PAGE

    1 Basic Gain Stage ............................................................. AN72·1


    2 Adding a PNP Transistor to the Basic Gain Stage ............................... AN72·2
    3 Adding a Current Mirror to Achieve a Non-inverting Input ....................... AN72·2
    4 The Amplifier Stage ........................................................... AN72·3
    5 Open-loop Gain Characteristics ............................................... AN 72·3
    6 Schematic Diagram of the LM3900 ............................................. AN72A
    7 An Equivalent Circuit of a Standard IC Op Amp ................................ AN72A
    8 An Equivalent Circuit of the "Norton" Amplifier ................................. AN72·4
    9 Applying the LM3900 Equivalent Circuit ........................................ AN72·5
    10 Biasing Equivalent Circuit ..................................................... AN72·5
    11 AC Equivalent Circuit ......................................................... AN72·6
    12 Inverting AC Amplifier Using Single-supply Biasing ............................. AN72·6
    13 Non-inverting AC Amplifier Using Voltage Reference Biasing .................... AN72·6
    14 Inverting AC Amplifier Using N VeE Biasing ................................... AN72·7
    15 Negative Supply Biasing ...................................................... AN72·7
    16 A High ZINHigh Gain Inverting AC Amplifier ................................... AN72·7
    17 An Amplifier with a DC Gain Control ........................................... AN72·8
    18 A Line-receiver Amplifier ...................................................... AN72·8
    19 A DC Amplifier Employing Common-mode Biasing ............................ AN72·8
    20 An Ideal Circuit Model of a DC Amplifier with Zero Input Voltage ............... AN72·8
    21 A Non-inverting DC Amplifier with Zero Volts Output for Zero Volts Input ....... AN72·9
    22 Voltage Transfer Function for a DC Amplifier with a Voltage Gain of 10 .......... AN72·9
    23 A DC Power Amplifier ......................................................... AN72·9
    24 Ground Referencing a Differential Input DC Voltage ............................ AN72·9
    25 A Network to Invert and to Ground Reference a Negative DC
    Differential Input Voltage ...................................................... AN72·10
    26 A Unity-gain DC Buffer Amplifier .............................................. AN72·10
    27 Simple Voltage Regulators .................................................... AN72·11
    28 Reducing (VI N - VauT ) ........................................................ AN72·11
    29 High VIN Protection and Self-regulation ........................................ AN72·12
    30 A High VIN Protected, Low (VIN - VOUT ) Regulator ............................. AN72·12
    31 RedUCing VIN Dependence .................................................... AN72·12
    32 Adding Short-circuit Current Limiting .......................................... AN72·12
    33 BiaSing Considerations ........................................................ AN72·13
    34 A High Pass Active Filter ...................................................... AN72·14
    35 A Low Pass Active Filter ....................................................... AN72·14
    36 Biasing the Low Pass Filter .................................................... AN72·15

    AN72·iii
    LIST OF ILLUSTRATIONS (Con't)

    FIGURE
    NUMBER TITLE PAGE
    37 Biasing Equivalent Circuit ..................................................... AN72-15
    38 A One Op amp Bandpass Filter ............................................... AN72-16
    39 A Two Op amp Bandpass Filter ............................................... AN72-16
    40 The "Bi-quad" RC Active Bandpass Filter ...................................... AN72-16
    41 A Sinewave Oscillator ......................................................... AN72-19
    42 A Squarewave Oscillator ...................................................... AN72-19
    43 A Pulse Generator ............................................................ AN72-20
    44 A Triangle Waveform Generator ............................................... AN72-21
    45 Gated Sawtooth Generators ................................................... AN 72-22
    46 Generating Very Slow Sawtooth Waveforms .................................... AN72-22
    47 Pumping the Staircase Via Input Differentiator .................................. AN72-23
    48 A Free Running Staircase Generator ........................................... AN72-23
    49 An Up-down Staircase Generator .............................................. AN72-24
    50 A Voltage Controlled Oscillator ................................................ AN72-24
    51 Adding Input Common-mode Biasing Resistors ................................. AN72-25
    52 Reducing Temperature Drift ................................................... AN72-25
    53 Improving Mark/Space Ratio .................................................. AN72-25
    54 Phase Comparator ............................................................ AN72-26
    55 A Phase-locked Loop ......................................................... AN72-26
    56 An "OR" Gate ................................................................. AN72-26
    57 An "AND" Gate ............................................................... AN72-27
    58 A Large Fan-in "AND" Gate .................................................... AN72-27
    59 A Bi-stable Multivibrator ....................................................... AN72-27
    60 A Trigger Flip Flop ............................................................ AN72-27
    61 A Two-amplifier Trigger Flip Flop .............................................. AN72-27
    62 A One-shot Multivibrator ...................................................... AN72-28
    63 A One-shot Multivibrator with an Input Comparator ............................. AN72-28
    64 A One-amplifier One-shot (Positive Output) .................................... AN72-28
    65 A One-amplifier One-shot (Negative Output) ................................... AN72-29
    66 An Inverting Voltage Comparator .............................................. AN72-29
    67 A Non-inverting Low-voltage Comparator ...................................... AN72-29
    68 A Non-inverting Power Comparator ............................................ AN72-29
    69 A More Precise Comparator ................................................... AN72-30
    70 Schmitt-Triggers .............................................................. AN72-30
    71 Fixed Current Sources ........................................................ AN72-31
    72 A Voltage Controlled Current Source .......................................... AN72-31
    73 Fixed Current Sinks ........................................................... AN72-31
    74 A Voltage Controlled Current Sink ............................................. AN72-31
    75 An AC Amplifier Operating with ±15 Voc··················· ..................... AN72-32
    76 DC Biasing for ±15 VocOperation .............................................. AN72-32
    77 A DC Amplifier Operating with ±15 Voc ......................................... AN72-32
    78 A Basic Tachometer .......................................................... AN72-33
    79 Adding Biasing to Provide Vo = 0 Voc· .......................................... AN72-33
    80 A Frequency Doubling Tachometer ............................... : ............ AN72-33
    81 A Squaring Amplifier with Hysteresis ........................................... AN72-33
    82 .A Differentiator Circuit ........................................................ AN72-34
    83 A Difference Integrator ........................................................ AN72-34
    84 Reducing Ie "Effective" to Zero ................................................ AN72-34
    85 A Low-drift Ramp and Hold Circuit ............................................ AN72-35
    86 Sample-hold and Compare with New +VIN ...................................... AN72-35
    87 Audio Mixing or Selection ..................................................... AN72-35
    88 A Low Frequency Mixer ....................................................... AN72-36
    89 A Peak Detector .............................................................. AN72-36
    90 Sinking 20 to 30 mA Loads .................................................... AN72-36
    91 Boosting to 300 mA Loads .................................................... AN72-37
    92 Positive Feedback Power Oscillators ........................................... AN72-37
    93 A High Voltage Inverting Amplifier ............................................. AN72-37
    94 A High Voltage Non-inverting Amplifier ........................................ AN72-37
    95 A Line Operated Audio Amplifier .............................................. AN72-38
    96 A Dual Channel IC Driver for Class A Car Radios ............................... AN72-38
    97 T~~perature Sensing ...... : . ',: ................................................. AN72-38
    98 A Programmable Un1lunctlon ................................................ AN72-39
    99 Adding a Differential Input Stage .............................................. AN72-39

    AN72-iv
    THE LM3900-A NEW CURRENT-DIFFERENCING
    QUAD OF ±INPUT AMPLIFIERS

    1.0 AN INTRODUCTION TO THE NEW


    "NORTON" AMPLI FI ER 1.1 Basic Gain Stage

    The LM3900 represents a departure from con- The gain stage is basically a single common-
    ventional amplifier designs. Instead of using emitter amplifier. By making use of current
    a standard transistor differential amplifier at source loads, a large voltage gain has been
    the input, the non-inverting input function has achieved which is very constant over temper-
    been achieved by making use of a "current- ature changes. The output voltage has a large
    mirror" to "mirror" the non-inverting input dynamic range, from essentially ground to one
    current about ground and then to extract this V BE less than the power supply voltage. The
    current from that which is entering the invert- output stage is biased class A for small signals
    ing input terminal. Whereas the conventional but converts to class B to increase the load
    op amp differences input voltages, this ampli- current which can be "absorbed" by the ampli-
    fier differences input currents and therefore fier under large signal conditions. Power sup-
    the name "Norton Amp" has been used to indi- ply curreni drain is essentially independent of
    cate this new type of operation. Many biasing the power supply voltage and ripple on the
    advantages are realized when operating with supply line is also rejected. A very small
    only a single power supply voltage. The fact input biasing current allows high impedance
    that currents can be passed between the input feedback elements to be used and even lower
    terminals allows some unusual applications. "effective" input biasing currents can be real-
    If external, large valued input resistors are used ized by using one of the amplifiers to supply
    (to conver.t from input voltages to input cur- essentially all of the bias cu rrents for the
    rents) most of the standard op amp applications other amplifiers by making use of the "match-
    can be realized. ing" which exists between the 4 amplifiers
    which are on the same IC chip (see Figure 84).
    Many industrial electronic control systems are
    designed that operate off of only a single The simplest inverting amplifier is the common-
    power supply voltage. The conventional inte- emitter stage. If a current source is used in
    grated-circuit operational amplifier (IC op amp) place of a load resistor, a large open-loop
    is typically designed for split power supplies gain can be obtained, even at low power-supply
    (± 15 Voc ) and suffers from a poor output volt- voltages. This basic stage (Figure 1) is used
    age swing and a rather large minimum for the amplifier.
    common-mode input voltage range (approxi-
    mately + 2 Voc ) when used in a single power
    supply application. In addition, some of the
    performance characteristics of these op amps
    could be sacrificed-especially in favor of re-
    duced costs.
    v,
    To meet the needs of the designers of low-cost,
    single-power-supply control systems, a new v" n, + I,

    internally compensated amplifier has been


    deSigned that operates over a power supply
    voltage range of +4 Voc to 36 Voc with small
    changes in performance characteristics and FIGURE 1. Basic Gain Stage
    provides an output peak-to-peak voltage swing
    that is only 1V less than the magnitude of
    the power supply voltage. Four of these ampli- All of the voltage gain is provided by the gain
    fiers have been fabricated on a single chip and transistor, Q2' and an output emitter-follower
    are provided in the standard 14-pin dual-in-line transistor, Q" serves to isolate the load imped-
    package. ance from the high impedance that exists at the
    collector of the gain transistor, Q2' Closed-loop
    The cost, application and performance advan- stability is guaranteed by an on-chip capacitor
    tages of this new quad amplifier will guaran- C=3 pF, which provides the single dominant
    tee it a place in many single power supply open-loop pole. The output emitter-follower
    electronic systems. Many of the "housekeep- is biased for class-A operation by the current
    ing" applications which are now handled by source 12 ,
    standard IC op amps can also be handled by
    this "Norton" amplifier operating off the This basic stage can provide an adequate open-
    existing ± 15 V oc power supplies. loop voltage gain (70 dB) and has the desired

    AN72-1
    large output voltage swing capability. A dis- voltage then depends upon the difference (or
    advantage of this circuit is that the DC input error) between the two input voltages. An
    current, liN' is large; as it is essentially equal input common-mode voltage range specifica-
    to the maximum output current, lOUT , divided tion exists and, basically, input voltages are
    by ~ 2. For example, for an output current compared.
    capability of 10 mA the input current would be
    at least 1 tJA (assuming ~2 = 104 ). It would be For circuit simplicity, and ease of application
    desirable to further reduce this by adding an in single power supply systems, a non-inverting
    additional transistor to achieve an overall ~ 3 input can be provided by adding a standard IC
    reduction. Unfortunately, if a transistor is "current-mirror" circuit directly across the in-
    added at the output (by making 0, a Darling- verting input terminal, as shown in Figure 3.
    ton pair) the peak-to-peak output voltage swing
    would be somewhat reduced and if O 2 were
    made a Darlington pair the DC input voltage
    level would be undesirably doubled.

    To overcome these problems, a lateral PNP


    transistor has been added as shown in Fig- -'-'-
    ,-,o-+--_p--{
    ure 2. This connection neither reduces the
    output voltage swing nor raises the DC input
    voltage, but does provide the additional gain
    that was needed to reduce the input current. -"-

    "----+--oYo
    FIGURE 3. Adding a Current Mirror to Achieve a Non·
    inverting Input
    v,"

    This operates in the current mode as now


    input currents are compared or differenced
    FIGURE 2. Adding a PNP Transistor to the Basic Gain (this can be thought of as a Norton differential
    Stage amplifier). There is essentially no input
    common-mode voltage range directly at the
    input terminals (as both inputs will bias at one
    Notice that the collector of this PNP transistor, diode drop above ground) but if the input volt-
    0" is connected directly to the output terminal. ages are converted to currents (by use of input
    This "bootstraps" the output impedance of 0, resistors), there is then no limit to the common-
    and therefore reduces the loading at the high- mode input voltage range. This is especially
    impedance collector of the gain transistor, 0 3 , useful in high-voltage comparator applications.
    By making use of the input resistors, to convert
    In addition, the collector-base junction of the input voltages to input currents, all of the
    PNP transistor becomes forward biased under a standard op amp applications can be realized.
    large-signal negative output voltage swing con- Many additional applications are easily
    dition. The design of this device has allowed achieved, especially 'when operating with only
    0, to convert to a vertical PNP transistor dur- a single power supply voltage. This results
    ing this operating mode which causes the out- from the built-in voltage biasing that exists
    put to change from the class A bias to a class at both inputs (each input biases at + V BE )
    B output stage. This allows the amplifier to and additional resistors are not required to pro-
    sink more current than that provided by the vide a suitable common-mode input DC bias-
    current source, 12 , (1.3 mAl under large signal ing voltage level. Further, input summing can
    conditions. be performed at the relatively low impedance
    level of the input diode of the current-mirror
    circuit.
    1.2 Obtaining a Non·inverting Input Function
    1.3 The Complete Single·supply Amplifier
    The circuit of Figure 2 has only the invert-
    ing input. A general purpose amplifier requires The circuit schematic for a single amplifier
    two input terminals to obtain both an inverting stage is shown in Figure 4a). Due to the circuit
    and a non-inverting input. In conventional simplicity, four of these amplifiers can be fabri-
    op amp designs, an input differential amplifier cated on a single chip. One common biasing
    provides these required inputs. The output circuit is used for all of the individual amplifiers.

    AN72·2
    A new symbol for this "Norton" amplifier is The performance characteristics of each ampli-
    shown in Figure 4b). This is recommended to fier stage are summarized below:
    avoid using the standard op amp symbol as the
    basic operation is different. The current source Power-supply voltage range ..... 4 to 36Vocor
    symbol between the inputs implies this new ±2 to ±18 Voc
    current-mode of operation. In addition, it Bias current drain per amplifier
    stage ........................... 1.3 mAoc
    Open loop:
    v' Voltage gain (R L = 10k) .............. 70 dB
    Unity-gain frequency .............. 2.5 MHz
    Phase margin .................. 40 degrees
    Input resistance ..................... 1 M~
    Output resistance .................... 8 k~
    Output voltage swing .......... (Vee - 1) Vpp
    Input bias current .................. 30 nAoc
    Slew rate ........................... 0.5V/ fJ-s
    0 - - -....-0 OUTPUT
    As the bias currents are all derived from diode
    forward voltage drops, there is only a small
    change in bias current magnitude as the power-
    supply voltage is varied. The open-loop gain
    H
    INPUT 0------,-...., changes only slightly over the complete power
    supply voltage range and is essentially inde-
    pendent of temperature changes. The open-
    INPUT 0--<1>---1 loop frequency response is compared with the
    CRI "741" op amp in Figure 5. The higher unity-
    gain crossover frequency is seen to provide an
    additional 10 dB of gain for all frequencies
    (al ClrellltSl:liemiltlc
    greater than 1 kHz.

    120
    -\,410PAMP
    ~ 100
    I
    "~ 80
    \,. I
    c LMJ~OO
    ~ 60

    ~
    z
    c 40
    =loknFo~
    ~I -
    j 20 - RL
    BOTI" AMr"Fll"'
    (b) Nw.r "NORTON" Amplifier Symbol

    1 10 100 Ik 10k 10k 1M 10M


    FIGURE 4. The Amplifier Stage f - Frequencv.(Hz)

    FIGURE 5. Open-loop Gain Characteristics

    signifies that current is removed from the (-)


    input terminal. Also, the current arrow on the The complete schematic diagram of the
    (+) input lead is used to indicate that this LM3900 is shown in Figure 6. The one resis-
    functions as a current input. The use of this tor, R5 , establishes the power consumption of
    symbol is helpful in understanding the opera- the circuit as it controls the conduction of
    tion of the application circuits and also in doing transistor Q28' The emitter current of Q28 is
    additional design work with the LM3900. used to bias the NPN output class-A biasing
    current sources and the collector current of
    Q28 is the reference for the PNP current source
    The bias reference for the PNP current source,
    of each amplifier.
    Vp which biases Ql, is designed to cause the·
    upper current source (200 fJ-A) to change with
    temperature to give first order compensation The biasing circuit is initially "started" by
    for the f3 variations of the NPN output transis- Q20' Q 30 and CRa. After start-up is achieved,
    tor, Q3' The bias reference for the NPN "pull- Q 30 goes OFF and the current flow through
    down" current sink, Vn , (which biases Q7) is the reference diodes: CRs , CR 7 and CR8. is
    designed to stabilize this current (1.3 mAl to dependent only on VBe /(Ra + R 7 ). This guar-
    reduce the variation when the temperature is antees that the power supply current drain is
    changed. This provides a more constant pull- essentially independent of the magnitude of the
    down capability for the amplifier over the power supply voltage.
    temperature range. The transistor, Q4' pro-
    vides the class B action which exists under The input clamp for negative voltages is pro-
    large signal operating conditions. vided by the multi-emitter NPN transistor Q21'

    AN72-3
    FIGURE 6. Schematic Diagram of the LM3900

    One of the em itters of th is transistor goes to op amp (base currents). The output circuit is
    each of the input terminals. The reference modeled as an active voltage source which
    voltage for the base of Q 21 is provided by Rs depends upon the open-loop gain of the ampli-
    and R7 and is approximately Vee 12. fier, A v , and the difference which exists be-
    tween the input voltages, (V + - V-).

    f-I

    2.0 INTRODUCTION TO APPLICATIONS IN'UT~

    ~. !'"
    F
    OF THE LM3900
    OUT'UT

    Like the standard Ie op amp, the LM3900 has a


    wide range of applications. A new approach
    ('1 ::.(V•. VI
    'N'UT~
    must be taken to design circuits with this
    "Norton" amplifier and the object of this note is
    ~t !IB+
    to present a variety of useful circuits to indicate
    how conventional and unique new applications FIGURE 7. An Equivalent Circuit of a Standard IC
    can be designed-especially when operating Dp Amp
    with only a single power supply voltage.
    An equivalent circuit for the "Norton" ampli-
    To understand the operation of the LM3900 fier is shown in Figure 8. The (+) and (-)
    we will compare it with the more familiar inputs are both clamped by diodes to force
    standard Ie op amp. When operating on a them to be one-diode drop above ground-
    single power supply voltage, the minimum in- always! They are not free to move and the
    put common-mode voltage range of a standard "input common-mode voltage range" directly
    op amp limits the smallest value of voltage at these input terminals is very small-a few
    which can be applied to both inputs and still hundred mV centered about 0.5 Voc. This is
    have the amplifier respond to a differential
    input signal. In addition, the output voltage
    will not swing completely from ground to the
    power supply voltage. The output voltage
    depends upon the difference between the input
    H
    INPUT O-~~.....--,

    V' F.
    'V A. v-
    OUT'UT

    voltages and a bias current must be supplied ("


    to both inputs. A simplified diagram of a 'N'UT~
    standard Ie op amp operating from a single ~ fVD+ t Alit

    power supply is shown in Figure 7. The (+) -::-


    and (-) inputs go only to current sources and
    therefore are free to be biased or operated at FIGURE B. An Equivalent Circuit of the "Norton""
    any voltage values which are within the input Amplifier
    common-mode voltage range. The current
    sources at the input terminals, le+ and le-, why external voltages must be first converted
    represent the bias currents which must be sup- to currents (using resistors) before being ap-
    plied to both of the input transistors of the plied to the inputs-and is the basis for the

    AN72·4
    current-mode (or Norton) type of operation. If (2) is substituted into (1)
    With external input resistors-there is no limit
    to the "input common-mode voltage range".
    The diode shown across the (+) input actually
    (3)
    exists as a diode in the circuit and the diode
    across the (-) input is used to model the base-
    emitter junction of the transistor which exists
    which is an exact expression for Vo'
    at this input.

    Only the (-) input must be supplied with a


    DC biasing current, 18 . The (+) input couples
    R2
    only to the (-) input and then to extract from
    this (-) input terminal the same current (AI'
    the mirror gain, IS approximately equal to 1)
    which is entered (by the external circuitry)
    into the (+) input terminal. This operation
    is described as a "current-mirror" as the cur-
    rent entering the (+) input is "mirrored" or
    "reflected" about ground and is then extracted
    from the (-) input. There is a maximum or
    near saturation value of current which the v'
    "mirror" at the (+) input can handle. This is (a) ATYPical B'iied Amplll,er

    listed on the data sheet as "maximum mirror


    current" and ranges from approximately 6 mA R2
    at 25° C to 3.8 mA at 70° C.

    This fact that the (+) input current modulates or


    effects the (-) input current causes this ampli-
    fier to pass currents between the input termi-
    nals and is the basis for many new application
    circuits-especially when operating with only a
    single power supply voltage.

    The output is modeled as an active voltage


    (b) UsmgthelMJ90DEqulwientCuclt,t
    source which also depends upon the open-loop
    voltage gain, A v , but only the (-) input voltage,
    V-. (not the differential input voltage). Finally, FIGURE 9. Applying the LM3900 Equivalent Circuit
    the output voltage of the LM3900 can swing
    from essentially ground (+90 mV) to within one
    V BE of the power supply voltage.

    As an example of the use of the equivalent


    circuit of the LM3900, the AC coupled invert-
    ing amplifier of Figure 9a will be analyzed.
    Figure 9b shows the complete equivalent cir-
    cuit which, for convenience, can be separated
    into a biasing equivalent circuit (Figure 10)
    and an AC equivalent circuit (Figure 11). From
    the biasing model of Figure 10 we find the
    output quiescent voltage, Vo ' is:

    FIGURE 10. Biasing Equivalent Circuit


    and

    (2)
    "Z

    where

    18 INPUT bias current 130 nA)

    and
    Power supply voltage. FIGURE 11. AC Equivalent Circuit

    ANn-s
    As the second term usually dominates (Vo » 3.1 Single Power Suply Biasing
    V o) and 1+ »Ie and V+»V o+ we can sim-
    The LM3900 can be biased in several different
    plify (3) to provide a more useful design
    relationship ways. The circuit in Figure 12 is a standard
    inverting AC amplifier which has been biased
    _
    Vo =
    R2
    R3 V+ • (4) ,.
    .2

    Using (4), if R3 = 2R2 we find


    vo
    (5)
    VODC·
    v'
    "'2
    which shows that the output is easily biased Ay !::! - t,
    to one-half of the power supply voltage by
    using V+ as a biasing reference at the (+) input.
    FIGURE 12. Inverting AC Amplifier Using Single-supply
    The AC equivalent circuit of Figure 11 is the Biasing
    same as that which would result if a standard
    IC op amp were used with the (+) input ground-
    from the same power supply which is used to
    ed. The closed-loop voltage gain Av CL' is given
    operate the amplifier. (The design of this am-
    by:
    plifier has been presented in the previous sec-
    (6)
    tion.) Notice that if AC ripple voltages are
    present on the V+ power supply line they will
    couple to the output with a "gain" of 1/2.
    To eliminate this, one source of ripple filtered
    If Av (open-loop» ~. voltage can be provided and then used for
    Rl
    many amplifiers. This is shown in the next
    The design procedure for an AC coupled invert-
    section.
    ing amplifier using the LM3900 is therefore to
    first select R1 , CIN ' R2, and Coas with a stand-
    ard IC op amp and then to simply add R3 =
    2R2 as a final biasing consideration. Other 3.2 A Non-inverting Amplifier
    biasing techniques are presented in the fol-
    The amplifier in Figure 13 shows both a non-
    lowing sections of this note. For the switching
    inverting AC amplifier and a second method for
    circuit applications, the biasing model of Fig-
    DC biasing. Once again the AC gain of the
    ure 10 is adequate to predict circuit operation.
    amplifier is set by the ratio of feedback resis-
    tor to input resistor. The small signal imped-
    Although the LM3900 has four independent
    ance of the diode at the (+) input should be
    amplifiers, the use of the label "\4LM3900"
    added to the value of Rl when calculating gain,
    will be shortened to simply "LM3900" for the
    as shown in Figure 13.
    application drawings contained in this note.
    .J
    1M

    3.0 DESIGNING AC AMPLIFIERS

    The LM3900 readily lends itself to use as an


    AC amplifier because the output can be biased
    c" R1
    to any desired DC level within the range of the lOOK

    ~
    output voltage swing and the AC gain is inde-
    pendent of the biasing network. In addition, R2
    1M
    the single power supply requirement makes the
    51'
    LM3900 attractive for any low frequency gain v· o--'VII'r.....--.---<>-v-,,-,.. !~P~~:I~:S
    application. For lowest noise performance, the Av~~
    (+) input should be grounded (Figure 9a) and 51' Rl + rd

    the output will then bias at +V eE . Although rd = O~:6 !!

    the LM3900 is not suitable as an ultra low noise VODe


    V·
    ="2
    tape pre-amp, it is useful in most other
    applications. The restriction to only shunt feed-
    back causes a small input impedance. Trans- FIGURE 13. Non-inverting AC Amplifier Using Voltage
    Reference Biasing
    ducers which can be loaded can operate with
    this low input impedance. The noise degrada-
    tion which would result from the use of a large By making R2 = R3, Vooc will be equal to the
    input resistor limits the usefulness where low reference voltage which is applied to the resis-
    noise and high input impedance are both tor R2. The filtered V+/2 reference shown can
    required. also be used for other amplifiers.

    ANn·6
    3.3 "N VBE" Biasing
    .z
    A third technique of output DC biasing is best
    described as the uN VBE ' method. This tech-
    nique is shown in Figure 14 and is most useful
    with inverting AC amplifier applications. The

    .2
    10M

    FIGURE 15. Negative Supply Biasing


    Vo

    3.5 Obtaining High Input Impedance and High


    Gain
    Vooc = VlIE (1 +~)
    Av ~ - ~ For the AC amplifiers which have been pre-
    sented. a designer is able to obtain either high
    FIGURE 14. Inverting AC Amplifier Using N VSE gain or high input impedance with very little
    Biasing difficulty. The application which requires both
    and still employs only one amplifier presents a
    input bias voltage (V BE) at the inverting input new problem. This can be achieved by the use
    establishes a current through resistor R3 to of a circuit· similar to the one shown in Fig-
    ground. This current must come from the out- ure 16. When the Av from the input to point A
    put of the amplifier. Therefore. Vo must rise
    RJ R4
    ·to a level which will cause this current to flow 1M 1M
    through R2. The bias voltage, Va' may be cal-
    culated from the ratio of R2 to R3 as follows: - I,

    co

    f
    When NVSE biasing is employed, values for re-
    sistors R, and R2 are first established and then
    resistor R3 is added to provide the desired DC
    output voltage.

    For a design example (Figure 14), a Z in = 1M


    and Av ~ 10 are required.
    .,.. Av "- ~
    1
    FIGURE 16. A High ZIN High Gain Inverting AC
    Select R, = 1M. Amplifier

    is unity (R, = R3), the Av of the complete


    Calculate R2 ~ AvR, = 10M. stage will be set by the voltage divider network
    composed of R4 , R s' and C 2. As the value of
    Rs is decreased, the Av of the stage will ap-
    To bias the output voltage at 7.5 Voc ' R3 is proach the AC open loop limit of the amplifier.
    found as: The insertion of ca{lacitor C 2 allows the DC
    bias to be controlled by the series combina-
    R2 10M tion of R3 and R4 with no effect from Rs.
    R
    3
    =
    Vo 1&.._ Therefore, R2 may be selected to obtain the
    -1 0.5 desired output DC biasing level using any of
    VBE
    the methods which have been discussed. The
    circuit in Figure 16 has an input impedance of
    or
    1M and a gain of 100.

    3.4 Biasing Using a Negative Supply 3.6 An Amplifier with a DC Gain Control

    If a negative power supply is available, the cir- A DC gain control can be added to an ampli-
    cuit of Figure 15 can be used. The DC biasing fier as shown in Figure 17. The output of the
    current, I, is established by the negative supply amplifier is kept from being driven to satura-
    voltage via R3 and provides a very stable out- tion as the DC gain control is varied by pro-
    put quiescent point for the amplifier. viding a minimum biasing current via R 3. For

    AN72-7
    v' the problem becomes one of determining what
    ••
    1.5M type of network is necessary to provide an
    output voltage (Vo ) equal to zero when the
    input voltage (VIN ) is equal to zero. (See
    also section 10.16, "adding a Differential Input
    Stage").

    We will start with a careful evaluation of what

    "f"
    actually takes place at the amplifier inputs.
    The mirror circuit demands that the current
    10K flowing into the positive input (+) be equaled by
    a current flowing into the negative input (-).
    DC GAIN
    CONTROL
    {O ..... 'OVoci
    .,
    'K
    The difference between the cu rrent demanded
    and the current provided by an external source
    must flow in the feedback circuit. The output
    voltage is then forced to seek the level required
    FIGURE 17. An Amplifier with a DC Gain Control to cause this amount of current to flow. If, in
    the steady state condition Vo = VIN = 0, the
    amplifier will operate in the desired manner.
    maximum gain, CR 2 is OFF and both the cur- This condition can be established by the use
    rent through R2 and R3 enter the (+) input and of common-mode biasing at the inputs.
    cause the output of the amplifier to bias at ap-
    proximately 0.6 V+. For minimum gain, CR 2
    4.1 Using Common-mode Biasing for VI N =
    is ON and only the current through R3 enters
    the (+) input to bias the output at approxi- o VDC
    mately 0.3 V+. The proper output bias for large
    Common-mode biasing is achieved by placing
    output signal accomodation is provided for the
    equal resistors between the amplifier input
    maximum gain situation. The DC gain control
    terminals and the supply voltage (v+), as
    input ranges from OVoc for minimum gain to
    shown in Figure 19. When VIN is set to 0 volts
    less than 10Voc for maximum gain.
    v' Vo ~ VIN

    3.7 A Line-receiver Amplifier Av = ~

    A line-receiver amplifier is shown in Figure 18.


    The use of both inputs cancels out common- .2
    .3 ~ 13 .4
    ~" .,
    mode signals. The line is terminated by RLINE
    and the larger input impedance of the amplifier
    will not effect this matched loading.

    .,
    ,,,. ., I
    v,.o-JIA/Ir--1.----+I
    -I'
    ~
    I

    .,
    -Ol!g
    Rl " R2
    R3=R4
    RS ~ RG
    I

    C2 i
    FIGURE 19. A DC Amplifier Emploving Common-
    mode Biasing
    FIGURE 18. A Line-receiver Amplifier
    the circuit can be modeled as shown in Fig-
    ure 20, where:
    4.0 DESIGNING DC AMPLIFIERS

    The design of DC amplifiers using the LM3900


    tends to be more difficult than the design of
    AC amplifiers. These difficulties occur when
    designing a DC amplifier which will operate
    from only a single power supply voltage and yet
    provide an output voltage which goes to zero and
    volts DC and also will accept input voltages of
    zero volts DC. To accomplish this, the inputs
    must be biased· into the linear region (+V BE)
    with DC input signals of zero volts and the out- Because the current mirror demands that the
    put must be modified if operation to actual two current sources be equal, the current in
    ground (and not V SAT ) is required. Therefore, the two equivalent resistors must be identical.

    AN72·8
    v' enough to avoid excessively loading the ampli-
    R3=R4 fier. The value of RL may be significantly
    ,+=1- reduced by replacing the diode with an NPN
    RJ
    •• Reql" Req2 transistor.
    O.5V D.SV
    ~r---~-----r----,

    200 f---+---:;j<----j

    FIGURE 20. An Ideal Circuit Model of a DC Amplifier


    100 f----:-i'---+----j
    with Zero Input Voltage

    If this is true, both R2 and Rs must have a


    voltage drop of 0.5 volt across them, which 10 20 JD

    forces Vo to go to Vo MIN (V SAT ). VIN (mV)

    FIGURE 22. Voltage Transfer Function for a DC


    Amplifier with a Voltage Gain of 10
    4.2 Adding an Output Diode for Vo = 0 VDC
    4.3 A DC Coupled Power Amplifier IIL:5.
    For many applications a Vo MIN' of 100 mV may 3 Amps)
    not be acceptable. To overcome this problem
    a diode can be added between the output of the The LM3900 may be used as a power amplifier
    amplifier and the output terminal (Figure 21). by the addition of a Darl i ngton pai r at the
    output. The circuit shown in Figure 23 can
    deliver in excess of 3 amps to the load when
    OFFSETAIlJ the transistors are properly mounted on heat
    R1 sinks.
    R2
    15M
    250K
    "'
    15M R4
    1M
    v'

    "'
    lOOK

    v,"

    R6
    lOOK
    R,
    10K
    1
    C2
    l(1pF
    FIGURE 21. A Non·inverting DC Amplifier with Zero ~----~~----.-¢~
    R5
    Volts Output for Zero Volts Input 1M
    R,

    The function of the diode is to provide a DC FIGURE 23. A DC Power Amplifier


    level shift which will allow Vo to go to ground.
    With a load impedance (Rd connected,
    Vo becomes a function of the voltage divider 4.4 Ground Referencing a Differential Voltage
    formed by the series connection of R4 and R L .
    The circuit in Figure 24 employs the LM3900 to
    0.5 RL ground reference a DC differential input volt-
    IfR4 = 100RL' then V OMIN = age. Current 11 is larger than current 13 by a
    101 RI

    orV OMIN ~5mVDC'


    R1
    10M
    An offset voltage adjustment can be added as
    shown (R 1 ) to adjust Vo to OVDC with VIN =
    o Voc' 1
    The voltage transfer functions for the Circuit in
    Figure 21, both with and without the diode, are
    shown in Figure 22. While the diode greatly
    l v,o--"""""'-+--+I
    improves the operation around 0 volts, the
    voltage drop across the diode will reduce the R,
    10K
    peak output voltage swing of the stage by ap-
    proximately 0.5 volt.
    When using a DC amplifier similar to the one in FIGURE 24. Ground Referencing a Differential Input
    Figure 21, the load impedance should be large DC Voltage

    AN72·9
    factor proportional to the differential voltage, v'
    VR' The currents labeled on Figure 24 are given
    by:
    R1 R1
    l.SM 1.5M R3
    10M

    R4
    10M
    v, CR1
    lN914 Vo = VA

    R5
    (VI-rJ;1 10M
    I = v, R7 R,
    3
    R3 R6
    10M VR = V2 - VI
    -=-
    V a -¢
    and I4 =
    R4
    FIGURE 25. A Network to Invert and to Ground
    where Reference a Negative DC Differential
    ¢ == V BE at either input terminal of the LM3900. Input Voltage

    Since the input current mirror demands that voltage must be greater than one VeE but less
    1- = 1+; than the maximum output swing. Common-
    mode biasing can be added to extend V'N to
    and o Voc ' if desired.
    and
    R
    Therefore 1M
    14 = II - 12 - 13 '

    Substituting in from the above equation

    (VI - ¢)
    ----

    and as R, = R2 = R3 = R4 FIGURE 26, A Unity-gain DC Buffer Amplifier

    Va = (V, + V R - ¢I - (rJ;1 - VI + ¢ + rJ;

    5.0 DESIGNING VOLTAGE REGULATORS

    Many voltage regulators can be designed which


    make use of the basic amplifier of the LM3900.
    The resistors are kept large to minimize loading.
    The simplest is shown in Figure 27a where only
    With the 10 Mst resistors which are shown on
    a Zener diode and a resistor are added. The
    the figure, an error exists at small values of V,
    voltage at the (-) input (one VeE ~ 0.5 Voc )
    due to the input bias current at the (-) input.
    appears across R and therefore a resistor value
    For simplicity this has been neglected in the
    of 510st will cause approximately 1 mA of bias
    circuit description. Smaller R values reduce
    current to be drawn through the Zener. This
    the percentage error or the bias current can be
    biasing is used to reduce the noise output of
    supplied by an additional amplifier (see Sec-
    the Zener as the 30 nA input current is too
    tion 10.7.1).
    small for proper Zener biasing. To compen-
    sate for a positive temperature coefficient of
    For proper operation, the differential input volt- the Zener, an additional resistor can be added,
    age must be limited to be within the output R2, (Figure 27b) to introduce an arbitrary num-
    dynamic voltage range of the amplifier and the ber, N, of "effective" VeE drops into the ex-
    input voltage V2 must be greater than 1 volt. pression for the output voltage. The negative
    For example; if V2 = 1 volt, the input voltage temperature coefficient of these diodes will
    V, may vary over the range of 1 volt to -13 volts also be added to temperature compensate the
    when operating from a 15 volt supply. DC output voltage. For a larger output cur-
    Common-mode biasing may be added as shown rent, an emitter follower (Q, of Figure 27c) can
    in Figure 25 to allow both V, and V2 to be be added. This will multiply the 10 mA (max.)
    negative. output current of the LM3900 by the j3 of the
    added transistor. For example, a j3 = 30 will
    4.5 A Unity Gain Buffer Amplifier provide a max. load current of 300 mAo This
    added transistor also reduces the output imped-
    The buffer amplifier with a gain of one is the ance. An output frequency compensation
    simplest DC application for the LM3900. The capacitor is generally not required but may be
    voltage applied to the input (Figure 26) will be added, if desired, to reduce the output imped-
    reproduced at the output. However, the input ance at high frequencies.

    AN72·10
    5.1 Reducing the Input·output Voltage
    v,

    The use of an external PNP transistor will re-


    duce the required (V IN - VOUT) to a few tenths
    of a volt. This will depend on the saturation
    characteristics of the external transistor at the
    operating current level. The circuit, shown in
    Figure 28, uses the LM3900 to supply base drive
    tal B~slc CirCUlI to the PNP transistor. The resistors R, and R2
    are used to allow the output of the amplifier
    to turn OFF the PNP transistor. It is important
    that pin 14 of the LM3900 be tied to the +VIN
    - V"'Z +
    R2 line to allow this OFF control to properly oper-
    ate. Larger voltages are permissable (if the
    base-emitter junction of a, is prevented from
    entering a breakdown by a shunting diode. for
    example), but smaller voltages will not allow
    I' .,2..l the output of the amplifier to raise enough to
    give the OFF control.

    The resistor, R3 , is used to supply the required


    (b) TemperatureCompeflSatmg
    bias current for the amplifier and R4 is again
    used to bias the Zener diode. Due to a larger
    gain, a compensation capacitor, Co' is required.
    Temperature compensation could be added as
    was shown in Figure 27b.
    v,
    v'
    __----.....--..-0 Va : Vl~<l

    fc:lCartentBaostrng

    v'
    ..
    51'

    .2

    v, FIGURE 28. Reducing (VIN - V OUT )

    " 5.2 Providing High Input Voltage Protection

    (d) R~151Dg Vo Without Disturbing One of the four amplifiers can be used to regu-
    Temperature-Camp'"Allon
    late the supply line for the complete package
    FIGURE 27. Simple Voltage Regulators
    (pin 14), to provide protection against large
    input voltage conditions, and in addition, to
    supply current to an external load. This circuit
    is shown in Figure 29. The regulated output
    The DC output voltage can be increased and voltage is the sum of the Zener voltage, CR 2 ,
    still preserve the temperature compensation of and the VBE of the inverting input terminal.
    Figure 27b by ad,ding resistors RA and RB as Again, temperature compensation can be add-
    shown in Figure 27d. This also can be accom- ed as in Figure 27b. The second Zener, CR"
    plished without the added transistor, at. The is a low tolerance component which simply
    unregulated input voltage, which is applied to serves as a DC level shift to allow the output
    pin 14 of the LM3900 (and to the collector of voltage of the amplifier to control the con-
    a 1 , if used) must always exceed the regulated duction of the external transistor, a,. This
    DC output voltage by approximately 1V, when Zener voltage should be approximately one-
    the unit is not current boosted or approximately half of the CR 2 voltage to position the DC
    2V when the NPN current boosting transistor is output voltage level of the amplifier approx-
    added. imately in the center of the dynamic range.

    AN72·11
    resistors R3 and R6 provide gain (non-inverting)
    to allow establishing Vo at any desired voltage
    larger than Vz . Temperature compensation of
    either sign (±TC) can be obtained by shunting a
    resistor from either the (+) input to ground (to
    add + TC to Vol or from the (-) input to
    ~- .....----.-:---o Vo = Vzz tQ ground (to add - TC to Vol. To understand this,
    v"
    notice that the resistor, R, from the (+) input to
    £"' ground will add -N VBE to Vo where

    N = 1 + ~
    R
    and V BE is the base emitter voltage of the tran-
    sistor at the (+) input. This then also adds
    a positive temperature change at the output to
    provide the desired temperature correction.
    FIGURE 29. High YIN Protection and Self'regulation
    The added transistor, O2 , also increases the
    gain (which reduces the output impedance) and
    The base drive current for 0, is supplied via R,. if a power device is used for 0, large load
    The maximum current through R, should be currents (amps) can be supplied. This regula-
    limited to 10 mA as tor also supplies the power to the other three
    amplifiers of the LM3900.

    5.4 Reducing Input Voltage Dependence and


    Adding Short-circuit Protection
    To increase the maximum allowed input volt- To reduce ripple feedthrough and input voltage
    age, reduce the output ripple, or to reduce the dependence, diodes can be added as shown in
    (VIN - VOUT ) requirements of this circuit, the Figure 31 to drop-out the start circuit once
    connection described in the next section is
    recommended.

    5.3 High Input Voltage Protection and Low


    (VIN - VOUT)

    The circuit shown in Figure 30 basically adds


    one additional transistor to the circuit of Fig-
    ure 29 to improve the performance. In this
    circuit both transistors (0, and 02) absorb any
    high input voltages (and therefore need to be
    high voltage devices) without any increases in
    current (as with R, of Figure 29). The resis-
    tor R, (of Figure 30) provides a "start-up"
    cu rrent into the base of O 2 , FIGURE 31. Reducing YIN Dependence

    start-up has been achieved. Short-circuit pro-


    ~----4~--+-""'-"--O'" tection can also be added as shown in Figure 32.
    ..." "
    41KI,o~F
    Co

    "'"

    FIGURE 30. A High YIN Protected, Low (YIN -


    Yo UT ) Regulator

    FIGURE 32. Adding Short·circuit Current Limiting


    A new input connection is shown on this regu-
    lator (the type on Figure 29 could also be used)
    to control the DC output voltage. The Zener is The emitter resistor of O 2 will limit the maxi-
    biased via R4 (at approximately 1 mAl. The mum current of O 2 to (Vo - 2 V BE )/R s.

    AN72-12
    6.0 DESIGNING RC ACTIVE FILTERS Negative signs simply mean an increase in the
    value of a passive component causes a decrease
    in that filter performance characteristic. As an
    Recent work in RC active filters has shown that
    example, if a bandpass filter listed the follow-
    the performance characteristics of multiple-
    ing sensitivity factor
    amplifier filters are relatively insensitive to the
    tolerance of the RC components used. This
    makes the performance of these filters easier to
    control in production runs. In many cases
    where gain is needed in a system design it is
    This states that "if C 3 were to increase by 1%,
    now relatively easy to also get frequency
    the center frequency, Wo , would decrease by
    selectivity.
    0.5%." Sensitivity functions are tabulated in
    the reference listed at the end of this section
    The basis of active filters is a gain stage and
    and will therefore not be included here.
    therefore a multiple amplifier product is a
    valuable addition to this application area.
    A brief look at low pass, high pass and band-
    When additional amplifiers are available, less
    pass filters will indicate how the LM3900 can
    component selection and trimming is needed as
    be applied in these areas. A recommended text
    the performance of the filter is less disturbed
    (which provided these circuits) is, "Operational
    by the tolerance and temperature drifts of the
    Amplifiers", Tobey, Graeme, and Huelsman,
    passive components.
    McGraw Hill, 1971.

    The passive components do control the per-


    formance of the filter and for this reason car- 6.1 Biasing the Amplifiers
    bon composition resistors are useful mainly for Active filters can be easily operated off of a
    room temperature breadboarding or for final single power supply when using these multiple
    trimming of the more stable metal film or wire- single supply amplifiers. The general tech-
    wound resistors. Capacitors present more of a nique is to use the (+) input to accomplish the
    problem in range of values available, tolerance biasing function. The power supply voltage,
    and stability (with temperature, frequency, V+, is used as the DC reference to bias the
    voltage and time). For example, the disk output voltage of each amplifier at approxi-
    ceramic type of capacitors are generally not mately V+/2. As shown in Figure 33, unde-
    suited to active filter applications due to their sired AC components on the power supply line
    relatively poor performance. may have to be removed (by a filter capacitor,

    The impedance level of the passive compo-

    ~
    nents cim be scaled without (theoretically) af-
    fecting the filter characteristics. In an actual
    AI
    circuit; if the resistor values become too small
    R1
    (!O 10 kSG) an excessive loading may be placed v' +
    on the output of the amplifier which will reduce
    gain or actually exceed either the output cur-
    (1/ B'ls,ngFram.·'NollrFrte"PowerSupp1v
    rent or the package dissipation capabilities of
    the amplifier. This can easily be checked by
    calculating (or noticing) the impedance which v'
    is presented to the output terminal of the am- ~---
    plifier at the highest operating frequency. A
    second limit sets the upper range of impedance
    levels, this is due to the DC bias currents
    (~30 r'!A) and the input impedance of actual
    amplifiers. The solution to this problem is to
    reduce the impedance levels of the passive (hi BllslngFrom."ND,5y"PDWIISupplv

    components (!O10 MSG). In general, better per-


    formance is obtained with relatively low pas- FIGURE 33. Biasing Considerations
    sive component impedance levels and in filters
    which do not demand'high gain, high 0 (0;':50)
    and high frequency (fa >1 kHz) simultaneously. Figure 31 b) to keep the filter output free of this
    noise. One filtered DC reference can generally
    A measure of the effects of changes in the be used for all of the amplifiers as there is
    values of the passive components on the filter essentially no signal feedback to this bias point.
    performance has been given by "sensitivity
    functions". These assume infinite amplifier In the filter circuits presented here. all ampli-
    gain and relate the percentage change in a par- fiers will be biased at V+12 to allow the maxi-
    ameter of the filter, such as center frequency mum AC voltage swing for any given DC power
    (fa), 0, or gain to a percentage change in a supply voltage. The inputs to these filters
    particular passive component. Sensitivity func- will also be assumed at a DC level of V+12
    tions which are small are desirable (as 1 or 1/2). (for those which are direct coupled).

    AN72-13
    6.2 A High Pass Active Filter Start by selecting C 1 = 300 pF and then from
    equation (1)
    A single amplifier high pass RC active filter
    RI
    is shown in Figure 34. This circuit is easily
    biased using the (+) input of the LM3900. The
    resistor. R3 • can be simply made equal to R2 RI = 17.7 kil
    and a bias reference of V+/2 will establish the
    output Q point at this value (V+/2). The input and from equation (2)
    is capacitively coupled (C l ) and there are R = _...!1~0_ _--,-(3",1_ _
    therefore no further DC biasing problems. 2 (6.28 x 103 ) (3 x 10. 10)

    C2
    410pF R2 = 15.9 Mil
    and from equation (3)
    C1
    C2 = ., = c 1

    r
    C1
    410pF

    Now we see that the value of R2 is quite large;


    R1
    vo but the other components look acceptable. Here
    v" : 11K,::"
    is where impedance scaling comes in. We can
    reduce R2 to the more convenient value of
    10 Mrl which is a factor of 1.59:1. Reducing R1
    fc "'lkHl R3 by this same scaling factor gives:
    10M

    17.7xl03 = 11.1kil
    1.59

    FIGURE 34. A High Pass Active Filter and the capacitors are similarly reduced in
    impedance as:

    The design procedure for this filter is to select


    (c = c =
    1 2 C 3)NEW = (1.59) (3001 pF

    the pass band gain. He. the Q and the corner C 1NEW = 477 pF.
    frequency. fe. A Q value of 1 gives only a
    slight peaking near the bandedge «2 dB) and
    To complete the design. R3 is made equal to
    smaller Q values decrease this peaking. The
    R2 (10 Mrl) and a VREF of V+12 is used to
    slope of the skirt of this filter is 12 dB/octave
    bias the output for large signal accomodation.
    (or 40 dB/decade). If the gain. Ho. is unity
    all capacitors have the same value. The design
    Capacitor values should be adjusted to use
    proceeds as:
    standard valued components by using imped-
    ance scaling as a wider range of standard
    Given: Ho. Q and we = 2"ITfe
    resistor values is generally a·vailable.
    To find: R1• R2• C1• C 2• and C 3
    6.3 A Low Pass Active Filter
    let C 1 = C 3 and choose a convenient starting
    value. A single amplifier low pass filter is shown in
    Figure 35. The resistor, R4 • is used to set the
    Then:
    R2
    1M
    (1 )

    vo
    and
    (3)

    fC :UHz
    R.
    15M
    GAIN" 1
    As a design example.

    Require: HO = I,
    FIGURE 35. A Low Pass Active Filter

    Q = 10,
    output bias level and is selected after the other
    and Ie = 1 kHz ( We = 6.28 • 103 rpsl. resistors have been established.

    AN72·14
    The design procedure is as follows:
    --~--
    11
    -~

    .1V o{'
    R1
    Given: Ho ' Q, and wc= 2rrfc A'11'12 1 RJ

    Let C, be a convenient value,


    .7V oc

    then
    (4)

    where K is a constant which can be used to ad-


    just component values. For example, with
    K = 1, C, = C 2 . Larger values of K can be used v'
    to reduce R2 and R3 at the expense of a larger
    value for C2 . FIGURE 36. Biasing the Low Pass Filter

    (5) equal resistor values (R, and R2) but simplifies


    the DC bias calculation as I, = 12 and we have
    a DC amplifier with a gain of -1 (so if the DC
    input voltage increases 1 Voc the output volt-
    4021HO +
    ,,] age decreases 1 Voc). The resistors R, and R2
    R
    2
    and
    = 1
    20 We C1
    t ± 1+
    K
    (6) are in parallel so that the circuit simplifies to
    that shown in Figure 37 where the actual resis-
    tance values have been added. The resistor R4
    is given by
    R3 = (7)
    we 2 CI 2R2IK)

    As a design example;
    or, using values
    Require: = I,
    HO
    R4 = 2 (IM2n + 266 k) ~ 1.5 Mn
    0=1,

    and f
    e = 1 kHz 1We = 6.28 x 103 rps). +lV oc

    5lJOK Rl R2 '" RI/2

    Start by selecting C, = 300 pF and K = 1 so


    C 2 is also 300 pF (equation 4). '1 RJ
    Z10K

    Now from equation (6)

    R
    2
    = 1
    2(1) (6.28 x 103) 13 x 10. 10)
    [1±~1

    +15Voc

    Then from equation (5)


    FIGURE 37. Biasing Equivalent Circuit
    Rl = R2 = 1.06 Mn

    and finally from equation (7) 6.4 A Single·amplifier Bandpass Active Filter

    R = 1 The bandpass filter is perhaps the most inter-


    3 16.28 x 103)2 13· x 10.10)2 (1.06 x 106) (t) esting. For low frequencies, low gain and low
    Q ( :510) requirements, a single amplifier real-
    ization can be used. A one amplifier circuit is
    shown in Figure 38 and the design procedure
    is as follows:
    To select R4• we assume the DC input level is
    7 Voc and the DC output of this filter is to Given: H o ' Q and Wo = 2rrf .
    also be 7 Voc. This gives us the circuit of
    Figure 36. Notice that Ho = 1 gives us not only

    AN72·15
    6.5 A Two-amplifier Bandpass Active Filter
    "
    510pF

    To allow higher Q (between 10 and 50) and


    higher gain, a two amplifier filter is required.
    This circuit, shown in Figure 39, uses only two
    capacitors. It is similar to the previous single
    amplifier bandpass circuit and the added am-
    v, plifier supplies a controlled amount of positive
    feedback to improve the response character-
    istics. The resistors Rs and Rs are used to bias
    the output voltage of the amplifiers at V+/2.
    10 ~ 1KHz R4
    0=5 62M
    GAIN = 1

    "
    OI.,F

    FIGURE 38. A One Op Amp Bandpass Filter

    Let C, C 2 and select a convenient starting "


    value.

    Then
    Q
    (8)

    FIGURE 39. A Two Op Amp Bandpass Filter

    R2 = ---~Q~--- (9)
    Again, Rs is simply chosen as twice R4 and Rs
    12Q2 - HO) w o c 1
    must be selected after R6 and R7 have been
    assigned values. The design procedure is as
    R =~ follows:
    (10)
    3 W C
    o 1
    Given: Q and fo
    and
    (11 )
    To find: R, through R7, and C, and C2

    As a design example; Let: C, = C 2 and choose a convenient starting


    value and choose a value for K to reduce the
    Require: HO = 1 spread of element values or to optimize sen-
    Q =5 sitivity (1 :S KTypicali/10).
    10 = 1 kHz 1Wo = 6.28 x 103 rps) •

    Start by selecting Then


    (12)
    c1 = c2 = 510pF.

    Then using equation (8)


    (13)
    5
    16.28 x 103 ) 15.1 x 10-1~
    R = ____R.!l_ _ __
    (14)
    Rl = 1.57 Mil, 3 Q2 _ 1 _ 2/K + l/KQ

    and using equation (9) and


    R2 = 5 (15)
    [2(25) - 1]16.28 x 103 ) 15.1 x 10-1~
    R2 = 32 kil (16)
    from equation (10)
    R3 = _ _~21=5~)_ __
    As a design example:
    16.28 x 103 ) 15.1 x 10-1~
    R3 = 3.13 Mil , Require: Q = 25 and 10 = 1 kHz.
    and finally, for biasing, using equation (11) Select: c1 = c2 = 0.1 IlF

    R4 = 6.2 Mil.
    and K=3.

    ANn-16
    Then from equation (12)

    Al = 40kil .,
    410K
    and from equation (13)
    A2 = 140 x 1031 31251
    [21251 - 1]
    A2 = 61 kil
    and from equation (14)

    A3 =
    40 x 103
    ----"""--''-'-'~--

    1251 2 - 1 - 2/3 + _1_


    31251

    FIGUAE 40. The "Bi-quad" RC Active Bandpass


    Filter

    And R7 is given by equation (15)


    The bandpass filter is shown in Figure 40 and
    A7 = 3140 kill = 120kil, the design procedure is:
    and the gain is obtained from equation (16)
    Given: Q and fa.
    HO =..J25 131 = 15123 dBI.
    To simplify: Let C l = C 2 and choose a con-
    venient starting value and also let 2Rl = R2 =
    To properly bias the first amplifier R3 and choose a convenient starting value.

    A5 = 2A4 = so kil Then:


    and the second amplifier is biased by Re. Notice (17)
    that the outputs of both amplifiers will be at
    V+/2. Therefore R6 and R7 can be paralleled
    and (18)

    or and for biasing the amplifiers we require

    A = 2\140111201 x 103 ] = 59 kil (19)


    S 160

    The mid-band gain is:


    These values, to the closest standard resistor
    values, have been added to Figure 39. (20)

    As a design example;
    6.6 A Three-amplifier Bandpass Active Filter
    Require: to = 1 kHzandQ = 50.
    To reduce Q sensitivity to element variation To find: Cl , C2 and Al through RS'
    even further or to provide higher Q (Q > 50)
    a three amplifier bandpass filter can be used. Choose: cl = c2 = 330 pF
    This circuit, Figure 40, pre-dates most of the
    literature on RC active filters and has been and 2Al = A2 = A3 = 360 kn, and Al = lS0 kn.
    used on analog computers. Due to the use
    of three amplifiers it often is considered too Then from equation (17).
    costly-especially for low Q applications. The
    multiple amplifiers of the LM3900 make this a A4 = 11.S x 1051 [21501 - 1]
    very useful circuit. It has been called the "Bi- A4 = 17.S Mil.
    Quad" as it can produce a transfer function From equation (18).
    which is "Quad" - radic in both numerator A5 = A7 = _ _ _ _1'--_ __
    and denominator (to give the "Bi"). A newer
    realization technique for this type of filter is 121r x 103113.3 x 10-101
    the "second-degree state-variable network." A5 = 4S3kil.
    Outputs can be taken at any of three points to And from equation (19),
    give low pass, high pass or bandpass response
    characteristics (see the reference cited). A6 = AS ~ 1 Mil.

    AN72-17
    From equation (20) the midband gain is 100 As an example, using Ao = 2800 for the LM3900
    (40 dB). The value of R4 is high and can be we can estimate the maximum frequency
    lowered by scaling only R, through R4 by the where a 0 0 = 50 would be reasonable as
    factor 1.78 to give:
    3
    2Rl = R
    2
    = R
    3
    = 3BOx 10
    1.78
    =200~ Rl = 100k.\l
    •
    ~ = 2.5 x 10.2 (2.8 x 103 ) + 0.5
    fa 5 x 10
    and or
    ~ = 1.9
    R4 = 17.8x lOB = 10 Mon. fa
    1.78
    therefore
    These values (to the nearest 5% standard) have
    been added to Figure 40.

    Again, using data of the LM3900, f. = 1 kHz


    so this upper frequency limit is approximately
    6.7 Conclusions
    2 kHz for the assumed 0 of 50. As indicated
    in equation (26) the value of OA can actually
    The unity-gain cross frequency of the LM3900 exceed the value of 0 0 (0 enhancement) and,
    is 2.5 MHz which is approximately three times as expected, the filter can even provide its
    that of a "741" op amp. The performance of the own input (oscillating). Excess phase shift in
    amplifier does limit the performance of the the high frequency characteristics of the ampli-
    filter. Historically. RC active filters started fier typically cause unexpected oscillations.
    with little concern for these practical problems. Phase compensation can be used in the Bi-
    The sensitivity functions were a big step for- Ouad network to reduce this problem (see
    ward as these demonstrated that many of the L.C. Thomas paper).
    earlier suggested realization techniques for RC
    active filters had passive component sensitivity
    functions which varied as Q or even Q2. The Designing for large passband gain also in-
    Bi-Quad circuit has reduced the problems with creases filter dependency on the characteristics
    the passive components (sensitivity functions of the amplifier and finally signal to noise ratio
    of 1 or 112) and recently the contributions of can usually be improved by taking gain in an
    the amplifier on the performance of the filter input RC active filter (again see L.C. Thomas
    are being investigated. An excellent treatment paper).
    ("The Biquad: Part I - Some Practical Design
    Considerations," L.C. Thomas, IEEE Transac-
    tions on Circuit Theory, Vol. CT-18, No.3, May Somewhat larger Q's can be achieved by add-
    1971) has indicated the limits imposed by the ing more filter sections in either a synchron-
    characteristics of the amplifier by showing that ously tuned cascade (filters tuned to same cen-
    the design value of Q (00 ) will differ from the ter frequency and taking advantage of the
    actual measured value of Q(OA) by the given bandwidth shrinkage factor which results from
    relationship the series connection) or as a standard multiple
    pOle filter. All of the conventiol)al filters can
    Q = _ _-=-=_Q_o=-_ __ be realized and selection is based upon all of
    (21)
    the performance requirements which the appli-
    A 1 + 2Qo Iw _ 2W I
    AO Wa a p
    cation demands. The cost advantages of the
    LM3900, the relatively large bandwidth and the
    ease of operation on a single power supply
    where Ao is the open loop gain of the amplifier, voltage make this product an excellent "build-
    w. is the dominant pole of the amplifier and wp ing block" for RC active filters.
    is the resonant frequency of the filter. The
    result is that the trade-off between 0 and cen-
    ter frequency (wp) can be determined for a ~
    given set of amplifier characteristics. When 7.0 DESIGNING WAVEFORM GENER~TORS
    QA differs significantly from 0 0 excessive de-
    pendence on amplifier characteristics is indi-
    cated. An estimate of the limitations of an The multiple amplifiers of the LM3900 can be
    amplifier can be made by arbitrarily allowing used to easily generate a wide variety of wave-
    approximately a 10% effect on OA which re- forms in the low frequency range (f :510 kHz).
    sults if Voltage controlled oscillators (VCO's) are also
    possible and are presented in section 8.0 "De-
    2QO (W _ 2wl = 0.1 signing Phase-locked Loops and Voltage Con-
    a p trolled Oscillators." In addition, power oscil-
    lators (such as noise makers, etc.) are presented
    or in section 10.11.3. The waveform generators
    which will be presented in this section are
    mainly of the switching type, but for complete-
    ness a sinewave oscillator has been included.

    AN72·18
    7.1 A Sinewave Oscillator 7.2 Squarewave Generator

    The design of a sinewave oscillator presents The standard op amp squarewave generator
    problems in both amplitude stability (and pre- has been modified as shown in Figure 42. The
    dictability) and output waveform purity (THD).
    If an RC bandpass filter is used as a high Q
    resonator for the oscillator circuit we can ob- "'
    30K

    tain an output waveform with low distortion


    and eliminate the problem of relative center
    frequency drift which exists if the active filter
    were used simply to filter the output of a v,
    separate oscillator.

    V'
    "'
    lO
    o-JVl "M..-4....._-'lM_--' ;.f1..J
    to ~ lkHl
    A sinewave oscillator which is based on this
    principle is shown in Figure 41. The two-
    FIGURE 42. A Squarewave Oscillator
    amplifier RC active filter is used as it requires
    only two capacitors and provides an overall
    non-inverting phase characteristic. If we add capacitor, C" alternately charges and dis-
    a non-inverting gain controlled amplifier charges (via R,) between the voltage limits
    around the filter we obtain the desired oscilla- which are established by the resistors R2, R3
    tor configuration. Finally, the sinewave output and R4 . This combination produces a Schmitt-
    voltage is sensed and regulated as the average Trigger circuit' and the operation can be under-
    value is compared to a DC reference voltage, stood by noticing that when the output is low
    VREF • by use of a differential averaging circuit. (and if we neglect the current flow through
    It can be shown that with the values selected R4 ) the resistor R2 (3M) will cause the trigger
    for R'5 and R'6 (ratio of 0.64/1) that there is to fire when the current through this resistor
    first order temperature compensation for CR 3 equals the current which enters the (+) input
    and the internal input diodes of the IC ampli- (via R3). This gives a firing voltage of approxi-
    fier which is used for the "difference averager". mately R2/(R3) V+ (or V+/3). The other trip
    Further, this also provides a simple way to point, when the output voltage is high, is ap-
    regulate and to predict the magnitude of the proximately [2(R2/R3)] V+, as R3 = R4 • or
    output si newave as 2/3(V+). Therefore the voltage across the ca-
    pacitor, C" will be the first one-half of an ex-
    ponential waveform between these voltage trip
    limits and will have good symmetry and be es-
    sentially independent of the magnitude of the
    which is essentially independent of both tem- power supply voltage. If an unsymmetrical
    perature and the magnitude of the power sup- squarewave is desired, the trip points can be
    ply voltage (if V REF is derived from a stable shifted to produce any desired mark/space
    voltage source). ratio.

    "'
    200K

    v·
    "'
    51.
    R7
    CZ J9K

    "'
    l!iDK "'
    15DK "'
    ]g,
    Dl"f ""
    120K

    "'
    6Zn
    C"' GAIN CONTROllED AMPLIFIER v,

    C"' "10
    R12 ..
    IODK.-4J!tf-
    62.
    v'
    ""
    !i.1M

    ""
    62. v·

    "15 co,
    'M
    VOPEAK "ZVREF

    ""
    1.8M
    \.--'V\IIr---o+v REF
    10=1 kHz
    THO = 0.1% (Vo" 5 Vp)

    DIFFERENCE AVERAGER

    FIGURE 41. A Sinewave Oscillator

    AN72·19
    7.3 Pulse Generator At this time the output voltage will switch to a
    high state. VOH ;. and the current entering the
    The squarewave generator can be slightly mod- (+) input will increase to
    ified to provide a pulse generator. The slew
    rate limits of the LM3900 (0.5V/jJSec) must be v+ - v BE + V OHi - V BE
    1M+ = - - - - " ' "
    kept in mind as this limits the ability to pro- R3 R4
    duce a narrow pulse when operating at a high
    power supply voltage level. For example. with Also CR, goes ON and the capacitor. C,. charges
    a +15 Voc power supply the rise time. t" to via R,. Some of this charge current is diverted
    change 15V is given by: via R2 to ground (the (-) input is at VCESAT
    during this interval as the current mirror is
    t=~=~ demanding more current than the (-) input
    r Slew Rate 0.5V//lsee terminal can provide). The high trip voltage.
    VH • is given by
    t, = 30 /lsee.

    The schematic of a pulse generator is shown in


    Figure 43. A diode has been added. CR,. to
    allow separating the charge path to C, (via R,)
    (2)
    I CHARGE RI CRI
    J9K lN~

    1 R2 .....

    ~
    A design proceeds by first choosing the trip
    points for the voltage across C,. The resistors
    ~
    O.OII' F -r
    c,_ --1!..DI
    T'':''''( lM3900
    L.r.
    "" VO
    R3 and R4 are used only for this trip voltage
    control. The resistor R2 affects the discharge

    v,""
    +15V oc
    t,1 r + 1~~
    PW == IOQu:s
    :j~L time (the long interval) and also both of the
    trip voltages so this resistor is determined first
    from the required pulse repetition frequency
    PRF:l! 1kHz I/PRF (PRF). The value of R2 is determined by the
    RC exponential discharge from V H to VL as
    this time interval. T,. controls the PRF (T, =
    FIGURE 43. A Pulse Generator 1/PRF). If we start with the equation for the
    RC discharge we have
    from the discharge path (via R2). The circuit
    operates as follows. assume first that the out-
    put voltage has just switched low (and we will
    neglect the current flow through R4)' The
    or
    voltage across C, is high and the magnitude of
    the discharge current (through R2) is given by

    Ve , ,V BE
    or
    I Discharge ::::: - ' - - - -
    R2
    (3)
    This current is larger than that entering the
    (+) input which is given by
    To provide a low duty cycle pulse train we sel-
    ect small values for both V H and V L (such as
    3V and 1.5V) and choose a starting value for
    C,. Then R2 is given by
    The excess current entering the (-) input term-
    inal causes the amplifier to be driven to a low (4)
    output voltage state (saturation). This condi-
    tion remains for the long time interval (1/Pulse
    Repetition Frequency) until the R2C, dis-
    charge current equals the I R3 value (as CR, is
    OFF during this interval). The voltage across If R2 from (4) is not in the range of approxi-
    C, at the trip point. VL • is given by mately 100 kQ to 1 MQ. choose another value
    for C,. Now equation (1) can be used to find
    a value for R3 to provide the VL which was
    initially assumed. Similarly equation (2) allows
    or
    R4 to be calculated. Finally R, is determined
    (1 ) by the required pulse width (PW) as the capaci-
    tor. C,. must be charged from VL to VH by R,.

    AN72·20
    This RC charging is given by (neglecting the 5.0 Find Rl from equation (5).
    loading due to R2)
    A = 104

    ~ ~ "<;,) 1 -1O-8..en (1 _ 3 )
    114.2 - 0.7)
    v, "0", - V o' -
    or = 104
    AI -..en (1 __3_)
    13.5

    Al = ~ = 39.7 kn .
    0.252
    Al ~ ~ ~
    These values (to the nearest 5% standard) have
    -C 1..en [1 _ VH ]
    VOHi - VD been added to Figure 43.

    where T2 is the pulse width desired and Va 7.4 Triangle Waveform Generator
    is the forward voltage drop across CR 1 .
    Triangle waveforms are usually generated by
    As a design example: an integrator which receives first a positive DC
    input voltage then a negative DC input voltage.
    Required: Provide a lOOf.J.s pulse every 1 ms. The LM3900 easily provides this operation in a
    The power supply voltage is +15 Vac system which operates with only a single power
    supply voltage by making use of the current
    1.0 Start by choosing VL = 1.5V mirror which exists at the (+) input. This allows
    the generation of a triangle waveform without
    and VH = 3.0V requiring a negative DC input voltage.

    The schematic diagram of a triangle waveform


    2.0 Find R2 from equation (4) assuming C 1 = generator is shown in Figure 44. One amplifier
    0.01 f.J. F,

    10-8..en (3.0 )
    1.5

    A2 ~ =
    = 0.694 144kn.

    3.0 Find R3 from equation (1)


    SCHMITT TRIGGER
    (v+ - VeE) A2
    A3 =
    VL
    FIGUAE 44. A Triangle Waveform Generator

    115 - 0.5) 1.44x 105


    A3 = is doing the integration by operating first with
    1.5
    the current through RI , to produce the negative
    output voltage slope, and then when the output
    of the second amplifier (the Schmitt-Trigger) is
    A3 = 1.39Mn
    high, the current through R2 causes the output
    voltage to increase. If RI = 2R 2, the output
    waveform will have good symmetry. The tim-
    4.0 Find R4 from equation (2),
    ing for one-half of the period (T/2) is given by
    (V OHi - VeE)
    R4 = l = IA 1C 1) I:; Vo
    VH v+ - VeE
    2 v+ - VeE
    A2 R3
    or the output frequency becomes
    R4 = _~(~1",4.~2_--,-,,0.:::.57,),..-...,...~ v+ - VeE
    _ _3__ _ 15 0.5
    f =
    o 2A 1C 1 1:;Vo
    1.44 x 105 1.39 x 106
    where we have assumed Rl = 2R2, V BE is the
    DC voltage at the H input (0.5 Vac ), and I:;Vo

    AN72-21
    is the difference between the trip points of the -----!.- Cl
    Schmitt-Trigger. The design of the Schmitt-
    Trigger has been presented in the section on RI CRI
    Digital and Switching Circuits (9.0) and the RESET O-JlllIIr-...+<H
    trip voltages control the peak-to-peak excur-
    OUTPUT
    sion of the triangle output voltage waveform.
    .2
    The output of the Schmitt circuit provides a
    squarewave of the same frequency.

    • til) P01111veRamp
    7.5 Sawtooth Waveform Generator

    The previously described triangle waveform


    generator, Figure 44, can be modified to pro-
    duce a sawtooth waveform. Two types of
    waveforms can be provided, both a positive .,
    ramp and a negative ramp sawtooth waveform OUTPUT

    by selecting R, and R2. The reset time is also .2


    RESET O-"""IIr---1~
    controlled by the ratio of R, to R2. For example,
    if R, = 10 R2 a positive ramp sawtooth results :~ I
    and if R2 = 10 R, a negative ramp sawtooth 10
    can be obtained. Again, the slew rate limits of
    the amplifier (O.5V/jJ.s) will limit the minimum
    retrace time, and the increased slew rate of a
    negative going output will allow a faster re- FIGURE 45. Gated Sawtooth Generators
    trace for a positive ramp sawtooth waveform.

    To provide a gated sawtooth waveform, the cir-


    7.5.1 Generating a Very Slow Sawtooth
    cuits shown in Figure 45 can be used. In Fig- Waveform
    ure 45(a). a positive ramp is generated by inte-
    grating the current, I, which is entering the (+) The LM3900 can be used to generate a very
    input. Reset is provided via R, and CR, keeps slow sawtooth waveform which can be used to
    R, from loading at the H input during the generate long time delay intervals. The circuit
    sweep interval. This will sweep from Vo MIN is shown in Figure 46 and uses four amplifiers.
    to Vo MAX and will remain at Vo MAX until reset. Amps 1 and 2 are cascaded to increase the gain
    The interchange of the input leads, Figure 45(b), of the integrator and the output is the desired
    will generate a negative ramp, from Vo MAX very slow sawtooth waveform. Amp 3 is used to
    to Vo MIN' exactly supply the bias current to Amp 1.

    ","
    "
    10M

    >..;.;;;'---....-..... '0
    -oOIlTI'IIT

    "
    10M

    " (+15V g c!

    "
    '"
    "
    'OM SWEEP-IIIDSEC/V

    9",'K OIVDC

    Run ~ onttJV
    Run RATIO :~:~~::~ • 140 1
    CONTROL

    '.' ' 1"-'' ' -


    FIGURE 46. Generating Very Slow Sawtooth Waveforms

    AN72-22
    With resistor Rs opened up and the reset con-
    trol at zero volts. the potentiometer. Rs. is ad-
    justed to minimize the drift in the output volt-
    "~
    '~F Vo

    OUTPUT

    age of Amp 2 (this output must be kept in the


    linear range to insure that Amp 2 is not in satu-
    ration). Amp 4 is used to provide a bias refer- "•.f1..f1.
    ence which equals the DC voltage at the H
    input of Amp 3. The resistor divider. R7 and FIGURE 47. Pumping the Staircase Via Input
    R9. provides a 0.1 Voc reference voltage across Differentiator
    R9 which also appears across Rs. The current
    which flows through Rs. I. enters the H input
    of Amp 3 and causes the current through Rs to A free running staircase generator is shown in
    drop by this amount. This causes an imbalance Figure 4B. This uses all four of the amplifiers
    as now the current flow through R4 is no longer which are available in one LM3900 package.
    adequate to supply the input current of Amp 1.
    The net result is that this same current. I. is
    drawn from capacitor C 1 and causes the output
    voltage of Amp 2 to sweep slowly positive. As a
    result of the high impedance values used. the
    Yo .. , "\d
    .....

    PC component board used for this circuit must


    first be cleaned and then coated with silicone
    rubber to eliminate the effects of leakage cur-
    rents across the surface of the board. The DC
    leakage currents of the capacitor. C 1• must
    also be small compared to the 10 nA charging
    current. For example. an insulation resistance
    of 100.000 Mn will leak 0.1 nA with 10 Voc
    across the capacitor and this leakage rapidly
    increases at higher temperatures. Dielectric
    polarization of the dielectric material may not
    cause problems if the circuit is not rapidly
    cycled. The resistor. Rs. and the capacitor. C 1• FIGURE 48. A Free Running Staircase Generator
    can be scaled to provide other basic sweep
    rates. For the values shown on Figure 46 the
    10 nA current and the 1f.1F capacitor establish Amp 1 provides the input pulses which "pump
    a sweep rate of 100 seclvolt. The reset control up" the staircase via resistor R1 (see section 7.3
    pulse (Amp 3 (+) input) causes Amp 3 to go to for the design of this pulse generator). Amp 2
    the positive output saturation state and the does the integrate and hold function and also
    10 Mn (R4) gives a reset rate of 0.7 seclvolt. supplies the output staircase waveform. Amps
    The resistor. R1• prevents a large· discharge 3 and 4 provide both a compare and a one-shot
    current of C 1 from overdriving the (-) input and multivibrator function (see the section on Digi-
    overloading the input clamp device. ; For larger tal and Switching Circuits for the design of this
    charging currents. a resistor divider can be dual function one-shot). Resistor R4 is used to
    placed from the output of Amp 4 to ground and sample the staircase output voltage and to
    Rs can tie from this tap point directly to the compare it with the power supply voltage (V,,)
    H input of Amp 1. via R3 • When the output exceeds approxi-
    mately BO% of V+ the connection of Amps 3 and
    4 cause a 100 f.1 sec reset pulse to be generated.
    This is coupled to the integrator (Amp 2) via
    R 2 and causes the stai rcase output voltage to
    7.6 Staircase Waveform Generators . fall to approximately zero volts. The next pulse
    out of Amp 1 then starts a new stepping cycle.

    A staircase generator can be realized by sup-


    plying pulses to an integrator circuit. The LM- 7.7 A Pulse Counter and a Voltage Variable
    3900 also can be used with a squarewave input
    Pulse Counter
    signal and a differentiating network where
    each transition of the input squarewave causes
    a step in the output waveform (or two steps per The basic circuit of Figure 4B can be used as a
    input cycle). This is shown in Figure 47. These pulse counter simply by omitting Amp 1 and
    pulses of current are the charge and discharge feeding input voltage pulses directly to R1.
    currents of the input capacitor. C1 . The charge A simpler one-shoVcomparator which requires
    current. Ic. enters the (+) input and is mirrored only one amplifier can also be used in place of
    about ground and is "drawn into" the H input. Amps 3 and 4 (again. see the section on Digital
    The discharge current. 10. is drawn through the and SWitching Circuits). To extend the time
    diode at the input. CR1• and therefore also interval between pulses, an additional ampli-
    causes a step on the output staircase. fier can be used to supply base current to

    AN72-23
    Amp 2 to eliminate the tendency for the output many functions, the required linearity of the
    voltage to drift up due to the 30 nA input cur- transfer characteristic (frequency out to DC
    rent (see section 7.5.1). The pulse count can be voltage in) depends upon the application. For
    made voltage variable simply by removing the low distortion demodulation of an FM signal,
    comparator reference (R3) from V+ and using a high degree of linearity is necessary whereas
    this as a control voltage input. Finally, the in- a tracking filter application would not require
    put could be derived from differentiating a this performance in the VCO.
    squarewave input as was shown in Figure 47
    and if only one step per cycle were desired, the
    diode, CR, of Figure 47, can be eliminated. A VCO circuit is shown in Figure 50. Only two
    amplifiers are required, one is used to integrate
    the DC input control voltage, Vc , and the other
    7.B An Up·down Staircase Waveform Generator is connected as a Schmitt-trigger which moni-
    tors the output of the integrator. The trigger
    A staircase waveform which first steps up and circuit is used to control the clamp transistor,
    then steps down is provided by the circuit 0,. When 0, is conducting, the input current,
    shown in Figure 49. An input pulse generator 12, is shunted to ground. During this one-half
    cycle the input current, I" causes the output
    voltage of the integrator to ramp down. At the
    minimum point of the triangle waveform (out-

    "·16 put 1). the Schmitt circuit changes state and


    transistor 0, goes OFF. The current, 12, is
    exactly twice the value of I, (R 2 = R,/2) such
    that a charge current (which is equal to the
    magnitude of the discharge current) is drawn
    through the capacitor, C, to provide the in-
    creasing portion of the triangular waveform
    (output 1).

    FIGURE 49. An Up-down Staircase Generator

    provides the pulses which cause the output to


    step up or down depending on the conduction
    of the clamp transistor, 0,. When this is ON,
    the "down" current pulse is diverted to ground
    and the staircase then steps "up". When the
    upper voltage trip point of Amp 2 (Schmitt-
    Trigger-see section on Digital and Switching
    Circuits) is reached, 0, goes OFF and as a re-
    sult of the smaller "down" input resistor. (one-
    half the value of the "up" resistor, R,) the
    staircase steps "down" to the low voltage trip FIGURE 50. A Voltage Controlled Oscillator
    point of Amp 2. The output voltage therefore
    steps up and down between the trip voltages of
    the Schmitt-Trigger.
    The output frequency for a given DC input
    control voltage depends on the trip voltages of
    the Schmitt circuit (VH and VL ) and the com-
    B.O DESIGNING PHASE· LOCK ED LOOPS ponents R, and C, (as R2 = R,/2). The time to
    AND VOLTAGE CONTROLLED ramp down from V H to VL corresponds to one-
    half the period (T) of the output frequency and
    OSCILLATORS
    can be found by starting with the basic equa-
    tion of the integrator
    The LM3900 can be connected to provide a low
    frequency (f < 10 kHz) phase-locked loop (PL2).
    This is a useful circuit for many control applica- - _1_ f 11 d, (1 )
    tions. Tracking filters, frequency to DC conver- C
    ters, FM modulators and demodulators are
    applications of a PL2.
    as I, is a constant (for a given value of Vc )
    which is given by
    B.1 Voltage Controlled Oscillators (VCO)

    The heart of a PL2 is the voltage controlled 11 (2)


    oscillator (VCO). As the PL2 can be used for

    AN72·24
    equation (1) simplifies to A limit is reached when the triangular sweep
    output waveform exceeds the slew rate limit of
    the LM3900 (0.5V1fJS). Note that the output of
    the Schmitt circuit has to move up only one
    VSE to bring the clamp transistor, aI' ON, and
    or therefore output slew rate of this circuit is not
    a limit.
    t; va = __1_,_ (3)
    t;t C To improve the temperature stability of the
    veo, a PNP emitter follower can be used to
    Now the time, t;t, to sweep from VH to VL give approximate compensation for the VSE 's
    becomes at the inputs to the amplifier (see Figure 52).
    Finally to improve the mark to space ratio ac-
    curacy over temperature and at low control
    or
    voltages, an additional amplifier can be added
    such that both reference currents are applied to
    v'
    2(V H - VLI C
    T and
    11

    11
    ! (4)
    T 2(V H - VLI C

    Therefore, once VH, V L, Rl and e are fixed in


    value, the output frequency, f, is a linear func-
    tion of 11 (as desired for a VeO).

    The circuit shown in Figure 50 will require FIGURE 52. Reducing Temperature Drift
    Vc >V SE to oscillate. A value of Vc = 0 pro-
    vides fOUT = 0, which mayor may not be de-
    sired. Two common-mode input biasing resis- the same type of (inverting) inputs of the LM-
    tors can be added as shown in Figure 51 to 3900. The circuit to accomplish this is shown
    allow fOUT = fMIN for Vc = O. In general, if within dotted lines in Figure 53.
    these resistors are a factor of 10 larger than
    their corresponding resistor (Rl or R 2) a large
    control frequency ratio can be realized. Actu-
    ally, Vc could range outside the supply voltage
    limit of V+ and this circuit will still function
    properly.

    v'

    FIGURE 53. Improving Mark/Space Ratio

    8.2 Phase Comparator

    FIGURE 51. Adding Input Common-mode Biasing A basic phase comparator is shown in Figure 54.
    Resistors This circuit provides a pulse-width modulated
    output voltage waveform, Vol, which must be
    The output frequency of this circuit can be filtered to provide a De output voltage (this
    increased by reducing the peak-to-peak excur- filter can be the same as the one needed in the
    sion of the triangle waveform (output 1) by de- PL2 ). The resistor R2 is made smaller than Rl
    sign of the trip points of the Schmitt circuit. so the (+) input serves to inhibit the (-) input

    AN72-25
    signal. The center of the dynamic range is indi- 8.4 Conclusions
    cated by the waveforms shown on the figure
    (90 0 phase difference between fiN and fveo)' One LM3900 package (4 amplifiers) can pro-
    vide all of the operations necessary to make a
    phase-locked loop. In addition, a VCO is a gen-
    ,, ,,
    AI
    'lllfU'
    , , . 1 ,

    PULSE·WIDTH MODUll\TlON
    erally useful component for other system
    applications.

    >--o-IV\,-1~() Vo oc

    9.0 DESIGNING DIGITAL AND SWITCHING


    1"
    FIlTER
    CIRCUITS

    The amplifiers of the LM3900 can be over-


    RANGE OF VoDe driven and used to provide a large number of
    t.:; VODe <:;; v+ low speed digital and switching circuit applica-
    vo1 lf-r tions for control systems which operate off of
    PHASE DIAGRAM
    single power supply voltages larger than the
    standard +5 Voe digital limit. The large volt-
    FIGURE 54. Phase Comparator age swing and slower speed are both advan-
    tages for most industrial control systems. Each
    amplifier of the LM3900 can be thought of as
    The filtered DC output voltage will center at "a super transistor" with a i3 of 1,000,000
    3V+/4 and can range from V+/2 to V+ as the (25 nA input current and 25 mA output current)
    phase error ranges from a degrees to 180 and with a non-inverting input feature. In ad-
    degrees. dition, the active pull-up and pull-down which
    exists at the output will supply larger currents
    than the simple resistor pull-ups which are
    used in digital logic gates. Finally, the low
    8.3 A Complete Phase-locked Loop input currents allow timing circuits which mini-
    mize the capacitor values as large impedance
    A phase-locked loop can be realized with th ree levels can be used with the LM3900.
    of the amplifiers as shown in Figure 55. This
    has a center frequency of approximately 3 kHz.
    9.1 An "OR" GATE

    An OR gate can be realized by the circuit shown


    in Figure 56. A resistor (150 ~ from V+ to the
    (-) input keeps the output of the amplifier in a
    low voltage saturated state for all inputs A, B,

    r-----
    ""-:t and C at OV. If anyone of the input signals
    were to go high (,,=V+) the current flow through
    the 75 k S1 input resistor will cause the amplifier
    to switch to the positive output saturation state
    (Vo "= V+). The current loss through the other
    input resistors (which have an input in the low
    voltage state) represents an insignificant
    >-+-........., .., ...Jl.r amount of the total input current which is pro-
    '0 vided by the, at least one, high voltage input.
    More than three inputs can be OR'ed if desired.

    FIGURE 55. A Phase·locked Loop

    To increase the lock range, DC gain can be


    added at the input to the VCO by using the
    fourth amplifier of the LM3900. If the gain is
    inverting, the limited DC dynamic range out of
    the phase detector can be increased to improve FIGURE 56. An "OR" Gate
    the frequency lock range. With inverting gain,
    the input to the VCO could go to zero volts.
    This will cause the output of the VCO to go high The "fan-out" or logical drive capability is
    (V+) and will latch if applied to the (+) input of large (50 gates if each gate input has a 75 kS1
    the phase comparator. :l]herefore apply the resistor) due to the 10 mA output current cap-
    VCO signal to the (-) input of the phase com- ability of the LM3900. A NOR gate can be ob-
    parator or add the common-mode biasing resis- tained by interchanging the inputs to the
    tors of Figure 51. LM3900.

    AN72-26
    9.2 An "AND" Gate the "set" input causes the output to go high
    and a "reset" positive pulse will return the out-
    A three input AND gate is shown in Figure 57. put to essentially OVoc .
    This gate requires all three inputs to be high
    in order to have sufficient current entering the
    (+) input to cause the output of the amplifier to 9.4 Trigger Flip Flops
    switch high. The addition of R2 causes a smal-
    ler current to enter the (+) input when only two Trigger flip flops are useful to divide an input
    of the inputs are high. (A two input AND gate frequency as each input pulse will cause the
    would not require a resistor as R2). More than output of a trigger flip flop to change state.
    Again, due to the absence of a clocking signal
    input, this is for an asynchronous logic applica-
    tion. A circuit which uses only one amplifier
    24' is shown in Figure 60. Steering of the differ-
    24.
    entiated positive input trigger is provided by
    the diode CR2. For a low output voltage state,
    24.

    FIGURE 57. An "AND" Gate

    "
    IDOK

    three inputs becomes difficult with this resistor


    summing approach as the (+) input is too close
    to having the necessary current to switch just "
    prior to the last input going high. For a larger V,.~D~"+",,,,,,,.~-'W""--i
    fan-in an input diode network (similar to DTL) SL....I
    '.•
    ,
    '. I, '.
    is recommended as shown in Figure 58. Inter-
    change the inputs for a NAND gate.
    FIGURE 60. A Trigger Flip Flop

    v'
    CR2 shunts the trigger away from the (-) input
    and resistor R3 couples this positive input trig-
    ger to the (+) input terminal. This causes the
    CR2 ". tOOK
    output to switch high. The high voltage output
    state now keeps CR2 OFF and the smaller value
    CRl
    of (R5 + Rs) compared with R3 causes a larger
    CR. CRI positive input trigger to be coupled to the (-)
    input which causes the output to switch to the
    CR' low voltage state.
    CR.

    CRI f .. A'B'C'O-E-F

    ALL DIODES IN914 OR EQUIV.

    FIGURE 58. A Large Fan-in" AND" Gate

    9.3 A Bi-stable Multivibrator '..., ..,',.


    A bi-stable multivibrator (an asynchronous RS 10G,F T .J1Ilf
    flip-flop) can be realized as shown in Figure 59. INPUT I,,.
    Positive feedback is provided by resistor R4
    which causes the latching. A positive pulse at FIGURE 61. A Two-amplifier Trigger Flip Flop

    v' A second trigger flip flop can be made which


    consists of two amplifiers and also provides a
    Rl
    1M complimentary output. This connection is
    R'
    15DK shown in Figure 61.
    ReSET

    oTL Rl
    vo
    9.5 Monostable Multivibrators (One-shots)
    7SDK
    SET

    oTI, Monostable multivibrators can be made using


    one or two of the amplifiers of the LM3900.
    FIGURE 59. A Bi-stable Multivibrator In addition, the output can be designed to be

    AN72-27
    either high or low in the quiescent state. Fur- value. This exists in free-running oscillators
    ther, to increase the usefulness, a one-shot can where after a particular output level has been
    be designed which triggers at a particular DC reached a reset pulse must be generated to re-
    input voltage level to serve the dual role of pro- cycle the oscillator. This double function is
    viding first a comparator and then a pulse provided with the circuit of Figure 63. The
    generator.
    v'

    9.5.1 A Two·amplifier One-shot C1 Rl


    lDOpF 15M

    A circuit for a two-amplifier one-shot is shown


    in Figure 62. As the resistor, R2, from y+ to
    the (-) input is smaller than Rs (from y+ to
    the (+) input). amplifier 2 will be biased to a
    low-voltage output in the quiescent state. As a

    R'
    1M

    V'N
    TRIPS AT
    VIN ~ 08V'
    V1N mU1tlali
    V' ·-DBV· P'IOf
    to 12

    FIGURE 63. A One-shot Multivibrator with an Input


    Comparator

    FIGURE 62. A On_ot Multivibrator resistors Rs and Rs of amplifier 1 provide the


    inputs to a comparator and, as shown, an input
    signal. YIN, is compared with the supply volt-
    result, no current is supplied to the (-) input age, Y+. The output voltage of amplifier 1 is
    of amplifier 1 (via R3 ) which causes the output normally in a high voltage state and will fall
    of this amplifier to be in the high voltage state. and initiate the generation of the output pulse
    Capacitor C, therefore has essentially the full
    when YIN is Rs/Rs y+ or approximately 80% of
    V+ supply voltage across it (y+ - 2 VeE ). Now
    Y+. To keep VIN from disturbing the pulse
    when a differentiated trigger (due to C2) generation it is required that YIN fall to less
    causes amplifier 1 to be driven ON (output than the trip voltage prior to the termination of
    voltage drops to essentially zero volts) this the output pulse. This is the case when this
    negative transient is coupled (via C,) to the H circuit is used to generate a reset pulse and
    input of amplifier 2 which causes the output of therefore this causes no problems.
    this amplifier to be driven high (to positive
    saturation). This condition remains while C,
    discharges via (R,) from approximately y+ to
    approximately Y+I2. This' time interval is the 9.5.3 A One·amplifier One·shot (Positive Pulse)
    pulse width (PW). After C, no longer diverts
    sufficient current of R2 away from the (-) in- A one-shot circuit can be realized using only
    put of amplifier 2 (Le., C, is discharged to one amplifier as shown in Figure 64.
    approximately Y+12 Y) the stable DC state is
    restored-amplifier 2 output low and ampli-
    fier 1 output high.
    CRI

    This circuit can be rapidly re-triggered due to R3


    1M
    the action of the diode. CR,. This re-charges
    C, as amplifier 1 drives full output current
    capability (approximately 10 mAl through C" T"
    CR, and into the saturated (-) input of ampli-
    fier 2 to ground. The only time limit is the TRIGGER~ f-'vv.-<lI----","N---'
    10 mA available from amplifier 1 and the value INPUT """'"I
    C2
    of' C,. If a rapid reset is not required, CR, 100pF

    can be omitted.
    FIGURE 64. A One-amplifier One-shot (Positive
    Outputl
    9.5.2 A Combination One·shot/Comparator
    Circuit The resistor R2 keeps the output in the low volt-
    age state. A differentiated positive trigger
    In many applications a pulse is required if a causes the output to switch to the high voltage
    DC input signal exceeds a predetermined state and resistor Rs latches this state. The

    AN72·28
    capacitor, C 1, charges from essentially voltage must be larger than VBE , but there is no
    ground to approximately V+/4 where the cir- upper limit as long as the input resistor is large
    cuit latches back to the quiescent state. The enough to guarantee that the input current will
    diode, CR1, is used to allow a rapid re-triggering. not exceed 200}.J. A.

    9.5.4 A One-amplifier One-shot (Negative Pulse)


    9.6.2 A Comparator for Negative Input Voltages
    A one-amplifier one-shot multivibrator which
    has a quiescent state with the output high Adding a common-mode biasing network to the
    and which falls to zero volts for the pulse dura- comparator in Figure 66 makes it possible
    tion is shown in Figure 65. to compare voltages between zero and one volt
    as well as the comparison of rather large nega-
    tive voltages, Figure 67. When working with
    CR1
    negative voltages, the current supplied by the
    v,:lJ common-mode network must be large enough
    to satisfy both the current drain demands of the
    input voltages and the bias current requirement
    of the amplifier.

    v'

    NO NEGATIVE
    TRIGGER~ VOLTAGE LIMIT
    INPUT~ IF PROPERLY
    C2 BIASED
    1110pF
    1.5M 15M

    FI GURE 65. A One-amplifier One-shot (Negative lOOK


    "VREF
    Output) t{)2V DC
    vo
    lOOK
    +VIN
    The sum of the currents through R2 and R3
    keeps the (-) input at essentially ground. This
    causes Vo to be in the high voltage state. A FIGURE 67. A Non-inverting Low-voltage Comparator
    differentiated negative trigger waveform
    causes the output to switch to the low voltage
    state. The large voltage across C1 now pro-
    vides input current via R1 to keep the output 9.6.3 A Power Comparator
    low until C1 is discharged to approximately
    V+/10. At this time the output switches to
    When used in conjunction with an external
    the stable high voltage state.
    transistor, this power comparator will drive
    loads which require more current than the IC
    If the R4 C 2 network were moved to the (-) amplifier is capable of supplying. Figure 68
    input terminal, the circuit will trigger on a
    shows a non-inverting comparator which is
    differentiated positive trigger waveform.
    capable of driving a 12V, 40 mA panel lamp.

    v'
    9.6 Comparators

    The voltage comparator is a function required LAMP

    for most system operations and can easily be


    performed by the LM3900. Both an inverting
    and a non-inverting comparator can be obtained.

    9.6.1 A Comparator for Positive Input Voltages FIGURE 68. A Non·inverting Power Comparator

    The circuit in Figure 66 is an inverting compar-


    ator. To insure proper operation, the reference
    9.6.4 A More Precise Comparator
    ,. A more precise comparator can be designed by
    using a second amplifier such that the input
    ,.
    +VIlEFo-"""""-"i~
    voltages of the same type of inputs are com-
    pared. The (-) input voltages of two amplifiers
    are naturally more closely matched initially
    and track well with temperature changes. The
    FIGURE 66. An Inverting Voltage Comparator comparator of Figure 69 uses this concept.

    AN72-29
    v' current mirror, the output will switch to the
    high limit. With Vo high, the current demand-
    I(}OK ed by the mirror is increased by a fixed amount,
    12 , As a result, the 13 required to switch the
    output increases this same amount. Therefore,
    1M
    the switch points are determined by selecting
    resistors which will establish the required cur-
    rents at the desired input voltages. Reference
    current (I,) and feedback current (1 2 ) are set by
    the following equation.
    '-----'NI,,-------+v.
    1M

    1M

    FIGURE 69. A More Precise Comparator

    The current established by VREF at the invert- By adjusting the values of R B , R F , and R 1N ,
    ing input of amplifier 1 will cause transistor the switching values of V 1N may be set to any
    0, to adjust the value of VA to supply this levels desired.
    current. This value of VA will cause an equal
    current to flow into the non-inverting input of
    amplifier 2. This current corresponds more The non-inverting Schmitt-Trigger works in the
    exactly to the reference cu rrent of amplifier 1. same way except that the input voltage is ap-
    plied to the (+) input. The range of V1N may be
    very large when compared with the operating
    A differential input stage can also be added voltage of the amplifier.
    to the LM3900 (see section 10.16) and the re-
    sulting circuit can provide a precision compar-
    ator circuit.
    10.0 SOME SPECIAL CIRCUIT APPLICATIONS

    9.7 Schmitt-Triggers This section contains various special circuits


    which did not fit the order of things or which
    are one-of-a-kind type of applications.
    Hysteresis may be designed into comparators
    which use the LM3900 as shown in Figure 70.
    10.1 Current Sources and Sinks

    '·til
    The 'amplifiers of the LM3900 can be used in
    feedback loops which regulate the current in
    external PNP transistors to provide current
    8 9.5 sources or in external NPN transistors to pro-
    vide current sinks. These can be multiple
    tal INVERTING
    sources or single sources which are fixed in
    value or made voltage variable.

    10.1.1 A Fixed Current Source

    A multiple fixed current source is provided by


    the circuit of Figure 71. A reference voltage
    (b) NON·INVERTING (1 Voc ) is established across resistor R3 by the
    resistive divider (R3 and R4 ). Negative feed-
    back is used to cause the voltage drop across
    FIGURE 70. Schmitt-Triggers
    R, to also be 1 Voc. This controls the emitter
    current of transistor 0, and if we neglect the
    The lower switch point for the inverting small current diverted into the (-) input via the
    Schmitt-Trigger is determined by the amount of 1M input resistor (13.5 fJA) and the base current
    current flowing into the positive input with of 0, and 02 (an additional 2% loss if the f3 of
    the output voltage low. When the input cur- these transistors is 100), essentially this same
    rent, 13 , drops below the level required by the current is available out of the collector of 0 1 ,

    A~J72-30
    Larger input resistors can be used to reduce
    current loss and a Darlington connection can be
    used to reduce errors due to the j3 of 0,.

    (+1 5Vocl

    '------~D5VDC

    .J "'
    1M
    Rl IVae
    '2
    .,
    910ll

    (al ASIMPlE CURRENTSINK

    v·
    (1SVocl

    "
    120K .2
    1M
    FIGURE 71. Fixed Current Sources
    .J
    3D,
    The resistor, R2 , can be used to scale the col-
    lector current of O 2 either above or below the
    1 mA reference value. '---"V\IV--~ .J •

    .,
    J<

    10.1.2 A Voltage Variable Current Source


    (bj REDUCING TEMPERATURE DRIFT OF 10

    A voltage variable current source is shown in FIGURE 73. Fixed Current Sinks
    Figure 72. The transconductance is -(1/R 2 ) as
    the voltage gain from the input terminal to the
    emitter of 0, is -1. For a VIN = 0 Voc the 10.1.4 A Voltage Variable Current Sink
    output current is essentially zero mA DC. The
    resistors R, and Rs guarantee that the ampli-
    A voltage variable current sink is shown in Fig-
    fier can turn OFF transistor 0,.
    ure 74. The output current is 1 mA per volt of
    VIN (as R5 = 1 kQ and the gain is +1). This
    V· circuit provides approximately 0 mA output
    current for V IN = 0 Voc .

    V'

    !~ 10: 1 mAIVOlTIV'1II1

    '----'VVIr--....
    FIGURE 72. A Voltage Controlled Current Source
    lOOK
    .,
    1K

    10.1.3 A Fixed Current Sink


    FIGURE 74. A Voltage Controlled Current Sink
    Two current sinks are shown in Figure 73. The
    circuit of Figure 73(a) requires only one resistor
    and supplies an output current which is direct- 10.2 Operation From ±15 VOC Power Supplies
    ly proportional to this R value. A negative
    temperature coefficient will result due to the
    0.5 Voc reference being the base-emitter If the ground pin (no. 7) is returned to a nega-
    junction voltage of the (-) input transistor. If tive voltage and some changes are made in the
    this temperature coefficient is objectionable, biasing circuits, the LM3900 can be operated
    the circuit of Figure 73(b) can be employed. from ±15V oc power supplies.

    AN72-31
    10.2.1 An AC Amplifier Operating with been added for temperature compensation of
    ±15 Vec Power Supplies this biasing. Now, if we include these biasing
    resistors, we have a DC amplifier with the input
    An AC coupled amplifier is shown in Figure 75. biased at approximately zero volts. If feedback
    The biasing resistor, Rs ' is now returned to resistors are added around this biased ampli-
    ground and both inputs bias at one VSE above fier we get the schematic shown in Figure 77.
    the -VEE voltage (approximately -15 V ec ).
    "ON
    200K t'--,
    R' - .....
    1M I ...... ,

    r
    Vo
    I ,-
    I ;'
    C..
    D.l,11F
    + """'BIASED
    ..... / LM39DO FROM
    Co

    f
    fiGURE 16

    i
    O.OI.uF

    FIGURE 77. A DC Amplifier Operating with ± 15 Vec


    l',
    ,t ,.
    R, -15V oc
    This is a standard inverting DC amplifier con-
    nection. The (+) input is "effectively" at ground
    and the biasing shown in Figure 76 is used to
    FIGURE 75. An AC Amplifier Operating with take care of DC levels at the inputs.
    ± 15 Vec
    10.3 Tachometers
    With R f = RB , Vo will bias at approximately
    o Vec to allow a maximum output voltage Many pulse averaging tachometers can be built
    swing. As pin 7 is common to all four of the using the LM3900. Inputs can be voltage
    amplifiers which are in the same package, the pulses, current pulses or the differentiated
    other amplifiers are also biased for operation transitions of squarewaves. The DC output
    off of ±15 Vec . voltage can be made to increase with increas-
    ing input frequency, can be made proportional
    to twice the input frequency (frequency doub-
    10.2.2 A DC Amplifier Operating with ling for reduced output ripple), and can also be
    made proportional to either the sum or the dif-
    ±15 Vec Power Supplies
    ference between two input frequencies. Due to
    the small bias current and the high gain of the
    Biasing a DC amplifier is more difficult and
    LM3900, the transfer function is linear between
    requires that the ± power supplies be comple-
    the saturation states of the amplifier.
    mentary tracking (Le., I+Vcc I = I -VEE I)· The
    operation of this biasing can be easier under-
    stood if we start by first considering the ampli-
    fier without including the feedback resistors, 10.3.1 A Basic Tachometer
    as shown in Figure 76. If Rl = R2 = R3 + R4 =
    If an RC averaging network is added from the
    1 M~ and I+Vcc I = I-VEE I, then the current,
    output to the (-) input, the basic tachometer
    of Figure 78 results Current pulse inputs will
    +15V Dc * provide the desired transfer function shown on
    the figure. Each input current pulse causes a
    "'
    1M CR'
    small change in the output voltage. Neglecting
    the effects of R we have
    ,I
    VIN t ••
    1M
    (INVERTING O--+--"M-i
    INPUT)
    Vo

    ,t The inclusion of R gives a discharge path so


    the output voltage does not continue to inte-
    grate, but rather provides the time dependency
    R'
    SODK which is necessary to average the input pulses.
    If an additional signal source is simply placed
    in parallel with the one shown, the output be-
    ·COMPLEMENTARY TRACKING
    comes proportional to the sum of these input
    frequencies. If this additional source were ap-
    FIGURE 76. DC Biasing for ± 15 Vec Operation plied to the (-) input, the output voltage would
    be proportional to the difference between these
    input frequencies. Voltage pulses can be con-
    I, will bias V1N at zero volts DC (resistor R4 can verted to current pulses by using an input re-
    be used to adjust this). The diode, CR 1 , has sistor. A series isolating diode should be used if

    AN72·32
    When the input voltage goes high, the charging
    current of C IN, ICHG enters the (+) input, is mir-
    rored about ground and is drawn from the RC
    averaging network into the (-) input terminal.
    When the input voltage goes back to ground,
    the discharge current of C IN , IOISCHARGE will
    VODe
    also be drawn from the RC averaging network
    via the now conducting diode, CRI' This full
    wave action causes two current pulses to be
    drawn through the RC averaging network for
    each cycle of the input frequency.

    FIGURE 78. A Basic Tachometer

    a signal is applied to the (-) input to prevent


    :JlJL.'''''"'j'' CRI
    \:"~ VODe

    loading during the low voltage state of this


    input signal.

    10.3.2 Extending VOUT (Minimum) to Ground


    ····f· ~ '. ,
    The output voltage of the circuit of Figure 78 FIGURE 80. A Frequency Doubling Tachometer
    does not go to ground level but has a minimum
    value which is equal to the VBE of the (-) input
    (0,5 Voc). If it is desired that the output volt- 10.4 A Squaring Amplifier
    age go exactly to ground, the circuit of Fig-
    ure 79 can be used. Now with VIN = 0 Voc , A squaring amplifier which incorporates sym-
    Vo = OVoc due to the addition of the common- metrical hysteresis above and below the zero
    mode biasing resistors (180 kl1). The diode, output state (for noise immunity) is often
    needed to amplify the low level signals which
    are provided by variable reluctance transducers.
    In addition, a high frequency roll-off (lOW pass
    characteristic) is desirable both to reduce the
    natural voltage buildup at high frequencies and
    to also filter high frequency input noise disturb-
    ances. A simple circuit which accomplishes
    this function is shown in Figure 81. The input

    V'
    Y,.
    R"
    'M
    FIGURE 79. Adding Biasing to Provide Vo = 0 VOC

    CRI, allows the output to go below VCE SAT of


    the output, if desired (a load is required to pro-
    vide a DC path for the biasing current flow via
    the R of the averaging network). IDM
    R"

    V'
    10.3.3 A Frequency Doubling Tachometer
    FIGURE 81. A Squaring Amplifier with Hysteresis

    To reduce the ripple on the DC output voltage,


    the circuit of Figure 80 can be used to effec- voltage is converted to input currents by using
    tively double the input frequency. Input pulses the input resistors, RIN. Common-mode biasing
    are not required, a squarewave is all that is is provided by RBI and R B2 . Finally positive
    needed. The operation of the circuit is to aver- feedback (hysteresis) is provided by R f . The
    age the charge and discharge transient currents large source resistance, RIN, provides a low pass
    of the input capacitor, CIN . The resistor, RIN, is filter due to the "Miller-effect" input capaci-
    used to convert the voltage pulses to current tance of the amplifier (approximately 0.002IlF).
    pulses and to limit the surge currents (to ap- The amount of hysteresis and the symmetry
    proximately 200 uA peak-or less if operating about the zero volt input are controlled by the
    at high temperatures). positive feedback resistor, R f , and RBI and RS2 .

    AN72·33
    With the values shown in Figure 81 the trip 10.7 A Low Drift Sample and Hold Circuit
    voltages are approximately ±150 mV centered
    about the zero output voltage state of the trans- In sample and hold applications a very low
    ducer (at low frequencies where the low pass input biasing current is required. This is usu-
    filter is not attenuating the input signal). ally achieved by using a FET transistor or a
    special low input current IC op amp. The exist-
    10.5 A Differentiator ance of many matched amplifiers in the same
    package allows the LM3900 to provide some
    An input differentiating capacitor can cause the interesting low "equivalent" input biasing cur-
    input of the LM3900 to swing below ground rent applications.
    and actuate the input clamp circuit. Again,
    common-mode biasing can be used to prevent
    this negative swing at the input terminals of the 10.7.1 Reducing the "Effective" Input Biasing
    LM3900. The schematic of a differentiator Current
    circuit is shown in Figure 82. Common-mode
    One amplifier can be used to bias one or more
    additional amplifiers as shown in Figure 84.
    y'

    la

    -
    WEFFECTIVE~

    R1 .. R2
    FIGURE 82. A Diff.rentiator Circuit

    biasing is provided by RB, and RB2 . The feed-


    back resistor, Rf , is one-half the value of RIN AUXllliARV AMP FOR
    BIASING AMP 1
    so the gain is 1/2. The output voltage will bias
    at V+/2 which thereby allows both a positive
    and a negative swing above and below this bias
    point. The resistor, R1N, keeps the negative FIGURE 84. Reducing IB "Effective" to Zero
    swing isolated from the (-) input terminal and
    therefore both inputs remain biased at +VBE .
    The input terminal of Amp. 1 will only need to
    supply the signal current if the DC biasing cur-
    10.6 A Difference Integrator
    rent, I B" is accurately supplied via R,. The
    adjustment, R3, allows a zeroing of "Ie effec-
    A difference integrator is the basis of many of
    tive" but Simply omitting R3 and letting R, "
    the sweep circuits which can be realized uSing
    R2 (and relying on amplifier symmetry) can
    the LM3900 operating on only a single power
    cause Ie "effective" to be less than Ie 110
    supply voltage. This circuit can also be used
    (3 nA). This is useful in circuit applications
    to provide the time integral of the difference
    such as sample and hold, where small values of
    between two input waveforms. The schematic
    Ie "effective" are desirable.
    of the difference integrator is shown in Fig-
    ure 83.
    10.7.2 A Low Drift Ramp and Hold Circuit

    The input current reduction technique of the


    1M previous section allows a relatively simple
    ramp and hold circuit to be built which can be
    ramped up or down or allowed to remain at
    1M
    ·y,o---w_~ any desired output DC level in a "hold" mode.
    This is shown in Figure 85. If both inputs are
    at 0 Voc the circuit is in a hold mode. Raising
    FIGURE 83. A Difference Integrator either input will cause the DC output voltage to
    ramp either up or down depending on which
    one goes positive. The slope is a function of the
    This is a useful component for DC feedback magnitude of the input voltage and additional
    loops as both the comparison to a reference inputs can be placed in parallel, if desired, to
    and the integration take place in one amplifier. increase the input control variables.

    AN72·34
    10.8 Audio Mixer or Channel Selector
    RAMPDDWIII

    : J. o-~'",'"''v-.'"+'-+-I
    V,

    The multiple amplifiers of the LM3900 can be


    RAMP UP
    used for audio mixing (many amplifiers simUl-
    " r:"o-~WV-~ taneously providing signals which are added to
    generate a composite output signal) or for
    channel selection (only one channel enabled at
    a time). Three amplifiers are shown being
    summed into a fourth amplifier in Figure 87.

    FIGURE 85. A Low-drift Ramp and Hold Circuit

    10.7.3 Sample·hold and Compare with New


    +VIN
    An example of using the circuit of the previous
    section is shown in Figure 86 where clamping
    transistors, 0 1 and O2, put the circuit in a hold
    "
    mode when they are driven ON. When OFF the
    output voltage of Amp. 1 can ramp either up or
    down as needed to guarantee that the output
    voltage of Amp. 1 is equal to the DC input
    voltage which is applied to Amp. 3. Resistor
    R1 provides a fixed "down" ramp current which
    is balanced or controlled via the comparator,
    Amp. 3, and the resistor R4 . When 01 and O2
    are OFF a feedback loop guarantees that V01
    (from Amp. 1) is equal to +V'N (to Amp. 3).
    Amplifier 2 is used to supply the input biasing
    current to Amp. 1.
    FIGURE 87. Audio Mixing or Selection

    If a power amplifier were available, all four


    amplifiers could feed the single input of the
    power amplifier. For audio mixing all ampli-
    fiers are simulatneously active. Particular
    amplifiers can be gated OFF by making use of
    DC control signals which are applied to the (+)
    inputs to provide a channel select feature. As
    shown on Figure 87, Amp. 3 is active (as sw 3
    is closed) and Amps. 1 and 2 are driven to
    positive output voltage saturation by the 5.1 M
    which is applied to the (+) inputs. The DC out-
    put voltage bias level of the active amplifier
    is approximately 0.8 VDC and could be raised if
    FIGURE 86. Sample·hold and Compare with New larger signal levels were to be accommodated.
    +V'N Frequency shaping networks can be added
    either to the individual amplifiers or to the
    The stored voltage appears at the output, V 01 common amplifier, as desired. Switching tran-
    of Amp. 1, and as Amp. 3 is active, a continued sients may need to be filtered at the DC control
    comparison is made between VOl and V'N and points if the output amplifier is active during
    the output of Amp. 3 fully switches based on the switching intervals.
    this comparison. A second loop could force
    V, N to be maintained at the stored value (V01 )
    10.9 A Low Frequency Mixer
    by making use of V02 as an error signal for this
    second loop. Therefore, a control system could
    be manually controlled to bring it to a particu- The diode which exists at the (+) input can be
    lar operating condition; then, by exercising the used for non-linear Signal processing. An ex-
    hold control, the system would maintain this ample of this is a mixer which allows two input
    operating condition due to the analog memory frequencies to produce a sum and difference
    provided by V01 ' frequency (in addition to other high frequency

    AN72·35
    components). Using the amplifier of the feedback resistor is constantly loading C in ad-
    LM3900, gain and filtering can also be accom- dition to the current drawn by the circuitry
    plished with the same circuit in addition to the which samples Vo. These loading effects must
    high input impedance and low output imped- be considered when selecting a value for C.
    ance advantages. The schematic of Figure 88
    shows a mixer with a gain of 10 and a low pass The biasing resistor, RB ' allows a minimum DC
    single pole filter (1 M and 150 pF feedback ele- voltage to exist across the capacitor and the
    ments) with a corner frequency of 1 kHz. With input resistor, RI N' can be selected to provide
    gain to the input signal.

    1M 10.11 Power Circuits


    v'

    The amplifier of the LM3900 will source a maxi-


    mum current of approximately 10 mA and will

    f~f
    sink maximum currents of approximately
    v, 80 mA (if overdriven at the (-) input). If the
    I output is driven to a saturated state to reduce
    device dissipation, some interesting power cir-

    v'l"
    V,;"V 2 -=
    cuits can be realized. These maximum values
    of current are typical values for the unit opera-
    ting at 25° C and therefore have to be de-rated
    for reliable operation. For fully switched oper-
    ation, amplifiers can be paralleled to increase
    FIGURE 88. A Low Frequency Mixer cu rrent capabi Iity.

    one signal larger in amplitude, to serve as the


    local oscillator input (V,)' the transconduc- 10.11.1 Lamp and/or Relay Drivers (5: 30 rnA)
    tance of the input diode is gated at this rate (f,).
    A smaller signal (V2 ) can now be added at the Low power lamps and relays (as reed relays)
    second input and the difference frequency is can be directly controlled by making use of the
    filtered from the composite resulting waveform larger value of sink current than source cur-
    and is made available at the output. Relatively rent. A schematic is shown in Figure 90 where
    high frequencies can be applied at the inputs as the input resistor, R, is selected such that V1N
    long as the desired difference frequency is supplies at least 0.1 mA of input current.
    within the bandwidth capabilities of the ampli-
    fier and the RC low pass filter.
    v'
    10.10 A Peak Detector

    A peak detector is often used to rapidly charge


    a capacitor to the peak value of an input wave-
    ON
    form. The voltage drop across the rectifying
    diode is placed within the feedback loop of an ,.:r-L
    OFF OFF 20rnA 12V LAMP OR
    op amp to prevent voltage losses and tempera- 14mA lDV LAMP OR
    ture drifts in the output voltage. The LM3900 REED RELAY COIL

    can be used as a peak detector as shown in


    Figure 89. The feedback resistor, Rf , is kept
    FIGURE 90. Sinking 20 to 30 rnA Loads

    10.11.2 Lamp and/or Relay Drivers ( 5: 300 rnA)


    R.
    c"
    To increase the power capability, an external
    >---11*-....- ....-0 v, transistor can be added as shown in Figure 91.
    The resistors R, and R2 hold 0, OFF when the
    output of the LM3900 is high. The resistor, R2 ,
    limits the base drive when 0, goes ON. It is
    required that pin 14 tie to the same power
    supply as the emitter of 0, to guarantee that
    0, can be held OFF. If an inductive load is
    FIGURE 89. A Peak Detector used, such as a relay coil, a backswing diode
    should be added to prevent large inductive
    small (1 MI1) so that the 30. flA base current voltage kicks during the switching interval, ON
    will cause only a +30 mV error in Vo. This to OFF.

    AN72·36
    V' II 5V ot ~
    10.12.1 A High Voltage Inverting Amplifier

    An inverting amplifier with an output voltage


    """ swing from essentially 0 VOC to +300 Voe is
    shown in Figure 93. The transistor, must a"
    be a high breakdown device as it will have the
    full HV supply across it. The biasing resistor
    R3 is used to center the transfer characteristic
    and the gain is the ratio of R2 to R,. The load
    resistor, R L , can be increased, if desired, to
    reduce the HV current drain.

    FIGURE 91. Boosting to 300 rnA Loads ~flV (~300VDC)

    10.11.3 Positive Feedback Oscillators A,


    R1 A2 510K
    330K 10M

    If the LM3900 is biased into the active region


    and a resonant circuit is connected from the
    output to the (+) input, a positive feedback os-
    cillator results. A driver for a piezoelectric
    transducer (a warning type of noise maker) is
    shown in Figure 92. The resistors R, and R2
    bias the output voltage at V+/2 and keep the
    amplifier active. Large currents can be entered
    into the (+) input and negative currents (or V~ (+15Vocl

    currents out of this terminal) are provided by

    vor:::~o
    the epi-substrate diode of the IC fabrication.

    R1
    lOOK
    o +5 +10

    FIGURE 93. A High Voltage Inverting Amplifier

    10.12.2 A High Voltage Non·inverting Amplifier

    AUDIBLE OUTPUT A high voltage non-inverting amplifier is shown


    WARNING SOUND
    in Figure 94. Common-mode biasing resistors
    V~ (15V o d

    V+I+l,V oc l

    FIGURE 92: Positive Feedback Power Oscillators +H V 1+ JOOV oc ~

    When one of the amplifiers is operated in this ",1M


    RJ
    large negative input current mode, the other TOM

    amplifiers will be disturbed due to interaction.


    Multiple sounds may be generated as a result of
    using two or more transducers in various com-
    RJ
    binations, but this has not been investigated. 330K
    Other two-terminal RC, RLC or piezoelectric
    resonators can be connected in this circuit to
    produce an oscillator.
    v,I:::1 ~'30
    10.12 High Voltage Operation
    o lL"f--:
    The amplifiers of the LM3900 can drive an ex-
    ternal high voltage NPN transistor to provide
    a larger output voltage swing (as for an elec- FIGURE 94. A High Voltage Non·inverting Amplifier
    trostatic CRT deflection system) or to operate
    off of an existing high voltage power supply
    (as the +98 Voe rectified line). Examples of (R 2) are used to allow VIN to go to 0 Voc. The
    both type of circuits are presented in this output voltage, Va , will not actually go to zero
    section. due to R E , but should go to approximately

    AN72·37
    0.3 Voc. Again, the gain is 30 and a range of 3.) The input impedance is high (1 MS1).
    the input voltage of from 0 to +10 Voc will 4.) A large closed loop gain is easily achieved
    cause the output voltage to range from approxi- (80 dB).
    mately 0 to +300 Voc . 5.) The slow start-up delay is eliminated.
    6.) Two channels are available in one package.

    10.12.3 A Line Operated Audio Amplifier


    Again, the pin 14 voltage must be at least as
    An audio amplifier which operates off a high as the power supply used at the emitter of
    +98 Voc power supply (the rectified line volt- 0, to guarantee an OFF control for 0,.
    age) is often used in consumer products. The
    external high voltage transistor, 0, of Fig-
    ure 95, is biased and controlled by the LM3900.
    The magnitude of the DC biasing voltage which 10.14 Temperature Sensing
    appears across the emitter resistor of 0, is con-
    trolled by the resistor which is placed from the The LM3900 can be used to monitor the junc-
    (-) input to ground. tion temperature of the monolithic chip as
    shown in Figure 97(a). Amp. 1 will generate an
    +9SVoc
    output voltage which can be designed to
    undergo a large negative temperature change
    by design of R, and R2 . The second amplifier

    5K llcuJ compares this temperature dependent voltage


    with the power supply voltage and goes high
    at a designed maximum Tj of the IC.

    ~ I BIAS20mA
    10M
    l.)V oc
    R2

    RJ
    10M 62 ~,

    R1
    v,
    R4
    v' 0---,\1\1\_
    FIGURE 95. A Line Operated Audio Amplifier

    T,SENSE COMPARATOR

    10.13 A Dual·channel Class-A Driver for Auto


    Radios (a) Ie T, MONITOR

    A germanium power transistor is widely used in


    automotive class A audio amplifiers. As shown v'
    in Figure 96, two amplifiers can be cascaded

    -- .... R1

    R2

    RJ
    vo
    R4
    v'

    R5
    COMPARATOR
    -=-
    TEMP SENSE -=-
    (b) REMOTE TEMPERATURE SENSE

    I,. 1M
    A,IO'8
    NO """""lH'OuG" '"'" "
    0">< CHON,,, '.,,,,,,,[
    FIGURE 97. Temperature Sensing

    FIGURE 96. A Dual·channellC Driver for Class A


    Car Radios For remote sensing, an NPN transistor, 0, of
    Figure 97(b), is connected as an N VSE genera-
    to bias and to control the 2N176 power transis- tor (with R3 and Rs) and is biased via R, from
    tor. This circuit has many advantages over the the power supply voltage, V+ The LM3900
    standard discrete circuit which is used as: again compares this temperature dependent
    voltage with the supply voltage and can be
    1.) No electrolytic capacitors are used. designed to have Va go high at a maximum
    2.) The ripple on the power supply line is temperature of the remote temperature sensor,
    rejected. 0,.

    AN72-38
    10.15 A "Programmable Unijunction"

    If a diode is added to the Schmitt-trigger, a v'


    "programmable unijunction" function can be
    obtained as shown in Figure 98. For a low 10M
    input voltage, the output voltage of the LM3900
    is high and CRI is OFF. When the input voltage
    rises to the high trip voltage, the output falls
    to essentially OV and CRI goes ON to discharge
    the input capacitor, C. The low trip voltage

    y'

    MI
    'r l
    ... I FIGURE 99. Adding a Differential Input Stage
    Rc SWEEP I
    y' 0-"""......_------'
    FIGURE 98. A "Programmable Uniiunction" This will increase the gain and reduce the off-
    set voltage. Frequency compensation can be
    added as shown. The BV EBO limit of the input
    must be larger than approximately 1V to guar- transistors must not be exceeded during a large
    antee that the forward drop of CRI added to the differential input condition, or diodes and input
    output voltage of the LM3900 will be less than limiting resistors should be added to restrict
    the low trip Voltage. The discharge current can the input voltage which is applied to the bases
    be increased by using smaller values for R2 to of 0, and O 2 to ±Vo .
    provide pull down currents larger than the
    1.3 mA bias current source. The trip voltages
    of the Schmitt-Trigger are designed as shown in The input common-mode voltage range does
    section 9.7. not go exactly to ground as a few tenths of a
    volt are needed to guarantee that 0, or O 2 will
    not saturate and cause a phase change (and a
    10.16 Adding a Differential Input Stage resulting latch-up). The input currents will be
    small, but could be reduced further, if desired,
    A differential amplifier can be added to the by using FETS for 0, and O2 , This circuit can
    input of the LM3900 as shown in Figure 99. also be operated off of ±15 Voc supplies.

    AN72·39
    »
    zI
    R. T. Smathers, .....
    T. M. Frederiksen, ~
    W. M. Howard
    January 1973
    r-

    LM139/LM239/LM339 A QUAD OF
    ...s:
    W
    INDEPENDENTLY FUNCTIONING COMPARATORS
    to
    "-
    r-
    INTRODUCTION s:
    N
    The LM 139/LM239/LM339 family of devices is a be seen that operation with an input common W
    monolithic quad of independently functioning mode voltage of ground is possible. With both
    to
    comparators designed to meet the needs for a inputs at ground potential, the emitters of 0, and
    "-
    r-
    medium speed, TTL compatible comparator for
    industrial applications. Since no antisaturation
    0 4 will be at one V SE above ground and the emit·
    ters of O 2 and 0 3 at 2 VSE . For switching action
    s:
    W
    clamps are used on the output such as a Baker the base of 0 5 and Os need on Iy go to one V S E W
    clamp or other active circuitry, the output leakage above ground and since O 2 and 0 3 can operate to
    current in the OFF state is typically 0.5 nA. This
    makes the device ideal for system applications
    with zero volts collector to base, enough voltage is
    present at a zero volt common mode input to
    »
    where it is desired to switch a node to ground
    while leaving it totally unaffected in the OFF
    insure comparator action. The bases should not be
    taken more than several hundred millivolts below
    oc:
    state. ground, however, to prevent forward biasing a sub·
    strate diode which would stop all comparator
    »
    c
    Other features include single supply, low voltage
    action and possibly damage the device. If very
    operation with an input common mode range from large input currents were provided. o'TI
    ground up to approximately one volt below Vee.
    The output is an uncommitted collector so it may Figure 2 shows the comparator with the output
    be used with a pull·up resistor and a separate out· stage added. Additional voltage gain is taken z
    put supply to give switching levels from any vol· C
    tage up to 36V down to a VeE SAT above ground m
    (approx. 100 mVl. sinking currents up to 15 mAo +Vcc "0
    In addition it may be used as a single pole switch
    m
    to ground, leaving the switched node unaffected
    Z
    while in the OFF state. Power dissipation with all C
    four comparators in the OF F state is typically
    m
    Z
    4 mW from a single 5V supply (1 mW/comparator). -I
    Vout
    r-
    0(
    CIRCUIT DESCRIPTION 'TI
    Figure 1 shows the basic input stage of one of the
    c:
    Z
    four comparators of the LM139. Transistors 0,
    n
    +Vee
    -I
    o
    Z
    FIGURE 2. Basic LM139 Comparator Z
    C)
    through 0 7 and 0 8 with the collector of 0 8 left
    n
    open to offer a wide variety of possible applica·
    o
    tions. The addition of a large pull·up resistor from
    the collector of 0 8 to either +Vee or any other s:
    "0
    supply up to 36V both increases the LM139 gain
    and makes possible output switching levels to »
    ::D
    match practically any application. Several outputs
    may be tied together to provide an ORing function
    »
    -I
    FIGURE 1. Basic LM139 Input Stage
    or the pull·up resistor may be omitted entirely
    with the comparator then serving as a SPST switch
    o
    ::D
    through 0 4 make up a PNP Darlington differen·
    to ground. en
    tial input stage with 0 5 and 0 6 serving to give Output transistor 0 8 will sink up to 15 mA before
    single·ended output from differential input with the output ON voltage rises above several hundred
    no loss in gain. Any differential input at 0, and millivolts. The output current sink capability may
    0 4 will be amplified causing Os to switch OFF or be boosted by the addition of a discrete transistor
    ON depending on input signal polarity. It can easily at the output.

    AN74-1
    The complete circuit for one comparator of the COMPARATOR CIRCUITS
    LM139 is shown in Figure 3. Current sources 13 Figure 5 shows a basic comparator circuit for
    converting low level analog signals to a high level
    digital output. The output pull-up resistor should
    be chosen high enough so as to avoid excessive
    power dissipation yet low enough to supply
    enough drive to switch whatever load circuitry is
    used on the comparator output. Resistors R, and
    R2 are used to set the input threshold trip voltage
    (V REF ) at any value desired within the input
    common mode range of the comparator.

    V""-I-"\A o--+-<>-i
    INPUT
    :JlIT ov
    RpUlL_UP
    'V"

    FIGURE 3. Complete LMl39 Comparator Circuit V OUT

    and 14 are added to help charge any parasitic


    capacitance at the emitters of 0, and 0 4 to im-
    prove the slew rate of the input stage. Diodes D,
    and D2 are added to speed up the voltage swing FIGURE 5. Basic Comparator Circuit
    at the emitters of 0, and O 2 for large input volt-
    age swings.
    Comparators with Hysteresis
    Biasing for current sources I, through 14 is shown The circuit shown in Figure 5 suffers from one
    in Figure 4. When power is first applied to the basic drawback in that if the input signal is a
    circuit, current flows through the JFET 0'3 to slowly varying low level signal, the comparator
    bias up diode D5 . This biases transistor 0'2 which may be forced to stay within its linear region
    turns ON transistors 0 9 and 0'0 by allowing a path between the output high and low states for an
    to ground for their base and collector currents. undesireable length of time. If this happens, it runs
    the risk of oscillating since it is basically an uncom·
    +Vcc pensated, high gain op amp_ To prevent this, a
    small amount of positive feedback or hysteresis is
    ~~:-:t t t added around the comparator. Figure 6 shows a

    LINE? ? ? +Vcc

    ~ ~
    CURRENT SOURCES
    ~ INPUT

    FIGURE 4. Current Source Biasing Circuit


    ., "
    V IlEf
    Current from the left hand collector of 0 9 flows
    through diodes D3 and D4 bringing up the base of
    FIGURE 6. Comparator with Positive Feedback
    0" to 2 V BE above ground and the em itters of to I mprove Switching Time
    0" and 0'2 to one V BE • 0'2 will then turn OFF
    because its base emitter voltage goes to zero. This comparator with a small amount of positive feed-
    is the desired action because 0 9 and 0'0 are back. In order to insure proper comparator action,
    biased ON through 0", D3 and D4 so 0'2 is no the components should be chosen as follows:
    longer needed. The "bias line" is now sitting at a
    V BE below +V cc which is the voltage needed to RpULL_UP < R LOAD and
    bias the remaining current sources in the LM 139
    which will have a constant bias regardless of+Vcc R, > RpuLL.uP
    fluctuations. The upper input common mode This will insure that the comparator will always
    voltage is Vee minus the saturation voltage of switch fully up to +Vcc and not be pulled down
    the current sources (approximately 100 mV) by the load or feedback. The amount of feedback
    minus the 2 V BE of the input devices 0, and is chosen arbitrarily to insure proper switching
    O2 (or 0 3 and 0 4 ), with the particular type of input signal used. If the

    AN74-2
    output swing is 5V, for example, and it is desired When the input voltage V IN , rises above the refer-
    to feedback 1% or 50 mV, then R, "" 100 R2 . To ence voltage (V IN > V A'l. voltage, Vo , will go low
    describe circuit operation, assume that the in- (Vo = GND). The lower input trip voltage, V A2,
    verting input goes above the reference input is now defined by:
    (V IN > V REF ). This will drive the output, V o ,
    towards ground which in turn pulls V REF down
    through R,. Since V REF is actually the non-
    inverting input to the comparator, it too will drive
    the output towards ground insuring the fastest or
    possible switching time regardless of how slow the
    input moves. If the input then travels down to (2)
    V REF , the same procedure will occur only in the
    opposite direction insuring that the output will be
    driven hard towards +Vee. When the input voltage, VIN , decreases to V A2 or
    lower, the output will a]ain switch high. The total
    Putting hystemsis in the feedback loop of the hysteresis, /:;V A, provided by this network is
    comparator has far more use, however, than defined by:
    simply as an oscillation suppressor. It can be made
    to function as a Schmitt trigger with presettable
    trigger points. A typical circuit is shown in Fig-
    ure 7. Again, the hysteresis is achieved by shifting or, subtracting equation 2 from equation 1
    the reference voltage at the positive input when
    the output voltage Vo changes state. This network

    +Vcc=+15V

    To insure that Vo will swing between +Vee and


    ground, choose:

    RpULL-UP < RLOAD and (4)

    (5)

    RJ
    R2 lM'2 Heavier loading on RpULL.UP (i.e_smaller values of
    1 M~'
    R3 or R LOAD ) simply reduces the value of the
    maximum output voltage thereby reducing the
    amount of hysteresis by lowering the value of
    VoHIGH
    VA" For simplicity, we have assumed in the above
    equations that Vo high switches all the way up to
    +Vee.

    "p""
    VAl
    R3 ':h''''OLOW
    V A2
    To find the resistor values needed for a given set of
    trip points, we first divide equation (3) by equa-
    R2 R2 Rl
    tion (2). This gives us the ratio:

    R, R,
    1+- + -
    FIGURE 7. Inverting Comparator with Hysteresis /:"V A R3 R2
    -- = (6)
    VA2 R3 R3
    requires only three resistors and is referenced to 1+- + -
    the positive supply +Vee of the comparator. R2 R,
    This can be modeled as a resistive divider, R,
    and R2 , between +Vee and ground with the third
    If we let R, = n R3 , equation (6) becomes:
    resistor, R3 , alternately connected to +Vee or
    ground, paralleling either R, or R 2 . To analyze
    this circuit, assume that the input voltage, VIN , at
    the inverting input is less than VA. With (7)
    VIN ~ VA the output will be high (V o = +Ved.
    The upper input trip voltage, V A" is defined by:
    +Vee R2 We can then obtain an expression for R2 from
    VA' = :-::-~=,:-",,=,- equation (1) which gives
    (R,iiR 3 ) + R2

    or
    (8)
    +Vee R2 (R, + R 3 )
    (1)
    VA' = R, R2 + R, R3 + R2 R3

    AN74-3
    The following design example is offered: (V O " GND)_ For the output to switch, V 1N must
    rise up to V 1N , where V 1N , is given by:
    Given: V+ ~ +15V
    RLOAD~ 100krl
    VA' ~ +10V (9)
    V A2 ~ +5V
    To find: R" R 2 , R 3 , RpULL-UP
    As soon as Vo switches to +Vee, V A will step to a
    Solution:
    value greater than V REF which is given by:
    From equation (4) RpULL-UP < R LOAD
    RpULL-UP < 100 krl
    (10)
    so let R PU LL-UP ~ 3 krl

    From equation (5) R3> R LOAD


    To make the comparator switch back to its low
    R3> 100krl state (V o ~ GND) V 1N must go below V REF
    so let before V A will again equal V REF _ This lower trip
    point is now' given by:
    f'..V A 10-5
    From equation (7) n" V A2 = --5- ~ 1
    ( 11)

    and since R, " nR3


    this gives R, ~ 1 R3 " 1 Mrl The hysteresis for this circuit, f'..V 1N , is the differ·
    ence between V 1N , and V 1N 2 and is given by:
    500 kr2
    From equation (8) R 2 " ~--" 1 Mrl
    10 - 1

    These are the values shown in Figure 7. V REF (R, + R 2 ) V REF (R, + R 2 ) - Vee R,
    R2 R2
    The circuit shown in Figure 8 is a non-inverting
    comparator with hysteresis which is obtained with or
    only two resistors, R, and R 2 . In contrast to the
    first method, however, this circuit requires a separ-
    ate reference voltage at the negative input. The
    trip voltage, V A, at the positive input is shifted
    about V REF as Vo changes between +Vee and
    As a design example consider the following:
    ground.
    Given: R LOAD ~ 100 krl
    V 1N , " 10V
    V 1N 2" 5V
    +Vee" 15V
    To find: V REF , R" R2 and R3

    Solution:
    Again choose RpULL-UP < R LOAD to minimize
    loading, so let
    RpULL_UP" 3 krl

    I:
    VoHIGH VoLOW
    ~" f'..V 1N
    From equation (12) R2 Vee

    ,o"lIT
    ·\lcc \I'NI

    R, _ 10-5 _ 1

    RI
    '"H I:: Al
    'w
    V"'Z v,,,,
    R2 - ~-3

    R, ~ ~.£
    o 3
    5 '"
    ':'" V"
    10
    From equation (9) V REF " - - -
    FIGURE 8. Non-Inverting Comparator with Hysteresis
    1+~
    R2
    V 1N
    V REF ~ --1- ~ 7.5V
    Again for analysis, assume that the input voltage, 1 +-
    V 1N , is low so that the output, Vo, is also low 3

    AN74-4
    To minimize output loading choose made very large with respect to Rs
    (R6 ; 2000 Rs). The resultant hysteresis estab-
    R2 > RpULL-UP lished by this network is very small (L'IV, < 10 mV)
    or R 2 > 3 kD. but it is sufficient to insure rapid output
    so let voltage transitions. Diode 0, is used to insure that
    The value of R 1 is now obtained from equa-
    tion (12) +Vcc 15V

    These are the values shown in Figure 8.

    Limit Comparator with Lamp Driver


    R6
    The limit comparator shown in Figure 9 provides a R5 20M
    range of input voltages between which the output 10K

    devices of both LM139 comparators will be OFF.

    FIGURE 10. Zero Crossing Detector


    tV cc

    the inverting input terminal of the comparator


    never goes below approximately -100 mV. As the
    input terminal goes negative, 0, will forward bias,
    clamping the node between R, and R2 to approxi-
    mately -700 mV. This sets up a voltage divider
    with R2 and R3 preventing V 2 from going below
    ground. The maximum negative input overdrive is
    limited by the current handling ability of 0,.

    Comparing the Magnitude of


    Voltages of Opposite Polarity

    The comparator circuit shown in Figure 11 com-


    ., pares the magnitude of two voltages, V 1N , and

    FIGURE 9. Limit Comparator with Lamp Driver

    This will allow base current for 0 1 to flow


    through pull-up resistor R4 , turning ON Q, which
    lights the lamp. If the input voltage, V 1N , changes
    to a value greater than V A or less than VB, one of
    the comparators will switch ON, shorting the base
    of 0 1 to ground, causing the lamp to go OFF. If a FIGURE 11. Comparing the Magnitude of Voltages
    PNP transistor is substituted for 0 1 (with emitter of Opposite Polarity
    tied to +V cel the lamp will light when the input is
    above V A or below VB' V A and V B are arbitrarily V 1N 2 which have opposite polarities. The resultant
    set by varying resistors R" R2 and R3 . input voltage at the minus input terminal to the
    comparator, VA, is a function of the voltage
    Zero Crossing Detector divider from V1N , and V 1N 2 and the values of R 1
    and R2 • Diode connected transistor Q, provides
    The LM139 can be used to symmetrically square protection for the minus input terminal by clamp-
    up a sine wave centered arou nd zero volts by ing it at several hundred millivolts below ground_
    incorporating a small amount of positive feedback A 2N2222 was chosen over a 1 N914 diode
    to improve switching times and centering the input because of its lower diode voltage. If desired,
    threshold at ground (see Figure 10). Voltage a small amount of hysteresis may be added
    divider R4 and Rs establishes a reference voltage, using the techniques described previously. Correct
    V" at the positive input. By making the series magnitude comparison can be seen as follows: Let
    resistance, R, plus R2 equal to R s , the switching V1N , be the input for the positive polarity input
    condition, VI; V2 , will be satisfied when voltage and V 1N 2 the input for the negative polar-
    V 1N ; O. The positive feedback resistor, R6 , is ity_ If the magnitude of V 1N 1 is greater than that

    AN74-5
    of V IN 2 the output will go low (V OUT = GND). If of the comparator in addition to any capacitive
    the magnitude of V IN 1 is less than that of V IN 2. loading at the output which would degrade the
    however. the output will go high (V OUT = Veel. output slew rate.
    To analyze this circuit assume that the output is
    Magnetic Transducer Amplifier
    initially high. For this to be true. the voltage at the
    A circuit that will detect the zero crossings in the negative input must be less than the voltage at the
    output of a magnetic transducer is shown in Fig· positive input. Therefore. capacitor C, is dis·
    ure 12. Resistor divider. R, and R2 • biases the charged. the voltage at the positive input. V AI.
    positive input at +Vee/2. which is well within the will then be given by:
    common mode operating range. The minus input
    is biased through the magnetic transducer. This (13)

    tV cc

    R1 RPUll_lII' . 2Vee
    lDK then VAl = --3- (14)

    MAGNETIC
    PICK-UP
    II VOUT Capacitor C, will charge up through R4 so that
    when it has charged up to a value equal to V AI.
    the comparator output will switch. With the out·
    "::"
    put Vo = GND. the value of VA is reduced by
    .,
    lDK
    RJ
    !OM
    the hysteresis network to a value given by:

    +Vee
    VA2 = - 3 - (15)

    FIGURE 12. Magnetic Transducer Amplifier using the same resistor values as before. Capacitor
    C, must now discharge through R4 towards
    allows large signal swings to be handled without ground. The output will return to its high state
    exceeding the input voltage limits. A symmetrical (V o = +Veel when the voltage across the capaci·
    square wave output is insured through the positive tor has discharged to a value equal to V A2. For the
    feedback resistor R3 . Resistors R 1 and R2 can be circuit shown. the period for one cycle of oscilla·
    used to set the DC bias voltage at the positive tion will be twice the time it takes for a single RC
    input at any desired voltage within the input circuit to charge up to one half of its final value.
    common mode voltage range of the comparator. The period can be calculated from:

    OSCILLATORS USING THE LM139 V - V -'liRe (16)


    1 - MAX e
    The LM139 lends itself well to oscillator applica·
    tions for frequencies below several megacycles. where
    Figure 13 shows a symmetrical square wave gener·
    ator using a minimum of components. The output 2Vee
    VMAX = --3- (17)

    +lIcc
    and

    R .... Ll_U~ VMAX Vee


    V, =-2-=-3- (18)

    "'
    lOOK

    One period will be given by:

    1
    freq. = 2t, (19)
    "
    lOOK

    or calculating the expenential gives

    1
    -f = 2 (0.694) R 4 C, (20)
    FIGURE 13. Square Wave Generator req.

    Resistors R3 and R4 must be at least 10 times


    frequency is set by the RC time constant of R4 larger than R5 to insure that Vo will go all the
    and C, and the total hysteresis of the loop is set way up to +Vee in the high state. The frequency
    by R, • R2 and R 3 . The maximum frequency is stability of this circuit should strictly be a func·
    limited only by the large signal propagation delay tion of the external components.

    AN74-6
    Pulse Generator with Variable Duty Cycle t2 is then given by:

    The basic square wave generator of Figure 13 can (25)


    be modified to obtain an adjustable duty cycle
    pulse generator, as shown in Figure 14, by pro-
    viding a separate charge and discharge path for These terms will have a slight error due to the fact
    capacitor C 1 - One path, through R4 and 0 1 will that VMAX is not exactly equal to 2/3 Vee but is
    charge the capacitor and set the pulse width (t 1 )- actually reduced by the diode drop to:
    The other path, R5 and O2 , will discharge the
    capacitor and set the time between pulses (t 2 )- By (26)
    varying resistor R 5 , the time between pulses of the
    generator can be changed without changing the
    pulse width. Similarly, by varying R4 , the pulse therefore
    width will be altered without affecting the time
    between pulse>. Both controls will change the fre-
    (27)
    qeuncy of the generator, however. With the values

    and
    tVee

    (28)
    RpULL_Up
    AS 10K
    lOOK DZ
    Crystal Controlled Oscillator

    A simple yet very stable oscillator can be obtained


    by using a quartz crystal resonator as the feedback
    element. Figure 15 gives a typical circuit diagram

    tVee

    RI RpUll_UP
    lOOK XTAl 2K

    R3
    R2 1M
    1M

    R2
    200K

    FIGURE 14. Pulse Generator with Variable Duty Cycle

    R3

    given in Figure 14, the pulse width and time


    CI
    01.u F T 10llK

    between pulses can be found from:


    FIGURE 15. Crystal Controlled Oscillator

    (21b) of this. This value of R1 and R2 are equal so that


    the comparator will switch symmetrically about
    where +Vee12. The RC time constant of R3 and C 1 is set
    to be several times greater than the period of the
    oscillating frequency, insuring a 50% duty cycle by
    (22) maintaining a OC voltage at the inverting input
    equal to the absolute average of the output
    waveform.
    and
    When specifying the crystal, be sure to order series
    resonant along with the desired temperature coef-
    V MAX Vee ficient and load capacitance to be used.
    V1 = - 2 - = - 3 - (23)
    MOS Clock Driver
    which gives The LM139 can be used to provide the oscillator
    and clock delay timing for a two phase MOS clock
    driver (see Figure 16). The oscillator is a standard
    comparator square wave generator similar to the
    (24)
    2 one shown in Figure 13. Two other comparators

    AN74-7
    of the LM 139 are used to establ ish the desired put device of comparator 3 will be OFF which
    phasing between the two outputs to the clock prevents any current from flowing through R2 to
    driver. A more detailed explanation of the delay ground. With a control voltage. Vc. at the input
    circuit is given in the section under "Digital and to comparator 1. a current I, will flow through
    Switching Circuits." R, and begin discharging capacitor C, • at a linear
    rate. This discharge current is given by:

    (29)

    and the discharge time is given by:

    l:N
    I, = C, 6t' (30)

    6V will be the maximum peak change in the


    _15V
    .,~ voltage across capacitor C, which will be set by
    the switch points of comparator 2. These trip
    FIGURE 16. MOS Clock Driver points can be changed by simply altering the ratio
    of RF to Rs. thereby increasing or decreasing the
    amount of hysteresis around comparator 2. With
    RF = 100 krl and Rs = 5 krl. the amount of
    Wide Range VCO
    hysteresis is approximately ±5% which will give
    A simple yet very stable voltage controlled oscilla- switch points of +Vcc12 ± 750 mV from a 30V
    tor using a minimum of external components can supply. (See "Comparators with Hysteresis").
    be rea I ized using three comparators of the
    LM 139. The schematic is shown in Figure 17a. As capacitor C, discharges. the output voltage
    Comparator 1 is used closed loop as an integrator of comparator 1 will decrease until it reaches
    (for further discussion of closed loop operation see the lower trip point of comparator 2. which
    section on Operational Amplifiers) with compara· will then force the output of comparator 2 to
    tor 2 used as a triangle to square wave converter go to its low state (VSQ = GND).
    and comparator 3 as the switch driving the integra·
    tor. To analyze the circuit. assume that com· This in turn causes comparator 3 to go to its low
    parator 2 is its high state (V SQ = +Vcel which state where its output device will be in saturation.
    drives comparator 3 to its high state also. The out· A current 12 can now flow through resistor R2 to

    "Vcc-'+30V

    --"--
    R1
    IOOK!l 3K
    1%
    v,
    011'F
    >-+_~-<lV~
    m --,
    'V"

    R3
    ~+Vccl2

    ,.j
    10K
    R1
    50K "
    10' +Vec ll

    " .".

    -Vec lZ
    (a)

    R1

    .-----V"'Ij.'.....- ............'..' ......


    .<) +Vee

    "
    > ....---<lV~

    (b)

    FIGURE 17. Voltage Controlled Oscillator

    AN74-8
    ground. If the value of R2 is chosen as R1/2 can be selected by setting the Vee to which the
    a current equal to the capacitor discharge current pull·up resistor is connected to any desired level.
    can be made to flow out of C 1 charging it at the
    same rate as it was discharged. By making R2 = R1 /2,
    AND/NAND Gates
    current 12 will equal twice 11 , This is the control
    circuitry which guarantees a constant 50% duty A three input AND gate is shown in Figure 18-
    cycle oscillation independent of frequency or Operation of this gate is as follows: resistor
    temperature. As capacitor C 1 charges, the output divider R1 and R2 establishes a reference voltage
    of comparator 1 will ramp up until it trips at the inverting input to the comparator. The non-
    comparator 2 to its high state (VSQ = +V cc) inverting input is the sum of the voltages at the
    and the cycle will repeat. inputs divided by the voltage dividers comprised of
    R3 , R 4 , Rs and Rs. The output will go high only
    The circuit shown in Figure 17a uses a +30V sup-
    ply and gives a triangle wave of 1.5V peak-to-peak_
    <V e e'15V
    With a timing capacitor, C 1 equal to 500 pF, a
    frequency range from approximately 115 kHz
    down to approximately 670 Hz was obtained with
    a control voltage ranging from 50V down to R1
    J9K
    250 mV_ By reducing the hysteresis around com-
    parator 2 down to ±150 mV (R F = 100 kn, l15mV

    Rs = 1 kn) and reducing the compensating capaci-


    tor C2 down to _001 IlF, frequencies up to 1 MHz VOUT °A_B_C
    may be obtained. For lower frequencies
    (fa :0;: 1 Hz) the timing capacitor, C" should be
    increased up to approximately 1 IlF to insure that
    the charging currents, I, and 12 , are much larger ","
    than the input bias currents of comparator 1_
    ~~~v

    FIGURE lB. Three Input AND Gate


    Figure 17b shows another interesting approach
    to provide the hysteresis for comparator 2_ Two
    identical Zener diodes, Z, and Z2' are used to
    set the trip points of comparator 2. When the tri- when all three inputs are high, causing the voltage
    angle wave is less than the value required to Zener at the non-inverting input to go above that at
    one of the diodes, the resistive network, R, and inverting input. The circuit values shown work for
    R 2 , provides enough feedback to keep the compar- a "0" equal to ground and a "1" equal +15V. The
    ator in its proper state, (the input would otherwise resistor values can be altered if different logic
    be floating)_ The advantage of this circuit is that levels are desired. If more inputs are required,
    the trip points of comparator 2 will be completely diodes are recommended to improve the voltage
    independent of supply voltage fluctuations. The margin when all but one of the inputs are the" 1"
    disadvantage is that Zeners with less than one volt state. This circuit with increased fan·in is shown in
    breakdown voltage are not obtainable. This limits Figure 19.
    the maximum upper frequency obtainable because
    of the larger amplitude of the triangle wave. If a v'
    regulated supply is available, Figure 17a is pre-
    ferable simply because of less parts count and
    lower cost_
    R2
    lOOK
    ..
    lK

    Both circuits provide good control over at least


    VOUT
    two decades in frequency with a temperature
    coefficient largely dependent on the TC of the
    external timing resistors and capacitors. Remember
    that good circuit layout is essential along with
    the .011lF compensation capacitor at the output
    of comparator 1 and the series lOn, resistor and
    O_lIlF capacitor between its inputs, for proper
    operation. Comparator 1 is a high gain amplifier
    I
    used closed loop as an integrater so long leads ALL DIODES
    lN914
    and loose layout should be avoided.
    FIGURE 19. AND Gate with Large Fan·ln
    DIGITAL AND SWITCHING CIRCUITS
    The LM1391ends itself well to low speed «1 MHzl To convert these AND gates to NAND gates
    high level logic circuits. They have the advantage simply interchange the inverting and non-inverting
    of operating with high signal levels, giving high inputs to the comparator. Hysteresis can be added
    noise immunity, which is highly desirable for to speed up output transitions if low speed input
    industrial applications. The output SIgnal level signals are used.

    AN 74-9
    OR/NOR Gates gate having an uncommitted collector output
    The three input OR gate (positive logic) shown in (such as National's DM5401 IDM7401). In addition
    another comparator of the LM139 could also be
    Figure 20 is achieved from the basic AND gate
    used for output strobing, replacing Q, in Figure
    21, if desired. (See Figure 22.)
    +Vcc=15V

    One Shot Multivibrators


    .,
    200K A simple one shot multivibrator can be realized
    using one comparator of the LM139 as shown in
    Figure 23. The output pulse width is set by the

    'V ee

    "
    10apf
    "'M
    ' .. <>--1 H--+----j
    --.fL""
    FIGURE 20. Three Input OR Gate 1"" '0
    10 I,

    simply by increasing R, thereby reducing the


    reference voltage. A logic "1" at any of the inputs
    will produce a logic "1" at the output. Again a
    NOR gate may be implemented by simply revers- FIGURE 23. One Shot Multivibrator
    ing the comparator inputs. Resistor Rs may be
    added for the OR or NOR function at the expense
    values of C 2 and R4 (with R4 > 10 R3 to avoid
    of noise immunity if so desired.
    loading the output). The magnitude of the input
    Output Strobing trigger pulse required is determined by the resistive
    divider R, and R2 . Temperature stability can be
    The output of the LM 139 may be disabled by
    achieved by balancing the temperature coefficients
    adding a clamp transistor as shown in Figure 21. A
    of R4 and C2 or by using components with very
    low TC. In addition, the TC of resistors R, and R2
    +Vcc
    should be matched so as to maintain a fixed refer-
    ence voltage of +Vee/2. Diode D2 provides a rapid
    discharge path for capacitor C 2 to reset the one
    shot at the end of its pulse. It also prevents the
    non-inverting input from being driven below
    > ..... - - Q VOUT
    ground. The output pulse width is relatively inde-
    pendent of the magnitude of the supply voltage
    01 STROBE and will change less than 2% for a five volt change
    in +Vee.

    FIGURE 21. Output Strobing Using a Discrete Transistor

    strobe control voltage at the base of Q, will clamp


    the comparator output to ground, making it
    immune to any input changes. lL.
    +Vcc

    FIGURE 24. Multivibrator with Input Lock-Out

    >-+----0 VOUT The one shot multivibrator shown in Figure 24 has


    several characteristics which make it superior to
    that shown in Figure 23. First, the pulse width is
    lOGIC GATE OR
    independent of the magnitude of the power supply
    1f4lM139 voltage because the charging voltage and the inter-
    cept voltage are a fixed percentage of +Vee. In
    FIGURE 22. Output Strobing with TTL Gate addition this one-shot is capable of 99% duty cycle
    and exhibits input trigger lock-out to insure that
    If the LM139 is being used in a digital system the the circuit will not re-trigger before the output
    output may be strobed using any other type of pulse has been completed. The trigger level is the

    AN74-10
    voltage required at the input to raise the voltage at 1 mV at zero current along with an RSAT of 60£1
    point A higher than the voltage at point B. and is shows why the LM 139 so easily adapts itself to
    set by the resistive divider R4 and R,o and the oscillator and digital switching circuits by allowing
    network R,. R2 and R 3 . When the multivibrator the DC output voltage to go practically to ground
    has been triggered. the output of comparator 2 is while in the ON state.
    high causing the reference voltage at the non-invert-
    ing input of comparator 1 to go to +Vcc. This pre-
    vents any additional input pulses from disturbing 1400

    the circuit until the output pulse has been 120D


    lv
    -
    I I
    6011
    completed.
    1000
    f' I

    The value of the timing capacitor. C,. must be


    ;;
    .s BOO
    II V
    kept small enough to allow comparator 1 to com· j II 1.... 1,v
    pletely discharge C, before the feedback signal
    SOO
    1 mV@
    ri
    Jf
    400
    from comparator 2 (through R lO ) switches com-
    parator 1 OFF and allows C, to start an exponen- 200
    TA = 25°C
    tial charge. Proper circuit action depends on
    10 14 18
    rapidly discharging C 1 to a value set by R6 and Rg
    at which time comparator 2 latches comparator 1
    OFF. Prior to the establishment of this OFF state.
    C 1 will have been completely discharged by com- FIGURE 26. Typical Output Saturation Characteristics
    parator 1 in the ON state. The time delay. which
    sets the output pulse width. results from C 1 re-
    charging to the reference voltage set by R6 and Time Delay Generator
    Rg. When the voltage across C, charges beyond
    this reference. the output pulse returns to ground The final circuit to be presented under "Digital
    and the input is again reset to accept a trigger. and Switching Circuits" is a time delay generator
    (or sequence generator) as shown in Figure 27.
    Bistable Multivibrator
    Figure 25 is the circuit of one comparator of the
    LM139 used as a bistable multivibrator. A refer·
    ence voltage is provided at the inverting input by a "'OK "
    200K

    voltage divider comprised of R2 and R 3 . A pulse

    "' "m
    lOOK
    .""
    "
    .oK

    Q~
    RESET
    "
    .oK
    G-'M........>--j

    ·~r L-1~"
    I
    I
    I
    R

    ,,~

    9
    ~~:K
    tV.
    Vel
    ,
    'L--
    . '.
    V.

    '0 t, I. "
    ,
    ,

    I.

    ~~:DK 11/4LMll9~ii
    t----b-/.... "7L
    ~~:BK FIGURE 27. Time Delay Generator

    -=1;-
    This timer will provide output signals at prescribed
    FIGURE 25. Bistable Multivibrator
    time intervals from a time reference to and will
    automatically reset when the input signal returns
    applied to the SET terminal will switch the output to ground. For circuit evaluation. first consider the
    high. Resistor divider network R 1 • R 4 • and R5 quiescent state (V ,N ; 0) where the output of
    now clamps the non-inverting input to a voltage comparator 4 is ON which keeps the voltage across
    greater than the reference voltage. A pulse now C 1 at zero volts. This keeps the outputs of com-
    applied to the RESET input will pull the output parators 1. 2 and 3 in their ON state (V OUT ;
    low. If both Q and Q outputs are needed. another GND). When an input signal is applied. compara·
    comparator can be added as shown dashed in tor 4 turns OFF allowing C, to charge at an
    Figure 25. exponential rate through R 1. As this voltage rises
    past the preset trip points VA. VB and Vc of
    Figure 26 shows the output saturation voltage of comparators 1. 2 and 3 respectively. the output
    the LM 139 comparator verses the amount of voltage of each of these comparators will switch to
    current being passed to ground. The end point of the high state (V OUT ; +Vccl. A small amount of

    AN74-11
    hysteresis has been provided to insure fast switch-
    ing for the case where the Rc time constant has RE~~~NSE '~16IA CIRc'UIT Vee - +5V
    SHOWN IN FIGURE 3[)
    been chosen large to give long delay times. It is not
    necessary that all comparator outputs be low in
    the quiescent state. Several or all may be reversed mI·
    I
    as desired simply be reversing the inverting and III1
    non-inverting input connections. Hysteresis again !r'<.
    is optional. IiRESPONSEIIIFOR
    III

    CIRCUIT SHOWN

    LOW FREQUENCY OPERATIONAL : 1111'11 FiI~llllY


    10 100 lk 10k lOOk
    AMPLIFIERS
    FREnUENCY

    The LM 139 comparator can be used as an opera-


    FIGURE 29. Large Signal Frequency Response
    tional amplifier in DC and very low frequency AC
    applications (::;:100 Hz). An interesting combination tion scheme also ,hown in Figure 30. The DC level
    is to use one of the comparators as an op amp to shift due to the VSE of Q , allows the output
    provide a DC reference voltage for the other three
    comparators in the same package.

    Another useful application of an LM139 has the


    interesting feature that the input common mode Av ==100
    voltage range includes ground even though the
    amplifier is biased from a single supply and
    ground. These op amps are also low power drain
    devices and will not drive large load currents unless
    current boosted with an external NPN transistor.
    The largest application limitation comes from a
    relatively slow slew rate which restricts the power
    .-----.__-MIY-...---....-o V OUT

    A1
    bandwidth and the output voltage response time. 1K

    The LM139, like other comparators, is not inter-


    nally frequency compensated and does not have
    FIGURE 30. Improved Operational Amplifier
    internal provisions for compensation by external
    components. Therefore, compensation must be
    applied at either the inputs or output of the voltage to swing from ground to approximately
    device. Figure 28 shows an output compensation one volt less than +V cc. A voltage offset adjust-
    ment can be added as shown in Figure 31.

    +Vcc tVcc

    RJ
    15K
    AJ
    1M
    >-+--oVOUT
    +VINo-+---....-I
    V OUT

    A1
    lOIiK
    A2
    1K T C1
    O•5il F

    -= Av " ' I + * =101 ":"


    A1
    R2
    lOOK
    1K

    Av ==100
    FIGURE 28. Non-Inverting Amplifier

    FIGURE 31. Input Offset Null Adjustment


    scheme which utilizes the output collector pull-up
    resistor working with a single compensation capa-
    Dual Supply Operation
    citor to form a dominant pole. The feedback net-
    work, R, and R2 sets the closed loop gain at The applications presented here have been shown
    1 + R,!R2 or 101 (40 dB). Figure 29 shows the biased typically between +Vcc and ground for
    output swing limitations versus frequency. The out- simplicity. The LM139, however, works equally
    put current capability of this amplifier is limited by well from dual (plus and minus) supplies com-
    the relatively large pull-up resistor (15 k!l) so the monly used with most industry standard op amps
    output is shown boosted with an external NPN and comparators, with some applications actually
    transistor in Figure 30. The frequency response is requiring fewer parts than the single supply
    greatly extended by the use of the new compensa- equivalent.

    AN74-12
    17

    The zero crossing detector shown in Figure 10 can tV ee


    be implemented with fewer parts as shown in Fig·
    ure 32. Hysteresis has been added to insure fast
    transitions if used with slowly moving input sig·
    nals. It may be omitted if not needed, bringing the
    total parts count down to one pull·up resistor.
    VOUT

    R,

    !:I •• f

    J
    FIGURE 34. Non-Inverting Amplifier Using Dual Supplies

    saturation by drawing excessive current, thereby


    preventing the output low state from going all the
    way to -Vee.
    FIGURE 32. Zero Crossing Detector Using Dual Supplies

    MISCELLANEOUS APPLICATIONS
    The MOS clock driver shown in Figure 16 uses
    dual supplies to properly drive the MM0025 clock The following is a collection of various applica·
    driver. tions intended primarily to further show the wide
    versatility that the LM139 quad comparator has
    The square wave generator shown in Figure 13 can to offer. No new modes of operation are presented
    be used with dual supplies giving an output that here so all of the previous formulas and circuit
    swings symmetrically above and below ground (see descriptions will hold true. It is hoped that all of
    Figure 33). Operation is identical to the single the circuits presented in this application note will
    supply oscillator with the only change being in the suggest to the user a few of the many areas in
    lower trip point. which the LM139 can be utilized.

    tV ee
    Remote Temperature Sensor/Alarm
    R1
    lOOK
    The circuit shown in Figure 35 shows a temperature
    over·range limit sensor. The 2N930 is a National
    R4 process 07 silicon NPN transistor connected to pro·
    duce a voltage reference equal to a multiple of its
    base emitter voltage along with a temperature
    r-l rtVcc
    I L.J -Vee coefficient equal to a multiple of 2.2 mV tC. That
    VOUT
    multiple is determined by the ratio of R, to R2 .
    The theory of operation is as follows: with transis·
    tor Q, biased up, its base to emitter voltage will
    appear across resistor R,. Assuming a reasonably
    high beta ({3 > 100) the base current can be
    neglected so that the current that flows through
    resistor R, must also be flowing through R2 . The
    -Vee voltage drop across resistor R2 will be given by:

    FIGURE 33. Squarewave Generator Using Dual Supplies

    and
    Figure 34 shows an LM139 connected as an op
    amp using dual supplies. Biasing is actually simpler
    if full output swing at low gain settings is required
    by biasing the inverting input from ground rather so
    than from a resistive divider to some voltage
    between +V cc and ground. (31)

    All the applications shown will work equally well


    biased with dual supplies. If the total voltage As stated previously this base·emitter voltage is
    across the device is increased from that shown, the strongly temperature dependent, minus 2.2 mV tc
    output pull·up resistor should be increased to pre· for a silicon transistor. This temperature coeffi·
    vent the output transistor from being pulled out of cient is also multiplied by the resistor ratio R, IR 2 .

    AN74-13
    This provides a highly linear, variable temperature R2/R1 should be large to make the alarm more
    coefficient reference which is ideal for use as a sensitive to temperature variations. To vary the
    temperature sensor over a temperature range from trip points a potentiometer can be substituted
    approximately -65°C to +150°C. When this tem· for R3 and R4 . By the addition of a single feed·
    perature sensor is connected as shown in Figure 35 back resistor to the non-inverting input to provide
    it can be used to indicate an alarm condition of a slight amount of hysteresis, the sensor could
    either too high or too Iowa temperature excursion. function as a thermostat. For driving loads greater
    Resistors R3 and R4 set the trip point reference than 15 mA, an output current booster transistor
    voltage, VB, with switching occuring when VA ~ could be used.
    VB' Resistor R5 is used to bias up 0 1 at some
    low value of current simply to keep quiescent Four Independently Variable, Temperature
    power dissipation to a minimum. An 10 near Compensated, Reference Supplies
    10MA is acceptable.
    The circuit shown in Figure 36 provides four
    Using one LM139, four separate sense points are independently variable voltages that could be used
    available. The outputs of the four comparators for low current supplies for powering additional
    can be used to indicate four separate alarm condi- equipment or for generating the reference voltages
    tions or the outputs can be 0 R'ed together to needed in some of the previous comparator appli-
    indicate an alarm condition at anyone of the cations. If the proper Zener diode is chosen, these
    sensors. For the circuit shown the output will go four voltages will have a near zero temperature
    HIGH when the temperature of the sensor goes coefficient. For industry standard Zeners, this will
    above the preset level. This could easily be inverted be somewhere between 5.0 and 5.4V at a Zener
    by simply reversing the input leads. For operation current of approximately 10 mAo An alternative
    over a narrow temperature range, the resistor ratio solution is offered to reduce this 50 mW quiescent

    +Vcc

    .5

    - - -Z"~----If--l
    ,
    'I
    R3

    v,

    R4
    +
    1~
    J
    -=- ":"
    ., I
    I
    REMOTE
    SENSOR I
    I
    2N!lJG I
    I
    I
    ':'1
    FIGURE 35. Temperature Alarm

    +Vcc

    v, t---1>-------1
    VOUT 1 VOUT2

    D1 1!4lM1J!I

    10K T'M
    1K
    +Vcc

    FIGURE 36. Four Variable Reference Supplies

    AN74-14
    7

    power drain. Experimental data has shown that .,v


    any of National's process 21 transistors which have
    been selected for low reverse beta (!lR < .25) can
    Rl
    be used quite satisfactorily as a zero T.e. Zener. 10K
    When connected as shown in Figure 37, the T.e.

    v'

    01 ~ NATIONALPROCESS21
    SELECTED FOR LOW R,
    REVERSE ,I

    LEAVE BASE
    LEAD OPEN
    FIGURE 39. Paper Tape Reader With TTL Output

    Pulse Width Modulator


    FIGURE 37. Zero T.e. Zener
    Figure 40 shows the circuit for a simple pulse
    width modulator circuit. It is essentially the same
    of the base·emitter Zener voltage is exactly can· as that shown in Figure 13 with the addition of an
    celled by the T.e. of the forward biased base· input control voltage. With the input control
    collector junction if biased at 1.5 mAo The diode
    can be properly biased from any supply by adjust· +Vee

    ing R5 to set Iq equal to 1.5 mAo The outputs of


    any of the reference supplies can be current
    boosted by using the circuit shown in Figure 30. R'
    lOOK

    .v,
    R,
    Digital Tape Reader 10K Your

    Two circuits are presented here - a tape reader for RJ


    lOOK
    both magnetic tape and punched paper tape. The
    circuit shown in Figure 38, the magnetic tape

    .,v
    FIGURE 40. Pulse Width Modulator

    R' voltage equal to +V cc12, operation is basically the


    " same as that described previously. If the input
    control voltage is moved above or below +V cc12,
    however, the duty cycle of the output square wave
    111...-....1----- will be altered. This is because the addition of the
    control voltage at the input has now altered the
    trip points. These trip points can be found if the
    circuit is simplified as in Figure 41. Equations 13
    through 20 are still applicable if the effect of Rc
    is added, with equations 17 tbrough 20 being
    FIGURE 38. Magnetic Tape Reader with TTL Output
    altered for the condition where Vc +Vcc/2. *'
    reader, is the same as Figure 12 with a few resistor -tVee

    values changed. With a 5V supply, to make the


    output TTL compatible, and a 1 M!1 feedback R' R'
    resistor, ±5 mV of hysteresis is provided to insure lOOK R4
    lOOK
    lOOK R4
    lOOK
    fast switching and higher noise immunity. Using V,O--'IoIVv.....-'VIh-....
    flo V. Rc VB
    one LM 139, four tape channels can be read 10K RJ 10K RJ
    lOOK lOOK
    simultaneously.
    The paper tape reader shown in Figure 39 is VA" UPPER TRIP POINT VB. LOWER TRIP POINT
    essentially the same circuit as Figure 38 with the
    only change being in the type of transducer used. FIGURE 41. Simplified Circuit For Calculating Trip
    A photo·diode is now used to sense the presence or Points of Figure 40.
    absence of light passing through holes in the tape.
    Again a 1 M!1 feedback resistor gives ±5 mV of Pulse width sensitivity to input voltage variations
    hysteresis to insure rapid switching and noise will be increased by reducing the value of Rc
    immunity. from 10 k!1 and alternately, sensitivity will be

    AN74-15
    reduced by increasing the value of Rc. The values follower to avoid loading the output of the peak
    of R, and C, can be varied to produce any detector.
    desired center frequency from less than one hertz
    to the maximum frequency of the LM139 which
    will be limited by +Vcc and the output slew rate.
    v"

    Positive and Negative Peak Detectors


    Figures 42 and 43 show the schematics for simple
    positive or negative peak detectors. Basically the

    FIGURE 43. Negative Peak Detector

    For the negative peak detector, a low impedance


    v," current sink is required and the output transistor
    of the LM139 works quite well for this. Again
    the only discharge path will be the 1Mn resistor
    and any ~oad impedance used. Decay time is
    changed by varying the 1Mn resistor.
    ' - - - - - - - -....--41--0VOUT
    .2 Conclusion
    IMn

    The LM139 is an extremely versatile comparator


    package offering reasonably high speed while operat-
    FIGURE 42. Positive Peak Detector ing at power levels in the low mW region. By
    offering four independent comparators in one
    package, many logic and other functions can now
    LM139 is operated closed loop as a unity gain
    be performed at substantial savings in circuit
    follower with a large holding capacitor from the
    complexity, parts count, overall physical dimen·
    output to ground. For the positive peak detector a
    sions, and power consumption.
    low impedance current source is needed so an
    additional transistor is added to the output. When
    the output of the comparator goes high, current is For limited temperature range applications, the
    passed through Q, to charge up C,. The only LM239 or LM339 may be used in place of the
    discharge path wi II be the 1Mn resistor shunting LM139.
    C, and any load that is connected to VOUT • The
    decay time can be altered simply by changing the It is hoped that this application note will provide
    1Mn resistor higher or lower as desired. The out- the user with a guide for using the LM 139 and also
    put should be used through a high impedance offer some new application ideas.

    AN74·16

    /
    »
    2
    1
    B. Siegel "-J
    December 1972 C1I

    »
    "tJ
    "tJ
    APPLICATIONS FOR A HIGH SPEED FET INPUT OP AMP r-
    n
    INTRODUCTION
    The principal limitations in speed and bandwidth interdigitated monolithic pair that provide high
    »
    ~
    in IC FET input op amps have been reduced by
    over an order of magnitude with the introduction
    common mode rejection and input offset voltage
    tracking usually associated only with bipolar
    o
    2
    of the LH0062/LH0062C. Internal compensation
    assures unity gain stability with bandwidths in
    designs. The current mirror (Os and 0 7 ) converts
    to single ended operation in addition to providing
    en
    excess of 15 MHz. Voltage follower slew rate is active high impedance load for 0 4 and 0 5 thus "T1
    typically 75V Ills and is guaranteed in excess of providing high gain. 0 3 and D, provides a tem- o
    50V Ills. Furthermore, external components may perature compensated current source for the input :xJ
    be used to extend the slew rate to 120V Ills and
    settling times under Ills. The LH0062H (TO·5) is
    stage and as, Og, D2 and D3 form a class AB »
    pin compatible with LM101, LM741 and LH0022. J:
    A summary of the LH0062's performance char- G')
    acteristics is given in Table 1.
    J:
    PARAMETER ITA = 2S C) Q
    MIN TV' MAX UNITS
    en
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    Input Offset Voltage 20 50 mV
    m
    lnpul Bias Current
    Voltage Gam 50 100
    20 pA
    V/mV
    m
    Slew Rate 50 75 V//ls
    C
    Bandwidth 15 MH,
    "T1
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    ~
    TABLE 1. Summary of LH0062 Characteristics FIGURE 1. Simplified LH0062 Circuit Schematic

    output buffer. Detailed schematic is illustrated in


    2
    CIRCUIT DESCRIPTION "tJ
    Figure 2. Note that the FET inputs are protected
    by 5V zener diodes and input current under
    c:
    The LH0062 is basically a two stage ampl ifier ~
    (Figure 1) consisting of a N channel junction FET transient conditions should be limited by inserting
    input stage (0 1 and O 2 ) and a PNP output stage a 1 k ohm or larger resistor in series with one of the o
    (04 and 0 5 ), a, and O 2 are a well matched inputs. "tJ

    »
    s:"tJ

    .ALANCEI

    t~"';";"'---+';;;;"''''''''''''';;;;'''-+_'''''-G

    "'"

    ..
    ,

    FIGURE 2. Complete LH0062 Schematic

    AN75-1
    COMPENSATION CONSIDERATIONS

    R2
    As noted earlier, the LH0062 is internally com- 20'
    pensated for unity gain stability_ However, a few
    precautions are advised_ Like most wide band
    amplifiers, the LH0062 is sensitive to power supply
    AI
    inductance, and decoupling the supplies with O_lIlF 5K

    ceramic disc capacitors within an inch or two of


    OUTPUT
    the device will prevent spurious oscillations and
    save a fair amount of grief. The device is capable
    120V

    "

    FIGURE 5. Feed Forward Compensation

    AI
    lOOK
    "'l
    INPUT-.I\/I,,.,,....... not required, the device may be over-compensated
    as shown in Figure 6 to reduce bandwidth to
    5 MHz. This technique improves phase margin
    and reduces susceptibility to spurious oscillations
    in applications where speed is less critical.

    FIGURE 3. Isolating a Capacitive Load up to 500 pF


    "F

    of driving 50 to 100 pF loads; for larger loads, an


    R1
    isolation resistor, R3 as shown in Figure 3 is lOOK
    recommended. Alternatively, a current buffer such !l
    INPUT-"'iItv-.....

    as the LH0002 or LH0033 may be used for loads ">'~ ....-OUTPUT


    in excess of 500 pF with no degradation in slew
    rate as shown in Figure 4.

    FIGURE 6. Overcompensation
    "
    2-10pf

    Minimum settling time of less than 11ls to 0.1%


    for a 20V input step is obtained as illustrated in
    Figure 7. A small tweak capacitor, C 1 is recom-
    mended to cancel stray board layout capacitance,
    Cs . Once best value of trimmer capacitor C 1 is
    determined for a particular layout, it may be
    replaced with a fixed 1/alue.

    Not,ln!h .... mpl".b ...,lh",<m.llcap.tI!OO,Cl,I<


    ""d to CI""llh •• lf,,\< '(""I oop""tan" " th,,"p"'

    "
    2-10pF

    R2
    lOOK

    FIGURE 4. Driving Capacitances in Excess of


    500 pF and Loads
    AI
    IUIlK
    INPUT-'W.......~-~

    :~:" OUTPUT

    The LH0062 may be feed-forward compensated SETTliNG TIME - Ill'

    in inverting mode applications as shown in Figure


    5. This boosts slew rate to over 120V/Ils and
    bandwidth to over 30 MHz. When full bandwidth is FIGURE 7. Compensation for Minimum Settling Time

    AN75-2
    '7

    R1
    IK

    OUTPUT

    INPUT

    R9
    200K
    'S/HlOG'C--<r--4~r)'--t)o-+~_.J

    v'
    °HOLD ~ LOGIC","
    SAMPLE = LOGIC"O"

    FIGURE 8. High Speed Sample & Hold

    APPLICATIONS "
    2-iDpF

    The circuit of Figure 8 is a high speed sample and


    hold with sample acquisition time of lOllS for
    0.1% accuracy and aperture time of approxi·
    mately 25 ns. Resistor, Rs , is used to limit input
    current during power on and off transients.
    Although the inputs of the LH0062 are protected
    by back·to·back diodes excessive input current
    could damage the device. Resistor R9 and the pot, FIGURE 9. High Speed Peak Detector
    Ra , allow null of the output offset with negligible
    The circuit of Figure 10 is a programmable inte·
    effect on offset drift.
    grator with a range in period from 11ls to 1 ms. For
    best results C1 through C4 should be low leakage
    The peak detector of Figure 9 will acquire a +1 OV construction such as polycarbonate or polystyrene.
    peak signal in under 41ls with droop rates under A simple method of implementing the offset
    20 mV/sec. Reversing the polarity of diodes D, adjustment is to momentarily insert a lOOk ohm
    and D2 will allow peak detecting negative signals. resistor between pins 2 and 6 of the LH0062.
    Any ultra·low leakage diode may be substituted With the switches of the AH5009 off, the output
    for the 2N930 collector·base junction. may be set to zero with R2 •

    OUTPUT

    RJ
    PERIOD 2611K
    SELECT

    L ______ !l~9J EGO icfE,d'


    WHERE C=C"CZ,C].c.

    R1
    10K _ _ _ _- '
    INPUT _ _ _ _ _ _ _ _ _-'I/\{\r

    FIGURE 10. Programmable Integrator

    AN75·3
    '''UT~

    RI R2 R3
    49K 12K 4K

    FIGURE 11. Wide Band AC Voltmeter

    The circuit of Figure 11 is a wide band AC voltmeter


    capable of measuring AC signals as low as 15 mV
    at frequencies from 100 Hz to 500 kHz. Full scale
    sensitivity may be changed by altering the values
    OUTPUT
    R, through R6 (R =" V1N/100IlA). RI
    10K

    HEAT SINKING, GUARDING, FIGURE 12. Guard/Bootstrap for Unity Gain


    AND BOOTSTRAPPING
    Furthermore, the case of the LH0062 is electrically
    The LH0062 is specified for operation without an isolated, and the output may be tied to case in
    external heat sink. However, standby power is order to eliminate stray capacitance introduced
    typically 240 mW causing a junction rise of approx· by the header.
    imately 60°C. A clip·on heat sink can reduce
    internal heating hence reduce input bias current
    from 20 pA at 25°C ambient to 2 or 3 pA.
    Guarding input leads is recommended in stringent REFERENCES
    applications. An excellent discussion on guarding
    is given in AN·63 and the techniqu~s discussed are 1. R. K. Underwood, "New Design Techniques for
    directly applicable to the LH0062. Another benefit FET Op Amps," National Semiconductor AN·
    of guarding is reduced input capacitance. By boot· 63, March 1972.
    strapping the inputs, as shown in Figure 12, the
    apparent input capacitance is reduced to fractions 2. R. C. Dobkin, "LMl18 Op Amp Slews lOVI!1S,"
    of a pico·farad. National Semiconductor LB·17, September 1971.

    AN75·4
    Robert C. Dobkin ...,
    March 1969

    2
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    s:"'CJ
    INSTRUMENTATION AMPLIFIER r
    'TI

    The differential input single·ended output instru- LM 102 is specifically designed for voltage follower m
    mentation amplifier is one of the most versatile usage and has 10,000 MQ input impedance with ::JJ
    signal processing amplifiers available. It is used for 3 nA input currents. This high of an input imped·
    precision amplification of differential dc or ac ance provides two benefits: it allows the instru-
    signals while rejecting large values of common mentation amplifier to be used with high source
    mode noise. By using integrated circuits, a high resistances and still have low error; and it allows
    level of performance is obtained at minimum cost. the source resistances to be unbalanced by over
    10,000 ohms with no degradation in common
    mode rejection. The followers drive a balanced dif·
    Figure 1 shows a basic instrumentation amplifier ferential amplifier, as shown in Figure 1, which
    which provides a 10 volt output for 100 mV input, provides gain and rejects the common mode volt-
    while rejecting greater than ±11 V of common age. The gain is set by the ratio of R4 to R2 and
    mode noise. To obtain good input characteristics, Rs to R 3. With the values shown, the gain for
    two voltage followers buffer the input signal. The differential signals is 100.

    >"::""-4..-0UTPUT

    FIGURE 1. Differential·lnput Instrumentation Amplifier

    LB1-l
    Figure 2 shows an instrumentation ampl ifier where mode rejection of 60 dB, independent of gain. In
    the gain is Iinearly adjustable from 1 to 300 with a either circuit, it is possible to trim any, one of the
    single resistor. An LM101A, connectei:! as a fast resistors to obtain common mode rejection ratios
    inverter, is used as an attenuator in the feedback in excess of 100 dB.
    loop. By using an active attenuator, a very low
    impedance is always presented to the feedback For optimum performance, several items should be
    resistors, and common mode rejection is unaf- considered during construction. R I is used for
    fected by gain changes. The LM 101 A, used as zeroing the output. It should be a high resolution,
    shown, has a greater bandwidth than the LM107, mechanically stable potentiometer to avoid a zero
    and may be used in a feedback network without shift from occurring with mechanical disturbances.
    instability. The gain is linearly dependent on R6 Since there are several ICs operating in close prox-
    and is equal to 10-4 R6 • imity, the power supplies should be bypassed with
    .01 fJ.F disc capacitors to insure stability. The resis-
    To obtain good common mode rejection ratios, it tors should be of the same type to have the same
    is necessary that the ratio of R4 to R2 match the temperature coefficient.
    ratio of Rs to R3 . For example, if the resistors in
    circuit shown in Figure 1 had a total mismatch of A few applications for a differential instrumenta-
    0.1 %, the common mode rejection would be 60 dB tion amplifier are: differential voltage measure·
    times the closed loop gain, or 100 dB. The circuit ments, bridge outputs, strain gauge outputs, or low
    shown in Figure 2 would have constant common level voltage measurement.

    'GAIN ADJUST
    Av '1rR6

    Cl
    15GpF

    FIGURE 2. Variable Gain, Differential·lnput Instrumen·


    tation Amplifier

    LBl-2
    r-
    ttl
    Robert C. Dobkin N
    March 1969
    "T1
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    FEEDFORWARD COMPENSATION (')
    SPEEDS OP AMP o
    S
    "'C
    nals, Pin 1, as shown in Figure 2. This eliminates
    m
    A feedforward compensation method increases the Z
    slew rate of the LM101A from 0.5/1ls to 10V/Ils as the lateral PNP's from the signal path at high fre· (f)

    ~
    an inverting amplifier. This extends the usefulness quencies. Unity gain bandwidth is 10 MHz and
    of the device to frequencies an order of magnitude the slew rate is 1OV IllS. The diode can be added to
    higher than the standard compensation network. improve slew with high speed input pulses. o
    With this speed improvement, IC op amps may be z
    used in applications that previously required dis· (f)
    cretes. The compensation is relatively simple and "'C
    does not change the offset voltage or current of CZ;l!;IX 10-11
    •• m
    the amplifier. m
    C
    (f)
    In order to achieve unconditional closed loop sta·
    bility for all feedback connections, the gain of an >.;..".... -v,~
    o
    operational amplifier is rolled off at 6 dB per "'C
    octave, with the accompanying 90 degrees of
    phase shift, until a gain of unity is reached. The »
    frequency compensation networks shape the open Cl ·OPTIONAl TO IMPROVE RESPONSE
    S
    loop response to cross unity gain before the ampli· 158 pf WITH fAST·RISING INPUT STEPS. "'C
    fier phase shift exceeds lBO degrees. Unity gain for
    the LM101A is designed to occur at 1 MHz. The FIGURE 2. Feedforward Frequency Compensation
    reason for this is the lateral PNP transistors used
    for level shifting have poor high frequency reo Figure 3 shows the open loop response in the high
    sponse and exhibit excess phase shift about and low speed configuration. Higher open loop
    1 MHz. Therefore, the stable closed loop band· gain is realized with the fast compensation, as the
    width is limited to approximately 1 MHz. gain rolls off at about 6 dB per octave until a gain
    of unity is reached at about 10 MHz. Figures 4
    and 5 show the small signal and large signal tran·
    sient response. There is a small amount of ringing;
    "'.•• however, the amplifier is stable over a _55°C to
    .,
    3D.
    +125°C temperature range. For comparison, large
    signal transient" response with 30 pF frequency
    compensation is shown in Figure 6.
    >:;.........
    -VOUT

    '" r- TA = 25°C
    Vs=i15V

    .J. 1 1 '"
    100

    ~
    ~
    ~EEDFr\Ai,D- '"
    &1 80

    ""-
    30pf z l!
    ~ 60 135 ~
    FIGURE 1. Standard Frequency Compensation ...... ~
    ~
    -
    40

    " STANDARD/"
    ~ tt"
    1"- 1'J.
    90

    45
    :J

    Usually, the LM101A is frequency compensated ." I' I


    by a single 30 pF capacitor between Pins 1 and B, 10 100 lk 10k lOOk 1M 10M 100M
    FREQUENCY!Hz)
    as shown in Figure 1. This gives a slew rate of
    0.5V IllS. The feedforward is achieved by connect·
    ing a 150 pF capacitor between the inverting FIGURE 3. Open Loop Response for Both Frequency
    input, Pin 2, and one of the compensation termi· Compensation Networks

    LB2-1
    by the addition of 3 pF between Pins 1 and 8. A
    small capacitor C2 is needed as a lead across the
    feedback resistor to insure that the rolloff is less
    than 12 dB per octave at unity gain. The capacitive
    reactance of C1 should equal the feedback resis-
    tance between 2 and 3 MHz. For integrator appli-
    cations, the lead capacitor is isolated from the
    feedback capacitor by a resistor, as shown in
    Figure 8.

    FIGURE 4. Small Signal Transient Response with Feed·


    Feedforward compensation offers a marked im-
    forward Compensation provement over standard compensation. In addi-
    tion to having higher bandwidth and slew, there is
    vanishingly small gain error from DC to 3 kHz,.and
    less than 1% gain error up to 100 kHz as a unity
    gain inverter. The power bandwidth is also ex-
    tended from 6 kHz to 250 kHz. Some applications
    for this type of amplifier are: fast summing ampli-
    fier, pulse amplifier, DIA and AID systems, and
    fast integrator.

    .,
    30<

    FIGURE 5. Large Signal Transient Response with Feed·


    forward Compensation

    n
    .J v~
    ,oon

    FIGURE 1. Capacitive Load Isolation

    Cl
    FIGURE 6. Large Signal Transient Response with Stan·

    ,..,
    dard Compensation

    "
    IDpF

    As with all high frequency, high-gain amplifiers,


    certain precautions should be taken to insure
    stable operation. The power supplies should be
    bypassed near the amplifier with .01 /.IF disc ca-
    pacitors. Stray capacitance, such as large lands on
    printed circuit boards, should be avoided at Pins 1,
    2, 5, and 8. Load capacitance in excess of 75 pF
    should be decoupled, as shown in Figure 7; how-
    ever, 500 pF of load capacitance can be tolerated
    without decoupling at the expense of bandwidth FIGURE 8. Fast Integrator

    LB2-2
    April 1969

    ~
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    WORST CASE POWER DISSIPATION ~
    IN LINEAR REGULATORS rJ)
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    ."
    o
    The most frequent cause of failures of voltage The divider resistors required on the LM100
    ~
    regulators is excessive dissipation in the semicon- feedback to give a 24V output are 26.6k and m
    ductor components. Regulators using integrated 2.1 k. For a 1.8V sense voltage on the feedback ::J:J
    circuits are no exception to this. In fact, IC regu· terminal, the divider current will be 0.85 mAo
    lators are more prone to overdissipation because Since this current must be supplied by the inte- C
    they are not generally available in power packages, grated circuit, it must be subtracted from the rJ)
    because complete integrated circuits must be oper· available load current. Hence the maximum rJ)
    ated at a lower, maximum junction temperature output current, taking into account worse case ."

    ~
    than silicon power transistors, and because the conditions, is 2.1 mAo
    package must be able to dissipate the quiescent
    operating power of the control circuitry in addi- o
    tion to the power in the pass transistor. U5mA(MAX) 2.1 mA(MAXI z
    The problems and solutions presented here give z
    examples of the worst case calculations that Rl
    Cl Z&.6K r-
    should be used in designing voltage regulators with
    ICs. These questions were used in a contest spon:
    47pF 1%
    Z
    sored by National Semiconductor. The entries } -....- -. . 1.8V m
    ~
    received clearly showed that engineers have a
    marked tendency to be overly optimistic about the
    D.l5mA l R2
    Z.1SK
    1%
    ::J:J
    dissipation capability of the IC regulators as well ::J:J
    as the power ratings of the external power transis- m
    C)
    tors used with them. In a surprising number of c:
    cases the errors were of such a magnitude to cause r-
    almost certain, premature failure of the regulator FIGURE 1. Circuit Used in the Solution of Question 1. ~
    under the conditions specified. The questions and -I
    answers follow: o
    ::J:J
    2. What is the maximum allowable short-circuit rJ)
    1. What is the power limited full-load current for current for an LM104 regulator circuit, with a
    a 24V regulator using the LM100 (without a 2N2905A series pass transistor (without a heat
    heat sink) when the worst case operating condi- sink) when the worst case input is 20V at an
    tions are 125°C ambient and 40V input ambient of 85°C?
    voltage?
    The 2N2905A, without a heat sink, can dissi-
    The maximum chip temperature of the LM100 pate a maximum of 0.6W at 25°C. However,
    is 150°C, and the thermal resistance of the this must be derated by 3.42 mWtC for opera-
    TO-5 package is 150°C/W when no heat sink is tion at higher temperatures. Since an 85°C
    used. The permissable, junction-to-ambient ambient is 60° C higher than the temperature at
    temperature rise is 25°C with a 125°C ambient, which the transistors are specified, the maxi-
    so the maximum allowable package dissipation mum power rating must be reduced by
    is 167 mW. 205 mW, to 395 mW. With a shorted output,
    The worst case quiescent current of the LM100 the voltage dropped across the current limit
    is 3.0 mAo With a 40V input voltage, this pro- sense resistor is 0.5V, so the voltage across the
    duces an internal dissipation of 120 mW, even external pass transistor will be 19.5V for 20V
    with no load. Therefore, the device can only input. This means that the 395 mW maximum
    dissipate another 47 mW in supplying the load dissipation rating will be exceeded for short-
    current. With 40V in and 24V out, the input- circuit currents greater than 20.2 mAo
    output voltage differential is 16V. This means
    that 2.95 mA can be supplied through the in- 3. In the previous example, what is the maximum
    ternal pass transistor without exceeding the current when the case temperature of the
    ratings. 2N2905A is held to 100°C?

    LB3-1
    The maximum dissipation of the 2N2905A is where dissipation is most significant. This
    3W at 25°C case temperature, but this must be means that the base current tor a 5A load cur-
    derated by 17.2 mW/oC for higher case tem- rent will be O.33A. The worst case emitter-base
    peratures. With a 100°C case temperature, the voltage of the 2N3772 at 5A will be about 1V,
    allowable dissipation is reduced by 1.29W to so the current through the 68Q emitter-base
    1.71W. resistor will be 15 mAo Hence, the PNP driver
    must supply a total current of 345 mAo
    As in the previous example, the voltage across
    the pass transistor will be 19.5V. This gives a The voltage dropped across the PNP driver will
    d i ssi pat i on-limited short-circuit current of be the 12V input output voltage differential,
    88mA. less the 1V dropped across the current sense
    resistor and the 1V dropped across the emitter-
    base junction of the 2N3772. Therefore, the

    .,
    4.lj.lF
    PNP driver operates with lOV across it and dis-
    sipates about 3.5W.

    5. Could a 2N2905A be used in the example


    above if the maximum ambient were 85°C?
    } - - - -....- -.....--V,.D
    Even with an infinite heat sink, the 2N2905A
    can dissipate only 2W at 85°C. Therefore, it
    cannot be used.

    The answers to these questions show that the


    maximum output current of a regulator can be
    •• substantially less than might be expected from a
    - - _ v.. ·-zov
    L -_ _ _ _.......~-...;.... . cursory analysis of the circuit_ Detailed aFlalysis
    under worst case conditions is necessary to insure
    a reliable design. These calculations are more
    FIGURE 2. Circuit Used in the Solution of Questions 2 important than most other design calculations
    and 3. because errors do not result in somewhat degraded
    performance that usually shows up in checking out
    4. In the negative regulator with foldback current the equipment. Instead, these errors cause failures
    limiting, what will be the worst case dissipation that do not always show up during checkout, but
    in the PNP driver, 0" with full load and a 24V can occur in field operation.
    input voltage?
    The 2N3772 is specified to have a minimum Additional information on the design of reliable
    current gain of 15 at lOA and 25°C. It would voltage regulators is given in application notes
    be reasonable to assume a minimum current AN-21 and AN-23, available from National
    gain of 15 at 5A for elevated temperatures Semiconductor.

    ':'

    .
    HZ
    .K .,
    zz.,
    +
    ••"K
    ~
    }-'---+-IP----;--+--..;;...YouT z -IZV

    ., .,D.'
    UK
    '"
    !4.lA
    cz
    1 4 71lF
    • t
    IV 'SmA !
    I
    .........----'------<II......--<II...... - - V1N =-24V

    FIGURE 3. Circuit Used in the Solution of QUestions 4 and 5_

    LB3-2
    Robert C. Dobkin
    April 1969
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    ::1:1
    o:J
    l>
    :2
    C
    FAST COMPENSATION EXTENDS ~
    POWER BANDWIDTH C
    -I
    ::I:
    In all IC operational amplifiers the power band- 1 MHz. For closed loop gains between 1 and 10,
    width depends on the frequency compensation. more frequency compensation must be used to
    Normally, compensation for unity gain operation insure that the open loop gain has been rolled off
    is accompanied by the lowest power bandwidth. A soon enough to cross the closed loop gain before
    technique is presented which extends the power 1 MHz is reached.
    bandwidth of the LM 101 A for non-inverting gains
    of unity to ten, and also reduces the gain error at The power bandwidth of an operational amplifier
    moderate frequencies. depends on the current available to charge the fre-
    quency compensation capacitors_ For unity gain
    In order to achieve unconditional stability, an operation, where the compensation capacitor is
    operational amplifier is rolled off at 6 dB per largest, the power bandwidth of the LM101A is
    octave, with an accompanying 90 degrees of phase 6 kHz. Figure 1 shows an LM101A with unity gain
    shift, until a gain of unity is reached. Unity gain in
    most monolithic operational amplifiers is limited
    to 1 MHz, because the lateral PNP's used for level
    shifting have poor frequency response and exhibit
    excess phase shift at frequencies above 1 MHz_
    Hence, for stable operation, the closed loop band-
    width must be less than 1 MHz where the phase
    shift remains below 180 degrees_

    For high closed loop gains, less severe frequency


    compensation is necessary to roll the open loop
    gain off at 6 dB per octave until it crosses the
    closed loop gain. The frequency where it crosses FIGURE 1. LM101A With Standard Frequency Com-
    must, as previously mentioned, be less than pensation.

    LB4-1
    compensation and Figure 3 shows the open loop than the impedance of the 300 pF capacitor and
    gain as a function of frequency. the gain rolls off at 6 dB per octave. The open
    loop gain plot is shown in Figure 3_ To insure suf-
    A two-pole frequency compensation network, as ficient drive to the 300 pF capacitor, it is con-
    shown in Figure 2, provides more than a factor of nected to the output, Pin 6, rather than Pin 8.
    With this frequency compensation method, the
    power bandwidth is typically 15-20 kHz as a fol-
    lower, or unity gain inverter.

    120

    100

    ~~
    80 -
    d}.. ~
    ; 60
    ~( tto
    - -<",.o<~~
    z ..
    ~ 40

    20 1\
    r'\.
    '\
    FIGURE 2. LM101A with Frequency Compensation to -20
    Extend Power Bandwidth. 1 10 100 lK 10K lOOK 1M 10M
    FREQUENCY 1Hz)

    two improvement in power bandwidth and re-


    duced gain error at moderate frequencies. The net- FIGURE 3. Open Loop Response for Both Frequency
    Compensation Networks.
    work consists of a 30 pF capacitor, which sets the
    unity gain frequency at 1 MHz, along with a
    300 pF capacitor and a 10k resistor. By dividing
    the ac output voltage with the 10k resistor and This frequency compensation, in addition to ex-
    300 pF capacitor, there is less ac voltage across the tending the power bandwidth, provides an order of
    30 pF capacitor and less current is needed for magnitude lower gain error at frequencies from DC
    charging. Since the voltage division is frequency to 5 kHz. Some applications where it would be
    sensitive, the open loop gain rolls off at 12 dB per helpful to use the compensation are: differential
    octave until a gain of 20 is reached at 50 kHz_ amplifiers, audio amplifiers, oscillators, and active
    From 50 kHz to 1 MHz the 10k resistor is larger filters.

    LB4-2
    r
    OJ
    I
    Robert C. Dobkin C1I
    March 1969
    J:
    C)
    J:
    P
    Z
    o
    -I
    (")
    J:
    ."

    !:j
    m
    :lJ

    HIGH QNOTCH FILTER

    The twin "T" network is one of the few RC filter The junction of R3 and C3 , which is normally
    networks capable of providing an infinitely deep connected to ground, is bootstrapped to the out-
    notch. By combining the twin "T" with an LM102 put of the follower. Because the output of the
    voltage follower, the usual drawbacks of the net- follower is a very low impedance, neither the
    work are overcome. The Q is raised from the usual depth nor the frequency of the notch change;
    0.3 to something greater than 50. Further, the however, the Q is raised in proportion to the
    voltage follower acts as a buffer, providing a low amount of signal fed back to R3 and C3 . Figure 2
    output resistance; and the high input resistance of shows the response of a normal twin "T" and the
    the LM 102 makes it possible to use large resistance response with the follower added.
    values in the "T" so that only small capacitors are
    required, even at low frequencies. The fast re-
    sponse of the follower allows the notch to be used
    at high frequencies. Neither the depth of the notch
    nor the frequency of the notch are changed when
    the follower is added.

    Figure 1 shows a twin "T" network connected to


    an LM102 to form a high Q, 60 Hz notch filter.

    FREQUENCY 1Hz!

    VOUT
    FIGURE 2. Response of High and Low Q Notch Filter
    JVI,.,........-;
    v,. - ........,.,."..........

    In applications where the rejected signal might


    deviate slightly from the null of the notch net-
    work, it is advantageous to lower the Q of the
    network. This insures some rejection over a wider
    range of input frequencies. Figure 3 shows a cir-
    CI C2
    nu,F ZlD,F cuit where the Q may be varied from 0.3 to 50. A
    fraction of the output is fed back to R3 and C3 by
    a second voltage follower, and the notch Q is
    dependent on the amount of signal fed back. A
    FIGURE 1. High Q Notch Filter second follower is necessary to drive the twin "T"

    LB5-1
    from a low-resistance source so that the notch fre- An interesting change in the high Q twin "T"
    quency and depth wi II not change with the poten- occurs when components are not exactly matched
    in ratio_ For example, an increase of 1 to 10 per-
    cent in the value of C3 will raise the Q, while
    degrading the depth of the notch. If the value of
    C3 is raised by 10 to 20 percent, the network pro-
    >,"-~"'VOUT vides voltage gain and acts as a tuned amplifier. A
    voltage gain of 400 was obtained during testing.
    Further increases in C3 cause the circuit to oscil-
    late, giving a clipped sine wave output.

    The circuit is easy to use and only a few items


    .
    50.
    need be considered for proper operation. To mini-
    mize notch frequency shift with temperature,
    silver mica, or polycarbonate, capacitors should be
    used with precision resistors. Notch depth depends
    on component match, therefore, 0.1 percent resis-
    FIGURE 3. Adjustable Q Notch Filter
    tors and 1 percent capacitors are suggested to
    minimize the trimming needed for a 60 dB notch.
    tiometer setting. Depending on the potentiometer To insure stability of the LM 102, the power sup-
    setting, the circuit in Figure 3 will have a response plies should be bypassed near the integrated circuit
    that falls in the shaded area of Figure 2. package with .01 /IF disc capacitors.

    LB5-2
    ?

    May 1969

    ."
    »
    en
    -I
    <
    FAST VOLTAGE COMPARATORS
    WITH LOW INPUT CURRENT
    o
    ~
    Monolithic voltage comparators are available today »
    C)
    which are both fast and accurate. They can detect
    the height of a pulse with a 5 mV accuracy within
    m
    40 ns. However, these devices have relatively high o
    input currents and low input impedances, which o
    reduces their accuracy and speed when operating
    from high source resistances. This is probably a
    :s'"CI
    basic limitation since the input transistors of the
    integrated circuit must be operated at a relatively
    »
    ::XJ
    high current to get fast operation. Further, the
    circuit must be gold doped to reduce storage time,
    a. Using a Ladder Network
    ~
    and this limits the current gain that can be " o
    ::XJ
    obtained in the transistors. High gain transistors
    operating at low collector currents are necessary to
    en
    get good input characteristics. ~
    One way of overcoming this difficulty is to buffer =i
    the input of the comparator. A voltage follower is ::t
    available which is ideally suited for this job. This '" LOG'~ r
    device, the LM102 4 , is both fast and has a low o
    ~
    input current. It can reduce the effective input b. Using a Binary-Weighted Network
    current of the comparator by more than three FIGURE 1. Comparator Circuits for Fast AID Converters
    orders of magnitude without greatly reducing Z
    the use of larger resistances in the ladder which
    speed. '"CI
    simpl ifies design of the switches drivi ng it.
    A comparator circuit for an AID converter which c:
    uses this technique is shown in Figure la. An It is possible to balance out the offset of the -I
    LM 102 voltage follower buffers the output of a LM 102 with an external 1 kn potentiometer, R•. o
    ladder network and drives one input of the com· The adjustment range of this balance control is
    large enough so that it can be used to null out the
    c:
    parator. The analog signal is fed to the other input ::XJ
    of the comparator. It should come from a low offset of both the buffer and the comparator. A ::XJ
    impedance source such as the output of a signal 10 kn resistor should be installed in series with m
    processing amplifier, or another LM102 buffer the input to the LM 102, as shown. This is required Z
    to make the short circuit protection of the device -I
    amplifier.
    effective and to insure that it will not oscillate.
    Clamp diodes, D I and D2 , are included to make This resistor should be located close to the inte-
    the circuit faster. These diodes clamp the output grated circuit.
    of the ladder so that it is never more than 0.7V
    different from the analog input. This reduces the A similar technique can be used with AID con-
    voltage excursion that the buffer must handle on verters employing a binary-weighted resistor net-
    the most significant bit and keeps it from slewing. work. This is shown in Figure 1b. The analog input
    If fast, low-capacitance diodes are used, the signal is fed into a scaling resistor, RI ' This resistor is
    to the comparator will stabilize approximately selected so that the input voltage to the LM102 is
    200 ns after the most significant bit is switched in. zero when the output of the DI A network corre·
    This is about the same as the stabilization time of sponds to the analog input voltage. Hence, if the
    the ladder network alone, as its speed is limited by DI A output is too low, the output of the LM 106
    stray capacitances. The diodes also limit the volt- will be a logical zero; and the output will change
    age swing across the inputs of the comparator, to a logical one as the DI A output exceeds the
    increasing its operating speed and insuring that the analog signal.
    device is not damaged by excessive differential The analog signal must be obtained from a source
    input voltage. impedance which is low by comparison to R I .
    The buffer reduces the loading on the ladder from This can be either another LM102 buffer or the
    45/lA to 20 nA, maximum, over a _55°C to output of the signal-processing amplifier. Clamp
    125°C temperature range. Hence, in most applica· diodes, D I and D2 , restrict the signal swing and
    tions the input current of the buffer is totally speed up the circuit. They also limit the input
    insignificant. This low current will often permit signal seen by the LM 106 to protect if from over-

    LB6-1
    loads. Operating speed can be increased even
    further by using silicon backward diodes (a degen·
    erate tunnel diode) in place of the diodes shown,
    as they will clamp the signal swing to about
    50 mV. The offset voltage of both the LM102 and
    the LM106 can be balanced out, if necessary,
    with R6 •
    The binary weighted network can be driven with a. Comparator for Signals of Opposite Polarity
    single pole, single·throw switches. This will result
    in a change in the output resistance of the network
    when it switches, but circuit performance will not
    be affected because the input current of the
    LM102 is negligible. Hence, using the LM102
    greatly simplifies switch design.
    Although it is possible to use a 710 as the voltage
    b. Zero Crossing Detector
    comparator in these circuits, the LM 106 offers
    several advantages. First, it can drive a fan out of
    10 with standard, integrated DTL or TTL. It also
    has two strobe terminals available which disable
    the comparator and give a high output when either
    of the terminals is held at a logical zero. This adds
    logic capability to the comparator in that it makes
    it equivalent to a 710 and a two·input NAND gate. c. Comparator for AC Coupled Signals
    If not needed, the strobe pins can be left uncon·
    FIGURE 2. Applications Requiring Low Input Current
    nected without affecting performance. The voltage Comparators
    gain of the LM106 is about 45,000, which is
    30 times higher than that of the 710. The in· polarity. Resistors (R, and R2 ) are required to
    creased gain reduces the error band in making a isolate the two signal sources. Frequently, these
    comparison. The LM 106 will also operate from the resistors must be relatively large so that the sigl1al
    same supply voltage as the LM 102, and other oper· sources are not loaded. Hence, the input current of
    ational amplifiers, for ±12V supplies. However, it the comparator must be reduced to prevent inac·
    can also be operated from ±15V supplies if a 3V curacies. Another example is the zero·crossing
    zener diode is connected in series with the positive detector in Figure 2b. When the input signal can
    supply lead. exceed the common mode range of the compara·
    tor (±5V for the LM1061. clamp diodes must be
    It is necessary to observe a few precautions when used. It is then necessary to isolate the comparator
    working with fast circuits operating from relatively from the input with a relatively large resistance to
    high impedances. A good ground is necessary, and prevent loading. Again, bias currents should be
    a ground plane is advisable. All the individual reduced. A third example, in Figure 2c, is a com·
    points in the circuit which are to be grounded, parator with an ac coupled input. An LM106 will
    including bypass capacitors, should be returned draw an input current which is twice the specified
    separately to the same point on the ground so that bias current when the signal is above the compari·
    voltages will not be developed across common lead son threshold. Yet, it draws no current when the
    inductance. The power supply leads of the inte· signal is below the threshold. This asymmetrical
    grated circuits should also be bypassed with low current drain wi II charge any coupling capacitor on
    inductance 0.01 f..I F capacitors. These capacitors, the input and produce an error. This problem can
    preferably disc ceramic, should be installed with be eliminated by using a buffer, as the input cur·
    short leads and located close to the devices. Lastly, rent will be both low and constant.
    the output of the comparator should be shielded
    from the circuitry on the input of the buffer, as The foregoing has shown how two integrated
    stray coupling can also cause oscillation. circuits can be combined to provide state·of-the·
    art performance in both speed and input current.
    Although the circuits shown so far were designed Equivalent results will probably not be achievable
    for use in AID converters, the same techniques in a single circuit for some time, as the technolo-
    apply to a number of other applications. Figure 2 gies required are not particularly compatible.
    gives examples of circuits which can put stringent Further, considering the low cost of monolithic
    input current requirements on the comparator. circuits, approaches like this are certainly
    The first is a comparator for signals of opposite economical.

    LB6-2
    r-
    o:l
    I
    Robert C. Dohkin .....
    August 1969
    -i
    ::XI
    l>
    (')

    TRACKING VOLTAGE REGULATORS "2


    Integrated circuit voltage regulators are available regulators are adjusted. The bottom resistor of the C>
    today which are economical and offer a high divider, R2 , is fixed at 2K. The top of the divider,
    degree of performance. There are both positive
    and negative regulators capable of achieving better
    R1 , is then calculated for the output voltage using
    1.6V as the reference voltage. To help compensate
    o<
    than 0.1% regulation under normal fluctuations in for the inaccuracies in the adjustment, output volt- !:i
    l>
    input supply and load. Due to production varia· ages are calculated slightly off from the desired
    tions, the internal reference voltage in these regula· values. For the 5 and 15V regulators, R I is calcu- C>
    tors may vary as much as 10% from unit to unit. lated to give a 2% low output voltage on the 5V m
    Normally, this causes no problems as most power regulator and a 2% high output voltage on the 15V ::XI
    supply circuits have an adjustment potentiometer regulator. m
    which is varied to obtain the correct output volt· (V ouT -1.6V) 20000- C>
    age. In systems with more than one regulated out· R, = 1.6V C
    put voltage, it is sometimes desirable to adjust all
    supplies with a single potentiometer. This results
    in savings by eliminating one or more potentio·
    Rs will now adjust both regulators to within 2% of
    the desired output for reference variations from
    1.6V to 2.0V. From the previous calculations, a
    E
    o
    meters as well as eliminating the need to adjust the 1.6V reference yields outputs of 4.9V and 15.3V. ::XI
    supplies individually. If the reference is 2.0V, Rs is adjusted to en
    Figure 1 shows a 5V and a 15V regulator with 324 ohms and the output voltages are 5.1 V and
    both outputs adjusted with a single potentiometer. 14.9V. If the reference is near the typical value of
    Although the technique is not exact, the error is 1.8V, both outputs are within 1% of nominal.
    typically under 2%. As shown in Figure 1, the These calculations do not account for resistor in-
    internal reference voltages for the LM 105' regula· accuracies. If 1% resistors are used there is an
    tors, available at pin 5, are tied together. This additional worst case error of 2% for each regula-
    insures that both regulators operate with the same tor. Resistor errors are inherent in any type of
    reference voltage. The lower resistors of the out- tracking regulator system, even if the adjustment is
    put divider, R2 , are connected through a common theoretically exact.
    adjustment potentiometer to ground. Rs adjusts
    both regulators for variations in the 1.8V refer- Actually, any number of regulators may be con-
    ence. Note that the wiper of Rs is connected to nected to a single adjustment resistor. The adjust-
    one side of the potentiometer. If a rheostat con- ment accuracy of this technique depends on the
    nection were used, the arm might open circuit output voltage differences among the regulators.
    during adjustment, causing large transients on the The previous example was a severe difference, and
    output. had only 2% accuracy. With close output voltages,
    such as 12V and 15V, the error is much smaller.
    The calculations of resistor values for the output The 12V regulator is calculated to 1/2% low and
    divider resistors are made with the consideration 15V regulator 1/2% high with the 1.6V reference.
    that the adjustment is not exact and that two Both regulators are then within 1/2% for reference
    *R. J. Widlar, "The LM105-An Improved Positive Regu-
    variations of 1.6 to 2.0 volts. This adjustment
    lator," National Semiconductor Corporation, AN 23, method is, of course, exact if two regulators have
    January, 1969. the same output.

    .. VOUT +5V
    lOUT "SZODIIIA
    .,
    0.15
    VouT +15V
    lOUT <20amA
    '"

    FIGURE 1. Tracking Positive Regulators

    LB7-1
    I
    Using a negative regulator to track a positive regu· typically matched to 1%. This means that the out·
    lator is a somewhat easier task. An inverting put of both regulators may be adjusted with 1%
    operational amplifier may be used to provide a accuracy by changing R, in Figure 2.
    negative output voltage while using a positive volt· The LM 104 may also be used with inverting gain
    age as a reference. The LM104t negative regulator for negative output voltages greater than the posi·
    is easily adapted for use as an inverting amplifier tive reference voltage. Figure 4 shows a circuit
    and provides several advantages over conventional where the -15V supply tracks a +5V supply. In
    operational ampl ifiers. It is designed to drive boost this configuration the non·inverting input is not
    transistors for higher output current as well as grounded, but tied to divider, Rs , R6 , between the
    providing a convenient method of current limiting negative output and ground. The output voltage
    the output. Further, the frequency compensation
    used on the LM 104 is optimized for transient equals + [Rs+ R6]
    VOUT = V R6- Rs
    response to line and load changes. Figure 2 shows
    tracking ±15V regulators. where V+ is the positive reference.
    The line regulation and temperature drift are
    determined primarily by the positive reference,
    "
    !17K "
    JIPF* with the negative output tracking. The reference
    1%
    must be a klw impedance source, such as an
    LM105 regulator, to insure that current drawn by
    .2 pin 9 of the LM 104 does not affect the reference
    23'
    1% voltage. Since the LM 104 is connected to a posi·
    tive voltage instead of ground, it sees a total volt·
    age equal to the sum of the unregulated negative
    input and the positive reference voltage. This
    reduces the maximum unregulated negative input
    voltage allowable, and should be considered during
    design. If the negative output voltage must be less
    than the positive reference or the decrease in maxi·
    mum unregulated input voltage cannot be tole·
    rated, an alternate method of constructing track·
    'SolldT'Mllum ing regulators is given elsewhere t. Of course, many
    FIGURE 2. Tracking Positive and Negative Regulators negative regulators may be slaved to a single posi·
    Operation is most easily understood by referring tive regulator.
    to the functional schematic of the LM 104 in Using standard linear integrated circuits, multiple
    Figure 3. The non·inverting input of the internal output positive and negative suppl ies may be ad·
    amplifier, pin 1, is connected to ground. The posi· justed to within 2% or less by a single resistor.
    tive 15V reference is connected through an inter· Although the absolute output is not exact, the
    nal 15K ohm input resistor, R16 , to the inverting regulation accuracy is still within 0.1%. These
    input. Feedback resistor, RIS , is also 15K ohm. techniques can result in savings by the elimination
    This forms a unity gain invelting amplifier with a of both time and materials when used.
    negative output voltage equal to the positive input
    voltage. The 15K ohm resistors in the LM 104 are
    tR. J. Widlar. "Designs for Negative Regulators," Nation-
    al Semiconductor Corporation, AN-21, December, 1968 .

    ...- -......M - -...-O:-....-O-vOUT

    I
    I
    .,
    un
    IL ________
    L--...---¢:-......
    _ ~-.Vw

    FIGURE 3. Functional Diagram of the LM104 Used as FIGURE 4. Tracking Regulators With Different Output
    an Amplifier Voltages

    LB7-2
    Robert C. Dobkin
    August 1969

    "C
    :r:J
    m
    n
    PRECISION AC/DC CONVERTERS Cii
    Although semiconductor diodes available today output is precisely clamped from going more posi-
    o
    :2
    are close to "ideal" devices, they have severe limi- tive than the reference voltage. When EIN is more
    tations in low level applications_ Silicon diodes positive than EREF, the LM101A functions as a »
    n
    have a 0_6V threshold which must be overcome summing amplifier with the feedback loop closed
    .........
    before appreciable conduction occurs. By placing through D1. Neglecting offsets, negative feedback c
    the diode in the feedback loop of an operational
    amplifier, the threshold voltage is divided by the
    keeps the summing node, and therefore the out-
    put, within 100 IN of the voltage at the non-
    n
    open loop gain of the amplifier. With the threshold inverting input. When E IN is about 100 Jl.V more n
    virtually eliminated, it is possible to rectify negative than ER EF, the output swings positive, o
    millivolt signals. reverse biasing D 1. Since D 1 now prevents negative :2
    feedback from controlling the voltage at the <
    m
    Figure 1 shows the simplest configuration for elim- inverting input, no clamping action is obtained. On :r:J
    inating diode threshold potential. If the voltage at both of the circuits in Figures 1 and 2 an output -I
    the non-inverting input of the amplifier is positive, clamp diode is added at pin 8 to help speed m
    response. The clamp prevents the operational :r:J
    r--------1~EOUT amplifier from saturating when D1 is reverse en
    biased.

    When D1 is reverse biased in either circuit, a large


    differential voltage may appear between the inputs
    E,. of the LM101A. This is necessary for proper oper-
    ation and does no damage since the LM 101 A is
    designed to withstand large input voltages. These
    circuits will not work with amplifiers protected
    with back to back diodes across the inputs. Diode
    protection conducts when the differential input
    FIGURE 1. Precision Diode
    voltage exceeds 0.6V and would connect the input
    and output together. Also, unprotected devices
    the output of the LM101A swings positive. When such as the LM709, are damaged by large differen-
    the amplifier output swings 0.6V positive, D1 tial input signals.
    becomes forward biased; and negative feedback
    through D1 forces the inverting input to follow The circuits in Figures 1 and 2 are relatively slow.
    the non-inverting input. Therefore, the circuit acts Since there is 100% feedback for positive input
    as a voltage follower for positive signals. When the signals, it is necessary to use unity gain frequency
    input swings negative, the output swings negative compensation. Also, when D1 is reverse biased, the
    and D1 is cut off. With D1 cut off no current feedback loop around the amplifier is opened and
    flows in the load except the 30 nA bias current of the input stage saturates. Both of these conditions
    the LM 101 A. The conduction threshold is very cause errors to appear when the input frequency
    small since less than 100 Jl.V change at the input exceeds 1.5 kHz. A higher performance precision
    will cause the output of the LM101A to swing half wave rectifier is shown in Figure 3. This cir-
    from negative to positive. cuit will provide rectification with 1% accuracy at
    frequencies from dc to 100 kHz. Further, it is easy
    A useful variation of this circuit is a precIsion to extend the operation to full wave rectification
    clamp, as is shown in Figure 2. In this circuit the for precision ac/dc converters.
    cz
    R.. "f
    E.. -JlA,.,.......------... - EouT

    Dl
    IN914 c>---'lM,-----()--EoUT

    D1
    INSI4

    D'
    IN91.
    -ERU .. usthl"ISOlirte
    D'
    IN!I"
    I"' ....nctafln.sthl.
    ZOOUrfDZlSalid.

    FIGURE 2. Precision Clamp FIGURE 3. Fast Half Wave Rectifier

    LB8-1
    R
    This precision rectifier functions somewhat differ- the output of A2 is - R: EI N. For positive input
    ently from the circuit in Figure 1- The input signal
    signals, A2 sums the currents through R3 and R6 ;
    is applied through R, to the summing node of an
    and
    inverting operational amplifier. When the signal is
    negative, D, is forward biased and develops an
    output signal, across R2 . As with any inverting
    EOUT=R7 [E~> E~~l
    amplifier, the gain is R2 /R,. When the signal goes . R7
    positive, D, is'non-conducting and there is no out- If R3 is 1/2 R6, the output is R6 E'N' Hence, the
    put. However, a negative feedback path is provided
    output is always the absolute value of the input.
    by D2 . The path through D2 reduces the negative
    output swing to -0.7V, and prevents the ampli-
    fier from saturating. Filtering, or averaging, to obtain a pure dc output
    is very easy to do. A capacitor, C2 , placed across
    Since the LM101A is used as an inverting amplifier, R7 rolls off the frequency response of A2 to give
    feed forward * compensation can be used. Feed-' an output equal to the average value of the input.
    forward compensation increases the slew rate to The filter time constant is R7C2 , and must be
    10V//ls and reduces the gain error at high fre- much greater than the maximum period of the
    quencies. This compensation allows the half wave input signal. For the values given in Figure 4, the
    rectifier to operate at higher frequencies than the time constant is about 2.0 seconds. This converter
    previous circuits ~ith no loss in accuracy. has beUer than 1% conversion accuracy to above
    100 kHz and less than 1% ripple at 20 Hz. The
    The addition of a second amplifier converts the output is calibrated to read the rms value of a sine
    half wave rectifier to a full wave rectifier. As is wave input.
    shown in Figure 4,the half wave rectifier is con-
    nected to inverting amplifier A2 . A2 sums the half As with any high frequency circuit some care must
    wave rectified signal and the input signal to be, taken during construction. Leads should be
    provide a full wave output. For negative input kept short to avoid stray capacitance and power
    signals the output of AI is zero and no current supplies bypassed with .01 /IF disc ceramic capac-
    flows through R3 . Neglecting for the moment C2 , itors. Capacitive 'loading of the fast rectifier
    circuits must be less than 100 pF or decoupling
    *R. C. Dobkin, "Feedforward Compensation Speeds Op becomes necessary. The diodes should be rea-
    Amp," National Semiconductor Corporation, L8·2. April, sonably fast and film type resistors used. Also, the
    1969. amplifiers must have low bias currents.

    ..
    .&
    'OK
    Rl
    C2
    IOfolF

    .OK

    ..iIr-~.-.......W..--+-EoUT
    r-......J\jIll.-......---."'

    D2
    lN914

    -feedfolWllrl!complnatlon
    ClllblulldlDmakt.fnt
    CJ' fullwnerectdlHwlthoul
    lOpF
    .tdter.

    FIGURE 4. Precision AC to DC Converter

    LB8-2
    Robert C. Dobkin
    August 1969

    c
    z
    <:m
    ::u
    en
    l>
    r-
    OJ
    l>
    r-
    l>
    Z
    (')
    :2
    C)

    -I
    UNIVERSAL BALANCING TECHNIQUES m
    (')
    IC op amps are widely accepted as a universal This adjustment method is also useful when the ::I:
    analog component. Although the circuit designs -feedback element is a capacitor or non-linear :2
    may vary, most devices are functionally inter-
    changeable. However, offset voltage balancing
    device.
    oC
    remains a personality trait of the particular am- Rl
    m
    plifier design. The techniques shown here allow en
    offset voltage balaBcing without regard to the R4
    internal circuitry of the amplifier. INPUT· ......WIl-4t-l

    DUTPUT

    Rl RI
    R2 200K
    lOOK
    ::K >0.......1\1""....
    -v R2
    100

    OUTPUT RANGE = tV (1*)


    Rl =2000 RlIIR4 FIGURE 2. Offset Voltage Adjustment for Inverting Am-
    R4I1Rl<10k!l plifiers Using Any Type of Feedback Ele-
    RANGE -:±V (RJ~lR4) ment

    FIGURE 1. Offset Voltage Adjustment for Inverting Am- This technique of supplying a small voltage effec-
    plifiers Using 10 kn. Source Resistance or
    Less
    tively in series with the input is also used for
    adjusting non-inverting amplifiers. As is shown in
    Figure 3, divider R I , R2 reduces the voltage at the
    The circuit shown in Figure 1 is used to balance arm of the pot to ±7.5 mV for offset adjustment.
    out the offset voltage of inverting amplifiers hav- Since R2 appears in series with R4 , R2 should be
    ing a source resistance of 10 kn or less. A small considered when calculating the gain. If R4 is
    current is injected into the summing node of the greater than 10 kn the error due to R2 is less
    amplifier through R I. Since -R I is 2000 times as than 1%.
    large as the source resistance the voltage at the arm
    of the pot is attenuated by a factor of 2000 at the
    RS
    summing node. With the values given and ±15V
    supplies the output may be zeroed for offset volt- +v R1
    ages up to ±7.5 mV. 200K R4
    Rl
    SDK
    If the value of the source resistance is much larger R2 OUTPUT
    -V 100
    than 10 kn, the resistance needed for R I becomes
    too large. In this case it is much easier to balance RANGE=±V(~)
    out the offset by supplying a small voltage at the GAIN"l+~
    non-inverting input of the amplifier. Figure 2 INPUT R4+ R2

    shows such a scheme. Resistors R I and R2 divide


    the voltage at the arm of the pot to supply a FIGURE 3. Offset Voltage Adjustment for Non-Inverting
    ±7.5 mV adjustment range with ±15V supplies. Amplifiers

    LB9-1
    .,

    A voltage follower may be balanced by the tech- R2

    nique shown in Figure 4. R, injects a current


    which produces a voltage drop across R3 to cancel Rl
    the offset voltage. The addition of the adjustment El"'-""',."......H
    resistors causes a gain error, increasing the gain by INPUTS OUTPUT
    0.05%. This small error usually causes no problem. Rl
    E2 ..:.+......IV\,..... .-t
    The adjustment circuit essentially causes the offset
    voltage to appear at full output, rather than at low
    R3
    output levels, where it is a large percentage error. R5

    R3
    "-'II2oVKIor-..c ;:K
    R2=R3+R4
    lK R' -v
    R2 10 RANGE' ±v (~) (~)
    lOOK
    GAIN'~

    OUTPUT FIGURE 5. Offset Voltage Adjustment for Differential


    Amplifiers

    INPUT
    RANGE = ±V (w,) 1 kQ. If R3 is less than 1 K the shunting of R4 by Rs
    must be considered when choosing the value of
    FIGURE 4. Offset Voltage Adjustment for Voltage R3 ·
    Followers
    The techniques described for balancing offset volt-
    Differential amplifiers are somewhat more difficult age at the input of the amplifier offer two main
    to balance. The offset adjustment used for a differ- advantages: First, they are universally applicable
    ential amplifier can degrade the common mode to all operational amplifiers and allow device inter-
    rejection ratio. Figure 5 shows an adjustment cir- changeability with no modifications to the balance
    cuit which has minimal effect on the common circuitry. Second, they permit balancing without
    mode rejection. The voltage at the arm of the pot interfering with the internal circuitry of the am-
    is divided by R4 and Rs to supply an offset cor- plifier. The electrical parameters of the amplifiers
    rection of ±7.5 mV. R4 and Rs are chosen such are tested and guaranteed without balancing.
    that the common mode rejection ratio is limited Although it doesn't usually happen, balancing
    by the amplifier for values of R3 greater than could degrade performance.

    LB9-2
    '.7

    r-
    to
    Robert C. Dobkin ....
    o
    I

    January 1970

    (')

    ::JJ
    m
    C)
    C
    Ie REGULATORS SIMPLIFY r-
    POWER SUPPLY DESIGN
    ~
    o
    ::JJ
    en
    Although power supply requirements vary, IC To regulate negative voltages, the circu it in en
    voltage regulators can fulfill the majority of needs. Figure 2 is used. An LM104 2 contains the voltage ~
    Power supplies designed with ICs can give predict- reference and control circuitry while an external "tJ
    able regulation better than 0.1% with a minimum !:
    of engineering effort. Output voltages between 0 -n
    and 40V at currents of 10A are easily achieved. -<
    Further, with a minimum of changes, a single "tJ
    regulator circuit can be used for a wide variety of o
    output voltages and currents.
    ~
    m
    A basic 200 mA positive regulator circuit is shown ::JJ
    in Figure 1. The LM 105' contains the voltage
    reference and control circuitry while the external en
    C
    "tJ
    "tJ
    FIGURE 2. 200 rnA Negative Regulator !:(
    .--......;>-'IM--9-----(.--<1.... VOUT·,SII
    transistor is used to increase the power handling
    capacity. A reference voltage is generated by
    C
    m
    driving a constant current, determined by R I , en
    through R2 . The voltage across this resistor is fed C)
    into an error amplifier. The error amplifier con-
    trols the output voltage at twice the voltage across
    z
    R2 . The output voltage is resistor programmable
    with R2 and adjustable down to zero.

    Current limit in the LM104 is similar to the


    FIGURE 1. 200 rnA Positive Regulator LM 105. Voltage across R3 turns on an internal
    transistor that decreases drive to the output tran-
    sistors. This current limit sense voltage is also
    components set the output voltage, current limit temperature dependent, decreasing from 0.65V at
    and increase power handling capacity of the IC. 25°C to 0.45V at 125°C.
    The output voltage is set by R2 and R3 . A fraction
    of the output voltage is compared by an error Boosting the available output current from
    amplifier with an internal 1.8V reference. Any 200 mA is relatively simple. Figure 3 shows posi·
    error is amplified and used to drive the 2N3740
    power transistor. Since the open loop gain is large, ..---co---CHi'VI.-....- - - -....- ...
    -VDUT -1511
    there is little error and a high degree of regulation.

    Current limiting is set by R,. The voltage drop


    across R, is applied to the emitter base junction of
    a transistor in the IC. When the transistor is turned
    on, it removes drive from the series pass transistor;
    and the regulator output exhibits a constant cur-
    rent characteristic. Since the turn on voltage of a
    transistor is temperature dependent, so is the cur-
    rent limit. The current limit sense voltage is about FIGURE 3a. 2A Positive Regulator
    O.4V at 25°C decreasing linearly to 0.3V at 125°C.
    Therefore, the current limit resistor must be tive and negative 2A regulators. An additional
    chosen to provide adequate output current at the power transistor increases the current handling
    maximum operating temperature. capability of the regulator. Adding the boost tran-

    LB10-1
    . - - -....- - - 1 I - - - -...... GROUND Ground loops are worst yet, since voltage drops
    can be amplified and appear at the regulator's out-
    put_ In Figure 3, voltage drops between Pin 4 of
    the LM105 and the bottom of R3 are amplified by
    [ . ) _. . . ._ . . . . VOUT ·_IIY
    the ratio of R2/R3 and appear at the output_

    ..
    '""' When the regulator is powered from ac that is
    rectified and filtered, current flowing in the filter
    can sometimes cause an unusual ground loop
    problem_ For capacitor input filters, the peak
    V,N"-12V
    charging current is many times the average load
    -s.11II1I1I1I'UIII
    current_ Even a few milliohms of resistance can
    cause appreciable voltage drop during the peak of
    FIGURE 3b. 2A Negative Regulator the charging_ When the charging current produces
    a voltage drop between R3 and Pin 4 of the
    sistors increases the output current without LM 105, it appears as excessive ripple on the out-
    increasing the minimum input-output voltage put of the regulator_
    differential. The minimum differential will be 2 to
    3V, depending on the drive current required from Of course, single point grounding eliminates these
    the integrated circuit and operating temperature. problems, but this is not always possible_ Usually
    Low input-output voltage differential allows more it is sufficient to insure that load current does not
    efficient regulation. generate a voltage drop between the ground side of
    the voltage setting resistor and the ground of the
    Although the regulators are relatively simple, some IC_
    precautions must be taken to eliminate possible
    problems. First, when the regulator is used with In most cases, short circuit protection is the only
    boost transistors, a solid tantalum output capaci- fault protection needed_ However, for some regu-
    tor is needed. Unlike electrolytics, solid tantalum lator circuits, such as positive and negative regu-
    capacitors have low internal impedance at high lators used together, additional protection is neces-
    frequencies. This suppresses possible high fre- sary_ If the positive and negative supplies are
    quency minor loop oscillations as well as providing shorted together, it is possible to cause the output
    low output impedance at high frequency. Also, for voltage of one of the supplies to reverse, blowing
    the LM 1 04, the output capacitor frequency com- the IC. This is especially true if the current capa-
    pensates the regulator and must have good bil ities are different, such as a 200 mA negative
    frequency characteristics. supply and a 2A positive supply. A clamp diode
    between the output and ground of each supply
    The power transistors recommended are single- will prevent such polarity reversals. Also, clamp
    diffused, wide-base devices. These devices have diodes should be used to prevent input polarity
    fewer oscillation problems than double-diffused, reversal and input-output voltage differential
    planar transistors. Also, they seem less prone to reversal.
    failure under overload conditions. Of course, like
    the power transistors in any regulator, adequate The use of ICs in regulator circuits can enhance
    heat sinking is necessary. The heat sink should power supply performance while minimizing cost
    keep the transistor junction temperature at an and engineering time. Since only one IC is needed
    acceptable level for worst case conditions of for a wide range of outputs, the part cost, board
    maximum input voltage, maximum ambient space and purchasing problems are less when com·
    temperature and shorted output. By far, the major pared to discrete designs. Also engineering time is
    cause of regulator failures is inadequate heat saved since typical and worst case performance
    sinking. data, as well as application data, is available from
    the manufacturer before design is begun.
    Good construction techniques ara also important
    for regulator performance. If proper care is not REFERENCES:
    taken, ground loop errors and lead resistance drops
    1. R.J. Widlar, "An Improved Positive Regulator,"
    can easily become greater than regulator errors.
    For example, 0.05" wide, 2 oz. printed circuit
    National Semiconductor AN-23, January,
    1969.
    conductor has a resistance of about 0.007 Q per
    inch. For a 200 mA, 15V regulator, ten inches of 2. R.J. Widlar, "Designs for Negative Regulators,"
    conductor would decrease the regulation by a National Semiconductor AN-21, October,
    factor of 2. 1968.

    LB10-2
    r
    March 1970 ...
    OJ
    I

    -I
    :J:
    m
    r
    ...os:
    -'

    :I>
    2
    THE LM110-AN IMPROVED
    Ie VOLTAGE FOLLOWER
    :s:
    "'tI
    ::c
    There are quite a few applications where op amps the frequency response of general purpose o
    are used as voltage followers. These include sample amplifiers. Secondly, it was the first Ie to use <
    m
    and hold circuits and active filters as well as super-gain transistors. With these devices, high C
    general purpose buffers for transducers or other speed operation can be realized along with low
    high-impedance signal sources. The general use-
    fulness of such an amplifier is particularly en-
    input currents. n
    hanced if it is both fast and has a low input bias The LM 11 0 is a voltage follower that has been <
    o
    current. High speed permits including the buffer in designed to supersede the LM 102. It is consider·
    the signal path or within a feedback loop without ably more flexible in its application and offers
    r
    -I
    significantly affecting response or stability. Low substantially improved performance. In particular, )::>
    input current prevents loading of high impedance the LM 11 0 has lower offset·voltage drift, input C)
    sources, which is the reason for using a buffer in current and noise. Further, it is faster, less prone m
    the first place. to oscillations and operates over a wider range of

    The LM102, introduced in 1967, was designed


    supply voltages. o"r
    specifically as a voltage follower. Therefore, it was The advantages of the LM 11 0 over the LM 102 are r
    possible to optimize performance so that it described by the following curves. Improvements o
    worked better than general purpose Ie amplifiers not included are increased output swing under ~
    in this application. This was particularly true with load, larger small'signal bandwidth, and elimina· m
    respect to obtaining low input currents along with tion of oscillations with low·impedance sources. ::c
    high·speed operation. The performance of these devices is also compared
    with general·purpose op amps in Tables I and II.
    One secret of the LM102's performance is that The advantages of optimizing an Ie for this par·
    followers do not require level shifting. Hence, ticular slot are clearly demonstrated. Lastly, some
    lateral PNP's can be eliminated from the gain path. typical applications for voltage followers with the
    This has been the most significant limitation on performance capability of the LM 11 0 are given.

    r--rH~-------....,..-r-'· ,-+-=~=-+----- ......."

    LM102 LMll0

    Biggest design difference between the LM102 and LM110 is the elimination of the zener diodes (01
    and 02) in the biasing circuit. This reduces noise and permits operation at low supply voltages.

    LB11-1
    14 15
    12
    ~~'U~15J '"'''' lM110
    ,Ll Vs "t1IiV
    T..,=25°C
    Rs '"'3k ID
    l,,-Z5"e
    ili~"RT'ON <5"
    ID
    E
    LMI02 lMl10 I lMIIO ~lM,J2
    ~ -5

    1\
    1\ -ID

    I"
    '" ID"
    ,. 'OM ID.
    '00' I. IDM
    -15
    o 1 2 3 4 5 6 7
    FREQUENCY (Hz! FREQUENCY (Hz) TIME (j.ls)

    Power bandwidth of the lMl1 0 is five times larger Eliminating zeners reduces typical high frequency Large signal pulse response shows 40V/pS slew for
    than the LM102. noise by nearly a factor of 10. Worst Clse noise is LM110 and 10V!ps for LM10Z.leading edge over'
    reduced even more. High frequency noise of shoot on LM110 is virtually eliminated, so exter·
    lMl02 has caused problems when it was included nal clamp diode frequently required on the LM102
    inside feedback loop with other Ie up amps. is not needed.

    OFFSET·· BIAS·· SlEWt SUPPl V· OFFSET- BIAS· SLEW' SUPPLY·


    DEVICE VOLTAGE CURRENT RATE BANDWIDTHt CURRENT DEVICE VOLTAGE CURRENT RATE BANDWIDTHf CURRENT
    ImVI (nA) (V/loisl (MHz) (mAl (mV) (nA) IV/psi (MHz) (mAl

    lMl10 6.0 10 40 20 5.5 lM310 7.5 70 40 20 5.5


    lM102
    MC1556
    7.5
    6.0
    100
    30
    10
    2.5
    10 5.5
    , 5
    lM302
    MC1456
    15
    '0
    30
    30
    20
    2.5
    '0
    , 5.5
    1.5
    pA715
    lMl08
    7.5
    3.0
    4000
    3
    20
    0.3
    10 7.0
    0.6
    /JA715C
    lM308
    7.5
    7.5
    '500
    70
    20
    0.3
    '0
    ,, 10
    0.8
    lM10BA
    lM101A
    1.0
    3.0 100
    0.3
    0.6
    0.6
    3.0
    lM308A
    lM301A
    05
    7.5
    70
    250
    0.3
    0.6
    ,, 08
    3.0
    pA741 6.0 1500 0.6 3.0 /JA741C 6.0 500 0.6 3.0

    "MaXimum for _55°C ~ T A ~ 125°C -Maximum at 25°C

    ·Maxlmum at 25°C tTYPlcal at 25°C


    tTypical at 25°C
    Table I. Comparing Performance of Military Grade IC Table II. Comparison of Commercial Grade Devices.
    Op Amps in the Voltage·Follower Connection.

    ,.

    IT.ftoft "'"",~f\Io",,.t ........ ,,


    .101............"..
    ·WO ..... lld"tt
    'V"."""HIOGII •••"HU.. 1....... l .. V"'<
    .....,II•• pol,..."" ......_,."
    "'1"'''_''''''''''·"'

    High Pass Active Filter Low Drift Samp'e and Hold'"

    High Q Notch Filter Bandpass Filter

    LB11-2
    r-

    January 1970 ...


    OJ
    1

    »
    :2
    (")
    AN IC VOLTAGE COMPARATOR
    FOR HIGH IMPEDANCE CIRCUITRY <
    o
    ~
    The IC voltage comparators available in the past voltage. The PNPs drive a standard differential
    have been designed primarily for low voltage, high stage. The output of this stage is further amplified
    speed operation. As a result, these devices have by the 0 5 .0 6 pair. This feeds a lateral PNP, 0 9 , G)
    high input error currents, which limit their useful· that provides additional gain and drives the output m
    ness in high impedance circuitry. An IC is de· stage. (")
    scribed here that drastically reduces these error
    currents, with only a moderate decrease in speed. The output transistor is 0" which is driven by
    o
    the level shifting PNP. Current limiting is provided ~
    by R6 and 0; 0 to protect the circuit from inter· "tI
    This new comparator is considerably more flexible
    than the older devices. Not only will it drive RTL, mittent shorts. Both the output and the ground
    »
    ::D
    DTL and TTL logic; but also it can interface with
    MOS logic and FET analog switches. It operates
    lead are isolated from other points within the cir-
    cuit, so either can be used as the output. The V-
    »
    -i
    from standard ±15V op amp supplies and can terminal can also be tied to ground to run the o
    switch 50V, 50 mA loads, making it useful as a circuit from a single supply. The comparator will ::D
    driver for relays, lamps or light·emitting diodes. A work in any configuration as long as the ground "T1
    unique output stage enables it to drive loads refer·
    red to either supply or ground and provide ground
    terminal is at a potential somewhere between the
    supply voltages. The output terminal, however,
    o
    ::D
    isolation between the comparator inputs and the can go above the positive supply as long as the
    load. breakdown voltage of 0" is not exceeded. J:
    G)
    Another useful feature of the circuit is that it can J:
    be powered from a single 5V supply and drive
    DTL or TTL integrated circuits. This enables the
    IOD~~
    ~ - ~:~~: J ~
    designer to perform linear functions on a digital· LM111
    "tI

    11O~··V";;/m m
    circuit card without using extra supplies. It can,
    for example, be used as a low· level photodiode C
    detector, a zero crossing detector for magnetic
    transducers, an interface for high·level logic or a Vas = Ves + Rslos
    »
    :2
    precision multivibrator. 1 L-_~I __L--5_5'~C_ST_A~S_I2_5'~C (")
    1k 10k lOOk 1M lDM m
    '" INPUT RESISTANCE In!
    (")
    FIGURE 2. Illustrating the Influence of Source Resis- ::D
    tance on Worst Case, Equivalent I"put Offset (")
    Voltage. C
    ::j
    Figure 2 shows how the reduced error currents of ::D
    the LM 111 improve circuit performance. With the -<
    LM710 or LM 106, the offset voltage is degraded
    for source resistances above 200Q. The LM 111,
    however, works well with source resistances in
    excess of 30 kQ. Figure 2 applies for equal source
    resistances on the two inputs. If they are unequal,
    the degradation will become pronounced at lower
    resistance levels.

    Table I gives the important electrical character·


    istics of the LM 111 and compares them with the
    specifications of older ICs.
    FIGURE 1. Simplified Schematic of the LM111
    A few, typical applications of the LM 111 are illus·
    Figure 1 shows a simplified schematic of this trated in Figure 3. The first is a zero crossing
    versatile comparator. PNP transistors buffer the detector driving a MOS analog switch. The ground
    differential input stage to get low input currents terminal of the IC is connected to V-; hence, with
    without sacrificing speed. Because the emitter base ±15V supplies, the signal swing delivered to the
    breakdown voltage of these PNPs is typically lOV, gate of 0, is also ±15V. This type of circuit is
    they can also withstand a large differential input useful where the gain or feedback configuration of

    LB12-1
    Table" Comparing the LM111 with earlier Ie compara~ cent lamp, which is the load here, has a cold resis·
    tors. Values given are worst case over a _55°C to tance eight times lower than it is during normal
    12SoC temperature range, except as noted.
    operation. This produces a large inrush current,
    when it is switched on, that can damage the
    switch. However, the current limiting of the
    Parameter LMlll LM106 LM710 Units LM 111 holds this current to a safe value.
    Input Offset
    4 3 3 mV
    Voltage
    Input Offset
    0.02 7 7 !J.A
    Current
    Input Bias
    0.15 45 45 !J.A
    Current
    Common Mode
    ±14 ±5 ±5 V a. Zero Crossing Detector Driving Analog Switch
    Range
    Differential Input
    Voltage Range ±30 ±5 ±5 V
    Voltage Gain t 200 40 1.7 V/mV
    Response Time t 200 40 40 ns
    TO Tn
    Output Drive lOGIC

    Voltage 50 24 2.5 V
    Current 50 100 1.6 mA
    Fan Out
    8 16
    (DTL/TTL)
    b. Detector for Magnetic Transducer
    Power
    80 145 160 mW
    Consumption

    tTypical at 25°C.

    an op amp circuit must be changed at some pre·


    cisely·determined signal level. Incidentally, it is a

    "
    simple matter to modify the circuit to work with
    junction FETs. c. Comparator for Low Level Photodiode

    The second circuit is a zero crossing detector for a


    magnetic pickup such as a magnetometer or shaft·
    position pickoff. It delivers the output signal
    directly to DTL or TTL logic circuits and operates
    from the 5V logic supply. The resistive divider, R I
    -

    '''':1$'W
    .
    J _
    +

    lMl11

    ·'n,.'p.'ototynr ...... d ..... n .


    """'"'''0''"" v
    •

    _
    -
    I '

    '.

    and R2 , biases the inputs O.5V above ground, d. Driving Ground-Referred Load
    within the common mode range of the device. An
    optional offset balancing circuit, R3 and R4 , is FIGURE 3. Typical Applications of the LMlll.
    included.

    The next circuit shows a comparator for a low· The applications described above show that the
    level photodiode operating with MOS logic. The output·circuit flexibility and wide supply·voltage
    output changes state when the diode current range of the LM111 opens up new fields for Ie
    reaches 1 pA. At the switching point, the voltage comparators. Further, its low error currents permit
    across the photodiode is nearly zero, so its leakage its use in circuits with impedance levels above
    current does not cause an error. The output 1 kQ. Although slower than older devices, it is
    switches between ground and -10V, driving the more than an order of magnitude faster than op
    data inputs of MOS logic directly. amps used as comparators.

    The last circuit shows how a ground·referred load The LM111 has the same pin configuration as the
    is driven from the ground terminal of the LM 111. LM710 and LM106. It is interchangeable with
    The input polarity is reversed because the ground these devices in applications where speed is not of
    terminal is used as the output. An incandes· prime concern.

    LB12-2
    r-
    OJ
    November 1970 ....
    I

    CAl

    »
    "tJ
    "tJ
    C
    (")
    APPLICATIONS OF THE
    LM 173/LM273/LM373 FM OPERATION ~
    The LM173 family of multi-mode IF amplifier/ Grounding the AGe input, pin 1, closes the o
    z
    detectors has been designed for AM, FM and SSB
    applications in the communications market. It con-
    switch connecting the quadrature capacitor to the
    quadrature network terminal pin 6_ This network,
    en
    sists of two amplifier sections, a gain control stage, tuned to the nominal center frequency of the IF o"T1
    a fully balanced FM/SSB detector, and an active strip gives a phase shift that varies with frequency
    AM/SSB peak detector whose output matches the at pin 6 (input A of the quadrature detector) with -I
    AGe input characteristics_ respect to the signal at input B_ This produces a ::I:
    m
    r-
    s:
    ....
    ""'"
    CAl
    .......
    r-
    s:N
    CAl
    ""'"
    .......
    r-
    s:CAl
    •• DUAUAIU .. ...
    .... URu ..... t ...",
    SSIII.g .... T ""'CAl"
    FIGURE 1_ Block Diagram of LM173

    To convert between modes of operation, one pulse duration modulation of the detector output
    simply makes the appropriate dc connections and current which is integrated by the capacitor on
    takes the recovered signal trom the output of the pin 7. This capacitor may also be used for
    desired detector. Two pins are involved in pro- de-emphasis_ A considerable range for compromise
    gramming the mode of operation, pin 1 and pin 6. exists in the choice of Q of the quadrature
    Since AGe is not normally used for FM, grounding network. Increasing the Q results in greater output
    pin 1 closes the quad capacitor switch to enable level and distortion for a given frequency devia-
    the balanced mixer to function as an FM tion. Also, the parallel resonant impedance of the
    quadrature detector. Since the balanced mixer is network should be such that ~50 mV rms signal
    not required for AM, connecting a resistor from appears on the quadrature phase terminal to ensure
    pin 6 to ground unbalances the mixer allowing it switching action of the detector and maximum
    to pass signal. Also, this transfers the balance output. An alternate higher level audio signal may
    sensing circuitry from the input of the balanced be taken from the peak detector output pin 8.
    mixer in FM (or SSB) mode to the input of the
    AM detector. For example, FM operation is Precise dc balance of input B of the quadrature
    achieved as shown in Figure 2. detector is maintained by an active dc feedback

    ,---------------------------l
    I j-----' I
    I I I
    I
    I
    I
    I
    .:,; 00------+
    ,".. I .. ~.-. 'I~'
    "~"I'~!~~ ~
    ~

    FIGURE 2_ FM IF Connection

    LB13-1
    network. The dc feedback bypass pin must be network to the input of the active peak detector
    decoupled at low frequencies to ensure stability of for optimum AM performance. Pin 6 should not
    this loop. A 1.0llF shunted by a .01 IlF for good be grounded directly or excessive device current
    high frequency decoupling is quite adequate. Note drain may result. Lifting the AGC input from
    that a dc path through the input or interstage filter ground opens the quad capacitor switch, as
    is not necessary (or desirable). described earlier.

    AM OPERATION An improvement in signal to noise ratio may be


    In Figure 3, the LM 173 functions as an AM IF obtained when interstage filtering is not used, or is
    amplifier and detector by unbalancing the bal· fairly broad, by connecting a parallel resonant
    anced mixer and connecting the peak detector circuit in shunt with the signal path at pin 7.

    '-----------~~~~~~~~~~--------------------l

    I I I
    I I
    I
    I
    II
    ,J
    .. c>o---_;
    .~

    FIGURE 3. AM IF Connection

    output to the AGC input through an RC network SSB OPERATION


    with a suitable attack/decay time constant. De· In single sideband operation, we require both AGe
    creasing the value of Rl will increase the AGC and balanced mixer functions and therefore we do
    range of the system at the expense of recovered not ground pin 1 or pin 6. By injecting 25 mV rms
    output level due to the reduced dc drop across R1 . or greater BFO signal into balanced mixer input A
    This voltage drop results from the AGC bias at pin 6, the mixer acts as a product detector, and
    current. we obtain our recovered audio at pin 7. The peak
    detector may then be used to generate an audio
    The balanced mixer is disabled by applying an derived AGC voltage as shown in Figure 4. The
    offset voltage to input A with resistor R2 to connection of a manual gain control for CW opera·
    ground. Th is also transfers the active dc balance tion is also illustrated.

    1----- --------- --- - - ---------,


    I 1----- 1 I
    I ' I
    I
    I
    I
    I

    O---_+
    .~ll ...

    FIGURE 4. 55B and CW IF Connection

    LB13-2
    r-
    Robert C. Dobkin
    November 1970
    ...
    tD
    I

    .j::Io

    en
    "tI
    m
    m
    C
    C
    "tI

    SPEED UP THE LM108 WITH -I


    ~
    FEEDFORWARD COMPENSATION m
    r-
    Feedforward frequency compensation of opera·
    tional amplifiers can provide a significant increa~e
    in slew rate and bandwidth over standard lag com·
    When the LM 108 is used with feedforward com·
    pensation, it is less tolerant of capacitive loading
    and stray capacitance. Precautions must be taken
    ...oS:.
    pensation. When feedforward compensation is 00
    applied to the LM101A operational amplifier,' an 12.
    lB.
    order of magnitude increase in bandwidth results. 10. FEED FORWAR~ ~
    A simple feedforward network has also been devel· .. ~ 10
    , COMPENSATI~
    If-- :-.. 135 ;:
    oped for use with the LM 108 micropower ampli·
    ~t-=
    z
    fier to give a factor of five improvement in speed. ~ 60
    v'" ."
    It uses no active components and does not degrade
    the excellent dc characteristics of the LM108.
    ~>~ 4D
    2D
    , ~t-= m
    m
    !----+- STANDARD ~
    t--~OMPENSATlDN
    F--&- C
    ."
    Figure 1 shows a schematic of an LM 108 using the ·20
    " o
    new compensation. The signal from the inverting
    input is fed forward around the input stage by a
    1 10 100 Ik 10k lOOk 1M 10M
    ::u
    ~
    FREOUENCY 1Hz)

    500 pF capacitor, C,. At high frequencies it pro·


    vides a phase lead. With this lead, overall phase
    FIGURE 2. Open Loop Voltage Gain »
    ::u
    C2
    5p' to insure stability. If load capacitance is greater c
    than about 75 to 100 pF, it must be isolated as (')
    shown in Figure 3. A small capacitor is always o
    needed to provide a lead across the feedback resis·
    tor to compensate for strays at the input. About 3
    s:"tI
    INPUT-'W,.,........~ to 5 pF is the minimum value capacitor. Care must m
    be taken to minimize stray capacitance at Pins 1, 2 :2
    OUTPUT
    and 8 when feedforward compensation is used. en
    Additionally, when the source resistance on the
    noninverting input is greater than 10k, it should be ~
    bypassed with a .01 IlF capacitor. o
    C1
    5DDpf
    :2

    FIGURE 1. LM108 with Feedforward Compensation "'


    lOOK

    shift is reduced and less compensation is needed to


    keep the ampl ifier stable. The C2 - R, network
    provides lag compensation, insuring that the open
    INPUT -'IN'Ir-<_-I
    loop gain is below unity before 1800 phase shift 50.
    R4

    occurs. The open loop gain and phase as a function >~"IIIM""OUTPUT


    of frequency is compared with standard compensa·
    tion in Figure 2. C,

    The slew rate is increased from 0.3V Ills to about C1


    1·"'01.'
    1.3V/Ils and the 1 kHz gain is increased from 500 500pF

    to 10,000. Small signal bandwidth is extended to • C2>S~;D5 pF


    3 MHz. The bandwidth must be limited to 3 MHz
    because the phase shift through the lateral PNP FIGURE 3. Oocoupling Load Capacitance
    transistors used in the second stage becomes exces·
    sive at higher frequencies. With the LM10l A,
    10 MHz bandwidth was possible since the signal As with any externally compensated amplifier,
    was bypassed around the low frequency lateral increasing the compensation of the LM108 in·
    PNP's. Nonetheless, 3 MHz is very respectable for creases the stability at the expense of slew and
    a micropower amplifier drawing only 300 IlA qui· bandwidth. The circuit shown is for the fastest
    escent current. response. Increasing the size of C2 to 20 or 30 pF

    LB14-1
    '1

    will provide 2 or 3 times greater stability and


    capacitive load tolerance. Therefore, the size of
    the compensation capacitor should be optimized
    for the bandwidth of the particular application.

    The stability ofthe LM108 with feedforward com·


    pensation is indicated by the small signal transient
    responses shown in Figure 4. It is quite stable since
    there is Iittle overshoot and ringing even though
    the amplifier is loaded with a 50 pF capacitor.
    Large signal transient response for a 20V square
    wave is shown in Figure 5. The small positive over·
    shoot is not severe and usually causes no problems.

    FIGURE 5. Large Signal Transient Response of LM10B


    with Feedforward Compensation

    ever, it is still wise to bypass the supplies for drill


    since noise on the V+ line can be injected to the
    summing junction by the 500 pF feedforward
    capacitor.

    The new feedforward compensation is easy to use


    and offers a factor of five improvement over stan-
    dard compensation. Slew rate is increased to
    1.3V /l1s and power bandwidth extended to
    20 kHz. Also, gain error at high frequencies is
    reduced. This makes the LM108 more useful in
    precision applications where low dc error as well as
    FIGURE 4. Small Signal Transient Response of LM10B low ac error is desired.
    with Feedforward Compensation

    REFERENCE:
    The LM 108 is unusually insensitive to power sup-
    ply bypassing with the new compensation. Even 1. Robert C. Dobkin, "Feedforward Compensa-
    with several feet of wire between the device and tion Speeds Op Amp," National Semiconductor
    power supply, it does not become unstable. How- LB-2, March, 1969.

    LB14-2
    r-
    eD
    Robert C. Dobkin .....
    I

    U1
    January 1971

    HIGH STABILITY REGULATORS

    Monolithic IC's have greatly simplified the design The negative regulator shown in Figure 2 operates
    of general purpose power supplies. With an IC similarly, except that discrete transistors are used
    regulator and a few external components 0.1 % for the pass element. A transistor, Q" level shifts
    regulation with 1% stability can be obtained. How· the output of the LM 108 to drive output transis·
    ever, if the application requires better perfor· tors, Q3 and Q•. Current limiting is provided by
    mance, it is advisable to use some other design Q2' Capacitors C3 and C. frequency compensate
    approach. the regulator.

    Precision regulators can be built using an IC op In the positil)e regulator the use of an LM109
    amp as the control ampl ifier and a discrete zener instead of discrete power transistors has several
    as a reference, where the performance is deter· advantages. First, the LM109 contains all the bias·
    mined by the reference. Figures 1 and 2 show ing and current limit circuitry needed to supply a
    schematics of simple positive and negative regu· 1A load. This simplifies the regulator. Second, and
    lators. They are capable of providing better than probably most important, the LM109 has thermal
    0.01 % regulation for worst case changes of line, overload protection, making the regulator virtually
    load and temperature. Typically, the line rejection burn·out proof. If the power dissipation becomes
    is 120 dB to 1 kHz; and the load regulation is excessive or if there is inadequate heat sinking, the
    better than 10 IlV for a 1A change. Temperature is LM109 will turn off when the chip temperature
    the worst source of error; however, it is possible to reaches 175°C, preventing the device from being
    achieve less than oa 0.01 % ~hange in the output destroyed. Since no such device is available for use
    voltage over a-55 C to +125 C range. in the negative regulator, the heat sink should be
    large enough to keep the junction temperature of
    the pass transistors at an acceptable level for worst
    case conditions of maximum ambient temperature,
    maximum input voltage and shorted output.

    VOUT-IOV
    IOUT<IA
    Although the regulators are relatively simple, some
    precautions must be taken to eliminate possible
    problems. A solid tantalum output capacitor must
    be used. Unlike electrolytics, solid tantalum capac-
    "' itors have low internal impedance at high fre-
    "
    005% quencies. Low impedance is needed both for
    frequency compensation and to eliminate possible
    minor loop oscillations. The power transistor
    R5
    recommended for the negative regulator is a
    " single-diffused wide-base device. This transistor
    Rl
    10K
    1N8l!
    D1
    type has fewer oscillation problems than double
    ".
    R1 005%
    diffused transistors. Also, it seems less prone to
    failure under overload conditions.
    IDtl,rmlnnnn,.currtnl
    MIIybtldluslidto
    mlnlm,ZI IMrm,' ~"h
    Some unusual problems are encountered in the
    lSolodtintaiunI construction of a high stability regulator. Com-
    ponent choice is most important since the resis-
    FIGURE 1. High Stability Positive Regulator tors, amplifier and zener can contribute to
    temperature drift. Also, good circuit layout is
    needed to eliminate the effect of lead drops,
    pickup, and thermal gradients.
    The operation of both regulators is straight-
    forward. An internal voltage reference is provided The resistors must be low-temperature-coefficient
    by a high-stability zener diode. The LM 108A' wirewound or precision metal film. Ordinary 1%
    operational amplifier compares a fraction of the carbon film, tin oxide or metal film units are not
    output voltage with reference. In the positive regu- suitable since they may drift as much as 0.5% over
    lator, the output of the op amp controls the temperature. The resistor accuracy need not be
    ground terminal of an LM1092 regulator through 0.005% as shown in the schematic; however, they
    source follower, Q,. Frequency compensation for should track better than 1 ppm/"C. Additionally,
    the regulator is provided by both the R, C2 combi- wirewound resistors usually have lower thermo-
    nation and output capacitor, C3 . electric effects than film types. The resistor driving

    LBl5-1
    ••UK

    Ql
    2N4343

    tOettllllinnnner
    cuulInt.MIi,1te
    IdlusttdtDminlmllll
    Ihnmaldnh.
    tSalidtntllum

    .,
    D.'
    --4....- ...- - - - -...- - . J
    INpur-. . .

    FIGURE 2. High Stability Negative Regulator

    the zener is not quite as critical; but it should Good construction techniques are important. It is
    change less than 0.2% over temperature. necessary to use remote sensing at the load, as is
    shown on the schematics. Even an inch of wire will
    The excellent dc characteristics of the LM 108A degrade the load regulation. The voltage setting
    make it a good choice as the control amplifier. The resistors, zener, and the amplifier should also be
    offset voltage drift of less than 5 J1.V/"C con- shielded. 80ard leakages or stray capacitance can
    tributes little error to the regulator output. Low easily introduce 100 J1.V of ripple or dc error into
    input current allows standard cells to be used for the regulator. Generally, short wire length and
    the voltage reference instead of a reference diode. single-point grounding are helpful in obtaining
    Also the LM108 is easily frequency compensated proper operation.
    for regulator applications.

    Of course, the most important item is the refer-


    ence. The IN829 diode is representative of the
    better zeners available. However, it still has a
    temperature coefficient of 0.0005%/"C or a maxi- REFERENCES:
    mum drift of 0.05% over a _55°C to 125°C
    temperature range. The drift of the zener is usually 1. R.J. Widlar, "Ie Op Amp Beats FETs on Input
    linear with temperature and may be varied by Current," National Semiconductor AN-29,
    changing the operating current from its nominal December, 1969.
    value of 7.5 mAo The temperature coefficient
    changes by about 50 J1.V/oC for a 15% change in 2. R.J. Widlar, "New Developments in IC Voltage
    operating current. Therefore, by adjusting the Regulators," in 1970 International Solid·State
    zener current, the temperature drift of the Circuits Conference Digest of Technical Papers,
    regulator may be minimized. Vol. XIII, pp. 158-159.

    LB15-2
    r
    eo
    I
    ~
    Robert C. Dobkin
    en
    March 1971

    m
    »
    C/)

    !:(
    -I
    EASILY TUNED c:
    SINE WAVE OSCILLATORS :2
    m
    One approach to generating sine waves is to filter a amplitude of the square wave fed back to the filter C
    square wave. This leaves only the sine wave funda· input. Starting is insured by Rs and C5 which pro- C/)
    mental as the output. Since a square wave is easily vide dc negative feedback around the comparator.
    amplitude stabilized by clipping, the sine wave This keeps the comparator in the active region. :2
    output is also amplitude stabilized. A clipping os- m
    If a lower distortion oscillator is needed, the cir-
    cillator eliminates the problems encountered with
    agc stablized oscillators such as those using Wein
    cuit in Figure 2 can be used. Instead of driving the ~
    bridges. Additionally, since there is no slow agc
    tuned circuit with a square wave, a symmetrically »
    loop, the oscillator starts quickly and reaches final
    clipped sine wave is used_ The clipped sine wave,
    of course, has less distortion than a square wave
    <m
    amplitude within a few cycles. and yields a low distortion output when filtered.
    oC/)
    (')
    .,
    330K
    ., r
    50K
    r
    »
    .15-_-....--. -I
    o
    ::tI
    C/)

    "
    1K

    OJ
    15DpF
    .,
    10M
    t Cl:C2
    I helluencvA.dlu~1
    • AmphtudeAdlu~t

    Fo~-'_
    2 ~ 1:1 'I. RJ R\

    FIGURE 1. Easily Tuned Sine Wave Oscillator

    The circuit in Figure 1 will provide both a sine and This circuit is not as tolerant of component values
    square wave output for frequencies from below 20 as the one shown in Figure 1. To insure oscillation,
    Hz to above 20 kHz. The frequency of oscillation is it is necessary that sufficient signal is applied to
    easily tuned by varying a single resistor. This is a the zeners for clipping to occur. Clipping about
    considerable advantage over Wein bridge ci rcu its 20% of the sine wave is usually a good value. The
    where two elements must be tuned simultaneously level of clipping must be high enough to insure
    to change frequency. Also, the output amplitude is oscillation over the entire tuning range. If the clip-
    relatively stable when the frequency is changed. ping is too small, it is possible for the circuit to
    An operational amplifier is used as a tuned circuit, cease oscillation due to tuning, component aging,
    driven by square wave from a voltage comparator. or temperature changes. Higher clipping levels in-
    Frequency is controlled by Rlo R2 , C" ~, and crease distortion. As with the circuit in Figure 1,
    R3 , with R3 used for tuning_ Tuning the filter this circuit is self-starting_
    does not affect its gain or bandwidth so the output Table 1 shows the component values for the
    amplitude does not change with frequency. A various frequency ranges. Distortion from the cir-
    comparator is fed with the sine wave output to cuit in Figure 1 ranges between 0.75% and 2%
    obtain a square wave. The square wave is then fed depending on the setting of R3 . Although greater
    back to the input of the tuned circuit to cause tuning range can be accomplished by increasing
    oscillation. Zener diode, D" stabilizes the the size of R3 beyond 1kn, distortion becomes

    LB16-1
    .,Fco R5
    10K
    ",
    200K

    .,
    330K

    ••
    10K el' C2'

    OUTPUT

    t Cl ~ C2
    I FlfqulncvAdJul1
    • CllppmgLevelAdlul1
    FO=~
    2"C'\1'RJ Rl 150pF"
    FIGURE 2. Low Distortion Sine Wave Oscillator

    excessive. Decreasing R3 lower than 50n can bypassing is in order. Both the positive and
    make the filter oscillate by itself. The circuit in negative supplies should be bypassed with a O.lpF
    Figure 2 varies between 0.2% and 0.4% distortion disc ceramic capacitor. The fast transition at the
    for 20% clipping. output of the comparator can be coupled to the
    sine wave output by stray capacitance, causing
    About 20 kHz is the highest usable frequency for
    spikes on the output. Therefore the output of the
    these oscillators. At higher frequencies the tuned
    comparator with the associated circuitry should be
    circuit is incapable of providing the high Q band-
    shielded from the inputs of the op amp.
    pass characteristic needed to filter the input into a
    clean sine wave. The low frequency end of os- Component choice is also important. Good quality
    cillation is not limited except by capacitor size. resistors and capacitors must be used to insure
    temperature stability. Capacitor should be mylar,
    TABLE 1 polycarbonate, or polystyrene - electrolytics will
    MIN. MAX. not work. One percent resistors are usually
    adequate.
    C1 , C2 FREQUENCY FREOUENCY
    The circuits shown provide an easy method of
    0.47 pF 18 Hz 80 Hz generating a sine wave. The frequency of os-
    0.1 pF 80 Hz 380 Hz cillation can be varied over greater than a 4 to 1
    .022 pF 380 Hz 1.7 kHz range by changing a single resistor. The ease of
    .0047 pF 1.7 kHz 8 kHz tuning as well as the elimination of critical agc
    .002pF 4.4 kHz 20 kHz loops make these oscillators well suited for high
    volume production since no component selection
    is necessary.
    In both oscillators, feedforward compensation 3 is References:
    used on the LM101A amplifiers to increase their
    1. N.P. Doyle, "Swift, Sure Design of Active
    bandwidth. Feedforward increases the bandwidth
    Bandpass Filters," EON, Vol. 15, No.2, January
    to over 10 MHz and the slew rate to better than
    1 OV Ips. With standard compensation the 15,1970.
    maximum output frequency would be limited to 2. R.J. Widlar, "Precision IC Comparator Runs
    about 6 kHz. from 5V Logic Supply," National Semiconduc-
    Although these oscillators are not particularly
    tor AN-41, October, 1970.
    tricky, good construction techniques are im- 3. Robert C. Dobkin, "Feedforward Compensation
    portant. Since the amplifiers and the comparators Speeds Op Amp," National Semiconductor
    are both wide band devices, proper power supply L/3-2, March, 1969.

    LBl6-2
    Robert C. Dobkin
    ...,
    ~
    September 1971

    r-
    ...s::
    00

    LM118 OP AMP SLEWS 70 V!p.s o


    "C
    One of the greatest limitations of today's mono- Figure 1 shows a simplified schematic of the
    LM118. Transistors 0, and O2 are a conventional
    »
    lithic op amps is speed. With unity gain frequency
    differential input stage with emitter degeneration
    S
    compensation, general purpose op amps have "C
    1 MHz bandwidth and 0.3 VIlls slew rate. Opti- and resistive collector loads. 0 3 and 0 4 form the
    mized compensation as well as feedforward com· second stage which further amplify the signal and en
    level shift the signal towards V-. The collectors of
    r-
    pensation can improve op amp speed for some m
    applications. Specialized devices such as fast,unity· 0 3 and 0 4 drive a current inverter, 010 and 0"
    ~
    gain buffers are available wh ich provide partial
    solutions. This paper will describe a new high
    to convert from differential to single ended. 0 9 ,
    which has a current source load for high gain,
    en
    ~
    speed monolithic amplifier that offers an order drives a class B output. The collectors of the input
    o
    of magnitude increase in speed with no loss in
    flexibility over general purpose devices.
    stage and the base of 0 9 are available for offset
    balancing and external compensation.
    <
    .......
    't:
    The LM 118 is constructed by the standard six Frequency compensation is accomplished with !II
    mask monolithic process and features 15 MHz three internal capacitors. C, rolls off on half the
    bandwidth and 70 VIlls slew rate. It operates over differential input stage so that the high frequency
    a ±5 to ±18V supply range with little change in signal path is single-ended. Also, at high fre·
    speed. Additionally, the device has internal unity· quencies, the signal is fed forward around the
    gain frequency compensation and needs no exter· lateral PNP transistors by a 30 pF capacitor, C2 .
    nal components for operation. However, unlike This eliminates the excessive phase shift. Overall
    other internally compensated amplifiers, external frequency response is then set by capacitor, C3 ,
    feed forward compensation may be added to ap· which rolls off the amplifier at 6 dB/octive. As
    proximately double the bandwidth and slew rate. previously mentioned feedforward compensation
    for inverting applications can be applied to the
    DESIGN CONCEPTS base of 0 9 , Figure 2 shows the open loop fre·
    quency response of an LM 118. Table 1 gives
    In general purpose amplifiers the unity·gain band· typical specifications for the new amplifier.
    width is limited by the lateral PNP transistors used
    for level shifting. The response above 2 MHz is so
    poor that they cannot be used in a feedback
    amplifier. If the PNP transistors are used for level 120

    shifting only at DC or low frequencies and the 100


    signal is fed forward around the PNP transistors at 80
    high frequencies, wide bandwidth can be obtained "''"
    60
    without the excessive phase shift of the PNP 1i
    40
    transistors. ~

    ~ 20

    10 1110 It 10k lOOk 1M 10M 100M


    FREQUENCY (Hz)

    FIGURE 2. Open Loop Voltage Gain as a function of


    Frequency for LMl18.

    TABLE 1. Typical Specifications for the LMl18

    Input Offset Voltage 2 mV


    Input Bias Current 200 nA
    Offset Cu rrent 20 nA
    Voltage Gain 200K
    Common Mode Range ±11.5V
    Output Voltage Swing ±13V
    Small Signal Bandwidth 15 MHz
    FIGURE 1. Simplified Circuit of the LM118 Slew Rate 70 V IllS

    LB17-1
    OPERATING CONFIGURATION At high gains,or with high value feedback resistors
    R4 can be quite low-but not less than lOOn.
    Although considerable effort was taken to make
    When the LMl18 is used a fast integrator, with
    the LM 118 trouble free, high frequency ampli-
    a large feedback capacitor or with low values
    fiers are more prdne to oscillations than low
    of feedback resistance, R4 must be increased to
    frequency devices such as the LM101A. Care must
    8 kn to insure stability over a full -55°C to
    be taken to minimize the stray capacitance at the
    125°C temperature range.
    inverting input and at the output; however the
    LMl18 will drive a 100 pF load_ Good power One of the more important considerations for a
    supply bypassing is also in order-O_l JlF disc high speed amplifier is settling time. Poor settling
    ceramic capacitors should be used within a few time can cancel the advantages of having high slew
    inches of the amplifier_ Additionally, a small rate and bandwidth. For example-an amplifier can
    capacitor is usually necessary across. the feedback have severe ringing after a step input. A relatively
    resistor to compensate for unavoidable stray long time is then needed before the output volt-
    capacitance. age can be read accurately. Settling time is the
    time necessary for the output to slew through a
    Figure 3 shows feedforward compensation of the
    defined voltage change and settle to within a de-
    LMl18 for fast inverting applications. The signal
    fined error of its final output voltage. Figure 4
    is fed from the summing junction to the output
    stage driver by C, and R4. Resistors Rs , Rs and shows optimized compensation for settling to
    R7 have two purposes: they increase the internal .2
    operating current of the output stage to increase 5.
    slew rate and they provide offset balancing. The
    current boost is necessary to drive internal stray
    capacitance at the higher slew rate. Mismatch of .,
    5.
    the external resistors can cause large voltage offsets
    so offset balancing is necessary. For supply volt-
    ages other than ± 15V, R5 and Rs should be
    selecteo to draw about 500 JlA from Pins 1 and 5 .

    •2
    5K tSlew and settling Ilm~ to 0.1%
    fora lOY rup change 15800 ns

    .,
    5.
    FIGURE 4. Compensation for Minimum Settlingt Time

    within 0.1% error. Typically the settling time is


    800 ns for a simple inverter circuit as shown.
    Settling time is, of course, subject to operating
    conditions external to the IC such as closed loop
    gain, circuit layout, stray capacitance and source
    resistance. An optional offset balancing circuit,
    tSlew rate tvpll:allv 120VllJs.
    R3 and R4 is included.
    FIGURE 3. Feedforward Compensation for Greater
    Inverting Slew Rate t The LMl18 opens up new fields for IC operational
    amplifiers. It is more than an order of magnitude
    When using feedforward, resistor R4 should be faster than general purpose amplifiers while retain-
    optimized for the application. It is necessary to ing the ease of use features. It is ideally suited for
    have about 8 kn in the path from the output of analog to digital converters, active filters, sample
    the amplifier through the feedback resistor and and hold circuits and wide band amplification.
    through feedforward network to Pin 8 of the Further, the LM 118 has the same pin configuration
    device. The series resistance is needed to limit the as the LM101A or LM741 and is interchangeable
    bandwidth and prevent minor loop oscillation. with these devices when speed is of prime concern.

    L817-2
    I""

    Helge H_ Mortensen
    July 1972
    ...,
    !XI

    00

    +
    U'1
    -I
    o
    +5 TO -15 VOLTS DC CONVERTER ...
    I
    U'1

    <
    o
    INTRODUCTION I""
    -I
    It is frequently necessary to convert a DC voltage voltage minus VSAT - The current change in the en
    to another higher or lower DC-voltage while maxi- inductor is given by:
    mizing efficiency_ Conventional switching regula- C
    (')
    tors are capable of converting from a high input VSS .: VSAT Vss
    DC voltage to a lower output voltage and satisfying III ; L X TON '" L TON (1)
    (')
    the efficiency criteria_ The problem is a little more o
    troublesome if a higher output voltage than the Turning OFF the transistor the inductor current z
    input voltage is desired_ Particularly, generating
    DC voltage with opposite polarity to the input
    has a path through the catch diode and this in
    turn builds up a negative voltage across R L.
    <
    m
    voltage usually involves a complicated design_ ::a
    The figure also shows the current and voltage -I
    This brief demonstrates the use of the switching levels versus time. A capacitor in parallel to the m
    regulator idea for a +5 volts to -15 volts converter_ resistor will prevent the voltage from dropping ::a
    The converter has an application as a power supply to zero during the transistor ON time.
    for MOS memories in a logic system where only
    +5 volts is available_ However, the principle used Assuming a large capacitor, we cah also write the
    can be applied for almost any input output com- current change as:
    bination_
    VOUT - V D VOUT
    OPERATION III ; L X T OFF'" - L - X T OFF (2)

    The method by which the regulator generates the


    opposite polarity is explained in Figure 1. The In order to get a general idea of the operation for
    transistor Q is turned ON and OFF with a given certain input output conditions, we will develop
    duty cycle_ If the base drive is sufficient the volt- a set of equations.
    age across the inductor is equal to the supply
    During the transistor ON time, energy is loaded
    into the inductor. In the same time interval, the
    v" capacitor is drained due to the load resistor R L-

    --cr "..
    .... VOUT
    Drop in capacitor voltage:

    ILOAD X TON

    Ie lIV ; C (3)

    I~ A,
    L

    .;:- "=- J During the T OFF time the stored energy in the
    inductor is transferred to the load and capacitor .
    A rough estimate of T OFF can be expressed as:

    IINDUCTOR
    VSS (4)
    TOFF VOUT X TON

    The capacitor voltage will be restored with a


    1 i i i i I> t
    average current given by:
    L--TON~ToFF I

    lIV XC ILOAD X VOUT


    Ie; T OFF ; VSS (5)

    The total inductor current during the OFF time


    can be written as:

    FIGURE 1. Switching Circuit for Voltage Conversion (6)

    LB18-1
    Vss = +5V

    R5
    10K

    '1 = P~I~T ill. 75%

    .8 f = 6 kHz 80% DUTY


    lOan VRIPPLE = IOOmVfiil2OOrnAOUT
    IL" 200 rnA MAX
    VOUT "-15V
    C1
    L
    lO,oDOpF
    lmH

    .8
    2DK

    D2 C2
    INlaBD SODlJf

    FIGURE 2. Switching Regulator for Voltage Conversion

    Inspecting Figure 1. We find: By setting the duty cycle higher than first calcu-
    lated, the output voltage will tend to increase
    L'li Vss X TON above the desired output voltage of 15 volts.
    Ic = "2 -~ (7)
    However, an extra loop performed by 0, and
    the zener diode in conjunction with the resistor
    which yields: network will modify the oscillator duty cycle
    until the desired output level is obtained.
    2XLXlLOAOXVOUT
    TON = (8) The output voltage is given by:

    Taking into account that the efficiency is in the


    order of 75% the final expression is:

    1.5 X LX I LOAD X V OUT Data and results obtained with the design:
    TON = (9)
    V ,N 5 volts

    The above equations will be applied to the regu- V OUT -15 volts
    lator shown at Figure 2. The regulator must deliver lOUT max 200 mA
    -15 volts at 200 mA from a +5 volt supply. Using a Efficiency ~ 75%
    1 mH inductor the TON time for O 2 is 0.18 ms
    from equation 9. T OFF is 60 IlS from equation 4 Frequency ~ 6 kHz 80% duty cycle
    and the oscillator frequency to: VRIPPLE ~ 100 mV @ 200 mA load

    1 Line regulation: V ,N = 5V to 10V < 3% V OUT


    F = TON + T OFF"" 4 kHz I LOAD = 200 mA
    Load regulation: V ,N = 5V < 3% V OUT
    The LM311 performs a free running multivibrator lLOAD = 0 - 100 mA
    with high duty cycle. The I C is designed to operate
    from a standard single 5 volt supply and has a high
    output current capability for driving the switching
    REFERENCE
    transistor O 2 , The duty cycle is given by the volt-
    age divider R3 and R4 and the frequency of C, Widlar, R. J., "Designing Switching Regulators"
    in conjunction with R5 . AN2, National Semiconductor Corp.

    LB18-2
    Marvin VanderKooi
    August 1972
    ...
    I

    tD

    '"C
    :ll
    m
    C

    PREDICTING OP AMP SLEW RATE


    n
    -I
    LIMITED RESPONSE
    :2
    C)
    The following analysis of sine and step voltage
    responses applies to all single dominant pole op -dvo
    dt
    I=21TfV p
    (3)
    o
    amps such as the LM101A, LM107, LM108A, t=O '"C
    LM112, LM118 and the LM741. Each of these
    op amps has an open loop response curve with a »
    shape similar to the one shown in Figure 1. The
    (4)
    s:
    '"C
    distinguishing feature of this curve is the single
    low frequency turnover from a flat response to en
    a uniform -20 dB per decade of frequency (-6 dB/ where: Vo = output voltage r-
    octave) drop in gain, at least until the curve passes Vp = peak outpu t voltage m
    through the 0 dB line. Closing the loop to 40 dB
    . dvo
    ~
    (X 100) as shown with a dotted line on Figure 1
    does not change the shape of the curve, but it does
    S, = maximum dt ::c
    move the turnover to a higher frequency. These »-I
    open loop and closed loop response curves deter· The maximum sine wave frequency an amplifier
    mine the gain applied to small signal inputs. The with a given slew rate will sustain without causing
    m
    logical question then arises as to when a signal the output to take on a triangular shape is therefore r-
    can no longer be treated as a small signal and the
    amplifier response begins to deviate from this
    a function of the peak amplitude of the output
    and is ex pressed as:
    s:
    curve. ::::j
    m
    f max =~ (5) C
    120 21T Vp
    100 :tI
    ~ m
    ~
    z
    1i
    :l
    so
    60

    4D
    ." f'\,
    Equation 5 demonstrates that the borderline be·
    tween small signal response and slew rate limited
    response is not just a function of the peak output
    signal but that by trading off either frequency or
    en
    '"C
    o
    ~ 2D I'- peak amplitude one can continue to have a distor·
    :2
    "\. tion free output. Figure 2 shows a quick reference
    en
    r'\ graphical presentation of equation 5 with the area
    m
    -20
    1 10 100 HI Ilik lOOk 1M 10M above any VPEAK line representing an undistorted
    fREQUENCY (Hl)
    small signal response and the area below a given
    V PEAK line representing a distorted sine wave reo
    FIGURE 1. Open and Closed Loop Frequency Response sponse due to slew rate limiting.

    The answer lies in the slew rate limit of the op amp.


    The slew rate limit is the maximum rate of change
    IDD~~~ SMALL SIGNAL
    RESPONSE AREA

    of the amplifier's output voltage and is due to the ~ 10 V~~AK" 16V Ht-H+tt->ISI,*r'I
    VPEA f(=8V
    fact that the compensation capacitor inside the
    amplifier only has finite currents 1 available for
    charging and discharging. A sinusoidal output sig·
    nal will cease being small signal when its maximum 0.1

    rate of change equals the slew rate limit S, of the SLEW RATE
    LIMITING AREA
    amplifier. The maximum rate of change for a sine .01
    100 lk 10k 10l1li 1M
    wave occurs at the zero crossing and may be de·
    SINE WAVE fREQUENCY (Hz)
    rived as follows:

    FIGUR E 2. Sine Wave Response


    vo= Vpsin 2n ft (1)

    As a matter of convenience, ampl ifier manufac-


    dv
    dto = 2nf Vp cos 2n It (2)
    turers often give a "full-power bandwidth" or
    "large signal response" on their specification sheets.

    LB19·1
    This frequency can be derived by inserting the will go into slew rate limiting. The output will then
    amplifier slew rate and peak rated output voltage be a ramp function with a slope of S, and a rise time
    into equation 5. The bandwidth from DC to the equal to:
    resulting f max is the full-power bandwidth or "large
    signal response" of the amplifier. For example the
    full·power bandwidth of the LM741 with a 0.5V jl.s t' = V STEP (8)
    , S,
    S, is approximately 6 kHz while the full· power
    bandwidth of the LM 118 with an S, of 70 V /jl.s is
    approximately 900 kHz. Substituting equation 6 into equation 7 gives the
    critical value of VSTEP directly in terms of f3dB :
    The step voltage response at the output of an op
    amp can also be divided into a small signal response
    and a slew rate limited response. The single turnover VSTEP f3d8
    and uniform -20 dB/decade slope shown in the 0.35 ~S, (9)
    small signal frequency response curve of Figure 1
    are also characteristic of a low pass filter and one
    which can be graphed as shown in Figure 4. Any
    can in fact model an op amp as a low pass RC
    point in the area above a VSTEP line represents
    filter followed by a very wideband amplifier. Figure
    an undistored low pass filter type response and any
    3 shows a model ofaX 100 circu it with a 3 dB down
    point in the area below a given VSTEP line repre·
    rolloff frequency of 10kHz. From basic filter
    sents a slew rate limited response.

    ~
    f_=211~C i!i;i! 0.1 '~I~ijSl VSTEP=1V
    K
    ~~~~~[S~l~m~.~M~E~
    '3dB= 10kHz
    LIMITING AREA
    .01
    1k 10k 100k 1M 10M 10~
    FIGURE 3. Small Signal Op Amp Model
    J dB DOWN FREQUENCV, f3dB (Hz)

    theory 2 the 10% to 90% rise time of single pole FIGURE 4. Step Voltage Response
    low pass filter is:

    0.35 The above equations and graphs should allow one


    t =-- (6) to avoid the pitfalls of slew rate limiting and also
    , f3dB
    provide a means of using engineering tradeoffs to
    extend the response of the single dom inant pole
    which for this example would be 35 jl.S. Again this type of amplifier.
    small signal or low pass filter response ceases when
    the required rate of change of the output voltage REFERENCES
    exceeds the slew rate limit S, of the amplifier.
    Mathematically stated: 1. Solomon, J.E.; Davis, W.R.; and Lee, P.L.: "A
    Self-Compensated Monolithic Operational Am-
    plifier With Low Input Current and High Slew
    VSTEP >S (7) Rate", pp 14-15, ISSCC Digest Tech. Papers,
    t , -,
    February 1969.
    This means that as soon as the amplitude of the 2. Millman, J. and Hawkias, C.C.: "Electronic
    output step voltage divided by the rise time of the Devices and Circuits", pp 465-466, McGraw·
    circuit exceeds the S, of the amplifier, the amplifier Hill Book Company, New York, 1967.

    LB19·2
    r-
    OJ
    I
    Helge H. Mortensen N
    December 1972 o

    »
    A FULLY DIFFERENTIAL INPUT VOLTAGE AMPLIFIER
    "Cr-
    (INSTRUMENTATION AMPLIFIER) ~,

    c
    INTRODUCTION

    The instrumentation amplifier is useful for ampli· currents of the transistors are well matched for a
    ""m
    fying small differential signals which may be OV differential input signal. The current sources ::XI
    riding on high common mode voltage levels. These which bias Q 1 and Q2, are chosen to be 100llA m
    amplifiers are particularly useful in amplifying each to guarantee high {3 and low offset voltage in :2
    signals in the milli·volt range which are supplied Q 1 and Q2. -I
    from a high impedance source (>2kn).
    The gain of the amplifier is calculated as follows:
    »
    r-
    This brief will demonstrate how a low cost, high Any differential input voltage, Ll.V 1N , appears
    performance instrumentation amplifier can be across R1, and produces a current change Ll.I, which :2
    built using the newly introduced LM3900 quad is given by: ""tI
    amplifier. It is also indicated how a compact C
    transducer bridge amplifier system can be developed -I
    to take advantage of the versatility of the LM3900. Ll.1 (1)
    <
    o
    BASIC AMPLIFIER OPERATION This current change will show up in the collectors !:j
    Figure 1 shows the basic operation of the amplifier.
    of Q 1 and Q2 with opposite polarity. The input »
    C)
    mirror Of the LM3900 returns Ll.lo1 to the
    The bias of the LM3900 is set by the resistors R2 inverting input terminal where it is added (with m
    and R3 (neglecting for now, the transistors Q1 sign) to Ll.lo2 yielding a total current change of
    »
    and Q2). Current which enters the non·inverting
    input of the LM3900 will be "mirrored" about
    2Ll.1. This current flows through the feedback
    resistor, R3 , which causes an output voltage s:""tI
    V ~nd then will be drawn into the inverting change, Ll.Vo, which is given by:
    input terminal. This causes the current to flow
    r-
    through the feedback resistor, R3 , which establishes
    the output voltage level. If R2 = R3 and further, if
    "m
    R2 is connected to ground (OVL then the output ::XI
    voltage biasing level will also be exactly zero volts.
    It should be noticed that an OUTPUT OFFSET
    to yield a gain,
    :2
    CONTROL can be implemented by supplying a Cf)
    reference voltage, E R , between R2 and ground. -I
    ::XI
    C
    r----4~---....o(l V+=.15V (3)
    s:m
    '.J 2
    Av =R1" -I
    At this point it is convenient to evaluate the
    result obtained. The gain can be established by »
    -I
    •J one resistor (R 1 ) according to equation (3) .
    +~--1---t-~r __~~'M~ Conventional instrumentation amplifiers usually o
    have a gain given by: :2
    r
    VCOM
    »
    ~ ., 1M
    v,
    Av
    Constant
    +--- (4) s:
    ."
    R
    E.
    L----oV-=-15V
    !:
    l This means that the minimum gain of unity is
    obtained if R is left out (R = 00). Note that this is "m
    ::XI
    FIGURE 1. Basic Instrumentation Amplifier.
    different from the result indicated in equat.ion (3)
    where unity gain is obtained for

    AddingtransistorsQ1 and Q2, as shown in Figure 1


    will not disturb this biasing if the two collector (5)

    LB20·1
    and minimum gain (or maximum attenuation) is only the procedure for nulling the amplifier will
    obtained if R1 is left out (R 1 ; 00). This suggests be incl uded.
    that the amplifier can be turned OFF without
    disturbing the output voltage de bias. Letting R1 go to zero causes the amplifier to
    operate in the open-loop mode. The main offset
    The two current sources for 0 1 and O2 are
    implemented with a dual transistor (03 and 0 4 )
    in conjunction with an additional amplifier of the 120

    LM3900 as shown in Figure 2. The operation can 100


    be easily understood if R4 and R5 are incorpo·
    ~ BO r- RII.o
    rated within the amplifier, which then takes the 2
    60
    form of a conventional opamp closed loop regula· ~
    w
    tor- which maintains a reference voltage (the drop ~ 40

    across R6 ) at the emitter of ~. ~


    g 20
    R1 =2Mn

    PERFORMANCE -20
    10 100 1K 10K lOOK 1M 10M
    The performance of the complete instrumentation
    FREQUENCY (Hz)
    amplifier of Figure 2 is outlined below (Table 1
    and Figure 3).
    FIGURE 3. Frequencv Response

    TABLE 1. Typical Performance Characteristics


    voltage source is now the VSE mismatch of 0,
    GAIN
    Rangeofgaon -J4dB1R, EOOllondB(R , ~Ol
    and O2 , The output can be nulled by the OUTPUT
    G~on.s set accordIng 10 Av -
    '",
    R,
    OFFSET CONTROL (the reference voltage for R2 )
    or by adjusting the value of R2 • With R, = 00, the
    INPUT
    Vohageollsotrefecredto,nput"adJu,nblelOzero main offset voltage source is the mismatch in the
    Common mode and d,fferenllallnput ."Itage
    Pos supplvleu24V
    Neg supply leu 300 mV
    collector currents of 0 3 and 0 4 , This is easily
    Common mode 'elKI,on rallO al 10 Hz 115dB (gaonol 10001 adjusted via R12 . These first and second adjust-
    B,ascurrent (ellher ,npul)
    ments interact, however, after repeating the pro-
    Output of he I 'sadjustlble 10 zero
    cedure a couple of times a good result is obtained.
    Qutpulno.se 12 mV"",(openIOOill
    JmVrm.(ACL -66dBI
    FREQUENCY RESPONSE
    1 MHz (gain of 10001
    TRANSDUCER BIAS SOURCE
    Smalisl!lRlIllrequencyresponsel-JdB)
    3MHzIgalnofl)

    Having in mind that the LM3900 consists of four


    independent amplifiers makes it relatively easy to
    Since quantitative discussion of the sources of bias a transducer bridge with a constant current
    offset vo Itage is beyond the scope of th is brief, source using only one more of the amplifiers and
    one resistor. The technique is self-explanatory and
    is also shown in Figure 2.

    CONCLUSION

    A brief review of a new concept for an instrumen-


    tation amplifier has been presented. Many applica-
    tions can be derived from this basic connection
    which require amplifying the low level differential
    signals which are obtained from sensors such as
    strain gages, pressure transducers, and thermo-
    couples. The performance of this instrumentation
    amplifier is adequate for many system applications.
    (See National Semiconductor Application Note 72,
    "The LM3900 - A New Current-Differencing Ouad
    FIGURE 2. Bridge Amplifier of ± Input Amplifiers" for further information.)

    LB20-2
    ACKNOWLEDGMENTS

    Editor
    Marvin 1<. Vander Kooi

    Authors
    J. E. Byerly W. S. Routh
    G. Cleveland B. Siegel
    R. C. Dobkin R. S. Sleeth
    T. M. Frederiksen T. Smathers
    T. Hanna R. Stump
    R. Hirschfeld R. K. Underwood
    W. M. Howard L. VanDer Gaag
    E. L. Long M. K. Vander Kooi
    T. B. Mills R. J. Widlar
    W. B. Mitchell C. M. Wittmer
    H. H. Mortensen D. L. Wollesen
    D. Mrazek M. Yamatake
    Nalional Semiconductor Corporation
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