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    Exp 7 Vlsi5151

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    Sandeep Verma
    The document describes an experiment to design and simulate a 2x1 multiplexer (MUX) using the SymicaDE simulation tool. The experiment involves: 1) Designing the basic logic gates (AND, OR, inverter) using transistors in the tool. 2) Using the basic gates to design a 2x1 MUX circuit according to its functionality of selecting one of two inputs for the output based on a control signal. 3) Simulating the designed 2x1 MUX circuit and measuring the delay from the control signal to the output.

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    Exp 7 Vlsi5151

    Uploaded by

    Sandeep Verma
    49 views6 pages
    The document describes an experiment to design and simulate a 2x1 multiplexer (MUX) using the SymicaDE simulation tool. The experiment involves: 1) Designing the basic logic gates (AND, OR, inverter) using transistors in the tool. 2) Using the basic gates to design a 2x1 MUX circuit according to its functionality of selecting one of two inputs for the output based on a control signal. 3) Simulating the designed 2x1 MUX circuit and measuring the delay from the control signal to the output.

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    EXP 7 VLSI5151

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    The document describes an experiment to design and simulate a 2x1 multiplexer (MUX) using the SymicaDE simulation tool. The experiment involves: 1) Designing the basic logic gates (AND, OR, inverter) using transistors in the tool. 2) Using the basic gates to design a 2x1 MUX circuit according to its functionality of selecting one of two inputs for the output based on a control signal. 3) Simulating the designed 2x1 MUX circuit and measuring the delay from the control signal to the output.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    49 views6 pages

    Exp 7 Vlsi5151

    Uploaded by

    Sandeep Verma
    The document describes an experiment to design and simulate a 2x1 multiplexer (MUX) using the SymicaDE simulation tool. The experiment involves: 1) Designing the basic logic gates (AND, OR, inverter) using transistors in the tool. 2) Using the basic gates to design a 2x1 MUX circuit according to its functionality of selecting one of two inputs for the output based on a control signal. 3) Simulating the designed 2x1 MUX circuit and measuring the delay from the control signal to the output.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 6

    Date: 07/10/2020

    Experiment No. 7
    Aim: To design and Simulate 2x1 MUX using SymicaDE Tool .

    Tool & Apparatus Used: SymicaDE 3.1.0.0209

    Theory:

    AND GATE: The AND gate is a basic digital logic gate that implements logical conjunction - it
    behaves according to the truth table to the right. A HIGH output (1) results only if all the inputs
    to the AND gate are HIGH (1). If none or not all inputs to the AND gate are HIGH, LOW output
    results. The function can be extended to any number of inputs.

    OR GATE: The OR gate is a digital logic gate that implements logical disjunction – it behaves
    according to the adjacent truth table. A HIGH output (1) results if one or both the inputs to the
    gate are HIGH (1). If neither input is high, a LOW output (0) results. In another sense, the
    function of OR effectively finds the maximum between two binary digits, just as the
    complementary AND function finds the minimum.

    2X1 MUX: The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit
    designed to switch one of several input lines through to a single common output line by the
    application of a control signal. A 2-to-1 multiplexer consists of two inputs I0 and I1, one select
    input S and one output Y. Depends on the select signal, the output is connected to either of the
    inputs. Since there are two input signals only two ways are possible to connect the inputs to the
    outputs, so one select is needed to do these operations.

    A B A OR B A B A AND B
    0 0 0 0 0 0
    0 1 1 0 1 0
    1 0 1 1 0 0
    1 1 1 1 1 1

    Table 7.1 Truth Table of OR gate Table 7.2 Truth Table of AND gate
    Design and Simulation:

    Table 7.3 Design specifications of CMOS Inverter

    Parameters Values
    CMOS Technology PTM 130nm
    NMOS: W/L 360nm/180nm
    PMOS: W/L 720nm/180nm
    VDD 1.8V
    Input signal (Pulse) V1=1.8V, V2=0, Time
    Period=100ns, Pulse Width=50ns

    Figure 7.1 Schematic of AND gate(by connecting an inverter to NAND)

    Figure 7.2 Schematic of OR gate(by connecting an inverter to NOR)


    FIG7.3 Schematic of 2x1 MUX using AND OR gates and inverter

    FIG 7.4 Simulation of 2x1 MUX (using AND OR gates)


    Fig 7.5 Simulation of 2X1 MUX (using NMOS PMOS and INVERTER)

    Observation:
    INPUT SIGNAL PULSE-

    I0 = Vdd

    I1 = 0

    S: V1= 1.8 V, V2= 0V

    Period = 100nsec, Pulse Width=50nsec


    Figure 7.6 Transient result of 2x1 MUX output (using AND OR gates)

    Figure 7.7 Transient result of 2X1 MUX output( using NMOS PMOS and INVERTER)
    Result:

     Delay from S to OUTPUT (using AND OR GATE) = 1.85244e-010

     Delay from S to OUTPUT (using NMOS PMOS and INVERTER) = 1.56321e-010

     2X1 MUX circuit has been successfully designed using SymicaDE tool.
     Transient analysis is performed for the designed 2X1 MUX.

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