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    VVC Syllabus

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    Ramesh Mallai
    This document provides information about a course on Testing and Verification of VLSI Circuits. The course objectives are to study fault modeling and detection techniques, understand test generation for combinational and sequential logic circuits, and explore design for testability and self-test methods. The course covers fundamentals of testing, test generation and simulation, fault models, design and verification techniques, and timing verification of VLSI circuits over 5 units spanning 45 periods. Upon completing the course, students will be able to insert elementary testing hardware, analyze timing using Logical Effort analysis, estimate power consumption, and understand test generation and simulation concepts.

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    © All Rights Reserved

    VVC Syllabus

    Uploaded by

    Ramesh Mallai
    68 views1 page
    This document provides information about a course on Testing and Verification of VLSI Circuits. The course objectives are to study fault modeling and detection techniques, understand test generation for combinational and sequential logic circuits, and explore design for testability and self-test methods. The course covers fundamentals of testing, test generation and simulation, fault models, design and verification techniques, and timing verification of VLSI circuits over 5 units spanning 45 periods. Upon completing the course, students will be able to insert elementary testing hardware, analyze timing using Logical Effort analysis, estimate power consumption, and understand test generation and simulation concepts.

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    VVC SYLLABUS

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    This document provides information about a course on Testing and Verification of VLSI Circuits. The course objectives are to study fault modeling and detection techniques, understand test generation for combinational and sequential logic circuits, and explore design for testability and self-test methods. The course covers fundamentals of testing, test generation and simulation, fault models, design and verification techniques, and timing verification of VLSI circuits over 5 units spanning 45 periods. Upon completing the course, students will be able to insert elementary testing hardware, analyze timing using Logical Effort analysis, estimate power consumption, and understand test generation and simulation concepts.

    Copyright:

    © All Rights Reserved
    68 views1 page

    VVC Syllabus

    Uploaded by

    Ramesh Mallai
    This document provides information about a course on Testing and Verification of VLSI Circuits. The course objectives are to study fault modeling and detection techniques, understand test generation for combinational and sequential logic circuits, and explore design for testability and self-test methods. The course covers fundamentals of testing, test generation and simulation, fault models, design and verification techniques, and timing verification of VLSI circuits over 5 units spanning 45 periods. Upon completing the course, students will be able to insert elementary testing hardware, analyze timing using Logical Effort analysis, estimate power consumption, and understand test generation and simulation concepts.

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    VIVEKANANDHA COLLEGE OF ENGINEERING FOR

    WOMEN (Autonomous Institution Affiliated to Anna University


    Chennai)
    Elayampalayam, Tiruchengode – 637 205
    Programme M.E. Programme Code 205 Regulation 2015
    VLSI DESIGN / ELECTRONICS AND
    Department Semester II
    COMMUNICATION ENGINEERING

    Periods / Week Credit Maximum Marks


    Course Code Course Name
    L T P C CA ESE Total
    Testing and Verification of VLSI
    P15VD207 3 0 0 3 50 50 100
    Circuits
     To study the fault modeling and detection techniques.
    Course  To understand the test generation for combinational and sequential logic circuits.
    Objective  To explore the design for testability and self test methods.
     To study the fault diagnosis
    Unit – I FUNDAMENTALS OF TESTING Periods 9
    Scope of testing and verification in VLSI design process. Issues in test and verification of complex chips,
    embedded cores and SOCs; Fundamentals of VLSI testing.
    Unit – II TEST GENERATION AND SIMLUATION Periods 9
    Automatic test pattern generation. Design for testability. Scan design. Test interface and boundary scan.
    System testing and test for SOCs. Iddq testing.
    Unit – III FAULT MODELS Periods 9
    Fault models: Delay fault testing. BIST for testing of logic and memories. Test automation.
    Unit – IV DESIGN AND VERIFICATION OF VLSI CIRCUITS Periods 9
    Design verification techniques based on simulation, Analytical and Formal approaches. Functional
    verification of VLSI circuits.
    Unit – V TIMING VERIFICATION OF VLSI CIRCUITS Periods 9
    Timing verification. Formal verification. Basics of equivalence checking and model checking. Hardware
    emulation.
    Total Periods 45
    REFERENCES:
    M. Bushnell and V. D. Agrawal, "Essentials of Electronic Testing for Digital”, Memory and
    1.
    Mixed-Signal VLSI Circuits", Kluwer Academic Publishers, 2000.
    M. Abramovici, M. A. Breuer and A. D. Friedman, "Digital Systems Testing and Testable
    2.
    Design", IEEE Press, 1990.
    3. T.Kropf, "Introduction to Formal Hardware Verification", Springer Verlag, 2000.
    P. Rashinkar, Paterson and L. Singh, "System-on-a-Chip Verification-Methodology and
    4.
    Techniques", Kluwer Academic Publishers, 2001.

    Able to
     Insert elementary testing hardware into the VLSI chip
    Course
     Analyze VLSI circuit timing using Logical Effort analysis
    Outcome
     Estimate and compute the power consumption of a VLSI chip
     Understand the concept of test generation and simulation

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