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    4 - Verilog Language Elements

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    Rashmi Singh
    This document discusses key elements of the Verilog language including identifiers, keywords, comments, data types, integer and real number formats, and strings. It covers Verilog syntax rules and conventions for naming objects as well as the different types of comments, constants, nets, registers, and other basic building blocks used in Verilog. Examples are provided to illustrate various Verilog language constructs for writing synthesizable code.

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    4 - Verilog Language Elements

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    Rashmi Singh
    252 views12 pages
    This document discusses key elements of the Verilog language including identifiers, keywords, comments, data types, integer and real number formats, and strings. It covers Verilog syntax rules and conventions for naming objects as well as the different types of comments, constants, nets, registers, and other basic building blocks used in Verilog. Examples are provided to illustrate various Verilog language constructs for writing synthesizable code.

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    This document discusses key elements of the Verilog language including identifiers, keywords, comments, data types, integer and real number formats, and strings. It covers Verilog syntax rules and conventions for naming objects as well as the different types of comments, constants, nets, registers, and other basic building blocks used in Verilog. Examples are provided to illustrate various Verilog language constructs for writing synthesizable code.

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    252 views12 pages

    4 - Verilog Language Elements

    Uploaded by

    Rashmi Singh
    This document discusses key elements of the Verilog language including identifiers, keywords, comments, data types, integer and real number formats, and strings. It covers Verilog syntax rules and conventions for naming objects as well as the different types of comments, constants, nets, registers, and other basic building blocks used in Verilog. Examples are provided to illustrate various Verilog language constructs for writing synthesizable code.

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    of 12

    Verilog Language Elements

    Prof. A. K. Swain
    Asst. Prof., ECE Dept., NIT Rourkela

    EC6203: Reconfigurable System Design


    Identifiers
    Identifiers:
    • Identifiers are used to give name to object : module, net, register etc.
    • An identifier is any sequence of letters (a-z,A-Z), digits (0-9), the $ character, and the _ (underscore) character
    • First character must be a letter or an underscore.
    • Identifiers are case sensitive.
    Examples:
    Count , COUNT , _A2_B2, R67_69, FOUR$ // Count and COUNT are different.

    Escaped identifier:
    • An escaped identifier provides a way of including any of the printable
    ASCII characters in an identifier.
    • An escaped identifier starts with a \ (backslash)
    • Ends with a white space (a white space is a space, tab or a newline).
    Examples of escaped identifiers.
    \1234 , \.*.$ , \{ * * * * * * } , \~Q , \Output is same as Output

    Verilog Language Elements EC6203 Reconfigurable System Design


    Comments
    Keywords:
    • Verilog HDL defines a list of reserved identifiers that can only be used in certain contexts.
    • Only the lower case keywords are reserved words.
    • “always” keyword is distinct from “ALWAYS” identifier.
    • An escaped keyword is not treated the same as the keyword.
    • Thus, identifier \initial is distinct from the identifier initial (which is a keyword)

    Comments
    Two forms of comments in Verilog HDL.
    1. /* First form: Can
    extend across
    many
    lines */

    2. // Second form: Ends at the end of this line.

    Verilog Language Elements EC6203 Reconfigurable System Design


    Format
    • Verilog HDL is case-sensitive. That is, identifiers differing only in their case are distinct.
    • In addition, Verilog HDL is free-format, that is, constructs
    • may be written across multiple lines, or on one line.
    • White space (newline, tab, and space characters) have no special significance.

    Example:
    initial begin Top = 3'b001; #2 Top = 3'b011; end
    is same as:
    initial
    begin
    Top = 3 'b001;
    #2 Top = 3 'b011 ;
    end

    Verilog Language Elements EC6203 Reconfigurable System Design


    Value Set
    Verilog HDL has the following four basic values.
    i. 0: logic-0 or false
    ii. 1: logic-1 or true
    iii. x: unknown
    iv. z: high-impedance
    • A z in a value always means a high-impedance, a 0 always means a
    logic-0, and so on.
    • A z value at the input of a gate or in an expression is usually
    interpreted as an x.
    • Furthermore, the values x and z are case-insensitive, that is, the
    value
    0x1z is same as 0X1Z.
    A constant in Verilog HDL is made up of the above four basic values.
    There are three types of constants in Verilog HDL.
    i. Integer ii. Real iii. String

    Verilog Language Elements EC6203 Reconfigurable System Design


    Integers
    An integer number can be written in the following two forms.
    i. Simple decimal (22 and -25 etc.)
    ii. Base format
    Base Format Notation:
    The format of an integer in this form is: [ size ] 'base value
    size : size of the constant in number of bits,
    Base: is one of o or O (for octal), b or B (for binary),
    d or D (for decimal), h or H (for hexadecimal)
    Value: is a sequence of digits that are values from the base.
    Values x and z and the hexadecimal values a through f are case-insensitive.
    Example:
    5 'O37 : 5-bit octal , 4 ' D2 : 4-bit decimal , 4 'B1x_01 : 4-bit binary
    7 'Hx 7-bit x (x extended) , that is, xxxxxxx
    4 'hZ 4-bit z (z extended) , that is, zzzz.
    8 'h 2A Spaces are allowed between size and ' character and
    between base and value.

    Verilog Language Elements EC6203 Reconfigurable System Design


    Integers
    Examples:
    4 'd-4 Not legal: value cannot be negative
    3 ' b001 Not legal: no space allowed between ' and base b
    (2+3) ' d10 Not legal; size cannot be an expression.
    • A number in base format notation is always an unsigned number.
    • The size specification is optional in an integer of this form.
    • If no size is specified in an integer, the size of the number is the number
    of bits specified in the value.
    Examples: 'o721: 9-bit octal , 'hAF : 8-bit hex

    Verilog Language Elements EC6203 Reconfigurable System Design


    Integers
    Size specified is larger than the size specified for the constant:
    • The number is padded to the left with 0’s except for the case
    where the leftmost bit is a x or a z.
    Example:
    10'b10 : Padded with 0 to the left, 0000000010
    10'bxOx1 : Padded with x to the left, xxxxxxxOx1

    Size specified is smaller than the size specified for the constant: then
    • The leftmost bits are appropriately truncated.
    Example:
    3'b1001_0011 : same as 3'b011
    5'H0FFF : same as 5'H1F
    • The ? :- used as an alternate for value z in a number.
    • It may be used to improve readability in cases where the value z is
    interpreted as a don’t-care value

    Verilog Language Elements EC6203 Reconfigurable System Design


    Reals
    Reals : A real number can be specified in one of the following two forms.
    i. Decimal notation:
    Examples:
    2.0 , 5.678, 11572.12, 0.1
    ii. Scientific notation:
    Examples:
    23_5.1e2 = 23510.0; underscores are ignored
    3.6E2 = 360.0 (e is same as E)
    5E-4 = 0.0005
    Implicit conversion to integer is defined by the language.
    • Real numbers are converted to integers by rounding to the nearest integer.
    42.446, 42.45 when converted to integer yields 42
    92.5, 92.699 when converted into integer yield 93
    -15.62 to integer : -16
    -26.22 to integer : -26

    Verilog Language Elements EC6203 Reconfigurable System Design


    Strings
    Strings: A string is a sequence of characters within double quotes.
    • A string may not be split across lines.
    Examples:
    "INTERNAL ERROR"
    • A character is represented by an 8-bit ASCII value that treated as an unsigned integer.
    • Therefore a string is a sequence of 8-bit ASCII values.
    • To store the string "INTERNAL ERROR", a variable of size 8*14 is needed.
    Examples:
    reg [ 1 : 8*14 ] Message;
    …
    Message = "INTERNAL ERROR";

    • The \ (backslash) character can be used to escape certain special characters.


    \n - newline character , \t - tab ,\\ - the \ character itself
    \ * - the * character ,\206 - character with octal value 206

    Verilog Language Elements EC6203 Reconfigurable System Design


    Data Types
    Verilog HDL has two groups of data types.
    i . Net type:
    • A net type, represents a physical connection between structural elements.
    • Its value is determined from the value of its drivers such
    as a continuous assignment or a gate output.
    • If no driver is connected to a net, the net defaults to a value of z.
    ii. Register type:
    • A register type represents an abstract data storage element.
    • It is assigned values only within an always statement or an initial
    statement, and its value is saved from one assignment to the next.
    • A register type has a default value of x.

    Net Types : wire, tri, wor, trior, wand, triand, trireg,


    tri1, tri0, supply0, supply1
    Reg Types: reg, integer, time, real, realtime

    Verilog Language Elements EC6203 Reconfigurable System Design


    References
    Books:
    A Verilog HDL Primer: by J Bhasker.
    Design Through Verilog HDL: T.R. Padmanavan, B. Bala Tripura Sundari
    Verilog Digital Design Synthesis: Samir Palnitkar.

    website:
    asic-world.com
    www.xilinx.com

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