An5224 PDF
An5224 PDF
An5224 PDF
Application note
Introduction
In order to offload certain data transfer duties from the CPU, STM32 microcontrollers (MCUs) and microprocessors (MPUs)
embed direct memory access (DMA) controllers. The DMA can perform block-oriented data transfer upon a peripheral request
or a software trigger.
Each DMA channel has a software-configurable selection of the peripheral requesting its services. On legacy STM32 products,
the channel request selection is implemented within the DMA controller with a restricted list of peripheral requests for a given
channel. The software application cannot freely map any peripheral request to any channel.
STM32 DMA request routing capabilities are enhanced by a DMA request multiplexer (DMAMUX peripheral). The DMAMUX
adds more flexibility to give full dynamic DMA peripheral request mapping instead of pseudo-dynamic mapping. It offers fully
configurable routing of any DMA request from a given peripheral to any DMA controller and/or controller DMA channel.
This application note explains the various DMAMUX features of the products listed in the table below: how to configure the
DMAMUX as well as giving guidance on the use of the new synchronization and request generation capabilities.
For further information on DMAMUX in STM32 devices, refer to the product reference manuals available on www.st.com.
Table 1. Applicable products
STM32H7 Series
STM32G0 Series
STM32G4 Series
Microcontrollers
STM32L4+ Series
STM32L5 Series
STM32WB Series
Microprocessors STM32MP1 Series
1 DMAMUX description
A peripheral indicates a request for DMA transfer by setting its DMA request signal. The DMA request is pending
until it is served by the DMA controller that generates a DMA acknowledge signal, and the corresponding DMA
request signal is de-asserted.
In this document, the set of control signals required for the DMA request/acknowledge protocol is not explicitly
described and it is referred to as peripheral DMA request line.
The DMA request router can be considered as an extension of the DMA controller. It routes the DMA peripheral
requests to the DMA controller itself.
The DMAMUX request multiplexer enables routing a DMA request line from the peripherals to the DMA
controllers of the product. The routing function is ensured by a programmable multi-channel DMA request line
multiplexer. Each channel (DMAMUX channel 0 in the example of the figure below) selects a unique DMA request
line to forward (unconditionally or synchronously) to the associated DMA controller channel (DMA channel 0 in the
example of the figure below). This allows DMA requests to be managed with a high flexibility, maximizing the
number of DMA requests that run concurrently.
P1
P2
DMAMUX
channel 0
P3 DMA channel 0
...
Pn
...
channel 15
DMAMUX
DMA channel 15
2 DMAMUX features
The figure below represents a simplified DMAMUX block diagram. The “Request multiplexer” structure is
duplicated N times depending on the number of DMA channels managed by the DMAMUX.
DMAMUX_RGCnCR n+2
t 1 0 s 1 0
The DMAMUX is mainly composed of two components, the request multiplexer (or router block) and the
request generator.
The request multiplexer includes a synchronization unit per channel, with inputs/outputs as follows:
• Inputs:
– dmamux_reqx: DMA request from a peripheral (dmamux_req_inx) or from the request generator
(dmamux_req_genx)
dmamux_req_gen[0..n] are affected respectively to dmamux_req[1..n+1] and dmamux_req_inx are
affected starting from dmamux_req[n+2].
– dmamux_syncx: optional synchronization event
• Outputs:
– dmamux_req_outx: DMA request dmamux_reqx forwarded from the input to the output
– dmamux_evtx: optional generated event that may be used to trigger/synchronize other DMAMUX
channels
The request generator allows DMA request generation on interrupt signals or events, with input/output as follows:
• Input: dmamux_trgx, trigger event inputs to the request generator sub-block
• Output: dmamux_req_genx, DMA request from the request generator sub-block to the DMAMUX request
multiplexer channels
The number of request multiplexer blocks depends on the number of DMA channels managed by the DMAMUX.
For examples:
• For a 8 channels DMA, 8 request multiplexer channels must be available.
• For a product with two DMA controllers with 8 channels each, 16 request multiplexer channels must be
available.
The request generator is instantiated once by DMAMUX. It contains N channels (depending on the product)
capable of generating DMA requests. Refer to the 'DMAMUX implementation' section in the product reference
manual for more details.
Thanks to the request generator block, user software can trigger DMA transfers based on signals from peripherals
that do not implement the DMA requests.
dmamux_req
dmamux_req_out
Request counter auto-reload
dmamux_evt
dmamux_req_gen
dmamux_req_out
Request counter auto-reload (wait for new trigger)
dmamux_trg
Active trigger event edge
Generator request counter decremets after each transfer.
If a new trigger event is received while the generator is managing the previous triggered DMA request sequence,
then the request trigger event overrun flag bit OFx is asserted by the hardware in the status DMAMUX_RGSR
register.
3 DMAMUX examples
These examples use the STM32CubeMX tool version 4.26.1, running on STM32 microcontrollers (based on
Arm® cores).
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Figure 7. DMAMUX_RequestGen
SRAM4 buffer
DMAMUX2
Mux Ch 0
BDMA Ch 0
Req Gen ch 0
PF10
GPIOF ODR
EXTI PA0
0 EXTI
• DMAMUX_SYNC
This example uses the USART1 in DMA synchronized mode to send a countdown from 10 to 00 with 2
seconds period. The DMAMUX synchronization block is configured to synchronize the DMA transfer with the
LPTIM1 output signal. Each rising edge of the synchronization signal (LPTIM1 output signal) authorizes four
USART1 requests to be transmitted to the USART1 peripheral using the DMA. These four requests
represent the two characters '\n\r' plus the two characters count down itself from 10 to 00. LPTIM1 is
configured to generate a PWM with 2 seconds period.
Figure 8. DMAMUX_SYNC
SRAM buffer =
{10 to 00 }
DMAMUX1
Mux Ch 0
Synch
DMA Ch 0
usart1_tx_dma
NBREQ=4-1
10
09
TX 08
USART1
lptim1_out
2s
out
LPTIM1
4 Conclusion
The DMAMUX controller is designed to simplify embedded application resources allocation as it offers the
flexibility to dynamically allocate a peripheral to a DMA channel. Additionally it increases the DMA capabilities by
offering synchronization mechanism that allows an increased CPU offload from transfer control and
synchronization. Also the combination of synchronization and request generation can be used to implement
power optimized data transfer (in autonomous mode without CPU involvement).
Revision history
Contents
1 DMAMUX description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 DMAMUX features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Request routing and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 Unconditional request forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 DMAMUX examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Example using the synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Example using the DMAMUX request generator sub-block. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 STM32CubeH7 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
List of figures
Figure 1. DMAMUX request multiplexer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. DMAMUX simplified block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. DMA request line multiplexer channel - Event generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. DMA request generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Example using the synchronization (based on STM32CubeH7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Example using the request generator (based on STM32CubeH7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. DMAMUX_RequestGen. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. DMAMUX_SYNC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9