Uart Dma PDF
Uart Dma PDF
Uart Dma PDF
Abstract It has poor flexibility, the small application, and the poor
In this paper presents performance of DMA mode UART IP soft transportability; it’s usually unable to meet the high
core in embedded systems. In the past, UART IP hard core is requirements of the customer.
less flexibility, low performance and more time taken by the In this paper, UART IP soft core based on DMA mode can
CPU. So, the performance of embedded system is less. In this reduce elapsed time of CPU greatly in data transmission
paper used UART IF soft core based on DMA is used. It has less
occupancy time of CPU and improving the performance of the
process so that the performance of NIOSII system can be
whole NIOSII system. Design requirements can be better met improved and design requirement can be better met with
because of its high-performance, configurable parameters, less resources occupied, high speed, high flexibility and
portability besides high flexibility, practicality. It is design four high transportability.
sub modules and verify in a NIOSII embedded hardware system.
Index term:
NIOSII; UART; IP; DMA; AVALON bus II. Desigh Of Digital Circuits in Verilog
In integrated circuit technology, the design of gate level
I. Introduction is more time consuming so, UART IP core is used in
VERILOG. VERILOG can be used to describe and
The Universal Asynchronous Receiver Transmitter simulate the operation of digital circuits ranging from
(UART) module is one of the serial I/O modules available few gate to more complex gates. VERILOG can be
in the dsPIC33F/PIC24H device family. The UART is a used for the behavioral level design implementation of
full-duplex, asynchronous communication channel that a UART and it offers several advantages. These are
communicates with peripheral devices and personal the advantages of using VERILOG to implement UART:
computers using protocols such as RS-232, RS-485, LIN 1. VERILOG allows us to describe the function of
and IrDA®. The module also supports the hardware flow the transmitter in a more behavioral manner rather than
control option with UxCTS and UxRTS pins and includes focus on its actual implementation at the gate level .
the IrDA encoder and decoder. It transmit 9600 to 38400 2. VERILOG makes the design implementation easier to
bps for transmitting data bit Whole process of serial read and understand.
transmission is based upon the principle of shift register[1]. 3. It is easier to test the UART by the VERILOG
There are two primary forms of serial transmission: simulation and find out if any discrepancy occurs.[2]
Synchronous and Asynchronous.
Synchronous serial transmission requires that the
sender and receiver share a clock with one another, or III. UART IP Soft Core in DMA
that the sender provide a strobe or other timing signal
so that the receiver knows when to “read” the next bit of It has consumed time and high flexibility compare to
the data. Asynchronous serial communication has UART IP hard core module. The block diagram of UART
advantages of less transmission line, high reliability, and IP soft core in DMA as shown below.
long transmission distance, therefore is widely used in
data exchange between computer and peripherals. This
Asynchronous serial communication is usually
implemented by UART [2]. The entire UART IP soft core
in DMA mode mainly includes the following 5 sub-
modules: UART send controller, UART Receive
controller, Register file with the Interface of Avalon-MM
Slave [3], Master Read type DMA controller with the
interface of Avalon-MM Master [4] and Master Write type
DMA controller with the interface of Avalon-MM Master.
V. CONCLUSION
This paper describe the UART IP core based DMA has
been proposed. This technique has high flexibility and less
consume time of CPU that the performance of embedded
system is high. The baud rate generator and auto-tuning
approach in UART IP core based are simple and flexible,
which can be applied to other application designs as a
separate core.
REFERENCES
[1] Ananya Chakraborty, Surbhi, Sukanya Gupta, Swati
Deshkar, Pradeep Kumar Jaisal,”Design of UART
(Universal Asynchronous Receiver Transmitter) using
VHDL”, IJCST Vol. 3, Issue 1, Jan. - March 2012.
[2] FANG Yi-Yuan CHEN XUE- jun , “Design and
simulation Of UART serial communication Module
Based on VHDL”,2011.
[3] Altera Corp, Avalon-MM Slave reference manual.
[4] Altera Corp, Avalon-MM Maste reference manual.