Digitally Programmable Dual Full-Bridge MOSFET Driver: Description Features and Benefits

A3985
Digitally Programmable Dual Full-Bridge MOSFET Driver
FEATURES AND BENEFITS DESCRIPTION

▪ Serial interface for full digital control The A3985 is a flexible dual full-bridge gate driver suitable
▪ Dual full-bridge gate drive for N-channel MOSFETs for driving a wide range of higher power industrial bipolar
▪ Dual 6-bit DAC current reference 2-phase stepper motors or 2-phase brushless dc motors. It can
▪ Operation over 12 to 50 V supply voltage range also be used to drive two individual torque motors or solenoid
▪ Synchronous rectification actuators. Motor power is provided by external N-channel
▪ Cross-conduction protection power MOSFETs at supply voltages from 12 to 50 V.
▪ Adjustable mixed decay
Full digital control is provided by two serially-accessible
▪ Fixed off-time PWM current control
registers that allow programming of off-time, blank-time,
▪ Low-current idle mode
dead-time, mixed decay ratios, synchronous rectification,
master clock source selection, and division ratio and idle
mode. All internal timings are derived from a master clock
that can be generated on-chip or provided by an external
clock such as the system clock of the master controller. A
programmable divider allows for a wide range of external
PACKAGE: 38 pin TSSOP (suffix LD) system clock frequencies.
The internal fixed off-time PWM current-control timing is
programmed via the serial interface to operate in slow, fast,
and mixed current-decay modes. The desired load-current level
and direction is set via the serial port with a direction bit and
two 6-bit linear DACs in conjunction with a reference voltage.
The seven bits of control allow maximum flexibility in torque
Continued on the next page…

Not to scale
Typical Application
3985-DS, Rev. 5 November 22, 2019

MCO-0000739
A3985 Digitally Programmable Dual Full-Bridge MOSFET Driver
DESCRIPTION (CONTINUED)
control for a variety of step methods, from microstepping to full-step and programmable dead time.
drive. Load current in the external power MOSFET full-bridges is
set in 1.56% increments of the maximum value. In addition to crossover current control, internal circuit protection
provides thermal shutdown with hysteresis and undervoltage lockout.
The above-supply voltage required for the high-side N-channel
MOSFETs is provided by a bootstrap capacitor. Efficiency is Special power-up sequencing is not required. This component is
enhanced by using synchronous rectification and the power FETs supplied in a 38-pin TSSOP (package LD) with 100% matte tin
are protected from shoot-through by integrated crossover-control leadframe plating.
SELECTION GUIDE
Part Number Packing
A3985SLDTR-T Tape and reel, 4000 pieces per reel
ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units
Supply Voltage VBB –0.3 to 50 V
Logic Supply Voltage VDD –0.3 to 7 V
Logic Inputs and Outputs –0.3 to 7 V
SENSEx pins –1 to 1 V
Sxx pins –2 to 55 V
LSSx pins –2 to 5 V
GHxx pins Sxx to Sxx+15 V
GLxx pins –2 to 16 V V
Cxx pins –0.3 to Sxx+15 V
Operating Ambient Temperature TA Range S –20 to 85 °C
Junction Temperature TJ(max) 150 °C
Storage Temperature Tstg –55 to 150 °C
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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
Functional Block Diagram
+5 V VMOTOR
VDD VBB
VREG
Bandgap Regulator
CREG P
Phase 1A Bridge1
C1A
CBOOT1A
REF VREF
GH1A
High-Side
Drive RGH1A RGH1B
S1A
VREG
6-bit
GL1A
DAC Low-Side
Drive LSS1 RGL1A RGL1B
Programmable
PWM Timer SENSE1
SDO Blanking
Mixed Decay Phase 1B RSENSE1
P
Low-Side GL1B
Drive
S1B
Phase 1
Phase 1
SDI Control Logic High-Side GH1B
Drive CBOOT1B
C1B
VMOTOR
STR Serial Port Bridge2
Phase 2A C2A
CBOOT2A
GH2A
SCK Phase 2 High-Side
Phase 2 Drive RGH2A RGH2B
S2A
Control Logic
VREG
GL2A
Low-Side
Drive LSS2 RGL2A RGL2B
WC
Programmable
SENSE2
PWM Timer
Blanking RSENSE2
Phase 2B
Mixed Decay P
Low-Side GL2B
Drive
6-bit
DAC S2B
ENABLE
VREF GH2B
High-Side
Drive CBOOT2B
OSC Programmable Divider Protection
UVLO C2B
Oscillator TSD
GND
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ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise

Characteristics Symbol Test Conditions Min. Typ. Max. Units
Supply and Reference
Load Supply Voltage Range VBB 12 – 50 V
fMCK = 4 MHz, CLOAD = 1000 pF – – 10 mA
Load Supply Current IBB
ENABLE = High, outputs disabled – – 6 mA
Load Supply Idle Current IBBQ Word1:Bit D18 = 0 – – 100 µA
Logic Supply Voltage Range VDD 3.0 – 5.5 V
Logic Supply Current IDD – – 10 mA
Logic Supply Idle Current IDDQ Word1:Bit D18 = 0 – – 300 µA
Regulator Output VREG IREGInt = 30 mA 11.25 – 13 V
Bootstrap Diode Forward Voltage VfBOOT IfBOOT = 10 mA 0.6 0.8 1 V
Gate Output Drive
Turn-On Rise Time tr CLOAD = 1000 pF, 20% to 80% 80 120 160 ns
Turn-Off Fall Time tf CLOAD = 1000 pF, 80% to 20% 40 60 80 ns
Turn-On Propagation Delay tp(on) ENABLE low to gate drive on – 120 – ns
Turn-Off Propagation Delay tp(off) ENABLE high to gate drive off – 120 – ns
fMCK = 4 MHz,
Crossover Dead Time tDEAD 0.5 – 0.75 µs
Word1:Bits D1 and D2 = 00
Pull-Up On Resistance RDS(on)UP IGH = –25 mA 30 40 55 Ω
Pull-Down On Resistance RDS(on)DN IGL = 25 mA 14 19 24 Ω
Short-Circuit Current – Source1 ISC(source) –140 –110 –80 mA
Short-Circuit Current – Sink ISC(sink) 160 200 250 mA
GHx Output Voltage VGHx CBOOTx fully charged VC – 0.2 – – V
GLx Output Voltage VGLx VREG –0.2 – – V
Logic Inputs
Input Low Voltage VIL – – 0.3 VDD V
Input High Voltage VIH 0.7 VDD – – V
Input Hysteresis VIHys 150 300 – mV
Input Current1 IIN –1 – 1 µA
Output Low Voltage VOL SDO, IOL= 0.5 mA 0.5 V
Output High Voltage VOH SDO, IOH= –0.3 mA VDD –0.5 V
Output Leakage current1 IOleak SDO, STR = 1, 0 V< VO< VDD –1 1 µA
ELECTRICAL CHARACTERISTICS, continued, at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise

Current Control
Continued on the next page...
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fMCK = 4 MHz;
Blank Time tBLANK – 1 – µs
Word1:Bits D1 and D2 = 00
fMCK = 4 MHz,
Fixed Off-Time tOFF Word1:Bits D3 to D7 = 01010, and 21.75 – 22 µs
D15 = 0
Reference Input Voltage VREF 0.8 – 2 V
Internal Reference Voltage VREFInt 20 kΩ to VDD 1.9 2.0 2.1 V
Current Trip Point Error2 EITrip VREF = 2 V – – ±5 %
Reference Input Current1 IREF –3 0 3 µA
Internal Oscillator Frequency fOSC ROSC = 10 kΩ 3.2 4 4.8 MHz
Maximum Clock Input Frequency fEXTmax External clock selected – 10 – MHz
Master Clock Frequency fMCK 0.5 4 5 MHz
Protection
VREG Undervoltage Lockout VREGUV Decreasing VREG 7.5 8 8.5 V
VREG Undervoltage Lockout
VREGUVHys 100 200 – mV
Hysteresis
VDD Undervoltage Lockout VDDUV Decreasing VDD 2.45 2.7 2.95 V
VDD Undervoltage Lockout
VDDUVHys 50 100 – mV
Hysteresis
Overtemperature Shut Down TTSD Temperature increasing – 165 – °C
Overtemperature Shut Down
TTSDHys Recovery = TTSD – TTSDHys – 15 – °C
Hysteresis
ELECTRICAL CHARACTERISTICS, continued, at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise

Serial Data Timing
Serial Clock High Time tSCKH 50 – – ns
Serial Clock Low Time tSCKL 50 – – ns
Continued on the next page...
THERMAL CHARACTERISTICS
Characteristic Symbol Test Conditions* Value Units
4-layer PCB, based on JEDEC standard 51 °C/W
Package Thermal Resistance RθJA
1-layer PCB with copper limited to solder pads 127 °C/W
*Additional thermal information available on Allegro Web site.
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Strobe Lead Time tSTLD 30 – – ns

Strobe Lag Time tSTLG 30 – – ns
Strobe High Time tSTRH 150 – – ns
Data Out Enable Time tSDOE – – 40 ns
Data Out Disable Time tSDOD – – 30 ns
Data Out Valid Time from SCK Falling tSDOV – – 40 ns
Data Out Hold Time from SCK Falling tSDOH 5 – – ns
Data In Set-up Time to SCK Rising tSDIS 15 – – ns
Data In Hold Time from SCK Rising tSDIH 10 – – ns
WC Set-up Time to STR Rising tSWCS 15 – – ns
WC Hold Time from STR Rising tSWCH 50 – – ns
WC Hold Time from STR Falling tSLWCH 30 – – ns
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2Current Trip Point Error is the difference between actual current trip point and the target current trip point, referred to full scale (100%)
current: EITrip = 100 × (ITripActual – ITripTarget) / IFullScale %
Serial Data Timing Diagram
WC
tSLWCH tSWCS tSWCH
STR
tSTLD tSCKH tSCKL tSTLG tSTRH
SCK
tSDIS tSDIH
SDI D18 D17 D0

tSDOE tSDOD
tSDOV tSDOH
SDO ** D18* D17* D0*
Dx = Current data transfer block

Dx* = Previous data transfer block
** = Undefined, usually LSB from previous transfer
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Functional Description
Basic Operation tor, CREG, to ground. The value CREG should typically
The A3985 is a highly-configurable dual full-bridge FET be 40 times the value of the bootstrap capacitor for PWM
driver with built-in digital current control. All features are frequencies up to 14 kHz. Above 14 kHz, the minimum
accessed through a simple SPI (Serial Peripheral Interface) recommended value can be determined from the following
compatible serial port, allowing multiple motors to be con- formula:
trolled with as few as three wires.
Because the full-bridge control circuits are independently CREG > CBOOT × 3 × fPWM ,
controlled, the A3985 can be used to drive 2-phase bipolar where CREG and CBOOT are in nF, and fPWM is the maximum
stepper motors and 2-phase brushless dc (BLDC) motors. PWM frequency, in kHz. VREG is monitored, and if the volt-
The current in each of the two external power full-bridges age becomes too low, the outputs will be disabled.
(which are all N-channel MOSFETs) is regulated by a fixed REF The reference voltage, VREF, at this pin sets the
off-time PWM control circuit. The full‑bridge current at each
maximum (100%) peak current. The REF input is internally
step is set by the value of an external current sense resistor,
RSENSEX , in the ground connection to the bridge, a reference limited to 2 V when a 20 kΩ pull-up resistor is connected
voltage, VREF, and the output of the DAC controlled by the between VREF and VDD. This allows the maximum refer-
serial data. ence voltage to be set without the need for an externally-
The use of PWM with N-channel MOSFETs provides the generated voltage. An external reference voltage below the
most cost-effective solution for a high efficiency motor drive. maximum can also be input on this pin. The voltage at VREF
The A3985 provides all the necessary circuits to ensure is divided by the range select ratio Gm to produce the DAC
that the gate-source voltage of both high-side and low-side
reference voltage level.
external MOSFETs are above 10 V, and that there is no cross-
conduction (shoot through) in the external bridge. Specific OSC The PWM timing is based on a master clock, typically
functions are described more fully in the following sections. running at 4 MHz. The master clock period is used to derive
Power Supplies the PWM off-time, dead time, and blanking time.
Two power connections are required. The motor power sup- The master clock frequency can be set by an internal oscil-
ply should be connected to VBB to provide the gate drive lator or by one of three division ratios of an external clock.
levels. Power for internal logic is provided by the VDD These four options are selected by bits D12 and D13 of the
input. Internal logic is designed to operate from 3 to 5.5 V, Control register word.
allowing the use of 3.3 or 5 V external logic interface cir-
cuits. When the A3985 is configured to use an external clock,
GND The ground pin is a reference voltage for internal logic this is input on the OSC pin and will usually provide more
and analog circuits. There is no large current flow through precision than using the internal oscillator. The three internal
this pin. To avoid any noise from switching circuits, this
divider alternatives provide flexibility in setting the master
should have an independent trace to the supply ground star
point. clock frequency based on available external system clocks.
VREG The voltage at this pin is generated by a low-drop-out If internal timing is selected, fOSC is configured by using
linear regulator from the VBB supply. It is used to oper- an external resistor, ROSC, connected from the OSC pin to
ate the low-side gate drive outputs, GLxx, and to provide GND. This sets the frequency (in MHz) to approximately:
the charging current for the bootstrap capacitors, CBOOTx.
fOSC ≈ 100 / (6 + 1.9 × ROSC) ,
To limit the voltage drop when the charge current is pro-
vided, this pin should be decoupled with a ceramic capaci- where ROSC, in kΩ, is typically between 50 kΩ and 10 kΩ.
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SDI, SCK, STR, SDO These are the serial port interface approximately VREG when the associated output Sxx terminal
pins. Data is clocked into SDI by a clock signal on SCK. The is low. When the output swings high, the voltage on this ter-
data is then latched by a signal on STR. Note, however, that minal rises with the output to provide the boosted gate volt-
SCK must be high for one setup time interval, tSTLG, before age needed for the high-side N-channel power MOSFETs.
STR goes high and SCK must remain high for one hold time The bootstrap capacitor should be ceramic and have a value
interval, tSTRH, after STR has gone high (see Serial Data of 10 to 20 times the total MOSFET gate capacitance.
Timing Diagram). If required, the serial data out pin, SDO, GH1A, GH1B, GH2A, and GH2B High-side gate drive
can be used to read back the previously-latched serial data or outputs for external N-channel MOSFETs. External series
to form a daisy chain for multiple controllers using a single gate resistors can be used to control the slew rate seen at
STR connection. (For bit assignment details, see the Bit the gate, thereby controlling the di/dt and dv/dt at the motor
Assignments table.) terminals. GHxx = 1 (high) means that the upper half of the
driver is turned on and will source current to the gate of the
WC This input provides a lockout capability for writing
high-side MOSFET in the external motor-driving bridge.
to the Control register. When set to logic high, no changes
GHxx = 0 (low) means that the lower half of the driver is
can be made to the Control register through the serial port.
turned on and will sink current from the external MOSFET
When at logic low, the data on the serial port will update the
gate circuit to the respective Sxx pin.
Control register (if selected by D0 = 1) while STR is high.
S1A, S1B, S2A, and S2B Directly connected to the
This provides a mechanism to avoid inadvertently changing
motor, these terminals sense the voltages switched across the
the Control register settings by erroneous or corrupt serial
load and define the negative supply for the floating high-side
data signals.
drivers. The discharge current from the high-side MOSFET
gate capacitance flows through these connections which
Gate Drive should have low impedance traces to the MOSFET bridge.
The A3985 is designed to drive external power N-channel GL1A, GL1B, GL2A, and GL2B Low-side gate drive
MOSFETs. It supplies the transient currents necessary to outputs for external N-channel MOSFETs. External series
quickly charge and discharge the external FET gate capaci- gate resistors (as close as possible to the MOSFET gate) can
tance in order to reduce dissipation in the external FET be used to reduce the slew rate seen at the gate, thereby con-
during switching. The charge and discharge rate can be trolling the di/dt and dv/dt at the motor terminals. GLxx = 1
controlled using an external resistor, RGx, in series with (high) means that the upper half of the driver is turned on
the connection to the gate of the FET. Cross-conduction is and will source current to the gate of the low-side MOSFET
prevented by the gate drive circuits which introduce a dead in the external motor-driving bridge. GLxx = 0 (low) means
time, tDEAD , between switching one FET off and the comple- that the lower half of the driver is turned on and will sink
mentary FET on. tDEAD is at least 2, 3, 4, or 6 periods of the current from the gate of the external MOSFET to the LSSx
master clock, depending on the corresponding value set in pin.
the Control register (Word 1: bits D1 and D2). tDEAD can be LSS1 and LSS2 Low-side return path for discharge of the
up to 1 cycle longer than the programmed value, to allow gate capacitors, connected to the common sources of the
synchronization with the master clock. low-side external FETs through low-impedance traces.
ENABLE This input simply turns off all of the power MOS- Internal PWM Current Control
FETs. Set to logic high to disable outputs. When at logic low, Each full-bridge is independently controlled by a fixed off-
the internal control enables the outputs as required. Inputs to time PWM current control circuit that limits the load current
the registers and the internal sequencing logic are all active in the phase to a desired value, ITrip. Initially, a diagonal pair
independent of the ENABLE input state. of source and sink MOSFETs are enabled and current flows
through the motor winding and the current sense resistor,
C1A, C1B, C2A, and C2B High-side connections for the RSENSEx. When the voltage across RSENSEx equals the
bootstrap capacitors, CBOOTx, and positive supply for high- DAC output voltage, the current sense comparator resets
side gate drivers. The bootstrap capacitors are charged to the PWM latch, which turns off the source MOSFET (slow
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decay mode) or the sink and source MOSFETs (fast decay Dead Time To prevent cross-conduction (shoot through)
mode). The maximum value of current limiting is set by the in the power full-bridge, a dead time, tDEAD , is introduced
selection of RSENSE and the voltage at the REF input, with a between switching one MOSFET off and switching the
transconductance function approximated by: complementary MOSFET on. The dead time, tDEAD, is
ITrip(max) = VREF / (Gm × RSENSE) , nominally half of tBLANK , but may be up to 1 cycle longer to
synchronize with the master clock.
where Gm is the range factor defined by in the Data register
(Word0: Bits D17 and D18). Mixed Decay Operation
The DAC output reduces the VREF output to the current Mixed decay is a technique that provides greater control
sense comparator, VDAC, in precise steps: of phase currents while the current is decreasing. When a
VDAC = [(1 + DAC) × VREF] / 64 , stepper motor is driven at high speed, the back EMF from
where DAC is the decimal equivalent value of the Bridge the motor will lag behind the driving current. If a passive
DAC bits in the Data register (Word0: Bits D1 through D6 current decay mode, such as slow decay, is used in the cur-
for Bridge 1, Bits 9 through 14 for Bridge 2). (Active codes rent control scheme, then the motor back EMF can cause the
are represented by the values 1 through 63. Programming a phase current to rise out of control. Mixed decay eliminates
DAC input code to 0 disables the corresponding bridge, and this effect by putting the full-bridge initially into fast decay,
results in minimum load current.) and then switching to slow decay after some time. Because
The current trip level for each DAC value then becomes: fast decay is an active (driven) decay mode, this portion of
the current decay cycle will ensure that the current remains
ITripDAC = VDAC / (Gm × RSENSE) . in control. Using fast decay for the full current decay time
(off-time, tOFF) would result in a large ripple current, but
PWM Timer Function All bridge control timing is based switching to slow decay once the current is in control will
on the master clock. The PWM timer is programmed via the reduce the ripple current value. The portion of the off-time
serial port to provide fixed off-time PWM signals to the con- that the full-bridge has to remain in fast decay will depend
trol block. The off-time, tOFF , is selected by programming on the characteristics and the speed of the motor.
the Off-Time bits in the Control register (Word1, Bits D3
through D7) using the serial port. tOFF may be up to 1 cycle When the phase current is rising, the motor back EMF does
longer than the programmed value, to synchronize with the not affect the current control, and slow decay may be used
master clock. to minimize the phase current ripple. The A3985 must be
Blanking When a source driver is turned on, a current programmed to switch between slow decay, when the cur-
spike occurs due to the reverse-recovery currents of the rent is rising, and mixed decay, when the current is falling.
clamp diodes and switching transients related to distributed To simplify this programming sequence the decay mode is
capacitance in the load. To prevent false overcurrent detec- included in the data word (Word0) with the phase current trip
tion due to this current spike, the output from the current level and the phase current direction.
sense comparator is ignored (blanked) for a duration of time When mixed decay is used, the portion of the off-time that
called the blank time. The blank timer runs, when a source the full-bridge remains in fast decay, tFD , is selected by pro-
power MOSFET is turned on, to provide the programmable gramming the Fast Decay Time bits in the Control register
blanking function The blank timer is reset when PHASE is (Word1, Bits D8 through D11). If tFD is set longer than tOFF ,
changed. the device effectively operates in full fast decay mode.
The blank time can be set to 4, 6, 8, or 12 periods of the mas- Selecting between slow decay and mixed decay is done by
ter clock by programming the blank time bits in the Control programming the Mode bits in the Data register (Word0, Bits
register (Word1, Bits D1 and D2) using the serial port. D8 and D16) using the serial port.
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Synchronous Rectification When a PWM off-cycle Data is received on the SDI pin and clocked through a shift
is triggered, load current recirculates according to the decay register on the rising edge of the clock signal received on the
mode selected by the control logic. The synchronous rectifi-
cation feature turns on the appropriate MOSFETs during the SCK pin. STR is normally held high, and is only brought low
current decay and effectively shorts out the body diodes with to initiate a write cycle. No data is clocked through the shift
the low RDS(ON) of the MOSFET. This lowers power dis-
register when STR is high.
sipation significantly and eliminates the need for additional
Schottky diodes.
The 18 data bits for a register are input MSB first, fol-
Synchronous rectification can be set to one of three distinct lowed by the register select bit, D0. After D0 is clocked
modes by programming the Synchronous Rectification bits
in the Control register (Word1, Bits D14 through D15) using into the shift register, STR goes high to latch the data into
the serial port. The modes are: the selected register. When this occurs, the internal control
• Active This mode prevents reversal of the load current by
circuits immediately act on the new data.
turning off synchronous rectification when a zero current
level is detected. This prevents the motor winding from
The Control register can only be written if the WC pin is at
conducting in the reverse direction.
• Passive This mode allows reversal of current, but will logic low. If WC is high and D0 = 1 (indicating the Control
turn of the synchronous rectifier circuit if the load current register), the data will be ignored on the rising edge of STR.
inversion ramps up to the current limit, ITripDAC.
• Disabled During this mode, MOSFET switching does not The state of the WC pin does not affect writing to the Data
occur during load recirculation. Usually, this setting would register, and the pin can be tied to GND when Control regis-
only be used with 4 additional external clamp diodes per
ter protection is not required.
bridge.
Shutdown Operation In the event of an overtempera- Note that the number of bits clocked through the shift reg-
ture fault, or an undervoltage fault on VREG, the gate drive ister is irrelevant and only the last 19 bits before STR goes
outputs are disabled until the fault condition is removed.
At power-up, and in the event of low voltage at VDD, the high will be latched. This allows several A3985 devices to be
under voltage lockout (UVLO) circuit disables the gate drive daisy-chained and updated together with a single STR rising
outputs until the voltage at VDD reaches the minimum level.
edge.
Once VDD is above the minimum level, the data in the serial
port is reset to all 0s, ensuring a safe power-up condition.
Data Register (Word 0) Bit Assignments
Serial Interface
The A3985 is controlled by a 3-wire serial port using data, This section describes the function of the individual bit
clock and strobe inputs on the SDI, SCK and STR pins values in the Data register, one of the two registers accessed
respectively. An additional serial data output on SDO can
through the serial port. The assignments are summarized in
be used to connect several A3985s in a serial daisy chain.
The programmable functions allow maximum flexibility in the Bit Assignments table.
configuring the PWM to the motor drive requirements. The
serial data is written as two 19-bit words: 18 bits of data plus D0 – Register Select Indicates which register should
1 bit to select the destination register. receive the data. For the Data register, this is set to 0.
Serial Port Write Timing Operation The serial port tim-
ing requirements are specified in the electrical characteristics D1 through D6 – Bridge 1 Linear DAC These six bits
table, and illustrated in the Serial Data Timing diagram. set the desired current level for Bridge 1. Setting all six bits
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to 0 disables Bridge 1, with all drivers off (see Internal PWM Control Register (Word 1) Bit Assignments
Current Control, in the Functional Description section).
This section describes the function of the individual bit val-
D7 – Bridge 1 Phase Controls the direction of output cur- ues in the Control register, one of the two registers accessed
rent for Bridge (load) 1. through the serial port. The assignments are summarized in
D7 S1A S1B
the Bit Assignments table.
0 L H Note that the Control register can only be updated when the
1 H L WC pin is logic low.
D8 – Bridge 1 Mode Determines whether slow decay is D0 – Register Select Indicates which register should
forced or mixed decay, according to Word 1 Bits D3 to D11, receive the data. For the Control register, this is set to 1.
is allowed.
D1 and D2 – Blank Time These two bits set the value of
D8 Mode
the scaling factor, α / fMCK, used for determining tBLANK for
0 Mixed-decay
the current-sense comparator. The factor for tDEAD also is set,
1 Slow-decay because tDEAD = tBLANK / 2 .
D9 – D14 Bridge 2 Linear DAC These six bits set the
desired current level for Bridge 2. Setting all six bits to 0 D2 D1 tBLANK tDEAD
(tBLANK/ 2)
disables Bridge 2, with all drivers off (see Internal PWM
Current Control, in the Functional Description section). 0 0 4 / fMCK 2 / fMCK
0 1 6 / fMCK 3 / fMCK
D15 – Bridge 2 Phase Controls the direction of output
current for Bridge (load) 2. 1 0 8 / fMCK 4 / fMCK
1 1 12 / fMCK 6 / fMCK
D15 S2A S2B
0 L H D3 through D7 – Fixed Off Time These five bits set the
1 H L fixed off-time for the internal PWM control circuitry. Fixed
off-time is defined by:
D16 – Bridge 2 Mode Determines whether slow decay is
forced or mixed decay, according to Word 1 Bits D3 to D11, tOFF = [(1 + n) × (8 / fMCK)] – 1 / fMCK ,
is allowed.
where n = 0 to 31.
D16 Mode
0 Mixed-decay
For example, with a master clock frequency of 4 MHz, the
fixed off-time time would be adjustable within the range
1 Slow-decay
1.75 to 63.75 µs, in increments of 2 µs.
D17 and D18 – Gm Range Select These bits determine
the range scaling factor, Gm , used in PWM current control, D8 through D11 – Fast Decay Time These four bits set
according to the following formula: the fast decay portion of fixed off-time for the internal PWM
control circuitry. The fast-decay portion is defined by:
ITripDAC = VDAC / (Gm × RSENSEx)
D18 D17 Gm tFD = [(1 + n) × 8 / fMCK)] – 1 / fMCK ,
0 0 8 where n = 0 to 15.
0 1 12
For example, with a master clock frequency of 4 MHz, the
1 0 16
fast decay time would be adjustable within the range
1 1 20
1.75 to 32.75 µs, in increments of 2 µs.
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Note that, for tFD > tOFF , the device effectively operates in modes are described in the synchronous rectification section
full fast-decay mode. of the Functional Description section.
D12 and D13 – Master Clock Control An internal Synchronous
oscillator can be used for the timing functions, and if more D15 D14
Rectification Mode
precise control is required, an external clock can be input to 0 0 Disabled
the OSC terminal (for configuration information, refer to the
0 1 Disabled
Functional Description section). To accommodate a wider
range of external system clocks, an internal divider is pro- 1 0 Active
vided to generate the desired master clock frequency, fMCK , 1 1 Passive
according to the following table:
D16 and D17 – Reserved These bits are reserved for
testing and should be programmed to 0 during normal
D13 D12 Master Clock Source and fMCK operation.
0 0 Internal oscillator*
D18 – Idle Mode The device can be placed in a low
0 1 External clock rate
power mode by writing a 0 to D18. This disables the VREG
1 0 External clock rate / 2 regulator (to 0 V) and the outputs, and the device draws a
1 1 External clock rate / 4 lower load supply current. The undervoltage monitor circuit
*4 MHz typical, configurable with external resistor, ROSC. remains active. When leaving idle mode, D18 should be set
to 1 for at least 1 ms to allow the regulator to return VREG
D14 and D15 – Synchronous Rectification Two bits to its normal operating voltage (≈12 V) before attempting to
are used to set the mode for synchronous rectification. The enable any output driver.
Bit Assignments Table
Data Register Control Register
Word Bit Function Word Bit Function
D0 Register Select = 0 D0 Register Select = 1
D1 Bridge 1, DAC bit 0 (LSB) D1 Blank-time bit 0 (LSB)
D2 Bridge 1, DAC bit 1 D2 Blank-time bit 1 (MSB)
D3 Bridge 1, DAC bit 2 D3 Off-time bit 0 (LSB)
D4 Bridge 1, DAC bit 3 D4 Off-time bit 1
D5 Bridge 1, DAC bit 4 D5 Off-time bit 2
D6 Bridge 1, DAC bit 5 (MSB) D6 Off-time bit 3
D7 Bridge 1, Phase D7 Off-time bit 4 (MSB)
D8 Bridge 1, Mode D8 Fast-decay time bit 0 (LSB)
0 D9 Bridge 2, DAC bit 0 (LSB) 1 D9 Fast-decay time bit 1
D10 Bridge 2, DAC bit 1 D10 Fast-decay time bit 2
D11 Bridge 2, DAC bit 2 D11 Fast-decay time bit 3 (MSB)
D12 Bridge 2, DAC bit 3 D12 Master Clock Control bit 0 (LSB)
D13 Bridge 2, DAC bit 4 D13 Master Clock Control bit 1 (MSB)
D14 Bridge 2, DAC bit 5 (MSB) D14 Synchronous Rectification Control bit 0 (LSB)
D15 Bridge 2, Phase D15 Synchronous Rectification Control bit 1 (MSB)
D16 Bridge 2, Mode D16 Reserved
D17 Range Select bit 0 D17 Reserved
D18 Range Select bit 1 D18 Idle Mode
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Applications Information
Current Sensing grounded (tip and barrel) probe. If the voltage at LSS
To minimize inaccuracies in sensing the IPEAK current exceeds the specified absolute maximum add additional
level caused by ground-trace IR drops, the sense resistor,
RSENSEx, should have an independent return to the supply clamping, capacitance, or both, between the LSS pin and the
ground star point. For low-value sense resistors, the IR drops AGND pin.
in the sense resistor PCB traces can be significant and should
Other layout recommendations:
be taken into account. The use of sockets should be avoided
as they can introduce variation in RENSESx due to their 1. Gate charge drive paths and gate discharge return paths
contact resistance. may carry transient current pulses. Therefore, the traces from
Thermal Protection
All drivers are turned off when the junction temperature GHxx, GLxx, Sxx, and LSSx should be as short as possible to
reaches 165°C typical. This is intended only to protect the reduce the inductance of the circuit trace.
A3985 from failures due to excessive junction temperatures.
2. Provide an independent connection from each LSS pin
Thermal protection will not protect the A3985 from continu-
ous short circuits. Thermal shutdown has a hysteresis of to the common point of each power bridge. It is not recom-
approximately 15°C. mended to connect LSS directly to the GND pin. The LSS
Circuit Layout
Since this is a switch-mode application, where rapid current connection should not be used for the SENSE connection.
changes are present, care must be taken during layout of the 3. Minimize stray inductance by using short, wide copper
application PCB. The following points are provided as guid-
runs at the drain and source terminals of all power FETs.
ance for layout. Following all guidelines will not always be
possible. However, each point should be carefully considered This includes motor lead connections, the input power bus,
as part of any layout procedure. and the common source of the low-side power FETs. This
Ground Connection Layout Recommendations:
1. Decoupling capacitors for the supply pins VBB, VREG, will minimize voltages induced by fast switching of large
and VDD should be connected independently, close to the load currents.
GND pin, and not to any ground plane. The decoupling
4. Consider the use of small (100nF) ceramic decoupling
capacitors should also be connected as close as possible to
the corresponding supply pin. capacitors across the source and drain of the power FETs to
2. If used, the oscillator timing resistor ROSC should be limit fast transient voltage spikes caused by trace inductance.
connected to the GND pin. It should not be connected to any
ground plane, supply common, or the power ground. The above are only recommendations. Each application is
3. The GND pin should be connected by an independent low- different and may encounter different sensitivities. Each
impedance trace to the supply common at a single point.
design should be tested at the maximum current, to ensure
4. Check the peak voltage excursion of the transients on
the LSS pin with reference to the GND pin using a close any parasitic effects are eliminated.
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C2A 1 38 C2B
GH2A 2 37 GH2B
PIN-OUT DIAGRAM S2A 3 Bridge 2 36 S2B
Control
GL2A 4 35 GL2B
NC 5 34 NC
VREG 6 33 LSS2
VBB 7 32 SENSE2
GL1A 8 31 WC
S1A 9 30 SDO
Serial
GH1A 10 Interface
29 SDI
C1A 11 28 STR
C1B 12 27 SCK
GH1B 13 26 NC
S1B 14 Bridge 1 25 VDD
Control
GL1B 15 24 NC
LSS1 16 23 OSC
SENSE1 17 22 NC
NC 18 21 REF
ENABLE 19 20 GND
Terminal List Table

Number Name Description
1 C2A Phase 2 bootstrap capacitor drive A connection
2 GH2A Phase 2 high-side gate drive A
3 S2A Phase 2 motor connection A
4 GL2A Phase 2 low-side gate drive A
5 NC No internal connection
6 VREG Regulator decoupling capacitor connection
7 VBB Motor supply voltage
8 GL1A Phase 1 low-side gate drive A
9 S1A Phase 1 motor connection A
10 GH1A Phase 1 high-side gate drive A
11 C1A Phase 1 bootstrap capacitor drive A connection
12 C1B Phase 1 bootstrap capacitor drive B connection
13 GH1B Phase 1 high-side gate drive B
14 S1B Phase 1 motor connection B
15 GL1B Phase 1 low-side gate drive B
16 LSS1 Phase 1 low-side source connection
17 SENSE1 Phase 1 bridge current sense input
19 ENABLE Output enable
20 GND Ground
21 REF Reference voltage
23 OSC External clock input, ROSC resistor connection
25 VDD Logic supply voltage
27 SCK Serial Data Clock
28 STR Serial Data Strobe
29 SDI Serial Data Input
30 SDO Serial Data Output
31 WC Write Configuration Enable
32 SENSE2 Phase 2 bridge current sense input
33 LSS2 Phase 2 low-side source connection
35 GL2B Phase 2 low-side gate drive B
36 S2B Phase 2 motor connection B
37 GH2B Phase 2 high-side gate drive B
38 C2B Phase 2 bootstrap capacitor drive B connection
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LD Package, 38-Pin TSSOP
1.60
9.70 ±0.10 4º 38 0.50 0.30

38
+0.06
0.15 –0.05
4.40 ±0.10 6.40 ±0.20 6.00
1 2
0.25 1 2
B PCB Layout Reference View
SEATING PLANE
38X C GAUGE PLANE All dimensions nominal, not for tooling use
SEATING
0.10 C PLANE (reference JEDEC MO-153 BD-1)
Dimensions in millimeters
0.22 ±0.05 0.50 A Terminal #1 mark area
1.20 MAX
B Reference pad layout (reference IPC SOP50P640X110-38M)
0.10 ±0.05
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
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Revision History
Number Date Description
5 November 22, 2019 Minor editorial updates
Copyright 2019, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.
For the latest version of this document, visit our website:
16
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Digitally Programmable Dual Full-Bridge MOSFET Driver: Description Features and Benefits

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Digitally Programmable Dual Full-Bridge MOSFET Driver: Description Features and Benefits

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A3985

Digitally Programmable Dual Full-Bridge MOSFET Driver

FEATURES AND BENEFITS DESCRIPTION

Continued on the next page…

3985-DS, Rev. 5 November 22, 2019

ABSOLUTE MAXIMUM RATINGS

Functional Block Diagram

ELECTRICAL CHARACTERISTICS at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise

Output High Voltage VOH SDO, IOH= –0.3 mA VDD –0.5 V

Output Leakage current1 IOleak SDO, STR = 1, 0 V< VO< VDD –1 1 µA

ELECTRICAL CHARACTERISTICS, continued, at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise

Continued on the next page...

ELECTRICAL CHARACTERISTICS, continued, at TA = 25°C, VDD = 5 V, VBB = 12 to 50 V, unless noted otherwise

Continued on the next page...

Strobe Lead Time tSTLD 30 – – ns

Serial Data Timing Diagram

SDI D18 D17 D0

SDO ** D18* D17* D0*

Dx = Current data transfer block

Terminal List Table

LD Package, 38-Pin TSSOP

9.70 ±0.10 4º 38 0.50 0.30

4.40 ±0.10 6.40 ±0.20 6.00

Copyright 2019, Allegro MicroSystems.

For the latest version of this document, visit our website:

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