Gigabit Multimedia Serial Link Serializer With LVDS System Interface

19-5138; Rev 4; 1/12
TION KIT
EVALUA BLE
AVAILA
Gigabit Multimedia Serial Link
Serializer with LVDS System Interface
General Description Features
MAX9249
The MAX9249 serializer with LVDS system interface S Pairs with Any GMSL Deserializer
utilizes Maxim’s Gigabit multimedia serial link (GMSL) S 2.5Gbps Payload Rate AC-Coupled Serial Link
technology. The MAX9249 serializer pairs with any with 8B/10B Line Coding
GMSL deserializer to form a complete digital serial link
S Supports Up to WXGA (1280 x 800) with 24-Bit
for joint transmission of high-speed video, audio, and Color
control data.
S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz
The MAX9249 allows a maximum serial payload data rate to 78MHz (4-Channel LVDS) Input Clock
of 2.5Gbps for a 15m shielded twisted-pair (STP) cable.
S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I2S
The serializer operates up to a maximum clock rate of
Audio Channel Supports High-Definition Audio
104MHz (3-channel LVDS) or 78MHz (4-channel LVDS).
This serial link supports display panels from QVGA (320 S Embedded Half-/Full-Duplex Bidirectional Control
x 240) to WXGA (1280 x 800) and higher with 24-bit color. Channel (100kbps to 1Mbps)
The 3-channel mode handles three lanes of LVDS data S Interrupt Supports Touch-Screen Functions for
(21 bits), UART control signals, and three audio signals. Display Panels
The 4-channel mode handles four lanes of LVDS data S Remote-End I2C Master for Peripherals
(28 bits), UART control signals, three audio signals, S Preemphasis Line Driver
and/or up to three auxiliary parallel inputs. The three
S Programmable Spread Spectrum on the Serial
audio inputs form a standard I2S interface, supporting
Outputs for Reduced EMI
sample rates from 8kHz to 192kHz and audio word
lengths of 4 to 32 bits. The embedded control chan- S Automatic Data-Rate Detection Allows “On-the-
nel forms a full-duplex, differential, 100kbps to 1Mbps Fly” Data-Rate Change
UART link between the serializer and deserializer. The S Input Clock PLL Jitter Attenuator
electronic control unit (ECU), or microcontroller (FC), can S Built-In PRBS Generator for BER Testing of the
be located on the MAX9249 side of the link (typical for Serial Link
video display), on the deserializer side of the link (typi-
S Line-Fault Detector Detects Serial Link Shorts to
cal for image sensing), or on both sides. In addition, the Ground, Battery, or Open Link
control channel enables ECU/FC control of peripherals
on the remote side, such as backlight control, grayscale S ISO 10605 and IEC 61000-4-2 ESD Protection
Gamma correction, camera module, and touch screen. S -40NC to +105NC Operating Temperature Range
Base-mode communication with peripherals uses either S 1.8V to 3.3V I/O, 1.8V Core, and 3.3V LVDS
I2C or the GMSL UART format. A bypass mode enables Supplies
full-duplex communication using custom UART formats.
S Patent Pending
The MAX9249 serializer driver preemphasis, along with
the channel equalizer on the GMSL deserializer, extends Applications
the link length and enhances the link reliability. Spread High-Resolution Automotive Navigation
spectrum is available on the MAX9249 to reduce EMI on
the serial link and the parallel output of the GMSL dese- Rear-Seat Infotainment
rializer. The serial output complies with ISO 10605 and Megapixel Camera Systems
IEC 61000-4-2 ESD protection standards.
The core supply for the MAX9249 is 1.8V. The I/O supply Ordering Information
ranges from 1.8V to 3.3V. The MAX9249 is available in PART TEMP RANGE PIN-PACKAGE
a 48-pin TQFP package (7mm x 7mm) with an exposed MAX9249GCM/V+ -40NC to +105NC 48 TQFP-EP*
pad. Electrical performance is guaranteed over the MAX9249GCM/V+T -40NC to +105NC 48 TQFP-EP*
-40NC to +105NC automotive temperature range.
/V denotes an automotive qualified part.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS
MAX9249
AVDD to AGND.....................................................-0.5V to +1.9V IEC 61000-4-2 (RD = 330ω, CS = 150pF)

LVDSVDD to AGND...............................................-0.5V to +3.9V Contact Discharge
DVDD to GND.......................................................-0.5V to +1.9V (RXIN_ _, RXCLKIN_) to AGND........................................±4kV
IOVDD to GND......................................................-0.5V to +3.9V (OUT+, OUT-) to AGND.................................................±10kV
Any Ground to Any Ground..................................-0.5V to +0.5V Air Discharge
RXIN_ _, RXCLKIN_ to AGND...............................-0.5V to +3.9V (RXIN_ _, RXCLKIN_) to AGND........................................±8kV
OUT+, OUT- to AGND..........................................-0.5V to +1.9V (OUT+, OUT-) to AGND.................................................±12kV
LMN_ to AGND (15mA current limit).....................-0.5V to +3.9V ISO 10605 (RD = 2kω, CS = 330pF)
All Other Pins to Any Ground............... -0.5V to (VIOVDD + 0.5V) Contact Discharge
OUT+, OUT- Short Circuit to Ground or Supply........Continuous (RXIN_ _, RXCLKIN_) to AGND........................................±6kV
Continuous Power Dissipation (TA = +70NC) (OUT+, OUT-) to AGND.................................................±10kV
48-Pin TQFP (derate 36.2mW/NC above +70NC).....2898.6mW Air Discharge
ESD Protection (RXIN_ _, RXCLKIN_) to AGND......................................±20kV
Human Body Model (RD = 1.5kω, CS = 100pF) (OUT+, OUT-) to AGND.................................................±30kV
(RXIN_ _, RXCLKIN_, OUT+, OUT-) to AGND.................±8kV Operating Temperature Range......................... -40NC to +105NC
All Other Pins to GND.......................................................±3kV Junction Temperature......................................................+150NC
Storage Temperature Range............................. -65NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
PACKAGE THERMAL CHARACTERISTICS (Note 1)
48 TQFP-EP
Junction-to-Ambient Thermal Resistance (θJA)........27.6NC/W
Junction-to-Case Thermal Resistance (θJC).................2NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VLVDSVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to
+105NC, unless otherwise noted. Differential input voltage |VID| = 0.1V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V
- |VID/2|. Typical values are at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (PWDN, SSEN, BWS, DRS, MS, CDS, AUTOS, SD/CNTL0, SCK, WS, CNTL_)
0.65 x
PWDN, SSEN, BWS, DRS, MS, CDS, AUTOS
VIOVDD
High-Level Input Voltage VIH1 V
0.7 x
SD/CNTL0, SCK, WS, CNTL_
VIOVDD
0.35 x
Low-Level Input Voltage VIL1 V
VIOVDD
Input Current IIN1 VIN = 0 to VIOVDD -10 +10 FA
Input Clamp Voltage VCL ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUT (INT)
VIOVDD -
High-Level Output Voltage VOH1 IOH = -2mA V
0.2
Low-Level Output Voltage VOL1 IOL = 2mA 0.2 V
VIOVDD = 3.0V to 3.6V 16 35 64
Output Short-Circuit Current IOS VO = 0V mA
VIOVDD = 1.7V to 1.9V 3 12 21
2 _______________________________________________________________________________________
DC ELECTRICAL CHARACTERISTICS (continued)
MAX9249
I2C AND UART I/O, OPEN-DRAIN OUTPUT (RX/SDA, TX/SCL, LFLT)
0.7 x
High-Level Input Voltage VIH2 V
VIOVDD
0.3 x
Low-Level Input Voltage VIL2 V
VIOVDD
Input Current IIN2 VIN = 0 to VIOVDD (Note 2) -110 +5 FA
Low-Level Open-Drain Output VIOVDD = 1.7V to 1.9V 0.4
VOL2 IOL = 3mA V
Voltage VIOVDD = 3.0V to 3.6V 0.3
DIFFERENTIAL OUTPUT (OUT+, OUT-)
Preemphasis off (Figure 1) 300 400 500
3.3dB preemphasis setting, VOD(P)
350 610
Differential Output Voltage VOD (Figure 2) mV
3.3dB deemphasis setting, VOD(D)
240 425
(Figure 2)
Change in VOD Between
DVOD 15 mV
Complementary Output States
Output Offset Voltage
VOS Preemphasis off 1.1 1.4 1.56 V
(VOUT+ + VOUT-)/2 = VOS
Change in VOS Between
DVOS 15 mV
Complementary Output States
VOUT+ or VOUT- = 0V -60
Output Short-Circuit Current IOS mA
VOUT+ or VOUT- = 1.9V 25
Magnitude of Differential Output
IOSD VOD = 0V 25 mA
Short-Circuit Current
Output Termination Resistance
RO From OUT+, OUT- to VAVDD 45 54 63 I
(Internal)
REVERSE CONTROL-CHANNEL RECEIVER (OUT+, OUT-)
High Switching Threshold VCHR 27 mV
Low Switching Threshold VCLR -27 mV
LINE-FAULT DETECTION INPUT (LMN_)
Short-to-GND Threshold VTG Figure 3 0.3 V
Normal Thresholds VTN Figure 3 0.57 1.07 V
VIO +
Open Thresholds VTO Figure 3 1.45 V
60mV
Open Input Voltage VIO Figure 3 1.47 1.75 V
Short-to-Battery Threshold VTE Figure 3 2.47
LVDS INPUTS (RXIN_ _, RXCLKIN_)
Differential Input High Threshold VTH 50 mV
Differential Input Low Threshold VTL -50 mV
_______________________________________________________________________________________ 3
MAX9249
DC ELECTRICAL CHARACTERISTICS (continued)

Input Differential Termination
RTERM 85 110 135 I
Resistance
Input Current IIN+, IIN- PWDN = high or low, IN+ and IN- are shorted -25 +25 FA
Power-Off Input Current IIN0+, IIN0- VAVDD = VDVDD = VIOVDD = 0V -40 +40 FA
POWER SUPPLY
fRXCLKIN_ = 16.6MHz 125 165
Worst-Case Supply Current fRXCLKIN_ = 33.3MHz 135 175
IWCS BWS = GND mA
(Figure 4) fRXCLKIN_ = 66.6MHz 150 190
fRXCLKIN_ = 104MHz 175 220
Sleep-Mode Supply Current ICCS LVDS inputs are not driven 45 125 FA
Power-Down Supply Current ICCZ PWDN = GND, LVDS inputs are not driven 5 80 FA
AC ELECTRICAL CHARACTERISTICS
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to +105NC, unless otherwise
noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|. Typical values are
at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
CLOCK INPUT (RXCLKIN_)
BWS = GND, VDRS = VIOVDD 8.33 16.66
BWS = GND, DRS = GND 16.66 104
Clock Frequency fRXCLKIN_ MHz
VBWS = VIOVDD, VDRS = VIOVDD 6.25 12.5
VBWS = VIOVDD, DRS = GND 12.5 78
I2C/UART PORT TIMING (Note 3)
30% to 70%, CL = 10pF to 100pF,
Output Rise Time tR 20 150 ns
1kI pullup to IOVDD
70% to 30%, CL = 10pF to 100pF,
Output Fall Time tF 20 150 ns
1kI pullup to IOVDD
Input Setup Time tSET I2C only (Figure 5) 100 ns
Input Hold Time tHOLD I2C only (Figure 5) 0 ns
SWITCHING CHARACTERISTICS (Note 3)
20% to 80%, VOD ≥ 400mV, RL = 100I,
Differential Output Rise/Fall Time tR, tF 90 150 ps
serial-bit rate = 3.125Gbps (Note 3)
3.125Gbps PRBS signal, measured at VOD
Total Serial Output Jitter tTSOJ1 = 0V differential, preemphasis disabled 0.25 UI
(Figure 6)
Deterministic Serial Output Jitter tDSOJ2 3.125Gbps PRBS signal 0.15 UI
CNTL_ Input Setup Time tSET CNTL_ (Figure 7) 3 ns
CNTL_ Input Hold Time tHOLD CNTL_ (Figure 7) 1.5 ns
RXIN_ _ Skew Margin tRSKM Figure 8 0.3 UI
4 _______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
MAX9249
(VDVDD = VAVDD = 1.7V to 1.9V, VIOVDD = 1.7V to 3.6V, RL = 100I ±1% (differential), TA = -40NC to +105NC, unless otherwise
noted. Differential input voltage |VID| = 0.15V to 1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|. Typical values are
at VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC.)
Spread spectrum enabled 2950
Serializer Delay (Note 4) tSD Figure 9 Bits
Spread spectrum disabled 390
Link Start Time tLOCK Figure 10 3.5 ms
Power-Up Time tPU Figure 11 3.5 ms
I2S INPUT TIMING
WS Frequency fWS Table 3 8 192 kHz
Sample Word Length nWS Table 3 4 32 Bits
(8 x 4) (192 x 32)
SCK Frequency fSCK fSCK = fWS x nWS x 2 kHz
x2 x2
0.35 x
SCK Clock High Time (Note 3) tHC VSCK R VIH, tSCK = 1/fSCK ns
tSCK
0.35 x
SCK Clock Low Time (Note 3) tLC VSCK ≤ VIL, tSCK = 1/fSCK ns
tSCK
SD/CNTL0, WS Setup Time tSET Figure 12 (Note 3) 2 ns
SD/CNTL0, WS Hold Time tHOLD Figure 12 (Note 3) 2 ns
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: Not production tested.
1 1
=
Note 4: Bit time = 0),
(BWS = (BWS= VIOVDD )
30 × fRXCLKIN_ 40 × fRXCLKIN_
_______________________________________________________________________________________ 5
Typical Operating Characteristics
MAX9249
(VDVDD = VAVDD = VIOVDD = 1.8V, VLVDSVDD = 3.3V, TA = +25NC, unless otherwise noted.)
TOTAL SUPPLY CURRENT TOTAL SUPPLY CURRENT

vs. RXCLKIN_ FREQUENCY vs. RXCLKIN_ FREQUENCY
(3-CHANNEL MODE) (4-CHANNEL MODE)
170 165
MAX9249 toc01
MAX9249 toc02
PRBS PATTERN PRBS PATTERN
160
160
TOTAL SUPPLY CURRENT (mA)
TOTAL SUPPLY CURRENT (mA)

155 PREEMP = 0x0B TO 0x0F
150 PREEMP = 0x0B TO 0x0F 150
145
140
140
130 135
PREEMP = 0x01 TO 0x04 130
120 PREEMP = 0x01 TO 0x04
125
PREEMP = 0x00 PREEMP = 0x00
110 120
5 25 45 65 85 105 5 20 35 50 65 80
RXCLKIN FREQUENCY (MHz) RXCLKIN FREQUENCY (MHz)
OUTPUT POWER SPECTRUM OUTPUT POWER SPECTRUM

vs. RXCLKIN_ FREQUENCY vs. RXCLKIN_ FREQUENCY
0 0
MAX9249 toc03
MAX9249 toc04
fRXCLKIN_ = 33MHz fRXCLKIN_ = 16.5MHz
-10 -10
0.5% SPREAD
OUTPUT POWER SPECTRUM (dBm)
OUTPUT POWER SPECTRUM (dBm)
0% SPREAD 0.5% SPREAD 0% SPREAD

-20 -20
-30 -30
-40 -40
-50 -50
-60 -60
-70 -70
-80 -80 2% SPREAD 4% SPREAD

2% SPREAD 4% SPREAD
-90 -90
30.5 31.5 32.5 33.5 34.5 35.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0
RXCLKIN FREQUENCY (MHz) RXCLKIN FREQUENCY (MHz)
MAXIMUM PCLK FREQUENCY MAXIMUM RXCLKIN_ FREQUENCY

vs. STP CABLE LENGTH (BER < 10-9) vs. 10m STP CABLE CL (BER < 10-9)
120 120
MAX9249 toc05
MAX9249 toc06
OPTIMUM PE/EQ SETTINGS

MAXIMUM RXCLKIN FREQUENCY (MHz)
MAXIMUM PCLK FREQUENCY (MHz)
100 100
80 80
60 OPTIMUM PE/EQ 60
SETTINGS
NO PE, EQS = LOW
40 NO PE, EQS = LOW 40
NO PE, EQS = LOW NO PE, EQS = HIGH
20 20
BER CAN BE AS LOW AS 10-12 FOR BER CAN BE AS LOW AS 10-12 FOR
CABLE LENGTHS LESS THAN 10m CL < 4pF FOR OPTIMUM PE/EQ SETTINGS
0 0
0 5 10 15 20 0 2 4 6 8 10
STP CABLE LENGTH (m) STP CABLE LOAD CAPACITANCE (pF)
6 _______________________________________________________________________________________
Pin Configuration
MAX9249
RX/SDA
TX/SCL
AGND
LMN0
LMN1
AVDD
OUT+
SSEN
OUT-
LFLT
DRS
INT
TOP VIEW
36 35 34 33 32 31 30 29 28 27 26 25
IOVDD 37 24 IOVDD
GND 38 23 GND
DVDD 39 22 DVDD
N.C. 40 21 AGND
BWS 41 20 CNTL2
PWDN 42 19 CNTL1
MAX9249
CDS 43 18 WS
MS 44 17 SCK
AUTOS 45 16 SD/CNTL0
N.C. 46 15 AVDD
AVDD 47 14 LVDSVDD
EP*
AGND 48 13 AGND
+
1 2 3 4 5 6 7 8 9 10 11 12
RXIN0-
RXIN0+
RXIN1-
RXIN1+
LVDSVDD
AGND
RXIN2-
RXIN2+
RXCLKIN-
RXCLKIN+
RXIN3-
RXIN3+
TQFP
*EXPOSED PAD.
Pin Description
PIN NAME FUNCTION
1–4, 7, 8, RXIN_-, Differential LVDS Data Inputs. Set BWS = low (3-channel mode) to use RXIN0_ to RXIN2_. Set
11, 12 RXIN_+ BWS = high (4-channel mode) to use RXIN0_ to RXIN3_.
3.3V LVDS Power Supply. Bypass LVDSVDD to AGND with 0.1FF and 0.001FF capacitors as close
5, 14 LVDSVDD
as possible to the device with the smaller value capacitor closest to LVDSVDD.
6, 13, 21,
AGND Analog Ground
29, 48
RXCLKIN-,
9, 10 LVDS Input for the LVDS Clock
RXCLKIN+
1.8V Analog Power Supply. Bypass AVDD to AGND with 0.1FF and 0.001FF capacitors as close
15, 32, 47 AVDD
as possible to the device with the smaller value capacitor closest to AVDD.
I2S Serial-Data Input with Internal Pulldown to GND. Disable I2S to use SD/CNTL0 as an additional
16 SD/CNTL0
input.
17 SCK I2S Serial-Clock Input with Internal Pulldown to GND
18 WS I2S Word-Select Input with Internal Pulldown to GND
Control Input 1 with Internal Pulldown to GND. Data is latched every RXCLKIN_ cycle (Figure 7).
CNTL1 is not available in 3-channel mode. Drive BWS high (4-channel mode) to use this input.
19 CNTL1
CNTL1 or RES (RES from VESA Standard Panel Specification) is mapped to DIN27 (see the
Reserved Bit (RES) section).
_______________________________________________________________________________________ 7
Pin Description (continued)
MAX9249
PIN NAME FUNCTION

Control Input 2 with Internal Pulldown to GND. Data is latched every RXCLKIN_ cycle (Figure 7).
20 CNTL2 CNTL2 is not available in 3-channel mode. Drive BWS high (4-channel mode) to use this input.
CNTL2 is mapped to DIN28.
1.8V Digital Power Supply. Bypass DVDD to GND with 0.1FF and 0.001FF capacitors as close as
22, 39 DVDD
possible to the device with the smaller value capacitor closest to DVDD.
23, 38 GND Digital and I/O Ground
I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to GND with 0.1FF and
24, 37 IOVDD 0.001FF capacitors as close as possible to the device with the smallest value capacitor closest to
IOVDD.
Receive/Serial Data. UART receive or I2C serial-data input/output with internal 30kI pullup to
25 RX/SDA IOVDD. In UART mode, RX/SDA is the Rx input of the MAX9249’s UART. In I2C mode, RX/SDA is
the SDA input/output of the MAX9249’s I2C master.
Transmit/Serial Clock. UART transmit or I2C serial-clock output with internal 30kI pullup to IOVDD.
26 TX/SCL In UART mode, TX/SCL is the Tx output of the MAX9249’s UART. In I2C mode, TX/SCL is the SCL
output of the MAX9249’s I2C master.
Spread-Spectrum Enable. Serial link spread-spectrum enable input requires external pulldown or
pullup resistors. The state of SSEN latches upon power-up or when resuming from power-down
27 SSEN
mode (PWDN = low). Set SSEN = high for Q0.5% spread spectrum on the serial link. Set SSEN =
low to use the serial link without spread spectrum.
28 LMN1 Line-Fault Monitor Input 1 (see Figure 3 for details)
OUT-,
30, 31 Differential CML Output+/-. Differential outputs of the serial link.
OUT+
33 LMN0 Line-Fault Monitor Input 0 (see Figure 3 for details)
Line Fault. Active-low, open-drain line-fault output with a 60kI internal pullup resistor. LFLT = low
34 LFLT
indicates a line fault. LFLT is high impedance when PWDN = low.
Interrupt Output to Indicate Remote Side Requests. INT = low upon power-up and when PWDN =
35 INT
low. A transition on the INT input of the GMSL deserializer toggles the MAX9249’s INT output.
Data-Rate Select. Data-rate range-selection input requires external pulldown or pullup resistors.
Set DRS = high for RXCLKIN_ frequencies of 8.33MHz to 16.66MHz (3-channel mode) or 6.25MHz
36 DRS
to 12.5MHz (4-channel mode). Set DRS = low for RXCLKIN_ frequencies of 16.66MHz to 104MHz
(3-channel mode) or 12.5MHz to 78MHz (4-channel mode).
40, 46 N.C. Internally Not Connected. Connect to GND or leave unconnected.
Bus-Width Select. Input width selection requires external pulldown or pullup resistors. Set BWS =
41 BWS
low for 3-channel mode. Set BWS = high for 4-channel mode.
42 PWDN Power-Down. Active-low power-down input requires external pulldown or pullup resistors.
Control Direction Selection. Control link direction selection input requires external pulldown or
43 CDS pullup resistors. Set CDS = low for FC use on the MAX9249 side of the serial link. Set CDS = high
for FC use on the GMSL deserializer side of the serial link.
Mode Select. Control link mode-selection input requires external pulldown or pullup resistors. Set
44 MS
MS = low to select base mode. Set MS = high to select the bypass mode.
8 _______________________________________________________________________________________
Pin Description (continued)
MAX9249
PIN NAME FUNCTION
Autostart Setting. Active-low power-up mode-selection input requires external pulldown or pullup
45 AUTOS resistors. Set AUTOS = high to power up the device with no link active. Set AUTOS = low to have
the MAX9249 power up the serial link with autorange detection (see Tables 8 and 9).
Exposed Pad. EP internally connected to AGND. MUST externally connect EP to the AGND plane
— EP
for proper thermal and electrical performance.
Functional Diagram
LFLT
RXCLKIN+/- 7x PLL DIVIDE BY 7 FILTER PLL SPREAD PLL
LMN0
FIFO CLKDIV LINE-FAULT DET
RXIN0+/- S P DIN[6:0] LMN1
RXIN1+/- S P DIN[13:7]
MAX9249
RXIN2+/- S P DIN[20:14]
RXIN3+/- S P DIN[26:21] 8B/10B
ENCODE P S CML Tx
CNTL1 MUX DIN27 PARITY
OUT+
CNTL2 DIN28
TERM
WS,
SD/CNTL0, AUDIO FIFO ACB OUT-
SCK
PRBS GEN UART/I2C REV CH Rx
STP CABLE,
TX/SCL Z0 = 100I
RX/SDA (DIFF)
IN-
GMSL DESERIALIZER
IN+
_______________________________________________________________________________________ 9
MAX9249
RL/2
OUT+
VOD
VOS
OUT-
RL/2
GND
((OUT+) + (OUT-))/2
OUT-
VOS(-) VOS(+) VOS(-)
OUT+
DVOS = |VOS(+) - VOS(-)|
VOD(+)
VOD = 0V
VOD(-) DVOD = |VOD(+) - VOD(-)| VOD(-)
(OUT+) - (OUT-)
Figure 1. Serial-Output Parameters
OUT+
VOS VOD(P) VOD(D)
OUT-
SERIAL-BIT
TIME
Figure 2. Output Waveforms at OUT+ and OUT-
10 ��
MAX9249
1.7V TO 1.9V
MAX9249 45kI* 45kI*

LMN0
LMN1
OUTPUT 5kI* 5kI*

LOGIC
(OUT+)
TWISTED PAIR
OUT+
OUT-
50kI* 50kI*
CONNECTORS
LFLT REFERENCE
VOLTAGE
GENERATOR
OUTPUT
LOGIC
(OUT-)
*Q1% TOLERANCE
Figure 3. Line-Fault Detector Circuit
RXCLKIN+
RXCLKIN-
RXIN0+ TO RXIN3+
RXIN0- TO RXIN3-
CNTL_
Figure 4. Worst-Case Pattern Input
______________________________________________________________________________________ 11
MAX9249
tR tF
TX/
SCL
tHOLD tSET
RX/
SDA
P S S P
Figure 5. I2C Timing Parameters
800mVP-P
t TSOJ1 t TSOJ1
2 2
Figure 6. Differential Output Template
IDEAL SERIAL-BIT TIME

RXCLKIN-
RXCLKIN+
RXIN_+/RXIN_-
tRSKM tRSKM
tSET tHOLD
VIHMIN IDEAL
CNTL_ MIN MAX
VILMAX
INTERNAL STROBE
Figure 7. Input Setup-and-Hold Times Figure 8. LVDS Receiver Input Skew Margin
12 ��
MAX9249
EXPANDED TIME SCALE
N-1 N N+1 N+2 N+3
RXIN_+/RXIN_-
RXCLKIN+
RXCLKIN-
N-1 N
OUT+/OUT-
FIRST BIT LAST BIT

tSD
Figure 9. Serializer Delay
RXCLKIN-
RXCLKIN+
tLOCK
350µs
SERIAL LINK INACTIVE SERIAL LINK ACTIVE
REVERSE CONTROL CHANNEL REVERSE CONTROL

CHANNEL ENABLED DISABLED CHANNEL ENABLED
PWDN MUST BE HIGH
Figure 10. Link Startup Time
______________________________________________________________________________________ 13
MAX9249
RXCLKIN+
RXCLKIN-
PWDN VIH1
tPU
POWERED UP, SERIAL

POWERED DOWN POWERED UP, SERIAL LINK ACTIVE
LINK INACTIVE
350µs
REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL

CHANNEL DISABLED CHANNEL ENABLED CHANNEL DISABLED CHANNEL ENABLED
Figure 11. Power-Up Delay
WS
tSCK
tHOLD tSET
tLC
SCK
tHOLD tSET tHC
SD/CNTL0
Figure 12. Input I2S Timing Parameters
14 ��
Detailed Description for video display), on the deserializer side of the link (typ-
MAX9249
ical for image sensing), or on both sides. In addition, the
The MAX9249 serializer with LVDS system interface control channel enables ECU/FC control of peripherals
utilizes Maxim’s GMSL technology. The MAX9249 serial- in the remote side, such as backlight control, grayscale
izer pairs with any GMSL deserializer to form a complete Gamma correction, camera module, and touch screen.
digital serial link for joint transmission of high-speed Base-mode communication with peripherals uses either
video, audio, and control data. I2C or the GMSL UART format. A bypass mode enables
The MAX9249 allows a maximum serial payload data full-duplex communication using custom UART formats.
rate of 2.5Gbps for a greater than 15m STP cable. The The MAX9249 serializer driver preemphasis, along with
serializer operates up to a maximum clock of 104MHz for the channel equalizer on the GMSL deserializer, extends
a 3-channel LVDS input or 78MHz for a 4-channel LVDS the link length and enhances the link reliability. Spread
input. This serial link supports display panels from QVGA spectrum is available on the MAX9249 to reduce EMI on
(320 x 240) up to WXGA (1280 x 800) with 24-bit color. the serial link and the parallel output of the GMSL dese-
The 3-channel mode handles three lanes of LVDS data rializer. The serial output complies with ISO 10605 and
(21 bits), UART control signals, and three audio signals. IEC 61000-4-2 ESD protection standards.
The 4-channel mode handles four lanes of LVDS data
(28 bits), UART control signals, three audio signals, and/ Register Mapping
or up to three auxiliary parallel inputs. The three audio The FC configures various operating conditions of the
inputs form a standard I2S interface, supporting sample MAX9249 and GMSL deserializer through internal regis-
rates from 8kHz to 192kHz and audio word lengths of ters. The default device addresses stored in the R0 and
4 to 32 bits. The embedded control channel forms a R1 registers of both the MAX9249 and GSML deserial-
full-duplex, differential, 100kbps to 1Mbps UART link izer are 0x80 and 0x90, respectively. Write to the R0/R1
between the serializer and deserializer. The ECU, or FC, registers in both devices to change the device address
can be located on the MAX9249 side of the link (typical of the MAX9249 or GMSL deserializer.
Table 1. Power-Up Default Register Map (see Table 12)

REGISTER POWER-UP
POWER-UP DEFAULT SETTINGS
ADDRESS DEFAULT
(MSB FIRST)
(HEX) (HEX)
SERID =1000000, serializer device address is 1000 000
0x00 0x80
RESERVED = 0
DESID =1001000, deserializer device address is 1001 000
0x01 0x90
RESERVED = 0
SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings depend on

SSEN pin state at power-up
0x02 0x1F, 0x3F AUDIOEN = 1, I2S channel enabled
PRNG = 11, automatically detect the pixel clock range
SRNG = 11, automatically detect serial-data rate
AUTOFM = 00, calibrate spread-modulation rate only once after locking

0x03 0x00
SDIV = 000000, autocalibrate sawtooth divider
______________________________________________________________________________________ 15
MAX9249
Table 1. Power-Up Default Register Map (see Table 12) (continued)

REGISTER POWER-UP
POWER-UP DEFAULT SETTINGS
ADDRESS DEFAULT
(MSB FIRST)
(HEX) (HEX)
SEREN = 0 (AUTOS = high), SEREN = 1 (AUTOS = low), serial link enable default depends
on AUTOS pin state at power-up
CLINKEN = 0, configuration link disabled
PRBSEN = 0, PRBS test disabled
0x03, 0x13,
0x04 SLEEP = 0 or 1, sleep-mode state depends on CDS and AUTOS pin state at power-up (see
0x83 or 0x93
the Link Startup Procedure section)
INTTYPE = 00, base mode uses I2C
REVCCEN = 1, reverse control channel active (receiving)
FWDCCEN = 1, forward control channel active (sending)
I2CMETHOD = 0, I2C packets include register address

DISFPLL = 1, filter PLL disabled
0x05 0x70
CMLLVL = 11, 400mV CML signal level
PREEMP = 0000, preemphasis off
0x06 0x40 RESERVED = 01000000
0x07 0x22 RESERVED = 00100010
RESERVED = 0000
0x0A
0x08 LFNEG = 10, no faults detected
(read only)
LFPOS = 10, no faults detected
0x0C 0x70 RESERVED = 01110000
SETINT = 0, interrupt output set to low
RESERVED = 00
0x0D 0x0F
DISRES = 0, RES mapped to DIN27
SKEWADJ = 1111, no X7PLL clock skew adjustment
0x03
0x1E ID = 00000011, device ID is 0x03
(read only)
0x0X RESERVED = 0000
0x1F
(read only) REVISION = XXXX, revision number
VESA Standard Panel Bitmapping Serial Link Signaling and Data Format
and Bus-Width Selection The MAX9249 high-speed data serial output uses
The LVDS input has two selectable widths, 3-channel CML signaling with programmable preemphasis and
and 4-channel. The MAX9249 accepts the VESA stan- AC-coupling. The GMSL deserializer uses AC-coupling
dard panel 3- or 4-channel LVDS (Table 2). Inputs on the and programmable channel equalization. When using
MAX9249 are mapped internally, according to Figures 13 both the preemphasis and equalization, the MAX9249/
and 14. In 3-channel mode, RXIN3_ and CNTL1/CNTL2 GMSL deserializer can operate up to 3.125Gbps over
are not available. For both modes, the SD/CNTL0, SCK, STP cable lengths to 15m or more.
and WS pins are for I2S audio. The MAX9249 accepts The MAX9249 serializer scrambles and encodes the
clock rates from 8.33MHz to 104MHz for 3-channel mode LVDS input data and sends the 8B/10B coded signal
and 6.25MHz to 78MHz for 4-channel mode. through the serial link. The GMSL deserializer recovers
16 ��
Table 2. Bus-Width Selection Using BWS
MAX9249
3-CHANNEL MODE 4-CHANNEL MODE
(BWS = LOW) (BWS = HIGH)
INPUT BITS
VESA STANDARD AUXILIARY SIGNALS VESA STANDARD AUXILIARY SIGNALS
PANEL MAPPING MAPPING PANEL MAPPING MAPPING
DIN[0:5] R[0:5] — R[0:5] —
DIN[6:11] G[0:5] — G[0:5] —
DIN[12:17] B[0:5] — B[0:5] —
DIN[18:20] HS, VS, DE — HS, VS, DE —
DIN[21:22] Not used Not used R6, R7 —
DIN[23:24] Not used Not used G6, G7 —
DIN[25:26] Not used Not used B6, B7 —
DIN27 Not used Not used RES* CNTL1
DIN28 Not used Not used — CNTL2
SD/CNTL0 — SD/CNTL0 — SD/CNTL0
*RES = Reserved (see the Reserved Bit (RES) section for details).
RXCLKIN-
RXCLKIN+
CYCLE N-1 CYCLE N
RXIN0+/RXIN0- DIN1 DIN0 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0
CNTL1 DIN27
CNTL2 DIN28
SD/CNTL0* SD*
*WITH I2S ENABLED; OTHERWISE CNTL0
Figure 13. LVDS Input Timing
______________________________________________________________________________________ 17
MAX9249
RXCLKIN-
RXCLKIN+
CYCLE N-1 CYCLE N
RXIN0+/RXIN0- R1 R0 G0 R5 R4 R3 R2 R1 R0
RXIN1+/RXIN1- G2 G1 B1 B0 G5 G4 G3 G2 G1
RXIN2+/RXIN2- B3 B2 DE VS HS B5 B4 B3 B2
RXIN3+/RXIN3- R7 R6 RES B7 B6 G7 G6 R7 R6
Figure 14. VESA Standard Panel Clock and Bit Assignment
the embedded serial clock and then samples, decodes, Reserved Bit (RES)
and descrambles before outputting the data. Figures In 4-channel mode, the MAX9249 serializes all bits of all
15 and 16 show the serial-data packet format before four lanes including RES by default. Set DISRES (D4 of
scrambling and 8B/10B coding. In 3-channel or 4-chan- Register 0x0D) to 1 to map CNTL1 to DIN27 instead of
nel mode, 21 or 28 bits come from the RXIN_ _ LVDS RES.
inputs. Control bits can be mapped to DIN27 and DIN28
in 4-channel mode. The audio channel bit (ACB) con- Reverse Control Channel
tains an encoded audio signal derived from the three I2S The MAX9249 uses the reverse control channel to
inputs (SD/CNTL0, SCK, and WS). The forward control- receive I2C/UART and interrupt signals from the GMSL
channel (FCC) bit carries the forward control data. The deserializer in the opposite direction of the video stream.
last bit (PCB) is the parity bit of the previous 23 or 31 bits. The reverse control channel and forward video data
coexist on the same twisted pair forming a bidirectional
link. The reverse control channel operates independently
24 BITS from the forward control channel. The reverse control
channel is available 500Fs after power-up. The MAX9249
temporarily disables the reverse control channel for
DIN0 DIN1 DIN17 DIN18 DIN19 DIN20 ACB FCC PCB 350Fs after starting/stopping the forward serial link.
R0 R1 B5 HS VS DE Data-Rate Selection
The MAX9249 uses the DRS input to set the RXCLKIN_
LVDS AUDIO frequency. Set DRS high for an RXCLKIN_ frequency of
DATA CHANNEL BIT
(3 CHANNELS) 6.25MHz to 12.5MHz (4-channel mode) or 8.33MHz to
FORWARD
16.66MHz (3-channel mode). Set DRS low for normal
CONTROL- operation with an RXCLKIN_ frequency of 12.5MHz
CHANNEL BIT
to 78MHz (4-channel mode) or 16.66MHz to 104MHz
PACKET (3-channel mode).
NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE PARITY
SET ACCORDING TO VESA STANDARD PANEL BITMAP. CHECK BIT
Figure 15. 3-Channel Mode Serial Link Data Format
18 ��
MAX9249
32 BITS
DIN0 DIN1 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIN24 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB
R0 R1 B5 HS VS DE R6 R7 G6 G7 B6 B7 CNTL2
LVDS LVDS AUDIO

DATA DATA CHANNEL/CNTL0
(RXIN[2:0]_) (RXIN3_) BIT
RES/CNTL1 FORWARD
CONTROL-
CHANNEL BIT
NOTE: LOCATIONS OF THE LVDS RGB DATA AND CONTROL SIGNALS
PACKET
ARE SET ACCORDING TO THE VESA STANDARD PANEL BITMAP.
PARITY
*DIN27 FROM LVDS DATA (RXIN3_) OR EXTERNAL PIN (CNTL1). CHECK BIT
Figure 16. 4-Channel Mode Serial Link Data Format
Table 3. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies

RXCLKIN_ FREQUENCY RXCLKIN_ FREQUENCY
WORD LENGTH (DRS = LOW) (DRS = HIGH)
(BITS) (MHz) (MHz)
12.5 15 16.6 > 20 6.25 7.5 8.33 > 10
8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192
18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192
20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192
24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192
32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192
Audio Channel spectrum settings do not affect the I2S data rate or WS
The I2S audio channel supports audio sampling rates clock frequency.
from 8kHz to 192kHz and audio word lengths from 4 bits
Control Channel and Register Programming
to 32 bits. The audio bit clock (SCK) does not have to
The control channel is available for the FC to send
be synchronized with RXCLKIN_. The MAX9249 auto-
and receive control data over the serial link simultane-
matically encodes audio data into a single bit stream
ously with the high-speed data. Configuring the CDS pin
synchronous with RXCLKIN_. The GMSL deserializer
allows the FC to control the link from either the MAX9249
decodes the audio stream and stores audio words in a
or the GMSL deserializer side to support video-display or
FIFO. Audio rate detection uses an internal oscillator to
image-sensing applications.
continuously determine the audio data rate and output
the audio in I2S format. The audio channel is enabled by The control channel between the FC and MAX9249 or
default. When the audio channel is disabled, the audio GMSL deserializer runs in base mode or bypass mode
data on the MAX9249 and GMSL deserializer is treated according to the mode selection (MS) input of the device
as a control pin (CNTL0). connected to the FC. Base mode is a half-duplex control
channel and the bypass mode is a full-duplex control
Low RXCLKIN_ frequencies limit the maximum audio
channel. In base mode, the FC is the host and can
sampling rate. Table 3 lists the maximum audio sam-
access the registers of both the MAX9249 and GMSL
pling rate for various RXCLKIN_ frequencies. Spread-
deserializer from either side of the link by using the GMSL
______________________________________________________________________________________ 19
UART protocol. The FC can also program the peripher- effect until after the acknowledge byte is sent. This
MAX9249
als on the remote side by sending the UART packets allows the FC to verify write commands received without
to the MAX9249 or GMSL deserializer, with the UART error, even if the result of the write command directly
packets converted to I2C by the device on the remote affects the serial link. The slave uses the SYNC byte to
side of the link (GMSL deserializer for LCD or MAX9249 synchronize with the host UART data rate automatically.
for image-sensing applications). The FC communicates If the INT or MS inputs of the GMSL deserializer toggles
with a UART peripheral in base mode (through INTTYPE while there is control-channel communication, the con-
register settings), using the half-duplex default GMSL trol-channel communication may be corrupted. In the
UART protocol of the MAX9249/GMSL deserializer. The event of a missed acknowledge, the FC should assume
device addresses of the MAX9249 and GMSL deserial- there was an error in the packet when the slave device
izer in base mode are programmable. The default values receives it, or that an error occurred during the response
are 0x80 for the MAX9249 and 0x90 for the GMSL dese- from the slave device. In base mode, the FC must keep
rializer. the UART Tx/Rx lines high for 16 bit times before starting
In base mode, when the peripheral interface uses to send a new packet.
I2C (default), the MAX9249/GMSL deserializer convert As shown in Figure 21, the remote-side device converts
packets to I2C that have device addresses different the packets going to or coming from the peripherals from
from those of the MAX9249 or GMSL deserializer. The the UART format to the I2C format and vice versa. The
converted I2C bit rate is the same as the original UART remote device removes the byte number count and adds
bit rate. or receives the ACK between the data bytes of I2C. The
In bypass mode, the MAX9249/GMSL deserializer ignore I2C’s data rate is the same as the UART data rate.
UART commands from the FC and the FC communi- Interfacing Command-Byte-Only
cates with the peripherals directly using its own defined I2C Devices
UART protocol. The FC cannot access the MAX9249/ The MAX9249 and GMSL deserializer UART-to-I2C con-
GMSL deserializer’s registers in this mode. Peripherals version interfaces with devices that do not require regis-
accessed through the forward control channel using the ter addresses, such as the MAX7324 GPIO expander. In
UART interface need to handle at least one RXCLKIN_ this mode, the I2C master ignores the register address
period of jitter due to the asynchronous sampling of the byte and directly reads/writes the subsequent data bytes
UART signal by RXCLKIN_. (Figure 22). Change the communication method of the
The MAX9249 embeds control signals going to the GMSL I2C master using the I2CMETHOD bit. I2CMETHOD = 1
deserializer in the high-speed forward link. Do not send sets command-byte-only mode, while I2CMETHOD = 0
a logic-low value longer than 100Fs in either base or sets normal mode where the first byte in the data stream
bypass mode. The GMSL deserializer uses a proprietary is the register address.
differential line coding to send signals back towards the
Interrupt Control
MAX9249. The speed of the control channel ranges from
The INT pin of the MAX9249 is the interrupt output and
100kbps to 1Mbps in both directions. The MAX9249/
the INT pin of the GMSL deserializer is the interrupt
GMSL deserializer automatically detect the control chan-
input. The interrupt output on the MAX9249 follows the
nel bit rate in base mode. Packet bit rates can vary up
transitions at the interrupt input. This interrupt function
to 3.5x from the previous bit rate (see the Changing the
supports remote-side functions such as touch-screen
Clock Frequency section). Figure 17 shows the UART
peripherals, remote power-up, or remote monitoring.
protocol for writing and reading in base mode between
Interrupts that occur during periods where the reverse
the FC and the MAX9249/GMSL deserializer.
control channel is disabled, such as link startup/shut-
Figure 18 shows the UART data format. Even parity is down, are automatically resent once the reverse control
used. Figures 19 and 20 detail the formats of the SYNC channel becomes available again. Bit D4 of register
byte (0x79) and the ACK byte (0xC3). The FC and the 0x06 in the GMSL deserializer also stores the interrupt
connected slave chip generate the SYNC byte and ACK input state. The INT output of the MAX9249 is low after
byte, respectively. Events such as device wake-up and power-up. In addition, the FC can set the INT output of
interrupt generate transitions on the control channel MAX9249 by writing to the SETINT register bit. In normal
that should be ignored by the FC. Data written to the operation, the state of the interrupt output changes when
MAX9249/GMSL deserializer registers does not take the interrupt input on the GMSL deserializer toggles.
20 ��
MAX9249
WRITE DATA FORMAT
SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES BYTE 1 BYTE N
MASTER WRITES TO SLAVE ACK
MASTER READS FROM SLAVE
READ DATA FRMAT

SYNC DEV ADDR + R/W REG ADDR NUMBER OF BYTES
MASTER WRITES TO SLAVE ACK BYTE 1 BYTE N
MASTER READS FROM SLAVE
Figure 17. GMSL UART Protocol for Base Mode
1 UART FRAME
START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP
FRAME 1 FRAME 2 FRAME 3
STOP START STOP START
Figure 18. GMSL UART Data Format for Base Mode
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
START 1 0 0 1 1 1 1 0 PARITY STOP START 1 1 0 0 0 0 1 1 PARITY STOP
Figure 19. SYNC Byte (0x79) Figure 20. ACK Byte (0xC3)
______________________________________________________________________________________ 21
MAX9249
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 0)

FC MAX9249/GMSL DESERIALIZER
11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME
MAX9249/GMSL DESERIALIZER PERIPHERAL

1 7 1 1 8 1 8 1 8 1 1
S DEV ID W A REG ADDR A DATA 0 A DATA N A P
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 0)

11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES ACK FRAME DATA 0 DATA N

1 7 1 1 8 1 1 7 1 1 8 1 8 1 1
S DEV ID W A REG ADDR A S DEV ID R A DATA 0 A DATA N A P
: MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
Figure 21. Format Conversion Between GMSL UART and I2C with Register Address (I2CMETHOD = 0)
UART-TO-I2C CONVERSION OF WRITE PACKET (I2CMETHOD = 1)

11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + WR REGISTER ADDRESS NUMBER OF BYTES DATA 0 DATA N ACK FRAME

1 7 1 1 8 1 8 1 1
S DEV ID W A DATA 0 A DATA N A P
UART-TO-I2C CONVERSION OF READ PACKET (I2CMETHOD = 1)

11 11 11 11 11 11 11
SYNC FRAME DEVICE ID + RD REGISTER ADDRESS NUMBER OF BYTES ACK FRAME DATA 0 DATA N

1 7 1 1 8 1 8 1 1
S DEV ID R A DATA 0 A DATA N A P
: MASTER TO SLAVE : SLAVE TO MASTER S: START P: STOP A: ACKNOWLEDGE
Figure 22. Format Conversion Between UART and I2C in Command-Byte-Only Mode (I2CMETHOD = 1)
22 ��
Table 4. CML Driver Strength (Default Level, CMLLVL = 11)
MAX9249
PREEMPHASIS SINGLE-ENDED VOLTAGE SWING
PREEMPHASIS LEVEL ICML IPRE
SETTING MAX MIN
(dB)* (mA) (mA)
(0x05, D[3:0]) (mV) (mV)
-6.0 0100 12 4 400 200
-4.1 0011 13 3 400 250
-2.5 0010 14 2 400 300
-1.2 0001 15 1 400 350
0 0000 16 0 400 400
1.1 1000 16 1 425 375
2.2 1001 16 2 450 350
3.3 1010 16 3 475 325
4.4 1011 16 4 500 300
6.0 1100 15 5 500 250
8.0 1101 14 6 500 200
10.5 1110 13 7 500 150
14.0 1111 12 8 500 100
*Negative preemphasis levels denote deemphasis.
Table 5. Serial Output Spread (0x05 D[5:4]) to reduce the driver strength down to
75% (CMLLVL = 10) or 50% (CMLLVL = 01) from 100%
SS SPREAD (%)
(CMLLVL = 11, default).
No spread spectrum.
000 Spread Spectrum
Power-up default when SSEN = low.
To reduce the EMI generated by the transitions on the
Q0.5% spread spectrum.
001 serial link and outputs of the GMSL deserializer, both
Power-up default when SSEN = high.
the MAX9249 and GMSL deserializer support spread
010 Q1.5% spread spectrum
spectrum. Turning on spread spectrum on the MAX9249
011 Q2% spread spectrum spreads the serial data and the GMSL deserializer out-
100 No spread spectrum puts. Do not enable spread for both the MAX9249 and
101 Q1% spread spectrum GMSL deserializer. The six selectable spread-spectrum
110 Q3% spread spectrum rates at the MAX9249 serial output are ±0.5%, ±1%,
111 Q4% spread spectrum ±1.5%, ±2%, ±3%, and ±4% (Table 5). Some spread-
spectrum rates can only be used at lower RXCLKIN_
Preemphasis Driver frequencies (Table 6). There is no RXCLKIN_ frequency
The serial line driver in the MAX9249 employs cur- limit for the 0.5% spread rate.
rent-mode logic (CML) signaling. The driver can be Set the MAX9249 SSEN input high to select 0.5% spread
programmed to generate a preemphasized waveform at power-up and SSEN input low to select no spread at
according to the cable length and characteristics. There power-up. The state of SSEN is latched upon power-up
are 13 preemphasis settings, as shown in Table 4. or when resuming from power-down mode. Whenever
Negative preemphasis levels are deemphasis levels in the MAX9249 spread spectrum is turned on or off, the
which the swing is the same as normal, but the no-tran- serial link automatically restarts and remains unavailable
sition data is deemphasized. Program the preemphasis while the GMSL deserializer relocks to the serial data.
levels through register 0x05 D[3:0] of the MAX9249. This Turning on spread spectrum on the MAX9249 or GMSL
preemphasis function compensates the high-frequency deserializer does not affect the audio data stream.
loss of the cable and enables reliable transmission over Changes in the MAX9249 spread settings only affect
longer link distances. Additionally, a lower power-drive the GMSL deserializer MCLK output if it is derived from
mode can be entered by programming CMLLVL bits RXCLKIN_ (MCLKSRC = 0).
______________________________________________________________________________________ 23
MAX9249
Table 6. Spread-Spectrum Rate Limitations

3-CHANNEL MODE 4-CHANNEL MODE
SERIAL LINK BIT RATE AVAILABLE SPREAD
RXCLKIN_ FREQUENCY RXCLKIN_ FREQUENCY
(Mbps) RATES
(MHz) (MHz)
< 33.3 < 25 < 1000 All rates available
33.3 to < 66.7 20 to < 50 1000 to < 2000 1.5%, 1.0%, 0.5%
≥ 66.7 ≥ 50 ≥ 2000 0.5%
Table 7. Modulation Coefficients and Maximum SDIV Settings

SPREAD-SPECTRUM MODULATION COEFFICIENT SDIV UPPER LIMIT
BUS-WIDTH MODE
SETTING (%) (DECIMAL) (DECIMAL)
0.5 104 63
1 104 40
1.5 152 54
4-Channel
2 204 30
3 152 27
4 204 15
0.5 80 63
1 80 52
1.5 112 63
3-Channel
2 152 42
3 112 37
4 152 21
Both devices include a sawtooth divider to control the fM = Modulation frequency

spread-modulation rate. Autodetection or manual pro- DRS = DRS pin input value (0 or 1)
gramming of the RXCLKIN_ operation range guarantees
a spread-spectrum modulation frequency within 20kHz fRXCLKIN_ = LVDS clock frequency
to 40kHz. Additionally, manual configuration of the MOD = Modulation coefficient given in Table 7
sawtooth divider (SDIV, 0x03 D[5:0]) allows the user to SDIV = 6-bit SDIV setting, manually programmed
set a modulation frequency according to the RXCLKIN_ by the FC
frequency. Always keep the modulation frequency
To program the SDIV setting, first look up the modulation
between 20kHz to 40kHz to ensure proper operation.
coefficient according to the part number and desired
Manual Programming of the bus-width and spread-spectrum settings. Solve the above
Spread-Spectrum Divider equation for SDIV using the desired pixel clock and modu-
The modulation rate for the MAX9249 relates to the lation frequencies. If the calculated SDIV value is larger
RXCLKIN_ frequency as follows: than the maximum allowed SDIV value in Table 7, set SDIV
to the maximum value.
fRXCLKIN_
fM= (1 + DRS) Sleep Mode
MOD × SDIV
The MAX9249/GMSL deserializer include low-power
sleep mode to reduce power consumption on the device
where: not attached to the FC (the GMSL deserializer in LCD
applications and the MAX9249 in camera applications).
Set the corresponding remote IC’s SLEEP bit to 1 to initi-
ate sleep mode. The MAX9249 sleeps immediately after
24 ��
Table 8. Startup Selection for Video-Display Applications (CDS = Low)
MAX9249
MAX9249 MS GMSL
AUTOS
CASE POWER-UP (GMSL DESERIALIZER LINK STARTUP MODE
(MAX9249)
STATE DESERIALIZER) POWER-UP STATE
Serialization Normal Both devices power up with serial link active
1 Low Low
enabled (SLEEP = 0) (autostart)
Serial link is disabled and the GMSL

deserializer powers up in sleep mode. Set
Serialization Sleep mode
2 High High SEREN = 1 or CLINKEN = 1 in the MAX9249
disabled (SLEEP = 1)
to start the serial link and wake up the GMSL
deserializer.
Both devices power up in normal mode with

Serialization Normal the serial link disabled. Set SEREN = 1 or
3 High Low
disabled (SLEEP = 0) CLINKEN = 1 in the MAX9249 to start the
serial link.
GMSL deserializer starts in sleep mode.

Serialization Sleep mode Link autostarts upon MAX9249 power-up.
4 Low High
enabled (SLEEP = 1) Use this case when the GMSL deserializer
powers up before the MAX9249.
setting its SLEEP = 1. The GMSL deserializer sleeps after Link Startup Procedure
serial link inactivity or 8ms (whichever arrives first) after
setting its SLEEP = 1. See the Link Startup Procedure Table 8 lists four startup cases for video-display applica-
section for details on waking up the device for different tions. Table 9 lists two startup cases for image-sensing
FC and starting conditions. applications. In either video-display or image-sensing
applications, the control link is always available after the
The FC side device cannot enter into sleep mode. If an high-speed data link or the configuration link is estab-
attempt is made to program the FC side device for sleep, lished and the MAX9249/GMSL deserializer registers or
the SLEEP bit remains 0. Use the PWDN input pin to the peripherals are ready for programming.
bring the FC side device into a low-power state.
Video-Display Applications
Configuration Link Mode For the video-display application, with a remote display
The MAX9249 includes a low-speed configuration link to unit, connect the FC to the serializer (MAX9249) and set
allow control-data connection between the two devices CDS = low for both the MAX9249 and GMSL deserializer.
in the absence of a valid clock input. In either display or Table 8 summarizes the four startup cases based on the
camera applications, the configuration link can be used settings of AUTOS and MS.
to program equalizer/preemphasis or other registers
before establishing the video link. An internal oscillator Case 1: Autostart Mode
provides RXCLKIN_ for establishing the serial configura- After power-up or when PWDN transitions from low to
tion link between the MAX9249 and GMSL deserializer. high for both the serializer and deserializer, the serial
Set CLINKEN = 1 on the MAX9249 to turn on the con- link establishes if a stable RXCLKIN_ is present. The
figuration link. The configuration link remains active as MAX9249 locks to RXCLKIN_ and sends the serial data
long as the video link has not been enabled. The video to the GMSL deserializer. The GMSL deserializer then
link overrides the configuration link and attempts to lock detects activity on the serial link and locks to the input
when SEREN = 1. serial data.
______________________________________________________________________________________ 25
MAX9249
CLINKEN = 0 OR
AUTOS PIN SEREN BIT SEREN = 1
SETTING POWER-UP VALUE
LOW 1
HIGH 0
CLINKEN = 0 OR
SEREN = 1 CONFIG LINK
PWDN = HIGH, CONFIG LINK
POWER-DOWN POWER-ON POWER-ON CONFIG UNLOCKED OPERATING
OR POWER-OFF IDLE LINK STARTING PROGRAM
AUTOS = LOW CLINKEN = 1 CONFIG LINK
LOCKED REGISTERS
SEREN = 1, SEREN = 0,
PWDN = LOW OR NO RXCLKIN_
RXCLKIN_ RUNNING
POWER-OFF
PWDN = HIGH
SEREN = 0, OR
POWER-ON,
NO RXCLKIN_
AUTOS = LOW PRBSEN = 0
VIDEO VIDEO LINK VIDEO LINK VIDEO LINK
ALL STATES
LINK LOCKING LOCKED OPERATING PRBS TEST
PRBSEN = 1
VIDEO LINK
UNLOCKED
Figure 23. State Diagram, CDS = Low (LCD Application)
Table 9. Startup Selection for Image-Sensing Applications (CDS = High)

AUTOS MAX9249 POWER-UP GMSL DESERIALIZER
CASE LINK STARTUP MODE
(MAX9249) STATE POWER-UP STATE
Normal
1 Low Serialization enabled Autostart
(SLEEP = 0)
MAX9249 is in sleep mode. Wake up the
Sleep mode Normal
2 High MAX9249 through the control channel (FC
(SLEEP = 1) (SLEEP = 0)
attached to the GMSL deserializer).
Case 2: Standby Start Mode Case 3: Remote Side Autostart Mode

After power-up or when PWDN transitions from low to After power-up or when PWDN transitions from low
high for both the serializer and deserializer, the GMSL to high, the remote device (GMSL deserializer) starts
deserializer starts up in sleep mode, and the MAX9249 up and tries to lock to an incoming serial signal with
stays in standby mode (does not send serial data). Use sufficient power. The host side (MAX9249) is in standby
the FC and program the MAX9249 to set SEREN = 1 to mode and does not try to establish a link. Use the FC and
establish a video link or CLINKEN = 1 to establish the program the MAX9249 to set SEREN = 1 (and apply a
configuration link. After locking to a stable RXCLKIN_ (for stable RXCLKIN_) to establish a video link or CLINKEN
SEREN = 1) or the internal oscillator (for CLINKEN = 1), = 1 to establish the configuration link. In this case, the
the MAX9249 sends a wake-up signal to the deserializer. GMSL deserializer ignores the short wake-up signal sent
The GMSL deserializer exits sleep mode after locking to from MAX9249.
the serial data and sets SLEEP = 0. If after 8ms the dese-
rializer does not lock to the input serial data, the GMSL
deserializer goes back to sleep, and the internal sleep bit
remains set (SLEEP = 1).
26 ��
MAX9249
AUTOS PIN POWER-UP VALUE
SETTING SEREN SLEEP
LOW 1 0 CLINKEN = 0 OR
HIGH 0 1 SEREN = 1
CLINKEN = 0 OR
SLEEP = 1 SEREN = 1 CONFIG LINK CONFIG LINK
FOR > 8ms SLEEP = 0, POWER-ON CONFIG UNLOCKED OPERATING
SLEEP WAKE-UP
SEREN = 0 IDLE CLINKEN = 1 LINK STARTED CONFIG LINK PROGRAM
REVERSE LINK
LOCKED REGISTERS
WAKE-UP SIGNAL
PWDN = HIGH, SEREN = 1,
SEREN = 0 OR
POWER-ON, SLEEP = 0, RXCLKIN_ RUNNING
SLEEP = 1 NO RXCLKIN_
AUTOS = HIGH SLEEP = 1
SEREN = 0 OR
NO RXCLKIN_
PWDN = HIGH, PRBSEN = 0
PWDN = LOW OR POWER-DOWN VIDEO LINK
POWER-ON VIDEO VIDEO LINK VIDEO LINK
ALL STATES OR
POWER-OFF AUTOS = LOW LINK LOCKING LOCKED OPERATING PRBSEN = 1 PRBS TEST
POWER-OFF
VIDEO LINK
UNLOCKED
Figure 24. State Diagram, CDS = High (Camera Application)
Case 4: Remote Side in Sleep Mode frame containing at least three rising edges (e.g., 0x66),
After power-up or when PWDN transitions from low to at a bit rate no greater than 1Mbps. The low-power wake-
high, the remote device (GMSL deserializer) starts up in up receiver of the MAX9249 detects the wake-up frame
sleep mode. The high-speed link establishes automati- over the reverse control channel and powers up. Reset
cally after MAX9249 powers up with a stable RXCLKIN_ the sleep bit (SLEEP = 0) of the MAX9249 using a regular
and sends a wake-up signal to the GMSL deserializer. control channel write packet to power up the device fully.
Use this mode in applications where the GMSL deserial- Send the sleep bit write packet at least 500Fs after the
izer powers up before the MAX9249. wake-up frame. The MAX9249 goes back to sleep mode
if its sleep bit is not cleared within 5ms (min) after detect-
Image-Sensing Applications
ing a wake-up frame.
For image-sensing applications, connect the FC to the
GMSL deserializer and set CDS = high for both the Applications Information
MAX9249 and GMSL deserializer. The GMSL deserial-
izer powers up normally (SLEEP = 0) and continuously Self-PRBS Test
tries to lock to a valid serial input. Table 9 summarizes The MAX9249/GMSL deserializer link includes a PRBS
both startup cases, based on the state of the MAX9249 pattern generator and bit-error verification function. Set
AUTOS pin. PRBSEN =1 (0x04 D5) first in the MAX9249 and then the
GMSL deserializer to start the PRBS test. Set PRBSEN
Case 1: Autostart Mode
=0 (0x04 D5) first in the GMSL deserializer and then the
After power-up, or when PWDN transitions from low to
MAX9249 to exit the PRBS self-test. The GMSL deserial-
high, the MAX9249 locks to a stable RXCLKIN_ and
izer uses an 8-bit register (0x0E) to count the number of
sends the high-speed data to the GMSL deserializer. The
detected errors. The control link also controls the start
GMSL deserializer locks to the serial data and outputs
and stop of the error counting. During PRBS mode, the
the video data and clock.
device does not count decoding errors and the GMSL
Case 2: Sleep Mode deserializer ERR output reflects PRBS errors only. Refer
After power-up or when PWDN transitions from low to to the respective GMSL deserializer data sheet for more
high, the MAX9249 starts up in sleep mode. To wake up details.
the MAX9249, use the FC to send a GMSL protocol UART
______________________________________________________________________________________ 27
MAX9249
Microcontrollers on Both Sides of the Changing the Clock Frequency

GMSL Link (Dual µC Control) Both the video clock rate (fRXCLKIN_) and the control-
Usually the microcontroller is either on the serializer channel clock rate (fUART) can be changed on-the-fly
(MAX9249) side for video-display applications or on the to support applications with multiple clock speeds. It is
deserializer side for image-sensing applications. For the recommended to enable the serial link after RXCLKIN_
former case, both the CDS pins of the MAX9249/GMSL stabilizes. Stop RXCLKIN_ for 5Fs and restart the serial
deserializer are set to low, and for the latter case, the link or toggle SEREN after each change in the RXCLKIN_
CDS pins are set to high. However, if the CDS pin of the frequency to recalibrate any automatic settings if a clean
MAX9249 is low and the same pin of the GMSL dese- frequency change cannot be guaranteed. The reverse
rializer is high, then the MAX9249/GMSL deserializer control channel remains unavailable for 350Fs after serial
connect to both FCs simultaneously. In such a case, the link start or stop. Limit on-the-fly changes in fUART to fac-
FCs on either side can communicate with the MAX9249/ tors of less than 3.5 at a time to ensure that the device
GMSL deserializer. recognizes the UART sync pattern. For example, when
Contentions of the control link can happen if the FCs lowering the UART frequency from 1Mbps to 100kbps,
on both sides are using the link at the same time. The first send data at 333kbps and then at 100kbps to have
MAX9249/GMSL deserializer do not provide the solution reduction ratios of 3 and 3.333, respectively.
for contention avoidance. The serializer/deserializer do LOCK Output Loopback
not send an acknowledge frame when communication For quick loss-of-lock notification, the GMSL deserializer
fails due to contention. Users can always implement a can loop back its LOCK output to the MAX9249 using
higher layer protocol to avoid the contention. In addi- the INT signal. Connect the LOCK output to the INT
tion, if UART communication across the serial link is not input of the GMSL deserializer. The interrupt output on
required, the FCs can disable the forward and reverse the MAX9249 follows the transitions at the LOCK output
control channel through the REVCCEN and FWDCCEN of the GMSL deserializer. Reverse control-channel com-
bits (0x04 D[1:0]) in the MAX9249/GMSL deserializer. munication does not require an active forward link to
UART communication across the serial link is stopped operate and accurately tracks the LOCK status of the
and contention between FCs no longer occurs. During video link. LOCK asserts for video link only and not for
dual FCs operation, if one of the CDS pins on either side the configuration link.
changes state, the link resumes the corresponding state
described in the Link Startup Procedure section. Line-Fault Detection
The line-fault detector in the MAX9249 monitors for line
As an example of dual FC use in an image-sensing appli-
failures such as short to ground, short to power supply,
cation, the MAX9249 can be in sleep mode and waiting
and open link for system fault diagnosis. Figure 3 shows
for wake-up by the GMSL deserializer. After wake-up, the
the required external resistor connections. LFLT = low
serializer-side FC sets the MAX9249 CDS pin low and
when a line fault is detected and LFLT = high when the
assumes master control of the MAX9249 registers.
line returns to normal. The line-fault type is stored in
Jitter-Filtering PLL 0x08 D[3:0] of the MAX9249. The fault-detector thresh-
In some applications, the input clock to the MAX9249 old voltages are referenced to the MAX9249 ground.
(RXCLKIN_) includes jitter that reduces link reliability. Additional passive components set the DC level of the
The MAX9249 has a programmable narrow-band jitter- cable (Figure 3). If the MAX9249 and GMSL deserializer
filtering PLL to attenuate frequency components outside grounds are different, the link DC voltage during normal
the PLL’s bandwidth (< 100kHz, typ). Enable the jitter- operation can vary and cross one of the fault-detection
filtering PLL by setting DISFPLL = 0 (0x05 D6). thresholds. For the fault-detection circuit, select the
resistor’s power rating to handle a short to the battery
and use surface-mount resistors with small case size to
minimize parasitic effects to the high-speed signal. Table
10 lists the mapping for line-fault types.
28 ��
Table 10. Line-Fault Mapping
MAX9249
REGISTER
BITS NAME VALUE LINE-FAULT TYPE
ADDRESS
00 Negative cable wire shorted to battery
01 Negative cable wire shorted to ground
D[3:2] LFNEG
10 Normal operation
11 Negative cable wire open
0x08
00 Positive cable wire shorted to battery
01 Positive cable wire shorted to ground
D[1:0] LFPOS
10 Normal operation
11 Positive cable wire open
Choosing I2C/UART Pullup Resistors and jitter to an acceptable level. The RC network for an
Both I2C/UART open-drain lines require pullup resis- AC-coupled link consists of the CML receiver termination
tors to provide a logic-high level. There are trade-offs resistor (RTR), the CML driver termination resistor (RTD),
between power dissipation and speed, and a compro- and the series AC-coupling capacitors (C). The RC time
mise made in choosing pullup resistor values. Every constant for four equal-value series capacitors is (C x
device connected to the bus introduces some capaci- (RTD + RTR))/4. RTD and RTR are required to match the
tance even when the device is not in operation. I2C transmission line impedance (usually 100I). This leaves
specifies 300ns rise times to go from low to high (30% to the capacitor selection to change the system time con-
70%) for fast mode, which is defined for data rates up to stant. Use at least 0.2FF high-frequency surface-mount
400kbps (see the I2C specifications in the AC Electrical ceramic capacitors, with sufficient voltage rating to with-
Characteristics section for details). To meet the fast- stand a short to battery, to pass the lower speed reverse
mode rise-time requirement, choose the pullup resistors control-channel signal. Use capacitors with a case size
so that rise time tR = 0.85 x RPULLUP x CBUS < 300ns. less than 3.2mm x 1.6mm to have lower parasitic effects
The waveforms are not recognized if the transition time to the high-speed signal.
becomes too slow. The MAX9249 supports I2C/UART
Power-Supply Circuits and Bypassing
rates up to 1Mbps.
The MAX9249 uses a VAVDD and VDVDD of 1.7V to
AC-Coupling 1.9V, and a VLVDSVDD of 3.0V to 3.6V. All single-ended
AC-coupling isolates the receiver from DC voltages up inputs and outputs on the MAX9249 derive power from a
to the voltage rating of the capacitor. Four capacitors— VIOVDD of 1.7V to 3.6V, which scale with IOVDD. Proper
two at the serializer output and two at the deserializer voltage-supply bypassing is essential for high-frequency
input—are needed for proper link operation and to pro- circuit stability.
vide protection if either end of the cable is shorted to a
Cables and Connectors
high voltage. AC-coupling blocks low-frequency ground
Interconnect for CML typically has a differential imped-
shifts and low-frequency common-mode noise.
ance of 100I. Use cables and connectors that have
Selection of AC-Coupling Capacitors matched differential impedance to minimize impedance
Voltage droop and the digital sum variation (DSV) of discontinuities. Twisted-pair and shielded twisted-pair
transmitted symbols cause signal transitions to start cables tend to generate less EMI due to magnetic-field
from different voltage levels. Because the transition time canceling effects. Balanced cables pick up noise as
is finite, starting the signal transition from different volt- common mode rejected by the CML receiver. Table 11
age levels causes timing jitter. The time constant for an lists the suggested cables and connectors used in the
AC-coupled link needs to be chosen to reduce droop GMSL link.
______________________________________________________________________________________ 29
MAX9249
Table 11. Suggested Connectors and Cables for GMSL

VENDOR CONNECTOR CABLE
JAE Electronics, Inc. MX38-FF A-BW-Lxxxxx
Nissei Electric Co., Ltd. GT11L-2S F-2WME AWG28
Rosenberger Hochfrequenztechnik GmbH D4S10A-40ML5-Z Dacar 538
Board Layout
RD
Separate the digital signals and CML/LVDS high-speed 1MI 1.5kI
signals to prevent crosstalk. Use a four-layer PCB with
separate layers for power, ground, CML/LVDS, and CHARGE-CURRENT- DISCHARGE
digital signals. Layout PCB traces close to each other LIMIT RESISTOR RESISTANCE
HIGH-
for a 100I differential characteristic impedance. The VOLTAGE CS STORAGE DEVICE
100pF UNDER
trace dimensions depend on the type of trace used DC CAPACITOR
TEST
SOURCE
(microstrip or stripline). Note that two 50I PCB traces
do not have 100I differential impedance when brought
close together—the impedance goes down when the
traces are brought closer.
Figure 25. Human Body Model ESD Test Circuit
Route the PCB traces for a CML/LVDS channel (there
are two conductors per CML/LVDS channel) in parallel to RD
maintain the differential characteristic impedance. Avoid 330I
vias. Keep PCB traces that make up a differential pair
equal length to avoid skew within the differential pair. CHARGE-CURRENT- DISCHARGE
LIMIT RESISTOR RESISTANCE
HIGH-
ESD Protection VOLTAGE CS STORAGE DEVICE
The MAX9249 ESD tolerance is rated for Human Body 150pF CAPACITOR UNDER
DC
TEST
Model, IEC 61000-4-2, and ISO 10605. The ISO 10605 SOURCE
and IEC 61000-4-2 standards specify ESD tolerance for
electronic systems. CML/LVDS I/O are tested for ISO
10605 ESD protection and IEC 61000-4-2 ESD protec-
tion. All pins are tested for the Human Body Model. The Figure 26. IEC 61000-4-2 Contact Discharge ESD Test Circuit
Human Body Model discharge components are CS =
100pF and RD = 1.5kI (Figure 25). The IEC 61000-4-2 RD
discharge components are CS = 150pF and RD = 330I 2kI
(Figure 26). The ISO 10605 discharge components are

CHARGE-CURRENT- DISCHARGE
CS = 330pF and RD = 2kI (Figure 27). LIMIT RESISTOR RESISTANCE
HIGH-
CS STORAGE DEVICE
VOLTAGE
330pF CAPACITOR UNDER
DC
TEST
SOURCE
Figure 27. ISO 10605 Contact Discharge ESD Test Circuit
30 ��
Table 12. Register Table (See Table 1 for Default Value Details)
MAX9249
REGISTER DEFAULT
BITS NAME VALUE FUNCTION
ADDRESS VALUE
D[7:1] SERID XXXXXXX Serializer device address 1000000
0x00
D0 — 0 Reserved 0
D[7:1] DESID XXXXXXX Deserializer device address 1001000
0x01
D0 — 0 Reserved 0
No spread spectrum. Power-up default when
000
SSEN = low.
Q0.5% spread spectrum. Power-up default when
001
SSEN = high.
010 Q1.5% spread spectrum
D[7:5] SS 000, 001
011 Q2% spread spectrum
100 No spread spectrum
0x02
0 Disable I2S channel
D4 AUDIOEN 1
1 Enable I2S channel
00 12.5MHz to 25MHz pixel clock
01 25MHz to 50MHz pixel clock
D[3:2] PRNG 11
10 50MHz to 104MHz pixel clock
11 Automatically detect the pixel clock range
00 0.5 to 1Gbps serial-bit rate
01 1 to 2Gps serial-bit rate
D[1:0] SRNG 11
10 2 to 3.125Gbps serial-bit rate
11 Automatically detect serial-bit rate
Calibrate spread-modulation rate only once after
00
locking
Calibrate spread-modulation rate every 2ms after
01
locking
D[7:6] AUTOFM 00
Calibrate spread-modulation rate every 16ms after
10
locking
0x03
Calibrate spread-modulation rate every 256ms
11
after locking
000000 Autocalibrate sawtooth divider
Manual SDIV setting. See the Manual
D[5:0] SDIV 000000
XXXXXX Programming of the Spread-Spectrum Divider
section.
______________________________________________________________________________________ 31
Table 12. Register Table (See Table 1 for Default Value Details) (continued)
MAX9249
REGISTER DEFAULT
ADDRESS VALUE
Disable serial link. Power-up default when
AUTOS = high. Reverse control-channel com-
0
munication remains unavailable for 350Fs after the
MAX9249 starts/stops the serial link.
D7 SEREN 0, 1
Enable serial link. Power-up default when
AUTOS = low. Reverse control-channel commu-
1
nication remains unavailable for 350Fs after the
MAX9249 starts/stops the serial link.
0 Disable configuration link
D6 CLINKEN 0
1 Enable configuration link
0 Disable PRBS test
D5 PRBSEN 0
1 Enable PRBS test
Normal mode. Default value depends on CDS and
0
0x04 AUTOS pin values at power-up.
D4 SLEEP 0, 1
Activate sleep mode. Default value depends on
1
CDS and AUTOS pin values at power-up.
00 Base mode uses I2C peripheral interface
D[3:2] INTTYPE 01 Base mode uses UART peripheral interface 00
10, 11 Base mode peripheral interface disabled
Disable reverse control channel from deserializer
0
(receiving)
D1 REVCCEN 1
Enable reverse control channel from deserializer
1
(receiving)
Disable forward control channel to deserializer
0
(sending)
D0 FWDCCEN 1
Enable forward control channel to deserializer
1
(sending)
32 ��
MAX9249
REGISTER DEFAULT
ADDRESS VALUE
0 I2C conversion sends the register address
D7 I2CMETHOD Disable sending of I2C register address 0
1
(command-byte-only mode)
0 Filter PLL active
D6 DISFPLL 1
1 Filter PLL disabled
00 Do not use
01 200mV CML signal level
D[5:4] CMLLVL 11
0000 Preemphasis off
0001 -1.2dB preemphasis
0x05 0011 -4.1dB preemphasis
0101 Do not use
0110 Do not use
0111 Do not use
D[3:0] PREEMP 0000
1000 1.1dB preemphasis
0x06 D[7:0] — 01000000 Reserved 01000000
0x07 D[7:0] — 00100010 Reserved 00100010
0000
D[7:4] — 0000 Reserved
(read only)
00 Negative cable wire shorted to battery
01 Negative cable wire shorted to ground 10
D[3:2] LFNEG
10 Normal operation (read only)
0x08
11 Negative cable wire open
00 Positive cable wire shorted to battery
01 Positive cable wire shorted to ground 10
D[1:0] LFPOS
10 Normal operation (read only)
11 Positive cable wire open
0x0C D[7:0] — 01110000 Reserved 01110000
______________________________________________________________________________________ 33
MAX9249
REGISTER DEFAULT
ADDRESS VALUE
0 Set INT low when SETINT transitions from 1 to 0
D7 SETINT 0
1 Set INT high when SETINT transitions from 0 to 1
D[6:5] — 00 Reserved 00
0 RES (LVDS interface) mapped to DIN27
D4 DISRES 0
1 CNTL1 mapped to DIN27
0000 Adjust x7 PLL clock skew + 50ps
0x0D 0101 Adjust x7 PLL clock skew + 350ps
0111 Do not use
D[3:0] SKEWADJ 1111
1000 Adjust x7 PLL clock skew - 50ps
1111 No x7PLL clock skew adjustment
Device identifier 00000011
0x1E D[7:0] ID 00000011
(MAX9249 = 0x03) (read only)
0000
D[7:4] — 0000 Reserved
0x1F (read only)
D[3:0] REVISION XXXX Device revision (read only)
X = Don’t care.
34 ��
MAX9249
Typical Application Circuit
1.8V
TXCLK+/- RXCLKIN+/- PCLKOUT PCLK

TX0+/- RXIN0+/- 45kI 45kI DOUT[20.0] RGB
TO TX2+/- TO RXIN2+/-
CDS HSYNC
GPU CDS VSYNC
AUTOS LMN1 DE
LMN0
MAX9260
ECU 5kI 5kI
MAX9249
DISPLAY
TO PERIPHERALS
OUT+ IN+ INT
Tx RX/SDA RX/SDA
UART OUT- IN-
Rx TX/SCL TX/SCL
50kI 50kI
LFLT LFLT SCL
INT INT LOCK SDA
MS MS WS WS
SCK
WS WS SD MAX9850
AUDIO SCK SCK

SCK
SD SD/CNTLO
SD MCLK
MAX9491
X1 CLK_OUT
VIDEO-DISPLAY APPLICATION
Chip Information Package Information

PROCESS: CMOS For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE PACKAGE OUTLINE LAND

TYPE CODE NO. PATTERN NO.
48 TQFP-EP C48E+8 21-0065 90-0138
______________________________________________________________________________________ 35
MAX9249
Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 1/10 Initial release —
1 3/10 Improved yield 2, 3
Added soldering temperature (reflow) to the Absolute Maximum Ratings section and
2 5/10 2, 24
corrected spread-spectrum modulation settings in Table 7
3 1/11 Added Patent Pending to Features 1
4 1/12 Corrected GND to AGND in Absolute Maximum Ratings 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

Gigabit Multimedia Serial Link Serializer With LVDS System Interface

Uploaded by

Copyright:

Available Formats

Gigabit Multimedia Serial Link Serializer With LVDS System Interface

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Gigabit Multimedia Serial Link Serializer With LVDS System Interface

Uploaded by

Copyright:

Available Formats

19-5138; Rev 4; 1/12

________________________________________________________________ Maxim Integrated Products 1

AVDD to AGND.....................................................-0.5V to +1.9V IEC 61000-4-2 (RD = 330ω, CS = 150pF)

DC ELECTRICAL CHARACTERISTICS (continued)

TOTAL SUPPLY CURRENT TOTAL SUPPLY CURRENT

TOTAL SUPPLY CURRENT (mA)

OUTPUT POWER SPECTRUM OUTPUT POWER SPECTRUM

OUTPUT POWER SPECTRUM (dBm)

0% SPREAD 0.5% SPREAD 0% SPREAD

-80 -80 2% SPREAD 4% SPREAD

MAXIMUM PCLK FREQUENCY MAXIMUM RXCLKIN_ FREQUENCY

OPTIMUM PE/EQ SETTINGS

PIN NAME FUNCTION

RXCLKIN+/- 7x PLL DIVIDE BY 7 FILTER PLL SPREAD PLL

DVOS = |VOS(+) - VOS(-)|

VOD(-) DVOD = |VOD(+) - VOD(-)| VOD(-)

Figure 1. Serial-Output Parameters

VOS VOD(P) VOD(D)

Figure 2. Output Waveforms at OUT+ and OUT-

MAX9249 45kI* 45kI*

OUTPUT 5kI* 5kI*

Figure 3. Line-Fault Detector Circuit

Figure 4. Worst-Case Pattern Input

Figure 5. I2C Timing Parameters

Figure 6. Differential Output Template

IDEAL SERIAL-BIT TIME

N-1 N N+1 N+2 N+3

FIRST BIT LAST BIT

Figure 9. Serializer Delay

SERIAL LINK INACTIVE SERIAL LINK ACTIVE

REVERSE CONTROL CHANNEL REVERSE CONTROL

PWDN MUST BE HIGH

Figure 10. Link Startup Time

POWERED UP, SERIAL

REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL REVERSE CONTROL

Figure 11. Power-Up Delay

tHOLD tSET tHC

Figure 12. Input I2S Timing Parameters

Table 1. Power-Up Default Register Map (see Table 12)

SS = 000 (SSEN = low), SS = 001 (SSEN = high), spread-spectrum settings depend on

AUTOFM = 00, calibrate spread-modulation rate only once after locking

Table 1. Power-Up Default Register Map (see Table 12) (continued)

I2CMETHOD = 0, I2C packets include register address

*WITH I2S ENABLED; OTHERWISE CNTL0

Figure 13. LVDS Input Timing

CYCLE N-1 CYCLE N

Figure 14. VESA Standard Panel Clock and Bit Assignment

Figure 15. 3-Channel Mode Serial Link Data Format

LVDS LVDS AUDIO

Figure 16. 4-Channel Mode Serial Link Data Format

Table 3. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies

MASTER WRITES TO SLAVE ACK

MASTER READS FROM SLAVE

READ DATA FRMAT

MASTER WRITES TO SLAVE ACK BYTE 1 BYTE N

MASTER READS FROM SLAVE

Figure 17. GMSL UART Protocol for Base Mode

START D0 D1 D2 D3 D4 D5 D6 D7 PARITY STOP

FRAME 1 FRAME 2 FRAME 3