CHIP DESIGN 1

Juan Valverde, Nanoelectronics MSc. Student. San Francisco de Quito University

MEMORY DEMUX DESIGN
SUMMARY REPORT
Abstract: This paper is going to present the main characteristics of the design and simulation of the Demux Memory on
the course of Chip Design, a part of a simple microprocessor. The designs (layouts) and simulated circuits on Microwind
3.5 are in 45nm technology, next this design will move to 0.18 um. It also contains the analysis of results of speed, delay,
power, power consumption, and an option on three different scenarios like typical case, worst-case (high temperature,
low voltage) and best-case (low temperature, high voltage).

Index Terms—Microwind, chip design, MOS technology, memory demux.

I. INTRODUCTION1 memory sweep form the WL[0] to WL[7].

T HIS document introduces the design and simulation

of a part of a microcontroller in CMOS technology,
on Microwind Software in a very small 45nm technology, Address
TABLE I
BINARY TRUTH TABLE FOR SELECTION CIRCUIT
WL WL WL WL WL WL WL WL
this user friendly program is intuitive and easier to [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
understand by students to learn the basic and advanced 0 0 0 0 0 0 0 0 0 0 1
ways to design, evaluate and validate the device 0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
performance testing the process, voltage, and temperature 0 1 1 0 0 0 0 1 0 0 0
(PVT) testing. 1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
II.SELECTION CIRCUIT 1 1 1 1 0 0 0 0 0 0 0

A. Description
The following figure shows the connections it has with the
This circuit decodes the input address (binary code) to
modules of the clock counter and the program memory.
activate one single row (decimal code). The row decoder
selects one row from 2 N, thanks to an N-bit row selection
address. This circuit is a basic binary to decimal decoder
based on a multiplexor. A single line is always activated
while all other lines are zero.

Fig. 2. Operation within the total design of the small microcontroller.

IV. 3X8 MEMORY DEMUX DESIGN

A. Design Stage
The design was made in Microwind 3.5 in the metal layer 1
and the highest metal 2. The complete design is seen in the
Fig. 1. Row selection circuit [1] and a simple selection circuit following figure which is zoomed to understand its design.

III. 3X8 MEMORY DEMUX BEHAVIOR

The following table summarizes the behavior of the
simple row selection circuit for a memory demux to
understand the impact of the program counter over the

1
J.V. Author is Nanoelectronics MSc. Student at the San Francisco de
Quito University, Quito ECUADOR (e-mail:
[email protected]).
 We can verify the behavior of the circuit looking at the
previous figure and making a comparison with the decimal
truth table

A. Results of PTV Testing

The following tables was extracted from the simulation,
we can see how the measured parameters has been
changing when I change the PTV testing scenarios
(Process, voltage and temperature), the following tables
shows the simulations cases on Microwind 3.5:

TABLE II
TYPICAL CASE SCENARIO (NORMAL) 27°C AND 1VOLT
Input Freq Delay L-H Delay H-L Power
[Mhz] [pS] [pS] [uW]
640 49.4 18.5 3.666

TABLE III
WORST CASE SCENARIO (SLOW) 125°C AND 0.85VOLT
Input Freq Delay L-H Delay H-L Power
[Mhz] [pS] [pS] [uW]
640 91.0 32.4 2.546
Fig. 3. Complete design of the 3x8 Memory Demux
TABLE IV
It is seen that the output WL [0] depends on the connections BEST CASE SCENARIO (FAST) -50°C AND 1.15VOLT
to the inputs of the AND gate of three inputs, so the design Input Freq Delay L-H Delay H-L Power
[Mhz] [pS] [pS] [uW]
of the gate is the same for all the WL excepting its
640 28.9 10.9 5.569
connection to the address bus.

V. SIMULATION STAGE
VI. CONCLUSION
A. Typical case and behavior • Microwind is an exceptional EDA software for
We can watch and analyze how the input counter is learn and student purpose. In the circuit we can
working and its effect over the WL outputs. see the pros and cons of the design, so we must
keep in mind the length and width of the mosfets
Address WL we use depending on the purpose. The design of
0 1 the Memory Demux is essential to read and write
1 2 the Program Memory of the device
2 4
3 8 • The typical frequency of operation given by the
4 16 chef is 640Mhz in which the data of delay, power
5 32 and typical values were analyzed, the maximum
6 64
7 128
frequency at which simulation was done is 2.5Ghz,
with which the problem section was analyzed and
solutions
• The design must have a compromise between the
delay and the device size.
• The design of the Memory Demux must satisfy the
clock frequency and the read and write time of the
memory.
• The Memory access (delay) is often the longest on
a microcontroller.

REFERENCES
Fig. 4. Input and outer voltage for the 3x8 Demux Memory Design. [1] E. Sicard, S. Delmas-Bendhia, “Advanced CMOS cell design”, in
CMOS Circuit Design, Simulator in hands. Ed. Mc Graw Hill, India,
2006.
[2] E. Sicard, S. Delmas-Bendhia, “Arithmetics”, in CMOS Circuit
Design, Simulator in hands. Ed. Mc Graw Hill, India.