1

EE 560
INTRODUCTION

Kenneth R. Laker, University of Pennsylvania

 ORDERING OF TOPICS 2

CMOS
Fabrication

MOS
Transistor
Model

Two Transistor Circuits

(Inverters)

Logic Circuits, Gates, Latches

Regular Structures µPs, Custom Logic

ROMs, RAMs, PLAs VLSI Sub-systems

System-Related Issues, Reliability, Manufacturability, Testability

Kenneth R. Laker, University of Pennsylvania

 3

INFORMATION SERVICE
INDUSTRY TRENDS
Video on
Demand
Speech
Processing/Recognition
Wireless/Cellular Data
Communication
Data Multimedia
Communication Applications
Consumer Portable
Electronics Computers
Mainframe Personal Network
Computers Computers Computers

1970 1980 1990 2000

 4

WHY MONOLITHIC INTEGRATION OF A LARGE

NUMBER OF FUNCTIONS ON A SINGLE CHIP?

• Less die area, compactness

• Less power consumption
• Less testing requirements at the system level
• Higher reliability, due to high quality on chip interconnect
• Higher speed, due to reduced interconnect length
• Significant cost savings
 5
MIMIMUM FEATURE SIZE (µm)
4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5 0.1 µm
0 YEAR
1975 1980 1985 1990 1995 2000
 CLASSIFICATION OF DIGITAL CIRCUIT TYPES 6

DIGITAL
CIRCUITS

STATIC DYNAMIC
CIRCUITS CIRCUITS

CLASSICAL TRANSMISSION CVSL

CMOS GATE CMOS CIRCUITS

DOMINO LOGIC NORA LOGIC TSPC LOGIC

CIRCUITS CIRCUITS CIRCUITS
Kenneth R. Laker, University of Pennsylvania
 MOS TRANSISTORS 7

G G

D
S S D
B B
G G

S D S D

B B

B S G D D G S B

p+ p+ n+ n+
n-well

p -substrate

Kenneth R. Laker, University of Pennsylvania

 8

G G

D
S S D
B B
G G

S D S D

B B

B S G D D G S B

p+ p+ n+ n+
p-well

n -substrate

Kenneth R. Laker, University of Pennsylvania

 9

nMOS and pMOS SWITCH SYMBOLS

AND
IDEAL CHARACTERISTICS
SYMBOLS SWITCH CHARACTERISTICS

Input Output
a a a b 0 a b Srong 0
s=0
N- SWITCH s N s
a b 1 a b Weak 1
b b s=1

Input Output
a a
a b 0 a b Weak 0
s=0
P- SWITCH s P s

a b 1 a b Strong 1
b b s=1
Kenneth R. Laker, University of Pennsylvania
 10

OUTPUT LOGIC LEVELS OF

N- AND P- SWITCHES

LEVEL SYMBOL SWITCH CONDITION

Strong 1 1 P-SWITCH gate = 0, source = VDD
Weak 1 1 N-SWITCH gate = 1, source = VDD

Strong 0 0 N-SWITCH gate = 1, source = VSS

Weak 0 0 P-SWITCH gate = 0, source = VSS

High Impedance Z N-SWITCH gate = 0 or

P-SWITCH gate = 1

Kenneth R. Laker, University of Pennsylvania

 11

COMPLEMENTARY CMOS SWITCH

SYMBOLS
-s SWITCH CHARACTERISTICS

a C b a b
Input Output
s s 0 a b Srong 0
-s -s
1 a b Strong 1

a b a b

s s

Kenneth R. Laker, University of Pennsylvania

 12

INVERTER TRUTH TABLE

INPUT OUTPUT
0 1
1 0

1 (V DD) input output

P
input output

N input output

0 (V SS )

Kenneth R. Laker, University of Pennsylvania

 13

1 (V DD)

P
input output
N

0 (V SS)

RESOLUTION OF GATE OUTPUT LEVELS

Pull-Down Pull-Up Combined
Output Output Output
0 Z 0
Z 1 1
Z Z Z
0 1 CROSSBARRED

Kenneth R. Laker, University of Pennsylvania

 14
CONNECTION & BEHAVIOR OF SERIES N- AND P- SWITCHES

s1 = 0 s1 = 0 s1 = 1 s1 = 1
a s2 = 0 s2 = 1 s2 = 0 s2 = 1
a a a a F s1
s1 N 0 1
0 off off
s2
s2 N
1 off on
b
b b b b

s1 = 0 s1 = 0 s1 = 1 s1 = 1
a s2 = 0 s2 = 1 s2 = 0 s2 = 1
a a a a F s1
s1 P 0 1
0 on off
s2
s2 P
1 off off
b
b b b b

Kenneth R. Laker, University of Pennsylvania

 15

CONNECTION & BEHAVIOR OF PARALLEL N- AND P- SWITCHES

a s1 = 0 s1 = 0 s1 = 1 s1 = 1
s2 = 0 s2 = 1 s2 = 0 s2 = 1
F s1
a a a a 0 1
0 off on
s1 N N s2 s2

1 on on

b b b b b

a s1 = 0 s1 = 0 s1 = 1 s1 = 1
s2 = 0 s2 = 1 s2 = 0 s2 = 1
F s1
a a a a 0 1
s1 P P s2 0 on on
s2

1 on off
b b b b b

Kenneth R. Laker, University of Pennsylvania

 2-INPUT CMOS NAND GATE 16

(A + B) A
P P out 0 1
0 1 1 OR

output B
A N
1 1 0
B
N
(A•B)
0
2-INPUT CMOS NAND GATE TRUTH TABLE

OUTPUT A-INPUT
0 1
U U
0 1 D 1 D
output
A Z Z
B-INPUT
U U

B 1 1 D Z D
Z 0

Kenneth R. Laker, University of Pennsylvania

 17

2-INPUT CMOS NOR GATE

NAND 1

P P

OUT
A N

B
N
1
0
P
(A•B)
B
A
A P out 0 1
output 0 1 0 OR
B
N N
1 0 0
0 (A + B)

Kenneth R. Laker, University of Pennsylvania

 COMPOUND GATES 18

F = ((A•B) + (C•D))
N - Half
F = ((A•B) + (C•D))
A N N C A N N C

B N N D B N N D
P - Half

F = ((A+B) • (C+D))

A P P B C P P D A P P B

C P P D

Kenneth R. Laker, University of Pennsylvania

 19

F = ((A•B) + (C•D))

A P P B

C P P D

A N N C

B N N D

Kenneth R. Laker, University of Pennsylvania

 2-INPUT MULTIPLEXER 20

-s

A C
A
B 0
s s output
output output 1s
A
B C B
s
-s
-s

A B s -s output
x 0 0 1 0 (B)
output = A.s + B .s
x 1 0 1 1 (B)
0 x 1 0 0 (A)
1 x 1 0 1 (A)

Key components in CMOS memory elements and data manipulation structures.

Kenneth R. Laker, University of Pennsylvania

 CIRCUIT AND SYSTEM REPRESENTATIONS 21

COMPLEX DIGITAL SYSTEM can be SUCCESSIVELY SUB-DIVIDED in a HIERARCHIAL

manner.
Highly automated techniques exist for converting HIGH LEVEL DESCRIPTIONS OF SYSTEM
BEHVIOR to a detailed implementation prescription to fabricate a CHIP.

To do this, a set of ABSTRACTIONS have been developed to describe integrated electronic

systems.
Designs are represented in THREE distinct DOMAINS:

1. Behavioral: what does the system do?

2. Structural: how are the elements connected together?
3. Physical: how is the structure to be built?
Each DESIGN DOMAIN can be specified at a variety of LEVELS of ABSTRACTION
- Architectural Higher Level
- Algorithmic
- Module or Functional Block
- Logical
- Switch
Lower Level
- Circuit
Kenneth R. Laker, University of Pennsylvania
 22
Behavioral Domain
Structural Domain
Applications
Operating Systems PC
RISC Procesor
Programs

Adder, gates, registers

Subroutines

Instructions
Circuit
Abstraction Transistors
Level Logic Abstraction
Transistors Level

Cells

Arcitectural Level

Modules

Chips, Boards, Boxes

Physical Domain
Kenneth R. Laker, University of Pennsylvania
 23

BEHAVIORAL REPRESNTATION

Behavior may be specified by:

1. Boolean expressions
2. Tables of input/output values
3. Algoritythms written in high level computer languages
4. Algoritythms written in Harware Description Languages (HDLs)
e.g. VHDL, Verilog
highest level lowest level
Algorithym -> Registers and communications -> ..... -> Boolean expressions

GOAL OF MODERN DESIGN SYSTEMS:

Convert spec at HIGHEST LEVEL possible into a system design in MINIMUM TIME
and with MAXIMUM LIKLIHOOD that the design will PERFORM AS DESIRED.

Kenneth R. Laker, University of Pennsylvania

 24

Example 1-1: pp 10
Design a one-bit binary adder circuit using 1 µm n-well CMOS
technology. The specificaions are:
1. Propogation Delay Times of SUM & CARRY_OUT signals: < 1.2 ns
2. Transition Delay Times of SUM & CARRY_OUT signals: < 1.2 ns
3. Circuit Die Area: < 1500 µm2
4. Dynamic Power Dissipation (@ VDD = 5 V and fmax = 20 MHz): < 1 mW

Kenneth R. Laker, University of Pennsylvania

 System Requirements 25

Architecture Definition and

Logic Design
Logic Diagram/Description
Technology
VLSI Design and Layout Design Rules
Device Models

Design Rule Check

FAIL Design Verification
Circuit Sim (SPICE)
PASS
Mask Generation

Silicon Processing

Wafer Testing, Packaging, Reliability Qualification

Kenneth R. Laker, University of Pennsylvania
 26

START: Boolean description of binary adder circuit:

A B C sum_out carry_out
A sum_out
FULL 0 0 0 0 0
B ADDER carry_out 0 0 1 1 0
C 0 1 0 1 0
DEFINE: 0 1 1 0 1
Input Variables: 1 0 0 1 0
addends: A, B 1 0 1 0 1
carry-in: C 1 1 0 0 1
Output Variables: 1 1 1 1 1
sum_out, carry_out

BOOLEAN FUNCTION:

sum_out = A + B + C = ABC + ABC + ABC + ACB

carry_out = AB + AC + BC
Kenneth R. Laker, University of Pennsylvania
 BOOLEAN FUNCTION: 27

SUM_OUT = A + B + C = ABC + ABC + ABC + ACB

CARRY_OUT = AB + AC + BC
A
B
C carry_out

A
B
C

sum_out

SUM_OUT= ABC + (A + B + C) CARRY_OUT

(use of carry_out to realize sum_out reduces circuit complexity
and chip area)
GATE LEVEL SCHEMATIC OF ONE-BIT FULL
ADDER CIRCUIT
Kenneth R. Laker, University of Pennsylvania
 A
28
B carry_out
C

A
B
C
sum_out

VDD
A B A B C

A carry_out
A

B VDD
B C

C
C A sum
_out
A
A
B B
B
A B C

TRANSISTOR LEVEL C
SCHEMATIC Kenneth R. Laker, University of Pennsylvania
 A B C VDD 29
A B
A carry_out
A
VDD
B C B
C sum_out
C A

A A
B B
A B C B
C
COLOR LEGEND
VDD VDD
n-Well
p-Well
n+
S_O C_O
Poly
p+ A
Gate Oxide B
Field Oxide
Metal 1 C
Metal 2
Metal 3
Contact/via
GND GND
Kenneth R. Laker, University of Pennsylvania
 A B C VDD 30
A B
A carry_out
A
VDD
B C B
C sum_out
C A

A A
B B
A B C B
C

Aternative schematic with nMOS and pMOS nets symmetrical

V DD
A B A B C A
B carry_out B
C VDD
A C
C sum_out
A

A A
B B
A B C B

Layout with W/L = 2 µm/0.8 µm C

Area 21 µm x 54 µm = 1134 µm2

 31

Layout with W/L = 2 µm/0.8 µm

Voltage (V)
A = 0, B = 1

5.0 C (carry_in)
SUM tPLH < 5 ns
tPLH
3.0
tPLH = 2 ns > 1.2 ns

1.0
tPHL

-1.0
20 22 24 26 28 30

Modified Layout Required

1. Increase W/L's of transistors
2. Consider more compact placement of transistors and reduce
interconnect in critcal paths

Kenneth R. Laker, University of Pennsylvania

 System Requirements 32

Architecture Definition and

Logic Design
Logic Diagram/Description
Technology
VLSI Design and Layout Design Rules
Device Models

Design Rule Check

FAIL Design Verification
Circuit Sim (SPICE)
PASS
Mask Generation

Silicon Processing

Wafer Testing, Packaging, Reliability Qualification

Kenneth R. Laker, University of Pennsylvania