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    Workshop Week 12 PDF

    Uploaded by

    Josue David Hernandez Viloria

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Workshop Week 12 PDF

    Uploaded by

    Josue David Hernandez Viloria
    19 views1 page

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    Workshop Week 12.pdf

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    19 views1 page

    Workshop Week 12 PDF

    Uploaded by

    Josue David Hernandez Viloria

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
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    Workshop Week 12.

    Problem # 1

    A computer system uses 16-bit memory addresses. It has a 2K-byte cache organized in a
    direct-mapped manner with 64 bytes per cache block. Assume that the size of each memory
    word is 1 byte.
    (a) Calculate the number of bits in each of the Tag, Block, and Word fields of the
    memory address.
    (b) When a program is executed, the processor reads data sequentially from the
    following word addresses:

    128, 144, 2178, 2182, 130, 2176

    All the above addresses are shown in decimal values. Assume that the cache is initially empty.
    For each of the above addresses, indicate whether the cache access will result in a hit or a
    miss. In case of a miss, indicate if it is a compulsory, capacity or conflict miss.

    Problem # 2

    Repeat Problem # 1, if the cache is organized as a 2-way set-associative cache that uses the
    LRU replacement algorithm.

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