Signals & Systems (Common To Ec/Tc/It/Bm/Ml)

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SIGNALS & SYSTEMS (Common to EC/TC/IT/BM/ML)

Sub Code : 06EC44 IA 25


Mark
s
Hrs/ Week : 04 Exam 03
Hours
Total Hrs. : 52 Exam 100
Mark
s

PART – A
UNIT 1:
Introduction: Definitions of a signal and a system, classification of signals, basic Operations on
signals, elementary signals, Systems viewed as Interconnections of operations, properties of
systems.
7 Hours
UNIT 2:
Time-domain representations for LTI systems – 1: Convolution, impulse response representation,
Convolution Sum and Convolution Integral.
6 Hours
UNIT 3:
Time-domain representations for LTI systems – 2: properties of impulse response representation,
Differential and difference equation Representations, Block diagram
representations.
7 Hours
UNIT 4:
Fourier representation for signals – 1: Introduction, Discrete time and continuous time Fourier series
(derivation of series excluded) and their properties .
6 Hours
PART – B
UNIT 5:
Fourier representation for signals – 2: Discrete and continuous Fourier transforms(derivations of
transforms are excluded) and their properties.
6 Hours
UNIT 6:
Applications of Fourier representations: Introduction, Frequency response of LTI systems, Fourier
transform representation of periodic signals, Fourier transform representation of discrete time
signals
7 Hours
UNIT 7:
Z-Transforms – 1: Introduction, Z – transform, properties of ROC, properties of Z – transforms,
inversion of Z – transforms.

07 Hours
UNIT 8:
Z-transforms – 2: Transform analysis of LTI Systems, unilateral Z- Transform and its application to
solve difference equations.
06 Hours

TEXT BOOK
Simon Haykin and Barry Van Veen “Signals and Systems”, John Wiley & Sons, 2001.Reprint 2002

REFERENCE BOOKS:
1. Alan V Oppenheim, Alan S, Willsky and A Hamid Nawab, “Signals and Systems” Pearson
Education Asia / PHI, 2nd edition, 1997. Indian Reprint 2002
2. H. P Hsu, R. Ranjan, “Signals and Systems”, Scham’s outlines, TMH, 2006
3. B. P. Lathi, “Linear Systems and Signals”, Oxford University Press, 2005
4. Ganesh Rao and Satish Tunga, “Signals and Systems”, Sanguine Technical Publishers, 2004
Question Paper Pattern: Student should answer FIVE full questions out of 8 questions to be set each
carrying 20 marks, selecting at least TWO questions from each part
Coverage in the Text:
UNIT 1: 1.1, 1.2, 1.4 to 1.8
UNIT 2: 2.1, 2.2
UNIT 3: 2.3, 2.4, 2.5
UNIT 4: 3.1, 3.2, 3.3, 3.6
UNIT 5: 3.4, 3.5, 3.6
UNIT 6: 4.1, 4.2, 4.3, 4.5, 4.6.
UNIT 7: 7.1, 7.2, 7.3, 7.4, 7.5
UNIT 8: 7.6 (Excluding ‘relating the transfer function and the State-Variable description, determining the
frequency response from poles and zeros) and 7.8
FUNDAMENTALS OF HDL (Common to EC/TC/IT/BM/ML)

Sub Code : 06EC45 IA 25


Mar
ks
Hrs/ : 04 Exa 03
Week m
PART-A Hou
UNIT 1: rs
Total Hrs. : 52 Exa 100
m
Mar
ks

Introduction: Why HDL? , A Brief History of HDL, Structure of HDL Module,


Operators, Data types, Types of Descriptions, simulation and synthesis, Brief
comparison of VHDL and
Verilog

6 Hours
UNIT 2:
Data –Flow Descriptions: Highlights of Data-Flow Descriptions, Structure of
Data-Flow Description, Data Type–vectors

6 Hours

UNIT 3:
Behavioral Descriptions: Behavioral Description highlights, structure of HDL
behavioral Description, The VHDL variable –Assignment Statement, sequential
statements.

7 Hours
UNIT 4:
Structural Descriptions: Highlights of structural Description, Organization of the
structural Descriptions, Binding, state Machines, Generate, Generic, and
Parameter
statements.

7 Hours
PART-B

UNIT 5: Procedures, Tasks, and Functions: Highlights of Procedures, tasks,


and Functions, Procedures and tasks, Functions.
Advanced HDL Descriptions: File Processing, Examples of File Processing
7 Hours

UNIT 6:
Mixed –Type Descriptions: Why Mixed-Type Description? VHDL User-Defined
Types, VHDL Packages, Mixed-Type Description examples
6 Hours

UNIT 7:
Mixed –Language Descriptions: Highlights of Mixed-Language Description, How
to invoke One language from the Other, Mixed-language Description Examples,
Limitations of Mixed-Language
Description
7 Hours
UNIT 8:
Synthesis Basics: Highlights of Synthesis, Synthesis information from Entity and
Module, Mapping Process and Always in the Hardware
Domain.
6 Hours

TEXT BOOKS:
1. HDL Programming (VHDL and Verilog)- Nazeih M.Botros- Dreamtech Press
2. (Available through John Wiley – India and Thomson Learning) 2006 Edition

REFERENCE BOOKS:
1. Verilog HDL –Samir Palnitkar-Pearson Education
2. VHDL -Douglas perry-Tata McGraw-Hill
3. A Verilog HDL Primer- J.Bhaskar – BS Publications
4. Circuit Design with VHDL-Volnei A.Pedroni-PHI

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