VLSI
VLSI
VLSI
Answer: c
Explanation: nMOS devices are formed in a p-type substrate of moderate doping level. nMOS
devices have higher mobility and is cheaper.
Answer: b
Explanation: The source and drain regions are formed by diffusing n-type impurity, it gives rise
to depletion region which extend in more lightly doped p-region. Thus Source and drain in a
nMOS device are isolated by two diodes.
Answer: b
Explanation: In depletion mode, source and drain are connected by conducting channel but the
channel can be closed by applying suitable negative voltage to the gate.
Answer: b
Explanation: In enhancement mode, the decive is in non conducting condition. For n-type FET,
thershold voltage is positive and p-type threshold voltage is negative.
Answer: d
Explanation: In enhancement mode the device is in non conducting mode, and its condition is
Vds = Vgs = Vs = 0.
7. nMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: nMOS transistors are acceptor doped. Acceptor is a dopant which when added
forms p-type region. Some of the accpetors are silicon, boron, aluminium etc.
9.. pMOS is
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor doped forms
p-type region and donor doped forms n-type region.
Answer: b
Explanation: Inversion layer in enhancement mode consists of excess of negative carriers that is
electron.
Answer: b
Explanation: The condition for linear region is Vgs > Vt. The power of MOS in linear region is
less. It is a power dissipating region.
Answer: b
Explanation: As source drain voltage Vds increases, the channel depth at the drain end decreases.
13. Speed power product is measured as the product of
a) gate switching delay and gate power dissipation
b) gate switching delay and gate power absorption
c) gate switching delay and net gate power
d) gate power dissipation and absorption
Answer: a
Explanation: Speed power product is measure in picojoules and it is the product of gate
switching delay and gate power dissipation.
MOS TRANSISTORS
Answer: d
Explanation: MOS transistors is formed as a sandwich consisting of a semiconductor layer, a
silicon-di-oxide layer and a metal layer.
Answer: c
Explanation: In MOS transistors, polycrystalline silicon is used for their gate region instead of
metal. Polysilicon gates have replaced all other older devices.
Answer: a
Explanation: Electrical charge or current flows from source to drain depending on the charge
applied to the gate region.
Answer: a
Explanation: Source and drain in the MOS transistors are doped with N-type material and
substrate is doped with p-type material.
Answer: a
Explanation: In N channel MOSFET, source is the more negative of the elements and in the case
of P channel MOSFET, it is the more positive of the elements.
Answer: a
Explanation: Enhancement mode transistor acts as open switch whereas depletion mode transistor acts
as normally closed switch.
Answer: b
Explanation: Depletion mode MOSFETs are more commonly used as resistors than as switches.
As permanently on switch it has high resistance.
Answer: a
Explanation: Enhancement mode MOSFETs are more commonly used as switches and depletion mode
devices are more used as resistors.
Answer: a
Explanation: Depletion mode transistors should be made large that is long and thin to create the
large „on‟ resistance.
12. Which expression is true?
a) charging time < discharging time
b) charging time > discharging time
c) charging time = discharging time
d) charging time and discharging time are not related
Answer: b
Explanation: When driving a capacitive output load, charging time will be long compared to the
discharging time.
13. Overheating in device occurs due to less number of resistors per unit area.
a) true
b) false
Answer: b
Explanation: When the number of resistors per unit area increases, the device may not dissipate
heat very well. This results in device overheating which leads to its failure.
Answer: a
Explanation: In all n channel MOSFET transistors, channel length is constant where as channel
width can be varied.
VLSI Design
Answer: a
Explanation: Very-large scale integration is the process of creating integrated circuit with
thousands of transistors into one single chip.
2. Medium scale integration has
a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates
Answer: c
Explanation: Small scale integration has one or more logic gate. Further improved technology is
medium scale integration which consists of hundred logic gates. Large scale integration has
thousand logic gates.
Answer: b
Explanation: As photolithography comes closer to fundamental law of optics, achieving high
accuracy in doping concentration becomes difficult, which leads to error due to variation.
Answer: d
Explanation: Designers must simulate multiple fabrication process or use system level technique
for dealing with effects of variation.
Answer: a
Explanation: As the die size shrinks due to scaling, the number of die per wafer increases and the
complexity of making the photomasks increases rapidly.
6. architecture is used to design VLSI
a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit
Answer: c
Explanation: SoC that is system on a chip architecture is used to design the very high level
integrated circuit.
Answer: a
Explanation: The order of the design flow of VLSI circuit is market requirement, architecture
design, logic design, HDL coding and then verification.
Answer: b
Explanation: First in first out (FIFO) technique and finite state machine technique is used in
the logic design of the VLSI circuits.
Answer: c
Explanation: Transistor-transistor logic offers higher integration density and it became the first
integrated circuit revolution.
10. Physical and electrical specification is given in
a) architectural design
b) logic design
c) system design
d) functional design
Answer: d
Explanation: Functional design defines the major functional units of the system,
interconnections, physical and electrical specifications.
Answer: a
Explanation: Problem statement is a high level representation of the system. Performance,
functionality and physical dimensions are considered here.
Answer: a
Explanation: Gate minimization technique is used to find the simplest, smallest and effective
implementation of the logic.
NMOS Fabrication
1. nMOS fabrication process is carried out in
a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals
Answer: a
Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high
purity.
2. impurities are added to the wafer of the crystal
a) n impurities
b) p impurities
c) siicon
d) crystal
Answer: b
Explanation: p impurities are introduced as the crystal is grown. This increases the hole
concentration in the device.
Answer: a
Explanation: Above a layer of silicon dioxide which acts as barrier, insulating layer is provided
upon which other layers may be deposited and patterned.
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where
diffusion is to take place.
Answer: b
Explanation: In nMOS device, the gate material could be metal or polysilicon. This polysilicon
layer has heavily doped polysilicon deposited by CVD.
Answer: c
Explanation: In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-
on-sapphire.
Answer: a
Explanation: In nMOS fabrication, etching is done using hydroflouric acid or plasma. Etching is
a process used to remove layers from the surface.
Answer: b
Explanation: The polysilicon layer consists of heavily doped polysilicon deposited by chemical
vapour deposition.
Answer: a
Explanation: Diffusion is carried out by heating the wafer to high temperature and passing a gas
containing the desired ntype impurity.
Answer: c
Explanation: The metal layer is masked and etched to form interconnection pattern. The metal
layer was formed using aluminium deposited over the formed surface.
Answer: a
Explanation: SIlicon-di-oxide is a very good insulator so a very thin layer is required in the
fabrication of MOS transistor.
Answer: b
Explanation: Boron is used to suppress the unwanted conduction between transistor sites. It is
implanted in the exposed regions.
Answer: c
Explanation: Aluminium is the suitable material used for the circuit interconnection or
connecting two layers.
CMOS Fabrication
Answer: d
Explanation: CMOS technology is used in developing microcontrollers, microprocessors, digital
logic circuits and other integrated circuits.
2. CMOS has
a) high noise margin
b) high packing density
c) high power dissipation
d) high complexity
Answer: b
Explanation: Some of the properties of CMOS are that it has low power dissipation, high packing
density and low noise margin.
Answer: a
Explanation: In CMOS fabrication, nMOS and pMOS are integrated in the same chip substrate.
n-type and p-type devices are formed in the same structure.
4. P-well is created on
a) p subtrate
b) n substrate
c) p & n substrate
d) none of the mentioned
Answer: b
Explanation: P-well is created on n substrate to accommodate n-type devices whereas p-type
devices are formed in the ntype substrate.
5. Oxidation process is carried out using
a) hydrogen
b) low purity oxygen
c) sulphur
d) nitrogen
Answer: a
Explanation: Oxidation process is carried out using high purity oxygen and hydrogen. Oxidation
is a process of oxidizing or being oxidised.
Answer: b
Explanation: Light sensitive polymer is used to form the photoresist layer. Photoresist is a light
sensitive material used to form patterned coating on a surface.
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where
diffusion is to take place.
Answer: a
Explanation: Few parts of photoresist layer is removed by treating the wafer with basic or acidic
solution. Acidic solutions are those which have pH less than 7 and basic solutions have greater
than 7.
9. P-well doping concentration and depth will affect the
a) threshold voltage
b) Vss
c) Vdd
d) Vgs
Answer: a
Explanation: Diffusion should be carried out very carefully, as doping concentration and depth
will affect both threshold voltage and breakdown voltage.
Answer: b
Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of lower
substrate bias effect.
Answer: b
Explanation: N-well is formed by using ion implatation or diffusion. Ion implantation is a
process by which ions of a material are accelerated in an electrical field and impacted into a
solid. Diffusion is a process in which net movement of ions or molecules play a major role.
Answer: d
Explanation: Aluminium is sputtered on the whole waffer before removing the excess metal from
the wafer.
1. MOS technology has more load driving capability.
a) true
b) false
Answer: b
Explanation: One of the disadvantage of MOS technology is it has limited load driving
capabilities.
Answer: a
Explanation: MOS devices have limited current sourcing and current sinking abilities.
Answer: d
Explanation: BiCMOS provides higher gain, better noise and high frequency characteristics than
MOS transistors.
Answer: a
Explanation: Some of the features of BiCMOS are low input impedance, low packing density,
unidirectional, high output drive current etc.
6. CMOS is
a) unidirectional
b) bidirectional
c) directional
d) none of the mentioned
Answer: a
Explanation: BiCMOS is unidirectional and CMOS is bidirectional.
Answer: b
Explanation: The quality of bipolar transistor can be improved by reducing the collector
resistance, which can be done by using the additional layer of n+ subcollector.
Answer: b
Explanation: BiCMOS is more advantageous and improved than CMOS and it can be used in I/O
and driver circuits.
Answer: a
Explanation: The advantages of E-beam masks are it has tighter layer to layer registration and it
has smaller feature sizes.
10. Which process is used in E-beam machines?
a) raster scanning
b) vector scanning
c) both of the mentioned
d) none of the mentioned
Answer: c
Explanation: The two approaches to the design of E-beam machines are raster scanning and
vector scanning.
Answer: a
Explanation: Vector scanning is faster but data handling involved is more complex. Vector
scanning is done between the end points.
Answer: b
Explanation: CMOS technology has high input resistance and is best for constructing simple
low-power logic gates.
Answer: b
Explanation: BiCMOS has potential for high standby leakage current and has high power
consumption compared to CMOS.
VLSI Questions and Answers – NMOS and
CMOS Fabrication
1. Lithography is:
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip
Answer: a
Explanation: Lithography is the process used to develop a pattern to a layer on the chip.
Answer: b
Explanation: Silicon oxide is patterned on a substrate using Photolithography.
3. Positive photo resists are used more than negative photo resists because:
a) Negative photo resists are more sensitive to light, but their photo lithographic resolution
is not as high as that of the positive photo resists
b) Positive photo resists are more sensitive to light, but their photo lithographic resolution
is not as high as that of the negative photo resists
c) Negative photo resists are less sensitive to light
d) Positive photo resists are less sensitive to light
Answer: a
Explanation: Negative photo resists are more sensitive to light, but their photo lithographic
resolution is not as high as that of the positive photo resists. Therefore, negative photo resists
are-used less commonly in the manufacturing of high-density integrated circuits.
Answer: c
Explanation: To create isolated active areas both the techniques can be used. Among them Local
Oxidation of Silicon(LOCOS) is most efficient.
6. The chemical used for shielding the active areas to achieve selective oxide growth is:
a) Silver Nitride
b) Silicon Nitride
c) Hydrofluoric acid
d) Polysilicon
Answer: b
Explanation: Selective oxide growth is achieved by shielding the active areas. Silicon nitride
(Si3N4) is used for shielding the active areas during oxidation, which effectively inhibits oxide
growth.
Answer: d
Explanation: Two ways to add dopants are diffusion and ion implantation.
8. To grow the polysilicon gate layer, the chemical used for chemical vapour deposition is:
a) Silicon Nitride(Si4N3)
b) Silane gas(SiH4 )
c) Silicon oxide
d) None of the mentioned
Answer: b
Explanation: Silicon Wafer is placed in a reactor with silane gas (SiH4), and they are heated
again to grow the polysilicon layer by chemical vapor deposition.
9. The process by which Aluminium is grown over the entire wafer , also filling the contact cuts
is:
a) Sputtering
b) Chemical vapour deposition
c) Epitaxial growth
d) Ion Implantation
Answer: a
Explanation: Aluminum is sputtered over the entire wafer, it also fills the contact cuts.
Answer: b
Explanation: The pad oxide and nitride are removed using a Chemical Mechanical Polishing
(CMP) step.
Answer: a
Explanation:Current processes seldom use a pure SiO2 gate oxide, but prefer to produce a stack
that consists of a few atomic layers, each 3–4 Å thick, of SiO2 for reliability, overlaid with a few
layers of oxy-nitrided oxide (one with nitrogen added).
1. Ids depends on
a) Vg
b) Vds
c) Vdd
d) Vss
Answer: b
Explanation: Ids depends on both Vgs and Vds. The charge induced is dependent on gate to
source voltage Vgs also charge can be moved from source to drain under influence of electric
field created by Vds.
Answer: b
Explanation: Ids can be given as charge induced in the channel(Qc) divided by transit time (Ʈ ).
Ids is equivalent to (-Isd).
Answer: a
Explanation: Transit time (Ʈ ) can be given by lenght of channel(L) by velocity(v). Transit time is
the time required for an electron to travel between two electrodes.
4. Velocity can be given as
a) µ / Vds
b) µ / Eds
c) µ x Eds
d) Eds / µ
Answer: b
Explanation: Velocity can be given as the product of electron or hole mobility(µ) and electric
field(Eds). It gives the flow velocity which an electron attains due to electric field.
5. Eds is given by
a) Vds / L
b) L / Vds
c) Vds x L
d) Vdd / L
Answer: a
Explanation: Electric field(Eds) can be given as the ratio of Vds and L. Eds is the electric field
created from drain to source due to volta Vds.
Answer: c
Explanation: The value of mobility of proton or hole at room temperature is 240 cm2/V sec. This
gives the measure of how fast an electron can move.
7. In resistive region
a) Vds greater than (Vgs – Vt)
b) Vds lesser than (Vgs – Vt)
c) Vgs greater than (Vds – Vt)
d) Vgs lesser than (Vds – Vt)
Answer: b
Explanation: In non saturated or resistive region, Vds lesser than Vgs – Vt where Vds is the
voltage between drain and source, Vgs is the gate-source voltage and Vt is the threshold voltage.
Answer: b
Explanation: The condition for saturation is Vds = Vgs – Vt, since at this point IR drop in the
channel equals the effective gate to channel voltage at the drain.
Answer: a
Explanation: The threshold voltage for nMOS depletion denoted as Vtd is negative.
Answer: c
Explanation: The current Ids remains fairly constant as Vds increases in the saturation region.
Answer: a
Explanation: In linear region of MOSFET, the channel is uniform and narrow. This is the
concentration distribution.
Answer: c
Explanation: In MOSFET, in saturation region, when Vds > (Vgs – Vth), the channel pinches off
that is the channel current at the drain spreads out.
Answer: b
Explanation: Increasing the threshold voltage, leads to small leakage current when turned off and
reduces current flow when turned on.
Answer: a
Explanation: MOSFET is used as current source. Bipolar junction transistor also acts as good
current source.
Answer: c
Explanation: The work function difference between gate and Si (Φms) is negative for silicon
substrate and polysilicon gate.
2. Substrate bias voltage is positive for nMOS.
a) true
b) false
Answer: b
Explanation: Substrate bias voltage Vsb is positive for pMOS and negative for nMOS.
Answer: a
Explanation: According to body effect, substrate is biased with respect to the source. Body effect
can be seen as a change in the threshold voltage.
Answer: c
Explanation: Increasing the substrate bias voltage Vsb, increases the threshold voltage because it
depletes the channel of charge carriers.
Answer: b
Explanation: Transconductance expresses the relationship between output current Ids and input
voltage Vgs.
Answer: b
Explanation: Transconductance gm of a MOS device can be increased by increasing its width
and it does not depend on length.
Answer: a
Explanation: Increasing the transconductance gm results in increase in input capacitance and area
occupied as it is directly proportional.
Answer: b
Explanation: Ids is inversely proportional to the length L of the channel and using this
relationship strong dependence of output conductance on channel length can be demonstrated.
Answer: d
Explanation: Switching speed of a MOS device depends on gate voltage above threshold and on
carrier mobility and inversely as the square of channel length.
Answer: b
Explanation: Surface mobility is dependent on the effective gate voltage (Vgs-Vt). Electron
mobility on oriented n-type inversion layer surface is larger than that on a oriented surface.
Answer: b
Explanation: MOS transistor is a majority carrier device,in which current in a conducting
channel between the source and drain is modulated by a voltage.
Answer: c
Explanation: The MOS transistor normally is at cut-off or becomes non-conducting with zero
gate bias (gate voltage-source voltage).
nMOS Inverter
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “nMOS Inverter”.
Answer: d
Explanation: Inverters are needed for restoring logic levels for NAND and NOR gates, sequential
and memory circuits.
Answer: a
Explanation: A basic inverter circuit consists of transistor with source connected to ground and a
load resistor connected from drain to positive supply rail Vdd.
Answer: b
Explanation: Depletion mode transistors are preferred to be used as load in inverter circuits as it
occupies lesser area and are produced on silicon sibstrate unlike resistors.
Answer: a
Explanation: For the depletion mode transistor, gate is connected to source so it is always on and
only the characteristic curve Vgs=0 is relevant.
Answer: a
Explanation: In nMOS inverter configuration, depletion mode devices are called as pull up and
enhancement mode devices are called as pull down transistor.
Answer: b
Explanation: The ratio of Zp.u/Zp.d where Z is determined by the length to width ratio of the
transistor, is given by 4/1.
Answer: a
Explanation: Pass transistors are transistor used as switches in series with lines carrying logic
levels due to its isolated nature of the gate.
9. An inverter driven through one or more pass transistors has Zp.u/Zp.d ratio of
a) 1/4
b) 4/1
c) 1/8
d) 8/1
Answer: d
Explanation: An inverter driven directly from output of another has the ratio of 4/1 and if driven
through one or more pass transistors has the ratio of 8/1.
10. In depletion mode pull-up, dissipation is high since current flows when
a) Vin = 1
b) Vin = 0
c) Vout = 1
d) Vout = 0
Answer: a
Explanation: In nMOS depletion mode pull-up, dissipation is high since current flows Vin =
logical 1.
Answer: c
Explanation: In complementary transistor pull-up no current flows either for logical 1 or 0, full
logical 1 and 0 levels are presented at the output.
CMOS Inverter
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “CMOS Inverter”.
Answer: d
Explanation: CMOS inverter has five distint regions of operation which can be determined by
plotting CMOS inverter current versus Vin.
2. If n-transistor conducts and has large voltage between source and drain, then it is said to be in
region
a) linear
b) saturation
c) non saturation
d) cut-off
Answer: b
Explanation: If n-transistor conducts and has large voltage between source and drain, then it is in
saturation.
3. If p-transistor is conducting and has small voltage between source and drain, then the it is said
to work in
a) linear region
b) saturation region
c) non saturation resistive region
d) cut-off region
Answer: c
Explanation: If p-transistor is conducting and has small voltage between source and drain, then it
is said to be in unsaturated resistive region.
4. In the region where inverter exhibits gain, the two transistors are in _ region
a) linear
b) cut-off
c) non saturation
d) saturation
Answer: d
Explanation: In the region where the inverter exhibits gain, the two transistors n and p operates
in saturation region.
Answer: a
Explanation: When both the transistors are in saturation, then act as current sources so that the
equivalent circuit is two current sources between Vdd and Vss.
Answer: d
Explanation: If βn = βp, then Vin = 0.5Vdd which implies that the changeover between logic
levels is symmetrically disposed about the point.
7. Mobility depends on
a) transverse electric field
b) Vg
c) Vdd
d) Channel length
Answer: a
Explanation: Mobility is affected by transverse electric field and thus also depends on Vgs and
the mobility of p-device and n-device are inherently unequal.
Answer: b
Explanation: In CMOS inverter, transistor is a awitch having finite on resistance and infinite off
resistance.
Answer: a
Explanation: CMOS inverter has low output impedance and this makes it less prone to noise and
disturbance.
Answer: a
Explanation: Input resistance of CMOS inverter is extremely high as it is a perfect insulator and
draws no dc input source.
Answer: a
Explanation: In CMOS inverter, increasing the fan-out also increases the propogation delay. Fan-
out is a term that defines the maximum number of digital inputs that the output of a single logic
gate can feed.
Answer: a
Explanation: Fast gate can be built by keeping the output capacitance small and by decreasing
the on resistance of the transistor.
Answer: b
Explanation: Transconductance gm of a bipolar transistor is given by gm = Ic/(kT/q).
Transconductance is the electrical characteristic relating the current through the output of a
device to the voltage across the input of a device.
Answer: b
Explanation: Transconductance gm is independent of process.
3. gm is on input voltage Vbe
a) inversely proportional
b) proportional
c) exponentially dependent
d) is not dependent
Answer: c
Explanation: Transconductance gm is exponentially dependent on input voltage Vbe ( base to
emitter voltage).
4. gm is to Ic
a) directly proportional
b) inversely proportional
c) not dependent
d) exponentially proportional
Answer: a
Explanation: Transconductance gm is directly proportional to Ic, collector current.
5. Transconductance is a
a) weak function
b) strong function
c) both
d) none of the mentioned
Answer: b
Explanation: Transconductance gm of bipolar is greater than gm of MOS if inputs are controlled
by equal amounts of charge.
7. Which of the following is true when inputs are controlled by equal amounts of charge?
a) Cg(MOS) = Cbase(bipolar)
b) Cg(MOS) greater than Cbase(bipolar)
c) Cg(MOS) lesser than Cbase(bipolar)
d) Cs(MOS) lesser than Cbase(bipolar)
Answer: a
Explanation: Cg(MOS) = Cbase(bipolar) when inputs are controlled by equal amounts of
charge, and then gm(bipolar) >> gm(MOS).
Answer: b
Explanation: Current/Area (I/A) of bipolar is five times better than CMOS and this can be
calculated using base resistance and base transit time.
Answer: d
Explanation: Bipolar transistors exhibits tun-on, turn-off, storage delays.
Answer: b
Explanation: In bipolar transistor, emitter region is heavily doped and base region is lightly
doped.
Answer: b
Explanation: Bipolar transistor is not symmetrical like other transistors.
BiCMOS Inverters
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “BiCMOS
Inverters”.
Answer: b
Explanation: In BiCMOS, bipolar transistors are used to drive output loads. Bipolar transistor
can also be used as amplifier, switch or as an oscillator.
Answer: c
Explanation: In BiCMOS circuits, MOS switches are used to perform logic functions. The ability
to turn the power MOS “ON” and “OFF” allows the device to be used as a very efficient switch
with switching speeds much faster than standard bipolar junction transistors.
Answer: b
Explanation: The nMOS and pMOS transistors used in BiCMOS device operates in enhancement
mode. Enhancement mode devices are mostly common switching elements in MOS.
Answer: a
Explanation: The inverter has low output impedance and low input impedance. These are some
of the properties of a BiCMOS inverter.
Answer: d
Explanation: The inverter has high current driving capability, occupies smaller area and has high
noise margins.
7. Output voltage swing should be reduced for a better performance of BiCMOS circuit.
a) true
b) false
Answer: a
Explanation: BiCMOS inverter needs high load current sinking and sourcing. Sinking provides a
grounded connection to the load, whereas sourcing provides a voltage source to the load.
10. For improved base current discharge, _ enhancement type nMOS devices have to be
added
a) two
b) three
c) one
d) four
Answer: a
Explanation: For improved base current discharge, two enhancement type nMOS transistors have
to be added.
Answer: b
Explanation: In BiCMOS circuit, the BJT transistors are in Totem pole configuration.
Answer: c
Explanation: MOSFETs provide zero static power dissipation and high input impedance.
Latch-up in CMOS
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Latch-up in
CMOS”.
1. In latch-up condition, parasitic component gives rise to conducting path
a) low resistance
b) high resistance
c) low capacitance
d) high capacitance
Answer: a
Explanation: In latch-up condition, parasitic component gives rise to low resistance conducting
path between Vdd and Vss with disastrous results. Carefull control during fabrication is
necessary to avoid this problem.
Answer: a
Explanation: Latch-up can be induced by glitches on the supply rail or by incident radiation.
Answer: a
Explanation: Two transistors and two resistances might bring up the latch-up effect in p-well
structure. These are associated with p-well and with regions of the substrate.
Answer: b
Explanation: An increase in substrate doping level with a consequent drop in the value of Rs can
be used as a remedy for latch-up problem.
Answer: b
Explanation: The introduction of guard rings can reduce the effect of latch-up problem. Guard
rings are diffusions which decouple the parasitic bipolar transistors.
6. Which process produces circuit which are less prone to latch-up effect?
a) CMOS
b) nMOS
c) pMOS
d) BiCMOS
Answer: d
Explanation: BiCMOS process produces circuits which are less likely to suffer from latch-up
problems where as CMOS circuits are very highly prone to latch-up problems.
Answer: b
Explanation: One of the main factor in reducing the latch-up effect is reduced n-well resistance
Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and higher
value of holding current is also required.
Answer: b
Explanation: The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base
region.
Answer: b
Explanation: The parasitic pnp transistor has the effect of reducing carrier lifetime in the n-base
region which results in radiation in beta.
Answer: b
Explanation: To reduce the latch-up effect, substrate resistance Rs should be low. Reduction of
Rs and Rw means that larger lateral current is necessary to invite latch-up.
Answer: a
Explanation: Latch-up is the generation of low-impedance path in CMOS chips between the
power suppply and ground rails.
Answer: a
Explanation: Latch-up occurs due to BJTs for a silicon-controlled rectifiers with positive
feedback and virtually short circuit the power and ground rail.
Answer: b
Explanation: BJT gain should be reduced by lowering the minority carrier lifetime through
doping of the substrate to lower the latch-up effect.
Answer: d
Explanation: These are the 3 advantages of BiCMOS over CMOS.
Answer: c
Explanation: BiCMOS is a combination of both MOSFET and BJT.
Answer: d
Explanation: BJT has the high current driving capability.
Answer: a
Explanation: npn BJTs are used in BiCMOS inverter.
Answer: c
Explanation: The other 2 are the merits of BiCMOS, Increased fabrication Complexity is a
demerit of BiCMOS circuits.
Answer: a
Explanation: BiCMOS is fabricated on the same substrate of nMOS.
Answer: a
Explanation: To make the doping concentration less than the emitter.
9. The collector contact region is doped with higher concentration of n-type impurities due to:
a) It creates a depletion region at the contact surface
b) It creates a low conductivity path between collector region and contact
c) It reduces a contact resistance
d) It can withstand high voltages as compared to collector region
Answer: c
Explanation: The collector contact region is doped with higher concentration of n-type impurities
reduces contact resistance.
Stick Diagram
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Stick Diagram”.
Answer: b
Explanation: Stick diagrams are those which convey layer information through color codes.
Thickness is not considered in this stick diagram representation.
Answer: c
Explanation: Green color is used to show the presence of n-diffusion layer. The n-type diffusion
will dope the source or drain region in the p-well region.
Answer: d
Explanation: Yellow color is used to represent implant layer.
Answer: c
Explanation: Black color is used to represent contact areas. This is the part where two different
touch or cross each other.
Answer: b
Explanation: Red is used to represent polysilicon layers. It is a semi-conductor like material and
is a hyper pure form of silicon.
Answer: d
Explanation: Brown color is used to represent buried contact. Buried contact is most widely
used, subject to fewer design rule restrictions and are smaller in area.
Answer: c
Explanation: Demarcation line separates n and p transistors. Demarcation line is similar to dotted
line in brown.
Answer: b
Explanation: Polysilicon layer should be over n-type layer. This is the standard pattern used in
stick diagram representation.
Answer: d
Explanation: Implant is represented using yellow color dotted lines. It is drawn in the middle of
the nMOS or pMOS whereever the implant is used.
12. Stick diagram gives the position of placement of the element.
a) true
b) false
Answer: b
Explanation: Stick diagram does not show exact placement of components, transistor length,
wire length and width, tub boundaries etc.
13. When two or more cuts of same type cross or touch each other, that represents
a) contact cut
b) electrical contact
c) like contact
d) cross contact
Answer: b
Explanation: When two or more sticks of same type cross or touch each other, then that forms a
contact called electrical contact.
Answer: a
Explanation: Circuit design concepts can be represented using stick diagrams and symbolic
diagrams. Stick diagrams represents different layers with color codes. Symbolic diagram
represents the structure with symbols with color codes.
Answer: c
Explanation: Process engineers wants design rules which are controllable and reproducible
process.
Answer: a
Explanation: Yes, the maturity level of the process line affects design rules.
Answer: d
Explanation: Design rules specify line widths, separations and extensions in terms of lambda.
Answer: c
Explanation: The spacing between two diffusion layers should be 3λ according to design rules
and standards.
Answer: c
Explanation: The width of the metal 1 layer should be 3λ and metal 2 should be 4λ.
Answer: a
Explanation: Implant for a n-mos depletion mode transistor should extend minimum of 2λ from
the channel in all the directions.
Answer: a
Explanation: Buried contacts are much better than butted contacts. In butted contacts the two
layers are joined together or binded together using adhesive type of material where as in buried
contact one layer is interconcted or fitted into another.
Answer: b
Explanation: Micron rules occupies or consumes lesser area. 50% of the area usage can be
reduced by using micron rules over lambda rules.
Answer: a
Explanation: Lambda rules gives scalable design rules and micron rules gives absolute
dimensions.
13. Devices designed with lambda design rules are prone to shorts and opens.
a) true
b) false
Answers: b
Explanation: Lambda design rules prevents shorting, opens, contact from slipping out of area to
be contacted.
Answer: a
Explanation: Diffusion and polysilicon layer are joined together using butting contact. In butting
contact the two layers are joined or binded together.
Answer: a
Explanation: Butting contact is complex process whereas buried contact is simple process
because butting contact should be done more carefully to serve well and be strong.
Answer: a
Explanation: Buried contact occupies smaller area than butting contact as in buried contacts one
layer will be completely within or almost within the another layer.
5. The oxide layer below the first metal layer is deposited using
a) diffusion method
b) chemical vapour deposition
c) solid deposition
d) scattering method
Answer: b
Explanation: The oxide layer below the first metal layer is depostied using chemical vapour
deposition method. This is a chemical process used to produce high quality high performance
solid materials.
Answer: b
Explanation: The minimum feature size for thick oxide is 3λ and minimum separation between
thinox regions is also 3λ.
Answer: a
Explanation: Hatching is compatible with monochrome encoding and also may be added to color
mask coding. It is designed using closely spaced lines or sticks.
Answer: d
Explanation: The minimum spacing between two n-well is 8.5 micro meter according to the
lambda based design rules.
11. Which can bring about variations in threshold voltage?
a) oxide thickness
b) ion implantation
c) poly variations
d) all of the mentioned
Answer: d
Explanation: One of the problem in the manufacture using design rule is that variation in
threshold voltage occurs. And this is caused by oxide thickness, ion implantation and poly
variations.
Answer: d
Explanation: Some of the advantages of generalised design rules are those are durable, scalable,
portable, increases designer efficiency and automatic translation to final layout can be done.
Answer: b
Explanation: Minimum diffusion space is 3λ to avoid the possibility of their associated regions
overlapping and conducting current.
Answer: a
Explanation: Two contact cuts should be 2λ apart to prevent holes from merging.
Sheet Resistance
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Sheet Resistance”.
Answer: a
Explanation: Area A of a uniform slab is given as the product of thickness t and width W of the
slab. Its unit is (micrometer)2.
Answer: a
Explanation: For a 5 micron technology, the Rs value for a metal is 0.03. It is the standard
typical sheet resistance values.
Answer: c
Explanation: For 2 micron technology, the Rs value for polysilicon is 15-30.
Answer: b
Explanation: The Rs values for p-diffusion is 2.5 times greater than that of the n-diffusion.
5. For 1.2 micron technology, the Rs value for diffusion is
a) 20-40
b) 20-45
c) 15-30
d) 25-50
Answer: b
Explanation: For 1.2 micron technology, the Rs value for diffusion is 20-45.
Answer: b
Explanation: The relationship between channel resistance and sheet resistance can be given as R
= Z*Rs. Sheet resistance is a measure of resistance of thin films that are nominally uniform in
thickness.
Answer: b
Explanation: Z ( length to width ) ratio can be given as the ratio of upper channel to lower
channel. It is just a numerical quantity and has no unit.
Answer: c
Explanation: Deposition of metal or silicon alloy can be done by either sputtering or evaporation.
Sputtering is a process whereby particles are ejected from a solid target material due to
bombardment of the target by energetic particles.
9. Deposition of metal can be done by co-evaporation.
a) true
b) false
Answer: a
Explanation: Deposition of metal or silicon alloy can also be done by co-evaporation from the
elements.
Answer: a
Explanation: Processing of the device is better using polysilicon than silicides even though the
properties of silicides are better than polysilicon.
Area Capacitance
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Area
Capacitance”.
Answer: a
Explanation: Conducting layer is separated from the substrate by using dielectric or insulating
layer as both are electrical insulators that can be polarized by an applied electric field.
Answer: c
Explanation: Area capacitane of diffusion region of 2 micron technology is 3.75 pF X 10(-4)
(micrometer)2.
Answer: b
Explanation: The relative capacitance of diffusion region of 5 micron technology is 0.25. The
relative value is calculated by comparing two values of same type.
Answer: c
Explanation: A feature size square has L = W and its gate to channel capacitance value is called
as square Cg.
Answer: b
Explanation: The standard square Cg value of a 1.2 micron technology is 0.0023 pF.
Answer: b
Explanation: Relative area for L = 20λ and W = 3λ is = (20λ X 3λ) / (2λ X 2λ) = 15. Relative
area has no unit as two quantities of same type have been used.
Answer: b
Explanation: The value of gate capacitance is one square Cg. This is the standard value.
Answer: b
Explanation: Delay unit of 5 micron technology is 0.1 nsec.
11. Delay unit of 1.2 micron technology is
a) 0.064 nsec
b) 0.0064 nsec
c) 0.046 nsec
d) 0.0046 nsec
Answer: c
Explanation: The delay unit of 1.2 micron technology is 0.046 nsec.
Answer: b
Explanation: The transition point of an inverter is 0.5 Vdd. Transition point is the point where
different phases of same substance can be obtained in equilibrium.
13. What is the desired or safe delay value for 5 micron technology?
a) 0.3 nsec
b) 0.5 nsec
c) 0.1 nsec
d) 0.2 nsec
Answer: a
Explanation: The desired or safe delay value for 5 micron technology is 0.3 nsec.
Inverter Delays
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Inverter Delays”.
Answer: b
Explanation: The resistance value associated with Rp.d. is 1Rs. This is the measure of difficulty
to pass current through the pull-down device.
Answer: c
Explanation: The overall delay of nMOS inverter pair is Ʈ +4Ʈ = 5Ʈ . This delay is the time
taken for the input signal to get inverted and arrive at the output.
Answer: c
Explanation: The inverter pair delay for inverters having 4:1 ratio is 5Ʈ . This measure of delay
is for two inverters, in which the output of the first is given as the input for the second inverter.
Answer: a
Explanation: The ratio of rise time to fall time can be equated to βn/βp. Rise time is the time
taken by a signal to change from a specified low value to a specified high value. Fall time is the
time taken for the amplitude of a pulse to decrease from a specified value to another specified
value.
Answer: d
Explanation: The value of µn = 2.5 µp. This shows that µn value is greater than that of the µp.
Answer: a
Explanation: Rise time is slower by a factor of 2.5 than fall time.
Answer: b
Explanation: The condition for achieving symmetrical operation is Wp = 2.5 Wn.
10. Rise time and fall time is to load capacitance CL
a) directly proportional
b) inversely proportonal
c) exponentially equal
d) not related
Answer: a
Explanation: Rise time and fall time is directly proportional to load capacitance CL.
Answer: b
Explanation: Rise time and fall time is inversely proportional to Vdd. This shows that if Vdd is
reduced fall time and rise time increases.
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Drivers”.
Answer: a
Explanation: For shorter delays low resistance should be used as delay is directly proportional or
related to resistance.
Answer: a
Explanation: As width of the channel increases, capacitive load also increases and with this the
area occupied also increases. The rate at which the width increases affects the stages N and load
capacitance.
Answer: a
Explanation: Delay per stage for logic 0 to 1 transition can be given as fƮ . With large f, N
decreases but delay per stage increases.
Answer: d
Explanation: Delay per stage for logic 1 to 0 transition can be given as 4fƮ . Using the delay for
transition from 1 to 0 and 0 to 1 total nMOS delay can be obtained.
Answer: b
Explanation: Total delay of an CMOS pair is equal to 7fƮ . This can be calculated by
knowing thee delay per stage of CMOS.
Answer: b
Explanation: The number of stages N can be given as ln(y)/ln(f). By knowing whether the
number of stages N is even or odd we can calculate the total delay for nMOS, CMOS etc.
9. When number of stages N is even, the total delay for nMOS can be given as
a) 1.5NfƮ
b) 2.5NfƮ
c) 3.5NfƮ
d) 4.5NfƮ
Answer: b
Explanation: When number of stages N is even, the total delay for nMOS can be given as
2.5NfƮ . This is calculated by using the formula (N/2)*5fƮ .
10. When number of stages N is even, the total delay for CMOS can be given as
a) 1.5NfƮ
b) 2.5NfƮ
c) 3.5NfƮ
d) 4.5NfƮ
Answer: c
Explanation: When number of stages N is even, the total delay for CMOS can be given as
3.5NfƮ . This is calculated by using the formula (N/2)*7fƮ .
Answer: c
Explanation: In BiCMOS driver, the input voltage Vbe is logarithmically proportional to the base
width Wb and on electron mobility.
Answer: a
Explanation: In BiCMOS drivers, the initial time Tin necessary to charge base emitter junction is
larger than the time TL requires to charge the output load capacitance.
Answer: d
Explanation: In BiCMOS drivers, a good bipolar transistor should have low Rc, high hfe, high
gm etc.
Propogation Delays
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Propogation
Delays”.
1. Propogation time is directly proportional to
a) x
b) 1/x
c) x2
d) 1/x2
Answer: c
Explanation: Propogation time is directly proportional to square of the propogation distance (x 2 ).
It is the time taken by the signal to move from input port to output port.
Answer: b
Explanation: The total resistance can be given as the product of nrRs where r is the relative
resistance per section in terms of Rs.
Answer: b
Explanation: Total capacitance can be given as the product of nc(square Cg) where c is the
relative capacitance per section in terms of square Cg.
Answer: c
Explanation: The overall delay is directly proportional to n2 , where n is the number of pass
transistors in series.
Answer: b
Explanation: The number of pass transistors connected in series can be increased by connecting
buffer in between.
Answer: a
Explanation: Buffer is used for long polysilicon runs because it increses the speed and reduces
the sensitivity to noise.
Answer: a
Explanation: The overall delay is directly proportional to the relative resistance r. Overall delay
is given as product of n^2rcƮ .
Answer: c
Explanation: Small disturbanes of noise switches the inverter stage between 0 and 1 or vice
versa. It disturbs the normal operation or behaviour.
Answer: a
Explanation: The buffer speeds up the rise time of propogated signal edge. A buffer is the
combination of two inverters in which one output is fed to the other as the input.
Answer: a
Explanation: Overall delay increases as n increases where n is the number of pass transistors
connected in series.
Wiring Capacitances
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Wiring
Capacitances”.
Answer: d
Explanation: The sources of capacitances which contribute to the total wiring capacitance are
fringing field capacitance, interlayer capacitance and peripheral capacitance.
Answer: c
Explanation: Total wire capacitance can be given as the sum of area capacitance and fringing
field capacitance.
Answer: d
Explanation: Interlayer capacitance occurs due to parallel plate effect between one layer and
another. When one capacitance value comes closer to another they create some combined effects.
Answer: a
Explanation: Metal to polysilicon capacitance should be higher than metal to substrate
capacitance. This is due to that when one layer underlies the other and in consequence interlayer
capacitance is highly dependent on layout.
Answer: c
Explanation: The smaller the source or drain area, the greater the relative value of peripheral
capacitance as they are both inversely related.
Answer: d
Explanation: Diffusion capacitance is given by the sum of area capacitance and peripheral
capacitance.
Answer: a
Explanation: Polysilicon is unsuitable for routing Vdd or Vss other than for very small distance
because of the relatively high Rs value of the polysilicon layer.
Answer: b
Explanation: Polysilicon layer has high voltage drop. It has moderate RC product.
11. Which layer has high capacitance value?
a) metal
b) diffusion
c) silicide
d) polysilicon
Answer: b
Explanation: Diffusion or active layer has high capacitance value due to which it has low or
moderate IR drop.
Answer: a
Explanation: Polysilicon layer has high resistance value and due to this it has high IR drop.
13. While measuring the output load capacitance Cgs,n and Cgs,p is not considered. Why?
a) Because Cgs,n and Cgs,p are the capacitances at the input nodes.
b) Because Cgs,n and Cgs,p does not exist during the operation of CMOS inverter
c) Because Cgs,n and Cgs,p are storing opposite charges and cancel out each other during
calculation of load capacitance
d) None of the mentioned
Answer: a
Explanation: Cgs,n and Cgs,p are gate to source capacitances of nMOS and pMOS transistors in
CMOS inverter. They are measured at input node. Therefore they are not considered for
calculation of load capacitance.
14. During the calculation of load capacitance of a 1st stage CMOS inverter, the input node
capacitances, Cgs,n and Cgs,p of the 2nd stage CMOS inverter is also considered.
a) True
b) False
Answer: b
Explanation: Instead thin oxide capacitance over the gate area is used for calculation.
Scaling Factors -1
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Scaling Factors -
1”.
Answer: d
Explanation: Microelectronic technology can be characterized by minimum feature size, number
of gates on one chip, power dissipation, die size, production cost etc and not by designing cost.
Answer: c
Explanation: Constant electric scaling model and constant voltage scaling model is used for
scaling.
Answer: a
Explanation: α is used as the scaling factor for linear dimensions where as β is used for supply
voltage Vdd, gate oxide thickness etc.
Answer: a
Explanation: For constant voltage model, β = α.
Answer: b
Explanation: Gate area Ag can be given as the product of length and the width of the channel.
Answer: c
Explanation: Gate area is given as the product of length and width of the channel and it can be
scaled by 1/α2 .
Answer: d
Explanation: Gate capacitance per unit area is scaled by β and this is given by €ox/D.
9. Parasitic capacitance is given by
a) Ax/d
b) Ax * d
c) d/Ax
d) Ax
Answer: a
Explanation: Parasitic capacitance is given by Ax/d where Ax is the area of the depletion region
and d is the depletion width.
Answer: d
Explanation: Parasitic capacitance is scaled by 1/α because area is scaled by 1/α^2 and d by 1/α.
Thus (1/α^2)/(1/α) we will get 1/α.
Scaling Factors -2
This set of VLSI Interview Questions and Answers for freshers focuses on “Scaling Factors -2”.
Answer: c
Explanation: Carrier density in channel Qon is scaled by 1. Carrier density is given by C0*Vgs
where C0 is scaled by β and Vgs is scaled by 1/β.
Answer: b
Explanation: Gate delay Td is given as the product of Ron, channel resistance and Cg the gate
capacitance.
Answer: c
Explanation: Maximum operating frequency f0 is scaled by α2/β. This is given by
(W/L)*(µ*C0*Vdd/Cg).
Answer: d
Explanation: Saturation current Idss is scaled by 1/β. This is given by (Co*µ/2)*W/L*(Vgs-Vt)2 .
6. Vgs is scaled by
a) α
b) β
c) 1/α
d) 1/β
Answer: d
Explanation: Gate to source voltage Vgs is scaled by 1/β. All voltages are scaled by 1/β.
7. Current density J is scaled by
a) α/β
b) β/α
c) α2/β
d) β2/α
Answer: c
Explanation: Current density J is scaled by α^2/β. Current density is given by Idss/A where Idss
is scaled by 1/β and area A by 1/α^2.
Answer: d
Explanation: Power dissipation per gate is scaled by 1/β^2. This is the sum of static component
Pgs and dynamic component Pgd.
Answer: d
Explanation: Power dissipation per unit area Pa is scaled by α2/β2. This is given by Pg/Ag where
Pg is scaled by 1/β2 and Ag by 1/α2.
Answer: c
Explanation: Saturation current is scaled by 1 in constant voltage model. This is because
saturation current is scaled by 1/β and here in constant voltage model β is 1.
11. In constant field model, maximum operationg frequency is scaled by
a) α
b) β
c) α2
d) β2
Answer: a
Explanation: In constant field model, maximum operating frequency is scaled by α. Maximum
operating frequency is scaled by α2/β and here in this model β = α.
12. In constant electric field model, power dissipation per unit area is scaled by
a) α
b) β
c) 1
d) β2
Answer: c
Explanation: Power dissipation per unit area is scaled by 1 in constant electric field model. This
is scaled by α2/β2 and here in constant electric field model β = α.
Switch Logic
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Switch Logic”.
Answer: a
Explanation: The subsystem of the circuit or system to be designed should have minimum
interdependence and complexity.
Answer: c
Explanation: The switch logic approach takes no static current from the supply rails and is faster
for small arrays.
Answer: a
Explanation: Power dissipation is small in switch logic approach since current only flows on
switching.
Answer: d
Explanation: Some of the features of switch logic approach are that it occupies more area,
eliminates undesirable threshold voltage and has low power dissipation.
Answer: a
Explanation: Basic AND and OR combination of switches are possible and are used in
switch logic. It is simple to design and easier.
Answer: a
Explanation: When logic levels are propogated through pass transistors are degraded by
threshold voltage.
Answer: b
Explanation: Switch logic approach is fast for smaller arrays and as the arrays becomes larger
more switches and gates are requires which makes it a bit slower and complex.
Answer: a
Explanation: Switch logic is designed using n or p pass transistors or from complementary
switches.
Gate Logic
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Gate Logic”.
Answer: d
Explanation: Gate logic is also called as restoring logic. This is a logic circuitry designed so that
even with an imperfect input pulse a standard output occurs at the exit of each successive logic
gate.
Answer: a
Explanation: Both NAND and NOR gates can be used in gate logic along with CMOS and AND
and OR logic can be used in switch logic.
Answer: c
Explanation: The CMOS inverter has no static current and no power dissipation. Static charge
remains until it is able to move away by means of electric discharge.
Answer: c
Explanation: NAND gate delay can be given as the product of number of inputs n and the nMOS
inverter delay Ʈ int.
Answer: b
Explanation: In CMOS NAND gate, p transistors are connected in parallel but once again the
geometries may require thought when several inputs are required.
Answer: b
Explanation: BiCMOS NAND can be used when large fan-out is necessary. Fan-out is a term
that defines the maximum number of digital inputs that the output of a single logic gate can feed.
Answer: c
Explanation: NOR gate is faster. NAND is more complex than NOR and thus NOR is faster and
efficient.
10. For a pseudo nMOS design the impedance of pull up and pull down ratio is
a) 4:1
b) 1:4
c) 3:1
d) 1:3
Answer: c
Explanation: For a pseudo nMOS design, the ratio of Zp.u. and Zp.d. is 3:1.
CMOS Logics
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “CMOS Logics”.
Answer: b
Explanation: In Pseudo-nMOS logic, n transistor operates in saturation region and p transistor
operates in resistive region.
Answer: c
Explanation: The power dissipation in Pseudo-nMOS is reduced to about 60% compared to
nMOS device.
Answer: a
Explanation: Pseudo-nMOS has higher pull-up resistance than nMOS device and thus inverter
pair delay is larger.
Answer: d
Explanation: In dynamic CMOS logic, four phase clock is used in which actual signals are used
to derive the clocks.
Answer: a
Explanation: In clocked CMOS logic, the logic is evaluated only in the on period of the clock.
And owing to the extra transistor in series, slower rise time and fall times are expected.
Answer: c
Explanation: In CMOS domino logic, single phase clock is used. Clock signals distributed on
one wire is called as single or one phase clock.
Answer: b
Explanation: CMOS domino logic is same as that of the dynamic CMOS logic with inverter at
the output line.
Answer: a
Explanation: CMOS domino logic structure occupies smaller area than conventional CMOS
logic as only n-block is used.
Answer: b
Explanation: In CMOS domino logic, only non inverting structures are possible because of the
presence of the inverting buffer.
Answer: b
Explanation: Clocked sequential circuits are two phase non overlapping clock signal. Clock
signals are distributed in two wires and it is non overlapping.
Answer: a
Explanation: Clocked circuitry are easier to design than the asynchronous sequential circuits. But
it is slower than the asynchronous sequential circuit.
Answer: a
Explanation: As the temperature is increased, storage time is halved. It is inversely proportional
to the storage time.
5. Inverting dynamic register element consists of transistors for nMOS and for
CMOS
a) two, three
b) three, two
c) three, four
d) four, three
Answer: c
Explanation: Dynamic register element consists of three transistors for nMOS and four for
CMOS.
6. Non inverting dynamic register storage cell consists of transistors for nMOS and
for CMOS
a) six, eight
b) eight, six
c) five, six
d) six, five
Answer: a
Explanation: Non inverting dynamic register storage cell consists of six transistors for nMOS
and eight for CMOS.
8. In a four bit dynamic shift register basic nMOS transistor or inverters are connected in
a) series
b) cascade
c) parallel
d) series and parallel
Answer: b
Explanation: The basic inverters or nMOS transistors are connected in cascade to obtain four bit
dynamic shift register.
Answer: d
Explanation: In four bit dynamic shift register , output is obtained parallely at inverters 2,4,6,8.
Answer: b
Explanation: For signals which are updated frequently dynamic storage elements are used. It can
be done at < 0.25 msec interval.
Floor Layout
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Floor Layout”.
Answer: c
Explanation: A 4-bit processor has two buses one is bidirectional to carry operand and output to
shifter and register array and another bus unidirectional to carry input.
Answer: a
Explanation: The IN and OUT bus line‟s relative positions are interchanged to make the cell
stretchable and to match the height of the block and spacings.
Answer: a
Explanation: The IN and OUT bus lines should be in metal rather than diffusion or polysilicon to
mate with the bus structures of other blocks.
4. Extensions are
a) vertical
b) horizontal
c) diagonal
d) happazard
Answer: b
Explanation: Extensions are horizontal or parallel to the stratified unit and rifts are described as
extension zones.
Answer: a
Explanation: Rifts and extensions should be placed where they cut a minimum amount of simple
geometry, one in polysilicon and one in diffusion.
Answer: a
Explanation: Rifts are used for smooth flow through buses as suggested and hence one in used in
polysilicon and other in diffusion.
Answer: b
Explanation: Input and output pads are made up of metal and it used to connect chips from one
circuitry to another.
Answer: c
Explanation: Bonding pads are positioned near to the edge of the chips although there will be a
Vdd bus between bonding pads and chip boundary.
Answer: d
Explanation: Output pads provide large current for off-wiring and also inputs to other devices.
But these pads uses minimum space.
Answer: d
Explanation: Built-in self test objectives are to reduce test pattern generation cost, to reduce
volume of test data and to reduce test time.
Answer: a
Explanation: In data compression technique, comparison is made on compacted test response
instead on entire test data.
Answer: c
Explanation: Signature analysis performs polynomial division that is division of data out of the
device under test.
Answer: b
Explanation: The signature analysis method is represented mathematically as R(x) = P(x) / C(x)
where R(x) is the signature, C(x) is characteristic polynomial.
5. Transition counting does the count of transition only in one specific direction at a time.
a) true
b) false
Answer: a
Explanation: Transition counting does the count of transition in specified direction ( 0 t0 1 or 1
to 0).
Answer: b
Explanation: Built-in logic block observer method uses signature analysis in conjunction with a
scan path.
Answer: b
Explanation: When B1=B2=0, storage elements are configured as scan path, they are connected
as serial shift register.
Answer: d
Explanation: When B1=1 and B2=0, the circuit is configured as LFSR mode and can be used as
either polynomial divider or random test pattern generator.
Answer: c
Explanation: When B1=0 and B2=1, in the final mode, the BILBO is reset.
Answer: d
Explanation: The type of error in self-checking techniques are simple errors, unidirectional errors
and multiple errors.
Answer: c
Explanation: The parity check detects simple errors using XOR gates and for each type of error,
approximate coding technique is used.
Answer: d
Explanation: Multiple errors are detected using duplication codes which consists of duplicating
the information.
Answer: b
Explanation: The MOS structure acts as a capacitor with metal gate and semiconductor acting as
parallel plate conductors and oxide as dielectric between them.
Answer: d
Explanation: The Fermi potential, which is a function of temperature and doping, denotes the
difference between the intrinsic Fermi level and the Fermi level.
Answer: a
Explanation: Metal being more positive compared to semiconductor.. Electric field exists from
metal to semiconductor.
4. Consider a MOS structure with equilibrium Fermi potential of the doped silicon substrate is
given as 0.3eV. Electron affinity of Si is 4.15eV and metal is 4.1eV. Find the built in potential of
the MOS system:
a) -0.8eV
b) 0.8eV
c) 0.9eV
d) -0.9eV
Answer: d
Explanation: Surface potential: qΦs = 4.15eV+0.55eV+0.3eV=5.0eV
qΦm-qΦs = 4.1eV – 5.0eV =-0.9eV.
5. When gate voltage is negative for enhancement mode n-MOS, the direction of electric field
will be:
a) Metal to semiconductor
b) Semiconductor to metal
c) No field exists
d) None of the mentioned
Answer: b
Explanation: When gate voltage is negative, holes in substrate are attracted towards surface
creating electric field from semiconductor to metal.
Answer:a
Explanation: When surface potential reaches –fermi potential, the surface inversion occurs. The
gate voltage which brings these changes is known as threshold voltage.
Answer: c
Explanation: Surface inversion occurs when gate voltage is equal to threshold voltage.
Answer: b
Explanation: For enhancement mode n-MOSFET, the threshold voltage is positive quantity.
Answer: d
Explanation: The threshold voltage depends on: The workfunction difference between gate and
channel, The gate voltage component to change surface potential, The gate voltage component to
offset the depletion charge and fixed charges in gate oxide
Noise Margin
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Noise Margin”.
1. Noise Margin is :
a) Amount of noise the logic circuit can withstand
b) Difference between VOH and VIH
c) Difference between VIL and VOL
d) All of the Mentioned
Answer: d
Explanation: Noise Margin is defined as the amount of noise the logic circuit can withstand, it is
given by difference between VOH and VIH or VIL and VOL.
Answer: b
Explanation: The VIL is the input voltage at which the slope of the transition will be equal to -1.
Answer: b
Explanation: The VIH is the input voltage at which the slope of the transition will be equal to -1.
In Transfer characteristics at 2 points we will find the slope to be -1.
4. The relation between threshold voltage and Noise Margin is:
a) Vth = sqrt(Noise Margin)
b) Vth = NMH – NML
c) Vth = (NMH+NML)/2
d) None of the metioned
Answer: d
Explanation: None.
Answer: b
Explanation: Noise margin = VIL-VOL.
Answer: a
Explanation: Noise margin =VOH – VIH.
Answer: c
Explanation: In Input the uncertain region is VIH and VIL.
9. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate
is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: c
Explanation: Logic output 0 from first gate is considered as logic input 0 at second gate as it lies
within the range.
10. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate
is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: b
Explanation: The level of output signal from 1st gate is higher than the range for low input at 2nd
gate. So it is uncertain.
Answer: b
Explanation: None.
12. If VIH of the 2nd gate is higher than VOH of the 1st gate, then logic output 0 from the 1st
gate is considered as :
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: b
Explanation: The level of output signal from 1st gate is higher than the range for low input at 2nd
gate. So it is uncertain.
Test Patterns
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Test Patterns “.
Answer: a
Explanation: Deterministic test pattern are used to detect specific faults or structural faults for a
circuit under test.
Answer: a
Explanation: Deterministic test pattern method is also known as stored test pattern method in the
context of BIST applications.
3. Which method uses finite state machine for developing the test pattern?
a) deterministic test pattern
b) algorithmic test pattern
c) random test pattern
d) exhaustive test pattern
Answer: b
Explanation: Algorithmic test pattern method uses the hardware finite state machine for
generating algorithmic test vectors for the circuit under test.
Answer: c
Explanation: A n-bit counter produces totally 2n number of all possible input combinations for
testing the circuit under test and it is called as exhaustive test pattern method.
Answer: a
Explanation: Exhaustive test pattern method detects all gate level struck-at fault and also
bridging fault.
Answer: b
Explanation: Exhaustive test pattern method does not detect all transistor level faults or delay
faults since those faults needs specific ordering.
Answer: a
Explanation: Exhaustive test pattern method is not suitable for circuit having large N values
since there is a limit for fault coverage.
advertisement
Answer: d
Explanation: Pseudo-random test pattern method have properties similar to random pattern
sequence but the sequence are repeatable.
Answer: c
Explanation: Random test pattern method is used for external functional testing of
microprocessors as well as in ATPG software.
Fault Models
This set of VLSI Multiple Choice Questions & Answers (MCQs) focuses on “Fault Models “.
Answer: d
Explanation: Some of the real defects in chip such as processing faults are missing contact
window, parasitic transistor and oxide breakdown.
Answer: a
Explanation: Some of the material defects are bulk defects and surface impurities. Bulk defects
are cracks and crystal imperfection and surface impurities occurs due to ion migration.
3. Electromigration is a
a) processing fault
b) material defects
c) time dependent failure
d) packaging fault
Answer: c
Explanation: Different types of real defects in chips are processing fault, material defects, time
dependent failure and packaging fault. Time dependent failures are dielectric breakdown and
electromigration.
Answer: b
Explanation: The relation fault – error – failure is correct. Error is caused by faults and failure
which is a deviation of the circuit is caused by error.
Answer: b
Explanation: For a circuit with k lines, 2k single stuck-at faults are possible and 3^k – 1 multiple
stuck-at faults are possible.
Answer: c
Explanation: For circuit with n lines, n2 bridging faults are possible. Bridging fault occurs when
two lines are connected when they should not be connected. It leads to wired AND or wired OR.
Answer: b
Explanation: When input is low, both P and N transistors are conducting causing increase in
quiescent current which leads to IDDQ fault.
Answer: a
Explanation: Transistor with stuck-open fault causes output floating. Stuck-open faults requires
two vector tests.
Answer: d
Explanation: In PLA, missing cross point in AND array leads to growth fault and missing cross
point in OR-array leads to disapperance fault.
Answer: d
Explanation: In PLA, extra crosspoint in AND-array leads to shrinkage or disapperance fault
whereas extra crosspoint in OR-array leads to appearance fault.
Answer: a
Explanation: The number of paths increases exponentially with number of gates. Propogation
delay of the path exceeds the clock interval.