Bias Power Supply For TV and Monitor TFT LCD Panels: Features
Bias Power Supply For TV and Monitor TFT LCD Panels: Features
Bias Power Supply For TV and Monitor TFT LCD Panels: Features
DESCRIPTION
The TPS65161 offers a compact power supply solution to provide all four voltages required by thin-film transistor
(TFT) LCD panel. With its high current capabilities, the device is ideal for large screen monitor panels and LCD
TV applications.
TYPICAL APPLICATION
L1 D1 Vs
10 μH SL22 18 V/1.3 A
Vin
12 V
C1
2 * 22 μF C4 R1
C3 TPS65161 C2
4 22 pF 825 kΩ
1 μF 8 3 * 22 μF
SUP SW
12 5
FREQ SW
20 1 C15 R2
VINB FB 56 kΩ
21 3 470 nF
VINB OS
22 23 D4
C16 AVIN GND
1 μF 16 27
EN1 GD GD D5
VGL C6 9 10 C5 0.47 μF VGH
−5 V/50 mA D2 0.47 μF EN2 DRP 32 V/50 mA
11 14
DRN FBP
13 17 R5
FBN Boot C13
D3 24 18 560 kΩ 0.47 μF
R3 REF SWB
C7 6 19
0.47 μF 620 kΩ PGND NC
7 15
PGND FBB
28 2 R6
SS COMP Cb 22 kΩ
R4 25 26
DLY1 DLY2 100 nF
150 kΩ
L2 Vlogic
C17 3.3 V/2.3 A
C9 C10 C11 22 nF 15 μH
C8 10 nF
220 nF 22 nF 10 nF
D6 R7 C14 C12
SL22 2 kΩ 10 nF 2 * 22 μF
R8
1.2 kΩ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS65161
www.ti.com
SLVS617 – APRIL 2006
DESCRIPTION (CONTINUED)
Compared to the TPS65160 and TPS65160A the device offers a higher output current for the step down
converter and allows to connect the positive charge pump supply (SUP) always to the output. Therefore in most
applications a simple charge pump doubler can generates VGH reducing external component count. The device
can be powered directly from a 12-V input voltage generating the bias voltages VGH and VGL, as well as the
source voltage VS and logic voltage for the LCD panels. The device consists of a boost converter to provide the
source voltage VS and a step-down converter to provide the logic voltage for the system. A positive and a
negative charge-pump driver provide adjustable regulated output voltages VGL and VGH to bias the TFT. Both
boost and step-down converters, as well as the charge-pump driver, operate with a fixed switching frequency of
500 kHz or 750 kHz, selectable by the FREQ pin. The TPS65161 includes adjustable power-on sequencing. The
device includes safety features like overvoltage protection of the boost converter and short-circuit protection of
the buck converter, as well as thermal shutdown. Additionally, the device incorporates a gate drive signal to
control an isolation MOSFET switch in series with VS or VGH. See the application circuits at the end of this data
sheet.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
(1)
ORDERING INFORMATION
TA UVLO OVERVOLTAGE ORDERING PACKAGE (2) PACKAGE
(typ) PROTECTION MARKING
Vs (typ)
–40°C to 85°C 6V 20 V TPS65161PWP TSSOP28 (PWP) TPS65161
(1)For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web
site at www.ti.com.
(2) The PWP package is available taped and reeled. Add R-suffix to the device type (TPS65161PWPR) to order the device taped and
reeled. The TPS65161PWPR package has quantities of 2000 devices per reel. Without suffix, the TPS65161PWP is shipped in tubes
with 50 devices per tube.
(3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(4) All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
TA ≤ 25°C TA = 70°C TA = 85°C
PACKAGE RTHJA
POWER RATING POWER RATING POWER RATING
28-Pin TSSOP 28°C/W (PowerPAD (5) soldered) 3.57 W 1.96 W 1.42 W
(5) See Texas Instruments application report SLMA002 regarding thermal characteristics of the PowerPAD package.
(6) The maximum output voltage is limited by the overvoltage protection threshold and not be the maximum switch voltage rating.
(7) See application section for further information.
ELECTRICAL CHARACTERISTICS
VIN = 12 V, SUP = VIN, EN1 = EN2 = VIN, VS = 15 V, VLOGIC = 3.3 V, TA = –40°C to 85°C, typical values are at TA = 25°C
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage range 8 14 V
VGH = 2 x VS, 0.2 2
Quiescent current into AVIN Boost converter not
switching
IQIN mA
VGH = 2 x VS, 0.2 0.5
Quiescent current into VINB Buck converter not
switching
Shutdown current into AVIN EN1 = EN2 = GND 0.1 2
ISD µA
Shutdown current into VINB EN1 = EN2 = GND 0.1 2
Shutdown current into SUP EN1 = EN2 = GND 0.1 4 µA
ISUP
Quiescent current into SUP VGH = 2 x VS 0.2 2 mA
VUVLO Undervoltage lockout threshold VIN falling 6 6.4 V
VREF Reference voltage 1.203 1.213 1.223 V
Thermal shutdown Temperature rising 155 °C
Thermal shutdown hysteresis 5 °C
LOGIC SIGNALS EN1, EN2, FREQ
VIH High-level input voltage EN1, EN2 2.0 V
VIL Low-level input voltage EN1, EN2 0.8 V
VIH High-level input voltage FREQ 1.7 V
VIL Low-level input voltage FREQ 0.4 V
EN1 = EN2 = FREQ = 0.01 0.1 µA
II Input leakage current
GND or VIN
CONTROL AND SOFT START DLY1, DLY2, SS
IDLY1 Delay1 charge current 3.3 4.8 6.2 µA
IDLY2 Delay2 charge current VTHRESHOLD = 1.213 V 3.3 4.8 6.2 µA
ISS SS charge current 6 9 12 µA
INTERNAL OSCILLATOR
FREQ = high 600 750 900
fOSC Oscillator frequency kHz
FREQ = low 400 500 600
(8) The maximum output voltage is limited by the overvoltage protection threshold and not be the maximum switch voltage rating.
(9) The GD signal is latched low when the main boost converter output VS is within regulation. The GD signal is reset when the input
voltage or enable of the boost converter is cycled low.
(10) The maximum charge-pump output current is typically half the drive current of the internal current source or current sink.
FB 1 28 SS
COMP 2 27 GD
OS 3 26 DLY2
SW 4 25 DLY1
Thermal PAD (see Note)
SW 5 24 REF
PGND 6 23 GND
PGND 7 22 AVIN
SUP 8 21 VINB
EN2 9 20 VINB
DRP 10 19 NC
DRN 11 18 SWB
FREQ 12 17 BOOT
FBN 13 16 EN1
FBP 14 15 FBB
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
This is the supply pin of the positive charge pump driver and can be connected to the input supply Vin or the
SUP 8 I output of the main boost converter Vs. This depends mainly on the desired output voltage VGH and numbers of
charge pump stages.
Frequency adjust pin. This pin allows setting the switching frequency with a logic level to 500 kHz = low and
FREQ 12 I
750 kHz = high.
Analog input voltage of the device. This is the input for the analog circuits of the device and should be bypassed
AVIN 22 I
with a 1-µF ceramic capacitor for good filtering.
VINB 20, 21 I Power input voltage pin for the buck converter.
This is the enable pin of the buck converter and negative charge pump. When this pin is pulled high, the buck
EN1 16 I converter starts up, and after a delay time set by DLY1, the negative charge pump comes up. This pin must be
terminated and not be left floating. A logic high enables the device and a logic low shuts down the device.
The boost converter starts only with EN1 = high, after the step-down converter is enabled. EN2 is the enable pin
of the boost converter and positive charge pump. When this pin is pulled high, the boost converter and positive
EN2 9 I charge pump starts up after the buck converter is within regulation and a delay time set by DLY2 has passed by.
This pin must be terminated and not be left floating. A logic high enables the device and a logic low shuts down
the device.
DRN 11 O Drive pin of the negative charge pump.
FBN 13 I Feedback pin of negative charge pump.
REF 24 O Internal reference output typically 1.213 V
PGND 6, 7 Power ground
This pin allows setting the soft-start time for the main boost converter VS. Typically a 22-nF capacitor needs to be
SS 28 O
connected to this pin to set the soft-start time.
Connecting a capacitor from this pin to GND allows the setting of the delay time between VLOGIC (step-down
DLY1 25 O
converter output high) to VGL during start-up.
Connecting a capacitor from this pin to GND allows the setting of the delay time between VLOGIC (step-down
DLY2 26 O
converter output high) to VS Boost converter and positive charge-pump VGH during start-up.
This is the compensation pin for the main boost converter. A small capacitor and, if required, a resistor is
COMP 2
connected to this pin.
FBB 15 I Feedback pin of the buck converter
SWB 18 O Switch pin of the buck converter
NC 19 Not connected
N-channel MOSFET gate drive voltage for the buck converter. Connect a capacitor from the switch node SWB to
BOOT 17 I
this pin.
FBP 14 I Feedback pin of positive charge pump.
DRP 10 O Drive pin of the positive charge pump.
This is the gate drive pin which can be used to control an external MOSFET switch to provide input to output
isolation of VS or VGH. See the circuit diagrams at the end of this data sheet. GD is an open-drain output and is
GD 27
latched low as soon as the boost converter is within 8% of its nominal regulated output voltage. GD goes high
impedance when the EN2 input voltage is cycled low.
GND 23 Analog ground
Output sense pin. The OS pin is connected to the internal rectifier switch and overvoltage protection comparator.
This pin needs to be connected to the output of the boost converter and cannot be connected to any other voltage
OS 3 I
rail. Connect a 470-nF capacitor from OS pin to GND to avoid noise coupling into this pin. The PCB trace of the
OS pin needs to be wide because it conducts high current.
FB 1 I Feedback of the main boost converter generating Vsource (VS).
SW 4, 5 I Switch pin of the boost converter generating Vsource (VS).
PowerPAD The PowerPAD needs to be connected and soldered to power ground (PGND).
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
MAIN BOOST CONVERTER (Vs)
η Efficiency main boost converter Vs vs Load current VS =15 V,VIN = 12 V 1
rDS(ON) N-channel main switch Q1 vs Input voltage and temperature 2
Soft-start boost converter CSS = 22 nF 3
PWM operation at full-load current 4
PWM operation at light-load current 5
Load transient response 6
STEP-DOWN CONVERTER (Vlogic)
η Efficiency main boost converter VS vs Load current VLOGIC = 3.3 V,VIN = 12 V 7
rDS(ON) N-channel main switch Q1 8
PWM operation - continuous mode 9
PWM operation - discontinuous mode 10
Soft start 11
Load transient response 12
SYSTEM PERFORMANCE
fosc Oscillation frequency vs Input voltage and temperature 13
Power-up sequencing EN2 connected to VIN 14
Power-up sequencing EN2 enabled separately 15
0.12
70
0.1
Efficiency − %
60
50 0.08
40
0.06
30
VI = 12 V, 0.04
20 VO = 15 V,
L = 10 H
0.02
10
0 0
0 0.5 1 1.5 2 −40 −20 0 20 40 60 80 100 120 140
IO − Output Current − A TA − Temperature − C
Figure 1. Figure 2.
VI = 12 V, VI = 12 V,
VO = 15 V/ 1.2 A, VO = 15 V/1.5 A
C(SS) = 22 nF
VSW
10 V/div
VO
50 mV/div
VS
5 V/div
II I(Inductor)
1 A/div 1 A/div
2 ms/div 1 s/div
Figure 3. Figure 4.
VI = 12 V , VI = 12 V, VS = 15 V,
CO = 3*22 F,
VO = 10 V/10 mA C(comp) = 22 nF,
L = 6.8 H,
FREQ= High
VSW VS
10 V/div 200 mV/div
VO
50 mV/div
IL I(Inductor)
500 mA/div 1 A/div
Figure 5. Figure 6.
60
Efficiency − %
0.15
50
40
0.1
30
20
VI = 12 V, 0.05
r
10 VO = 3.3 V,
L = 15 H
0 0
0 0.5 1 1.5 2 −40 −20 0 20 40 60 80 100 120 140
IO − Output Current − A TA − Temperature − C
Figure 7. Figure 8.
VI = 12 V,
VO = 3.3 V/45 mA
VSW
VSW
5 V/div
5 V/div
VO
VO 20 mV/div
20 mV/div
I(Inductor)
I(Inductor) VI = 12 V, 100 mA/div
1 A/div VO = 3.3 V/1.5 A
500 ns/div
500 ns/div
Figure 9. Figure 10.
VI = 12 V,
VO = 3.3 V/1.2 A
VO1
100 mV/div
VI = 12 V, V(logic) = 3.3 V,
CO = 2*22 F, FREQ = High
VO
1 V/div
IO
I(Inductor) 270 mA to 1.3 A
1 A/div
50 s/div
200 s/div
2 V/div
725 VGL
5 V/div
720
715
710
VS
705 5 V/div
VGH
700
10 V/div
695
−50 0 50 100 150
TA − Temperature − C 2 ms/div
POWER-UP SEQUENCING
EN2 ENABLED SEPARATELY
V Logic
2 V/div
VS
5 V/div
VGH
5 V/div
EN2
2 V/div
1 ms/div
Figure 15.
BLOCK DIAGRAM
AVIN FREQ SW SW
SS Q2
Bias
D
S
GND 500 kHz/ OS
Vref=1.213 V Clock Current Limit
750 kHz
Thermal DLY1 and
Oscillator
AVIN Shutdown Soft Start
DLY2 OS
Sequencing
Overvoltage
Comparator
IDLY
Vref SS
GM Amplifier
PGND
Sawtooth Comparator
FB Generator
Positive SUP SUP
VFB OS Charge Pump
1.154 V
I DRVP
GM Amplifier
Low Gain
Current
Control DRVP
VFB Vref
Soft Start
1.154 1.2 13 V Q3
VINB
AVIN Negative
Charge Pump FBP
VINB Step-Down
Current
Converter
Control
Regulator
DRVN
N Soft Start BOOT
8V
I DRVN
Q3
D
S
SWB
NC
Control Logic
FBN Current Limit
Ref
Vref
DLY1 Vref
DLY1 Compensation
Clock/2 and
Soft Start Sawtooth
IDLY
0.9 V
Vref Generator
Logic
DLY2 Clock/4 Clock
DLY2
0.6 V
Reference
Output
GD Clock
D Vref
VREF
S Clock Select During Short Circuit 1.2 13 V
and Soft Start
EN1 EN2
DETAILED DESCRIPTION
Boost Converter
The main boost converter operates in pulse-width modulation (PWM) and at a fixed switching frequency of
500 kHz or 750 kHz set by the FREQ pin. The converter uses an unique fast response, voltage-mode controller
scheme with input voltage feedforward. This achieves excellent line and load regulation (0.03%-A load
regulation typical) and allows the use of small external components. To add higher flexibility to the selection of
external component values, the device uses external loop compensation. Although the boost converter looks like
a nonsynchronous boost converter topology operating in discontinuous conduction mode at light load, the
TPS65161 maintains continuous conduction even at light-load currents. This is achieved with a novel
architecture using an external Schottky diode with an integrated MOSFET in parallel connected between SW
and OS. See the Functional Block Diagram. The intention of this MOSFET is to allow the current to go negative
that occurs at light-load conditions. For this purpose, a small integrated P-Channel MOSFET with typically 10-Ω
rds(on) is sufficient. When the inductor current is positive, the external Schottky diode with the lower forward
voltage conducts the current. This causes the converter to operate with a fixed frequency in continuous
conduction mode over the entire load current range. This avoids the ringing on the switch pin as seen with
standard nonsynchronous boost converter and allows a simpler compensation for the boost converter.
Thermal Shutdown
A thermal shutdown is implemented to prevent damage caused by excessive heat and power dissipation.
Typically, the thermal shutdown threshold is 155°C.
Step-Down Converter
The nonsynchronous step-down converter operates at a fixed switching frequency using a fast response voltage
mode topology with input voltage feedforward. This topology allows simple internal compensation, and it is
designed to operate with ceramic output capacitors. The converter drives an internal 3.2-A N-channel MOSFET
switch. The MOSFET driver is referenced to the switch pin SWB. The N-channel MOSFET requires a gate drive
voltage higher than the switch pin to turn the N-Channel MOSFET on. This is accomplished by a bootstrap gate
drive circuit running of the step-down converter switch pin. When the switch pin SWB is at ground, the bootstrap
capacitor is charged to 8 V. This way, the N-channel gate drive voltage is typically around 8 V.
Vs
I DRVP
DRP
Current Cfly
VG
VGH
Control
23 V/50 mA
Soft Start
Q3 C13
R5
0.47 µF
FBP
R6
If higher output voltages are required, another charge-pump stage can be added to the output.
Setting the output voltage:
V out 1.213 1 R5
R6
R5 R6
Vout
V
FB
1 R6
V out
1.213
1
Negative Charge Pump
The negative charge pump provides a regulated output voltage set by the external resistor divider. The negative
charge pump operates similar to the positive charge pump with the difference that it runs from the input voltage
VIN. The negative charge pump driver inverts the input voltage. The maximum negative output voltage is VGL =
(–VIN)+Vdrop. Vdrop is the voltage drop across the external diodes and internal charge-pump MOSFETs. In
case VGL needs to be lower than –VIN, an additional charge-pump stage needs to be added.
Setting the output voltage:
V out V R3 1.213 V R3
REF R4 R4
|Vout| |Vout|
R3 R4 R4
V 1.213
REF
The lower feedback resistor value, R4, should be in a range between 40 kΩ to 120 kΩ or the overall feedback
resistance should be within 500 kΩ to 1 MΩ. Smaller values load the reference too heavily, and larger values
may cause stability problems. The negative charge pump requires two external Schottky diodes. The peak
current rating of the Schottky diode has to be twice the load current of the output. For a 20-mA output current,
the dual-Schottky diode BAV99 is a good choice.
EN2
EN1
DLY2
VGH
Vs
V s, VGH Vin Vin
VLogic
Fall Time Depends on Load
Current and Feedback Resistor
VGL
DLY1
GD
EN2
EN1
DLY2
VGH
Vs
Vin Vin
VGH ,Vs
DLY1 VGL
GD
Undervoltage Lockout
To avoid misoperation of the device at low input voltages, an undervoltage lockout is included which shuts down
the device at voltages lower than 6 V.
With
Isw = converter switch current (minimum switch current limit = 2.8 A)
fs = converter switching frequency (typical 500 kHz/750 kHz)
L = Selected inductor value
η = Estimated converter efficiency (use the number from the efficiency curves or 0.8 as an estimation)
The peak switch current is the steady-state peak switch current that the integrated switch, inductor, and external
Schottky diode must be able to handle. The calculation must be done for the minimum input voltage where the
peak switch current is highest.
Setting the Output Voltage and Selecting the Feedforward Capacitor (Boost Converter)
The output voltage is set by the external resistor divider and is calculated as:
V out 1.146 V 1 R1
R2
Across the upper resistor, a bypass capacitor is required to achieve a good load transients response and to
have a stable converter loop. Together with R1, the bypass capacitor Cff sets a zero in the control loop.
Depending on the inductor value, the zero frequency needs to be set. For a 6.8-µH or 10-µH inductor, fz = 10
kHz and for a 22-µH inductor, fz = 7 kHz.
Cƒƒ 1 1
2 ƒ z R1 2 10 kHz R1
ƒz 1
2 Cc Rc
Lower input voltages require a higher gain and therefore a lower compensation capacitor value.
Cz 1 1 9.9 nF 10 nF
2 8 kHz R1 2 8 kHz 2k
Usually a capacitor value closest to the calculated value is selected.
With:
f = Switching frequency (750 kHz, 500 kHz minimal)
L = Inductor value (typically 15 µH)
∆IL= Peak-to-peak inductor ripple current
ILmax = Maximum inductor current
The highest inductor current occurs at maximum Vin. A more conservative approach is to select the inductor
current rating just for the typical switch current of 3.2 A.
Layout Consideration
The PCB layout is an important step in the power supply design. An incorrect layout could cause converter
instability, load regulation problems, noise, and EMI issues. Especially with a switching dc-dc converter at high
load currents, too-thin PCB traces can cause significant voltage spikes. Good grounding becomes important as
well. If possible, a common ground plane to minimize ground shifts between analog (GND) and power ground
(PGND) is recommended. Additionally, the following PCB design layout guidelines are recommended for the
TPS65161:
1. Separate the power supply traces for AVIN and VINB, and use separate bypass capacitors.
2. Use a short and wide trace to connect the OS pin to the output of the boost converter.
3. To minimize noise coupling into the OS pin, use a 470-pF bypass capacitor to GND.
4. Place the rectifier diode of the step down converter as close as possible to the SWB pin.
5. Use short traces for the charge-pump drive pins (DRN, DRP) of VGH and VGL because these traces carry
switching waveforms.
6. Place a 1-µF bypass capacitor from the SUP pin to GND.
7. Place the flying capacitors as close as possible to the DRP and DRN pin, avoiding a high voltage spike at
these pins.
8. Place the Schottky diodes as close as possible to the IC, respective to the flying capacitors connected to the
DRP and DRN.
9. Route the feedback network of the negative charge pump away from the drive pin traces (DRN) of the
negative charge pump. This avoids parasitic coupling into the feedback network of the negative charge
pump giving good output voltage accuracy and load regulation. To do this, use the FREQ pin and trace to
isolate DRN from FBN.
APPLICATION INFORMATION
L1 D1 Vs
10 μH SL22 15 V/1.5 A
Vin
12 V
C1
2 * 22 μF C4 R1
C3 TPS65161 C2
4 22 pF 680 kΩ
1 μF 8 3 * 22 μF
SUP SW
12 5
FREQ SW
20 1 C15 R2
VINB FB 56 kΩ
21 3 470 nF
VINB OS
22 23 D4
C16 AVIN GND
1 μF 16 27
EN1 GD GD D5
VGL C6 9 10 C5 0.47 μF VGH
−5 V/50 mA D2 0.47 μF EN2 DRP 26 V/50 mA
11 14
DRN FBP
13 17 R5
FBN Boot C13
D3 24 18 909 kΩ 0.47 μF
R3 REF SWB
C7 6 19
0.47 μF 620 kΩ PGND NC
7 15
PGND FBB
28 2 R6
SS COMP Cb 44.2 kΩ
R4 25 26
DLY1 DLY2 100 nF
150 kΩ
L2 Vlogic
C17 3.3 V/2.3 A
C9 C10 C11 22 nF 15 μH
C8 10 nF
220 nF 22 nF 10 nF
D6 R7 C14 C12
SL22 2 kΩ 10 nF 2 * 22 μF
R8
1.2 kΩ
L1 D1 Vs
10 μH SL22 18 V/1.3 A
Vin
12 V
C1
2 * 22 μF C4 R1
C3 TPS65161 C2
4 22 pF 825 kΩ
1 μF 8 3 * 22 μF
SUP SW
12 5
FREQ SW
20 1 C15 R2
VINB FB 56 kΩ
21 3 470 nF
VINB OS
22 23 D4
C16 AVIN GND
1 μF 16 27
EN1 GD GD D5
VGL C6 9 10 C5 0.47 μF VGH
−5 V/50 mA D2 0.47 μF EN2 DRP 32 V/50 mA
11 14
DRN FBP
13 17 R5
FBN Boot C13
D3 24 18 560 kΩ 0.47 μF
R3 REF SWB
C7 6 19
0.47 μF 620 kΩ PGND NC
7 15
PGND FBB
28 2 R6
SS COMP Cb 22 kΩ
R4 25 26
DLY1 DLY2 100 nF
150 kΩ
L2 Vlogic
C17 3.3 V/2.3 A
C9 C10 C11 22 nF 15 μH
C8 10 nF
220 nF 22 nF 10 nF
D6 R7 C14 C12
SL22 2 kΩ 10 nF 2 * 22 μF
R8
1.2 kΩ
L1 D1 Vs
Vin
12 V 10 µH SL22 SI2343 18 V/1.3 A
C18 R9
C1 C4 R1 220 nF 510 C19
2*22 µF C3 TPS65161 22 pF C2 kΩ
1 µF
1 µF SUP SW 825 kΩ 3* 22 µF
FREQ SW R10
FB C15 R2 100 kΩ
VINB D4
470 nF 56 kΩ
VINB OS GD
C16 AVIN GND C5
1 µF C6 EN1 GD GD 0.47 µF D5
VGL VGH
D2 0.47µF EN2 DRP
–5 V/50 mA 32 V/50 mA
DRN FBP
D3 FBN Boot R5 C13
REF SWB 560 kΩ 0.47 µF
C7 R3
0.47 µF 620 kΩ PGND NC
PGND FBB
R6
SS COMP
R4 Cb 22 kΩ
DLY1 DLY2
150 kΩ 100 nF
C17 L2
C9 22nF 15 µH Vlogic
C8 C10 C11
10 nF 3.3 V/2.3 A
220 nF 22 nF 10 nF
D6 C14
SL22 R7 C12
2 kΩ 10 nF 2*22 µF
R8
1.2 kΩ
Figure 21. Standard 12-V to 18-V Conversion Using an External Isolation MOSFET to Isolate Vs as well
as VGH
Vin L1 D1 Vs
12 V 10% 6.9 μH SL22 13.5 V/2 A
C1
2 * 22 μF C4 R1
C3 TPS65161 22 pF 820 kΩ C2
1 μF 8 4 3 * 22 μF
SUP SW
12 5
FREQ SW
20 1 C15 R2
VINB FB
21 3 470 nF 75 kΩ
VINB OS D4
22 23
C16 AVIN GND
1 μF 16 27 VGH
C6 EN1 GD GD D5 23 V/50 mA
VGL 9 10 C5 0.47 μF
−5 V/50 mA D2 0.47 μF EN2 DRP
11 14
DRN FBP
13 17 R5
D3 FBN Boot C13
24 18 1 MΩ
R3 SWB 0.47 μF
C7 620 kΩ 6 REF 19
0.47 μF PGND NC
7 15 R6
PGND FBB
28 2 76 kΩ
COMP
R4 25 SS 26 Cb
DLY1 DLY2 100 nF
150 kΩ
C17 L2 Vlogic
22 nF 15 μH 3.3 V/2.3 A
C8 C9 C10 C11
220 nF 22 nF 10 nF 10 nF
D6 R7 C14
SL22 2 kΩ 10 nF C12
2 * 22 μF
R8
1.2 kΩ
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