Paper On Power Factor Correction
Paper On Power Factor Correction
Paper On Power Factor Correction
MMCOE, Pune MMCOE, Pune MMCOE, Pune Asst. Prof, MMCOE, Pune
1. ABSTRACT
The novel model presented in this paper is used for correcting the power factor. The model is able to
work in both ways automatically as well as manually. The model is designed for an inductive load. Various
combination of capacitive banks are used according to the load. The model gives maximum of 0.95 power
factor. The appropriate combination of capacitor bank is selected by the microprocessor. The suggested model
gives a 3-stage power factor compensation.
2. INTRODUCTION
India is facing a big problem when it comes to supply of electricity to each village. So
in this situation, wasting of electricity power is undesirable. One of the major reason for
wastage of electrical power is low power factor. Power factor is nothing but the ratio of two
quantities i,e real power (Kw) and apparent power (Kvar). Less the ratio i,e power factor,
more will be the losses. Also it should not exceed the unity. As it responsible for loss. Most
of the inductive as well as domestic load is inductive which is responsible for low power
factor.
The electric machine like induction motor, transform, induction generator is major
source of inductive load which contributes to power factor less than unity. These inductive
loads are usually varying. This problem can be solved by connecting a capacitor bank in
parallel withsupply side. The suggested model compensates power factor from 0.75 to 0.95
for load of 18 Kw. This is done by switching 3 capacitor bank of rating- 2Kvar, 3Kvar,
5Kvar.
3. LITERATURE SURVEY
A capacitive load will be added to the actual load and thus convert the final output
power and hence power factor will be improved. The power factor is monitored manually by
referring the display on LCD panel [3].
Fig 1. Block diagram of a three stage capacitor bank power factor correcting device
The capacitor bank is selected based on current and voltage of main supply side. The
system selects the appropriate capacitor by giving signal to the corresponding contactor after
sensing of change in pf. Circuit breakers is employed for protection purpose. The CT will
sense the current and the data are fed to microprocessor. An arrangement for manual
selection of capacitor bank is also provided. The single line diagram for power factor
correction
Fig. 2: Single Line Diagram for 10 kVAR
The proposed system was tested and following results were obtained
Before After
p1
f
0.9
0.8
0.7
0.6
0.5 Before
0.4 After
0.3
0.2
0.1
0
5.1 8.3 9.95 kVAR
According to result given by system it is observed that as power factor increases the required
kVAR, which is to be minimised from the actual load, is increased.
Fig 6. Hardware implementation
6. Conclusion:
7. Future Scope:
The number of stages can be increased to give more accurate result. The proposed
model is capable of having 6 stages capacitor bank variations. The stepped variations of
capacitor bank can be modified to get smooth control.
8. References:
1. Rekendu Mandal; Sanjoy Kumar Basu; Asim Kar; Shyam Pada Chowdhary (1994)
“A Microcomputer – Based Power Factor Correction”, IEEE Transactions on
Industrial Electronics, Volume: 41, Issue: 3, Pages: 361-371.
2. Mr. A Kumar Tiwari ,“Automatic Power Factor correction using Capacitive bank” ,
Int. Journal of Engineering Research and Application ISSN: 2248-9622,Vol 2,Feb
2014
3. Praveen V.A.,“Automatic Power Factor correction Using Capacitor Bank and 8051
Microcontroller” Int. journal Engineering research and technology (IJIERT),ISSN:
2394-3696
4. Saurabh Kumar Sharma; Gaurav Kumar Sharma; Abhijeet Sharama, “A Review
Paper on Automatic Power factor Correction”, 2018 IJCRT,Volume 6, Issue 2 April
2018, ISSN: 2320-2882