DSP Selection Guide1

XtremeDSP Solutions
Selection Guide
June 2008
Introduction
Contents
DSP System Solutions..................4
DSP Devices.................................17
Development Tools.....................25
Complementary Solutions...........33
Resources....................................35
2 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

Introduction
A New Era of Signal Processing

Highest Performance FPGAs Why use FPGAs for Signal Processing?
For

Signal Processing There are five main benefits of using FPGAs for DSP applications.
It is no accident that Xilinx FPGAs serve an increasingly
1. Ability to handle very high computational workloads – FPGAs allow you to build highly
vital role in the design and development of today’s most
parallel architectures thereby allowing your sample rate to equal your clock rate. The
demanding digital signal processing (DSP) systems. benefit is systems with performance levels up to 500MSPS. This level of performance is
Superior performance, system-level cost- and power- ideal for building very fast single channel systems or slower rate systems that comprise
efficiency, faster time to market and unrivaled flexibility hundreds of channels.
are the hallmarks of FPGA-based DSP designs – value 2. Offload compute intensive tasks from your DSP processor and save valuable cycles for
propositions that havefound increasingly appreciative implementing other functions.
reception among leaders in markets like the communi-
3. Customize your architecture to suit your ideal algorithm – With FPGAs you have an
cations industry. array of MACs or multipliers to implement single or multi-tap architectures. The
Driven by the global demand for higher quality, reconfigurable nature of FPGAs means that once you have developed your algorithm,
higher bandwidth, and inexpensive wired and wireless you can construct the ideal architecture to implement the algorithm.
communications of voice, computer, and video data, 4. Reduce system cost – FPGAs allow you to integrate other components you will need in
the number and complexity of new communications your system and hence reduce the overall system cost. Examples include Serial RapidIO
standards has grown exponentially. This is due in large transceivers, PCI Express interfaces, glue logic and low rate control tasks.
part to the need for interoperability and data exchange 5. Power Efficiency – FPGAs deliver lowest power for high sample rate per GMAC. This will
across myriad layers of legacy and next-generation enable you to reduce Op-Ex cost of the system.
networks. Keeping pace with these standards and
the extremely critical price/performance/power ratios
Why FPGAs for DSP?
High Computational Workloads
they pose has been anything but trivial for system
vendors. Nonetheless, the flux continues to produce
opportunities for industrious innovators willing to
tackle the challenge.
In the dynamic markets served by high-performance
DSP solutions, the inherent flexibility of the FPGA
equates to:
• Faster time to market with leading-edge algorithmic-
solutions and standards implementations
• Easy-to-perform in situ remote adaptation to unfore
seenenvironmental and functional changes (and
therefore reduced operational costs)
• Extended life cycles for existing designs (and therefor-
ereduced capital expenditures)
• The perfect platform for innovative product design
and migration to keep pace with changing customer “Today, FPGAs play an increasing role in a wide range of DSP applications. We expect this trend to
demands and market requirements continue over the next several years”.
BDTI’s Analysis in their report “FPGAs for DSP”
June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 3

DSP System Solutions
Digital Communications
Wireless/Wired Communication Systems Overview
Example: Wireless Base Station

Target Applications
Use the new XtremeDSP
• 3G/4G Base Stations slices to efficiently
implement:
• Software Defined Radio
• Digital Radio Functions
• Smart Antenna Systems Narrowband
Digital Radio Card • Baseband Functions
• Telecoms Infrastructure • Spectrum
Channelization
• Satellite Broadcasting Systems XtremeDSP slices are
• DDC
used in the receive path
• Digital Audio Broadcasting Spread Spectrum
• Polyphase Transform (shown adjacent) and the
(eg. 3GPP2) • Matched Filter transmit path for
• Digital Video Broadcasting
corresponding transmit
• Fixed/mobile Wireless functions
Broadband
Multi-Carrier
Wireless/Wired DSP for Digital Communications

Xilinx FPGAs are widely used for performing signal processing tasks in
Communication Systems Overview
digital communication systems. The diagram above demonstrates
Wireless communication is experiencing rapid growth world-wide. some of these applications.
Channel bandwidth and power constraints, coupled with the
requirement for high data-rate transmission are driving system
designers to employ increasingly sophisticated signal processing
techniques to keep pace. These techniques require the need for
very high performance signal processing resources to deal with
transporting and processing digital information such as com- The Xilinx XtremeDSP IP portfolio for digital communications
pressed speech, audio, image and video reliably from a transmit provides a rich set of algorithms to support the development of
source to receivers. today’s advanced digital communication systems. For such systems,
Digital communications systems employ various transmission Xilinx FPGAs allow the integration of multiple channels on a single
schemes based on the transmission media, available bandwidth, device to reduce BOM cost and drive up channel density while
required bit-error-rate and communication latency. Xilinx FPGAs’ reducing power per channel.
ability to process sample rates in the hundreds of mega samples per The reconfigurable nature of Xilinx FPGAs also allows
second range provide the signal processing capability necessary to developers to future-proof designs through in-field upgradeability,
efficiently meet the demands of many RF and IF functions in and save thousands of dollars in maintenance costs.
narrow band, spread spectrum and multi-carrier systems. High performance signal processing, flexibility and upgradeability
make FPGAs the ideal choice for today’s wireless and wired
infrastructure applications.

Xilinx DSP Benefits for Digital Communication IP LogiCORE AllianceCORE Vendor

Communications Filters
• Solutions capable of handling sample FIR Filter Compiler 4
rates in radio, IF and base band stages Cascaded Integrator Comb (CIC) 4
of transmit and receive chains MAC FIR Filter 4

FIR Filter using DPRAM 4 eInfochips Inc.
•M ulti-channel support available on one
FIR Filter, Parallel Distributed Arithmetic 4 eInfochips Inc.
chip, with parameterizable IP cores Building Blocks
supporting digital communication Complex Multiplier 4
readily available CORDIC 4
• Very low power and cost per channel Multiplier Accumulator 4

Multiply Generator 4
• L ow risk through reprogrammability
Pipelined Divider 4
that provides flexibility for faster time- Sine Cosine Look Up Table 4
to-market and longer time-in-market Transform
FFT up to 64K point 4
FFT, Pipelined (Vectis-QuadSpeed) 4 RF Engines, Ltd.
DSP Algorithms for Digital FFT, Pipelined (Vectis HiSpeed) 4 RF Engines, Ltd.
Communications Modulation/Demodulation
The Xilinx CORE Generator™ system Digital Down Converter (DDC) 4
generates parameterizable algorithms Digital Up Converter (DUC) 4
(delivered as fully supported IP cores) that Direct Digital Synthesizer 4
are optimized for Xilinx FPGAs. Exploiting Digital Down Converter, High-Speed Wideband (4954-422) 4 Pentek, Inc.
these parameters allows you to make tradeoffs Digital Down Converter, Wideband (4954-421) 4 Pentek, Inc.
between performance and silicon area so DVB Satellite Modulator (MC-XIL-DVBMOD) 4 Avnet
that you can develop the ideal architecture to Compression
suit your algorithms. Use the Xilinx CORE 1-D Discrete Cosine Transform 4
Generator to design high-density designs in 2-D Discrete Cosine Transform (DCT) 4
Xilinx FPGAs and achieve high performance ADPCM, 1024 Channel Simplex (CS4190) 4 Amphion Semiconductor, Ltd.
results while also cutting your design time. ADPCM, 128 Simplex (CS4125) 4 Amphion Semiconductor, Ltd.
ADPCM, 16 Simplex (CS4110) 4 Amphion Semiconductor, Ltd.
The Xilinx CORE Generator system is included
ADPCM, 256 Channel Simplex (CS4130) 4 Amphion Semiconductor, Ltd.
in the ISE™ Foundation™ Design Tool and
ADPCM, 512 Channel Duplex (CS4180) 4 Amphion Semiconductor, Ltd.
comes with an extensive library of Xilinx
Discrete Cosine Transform (eDCT) 4 eInfochips Inc.
LogiCORE™ IP. These include DSP functions,
Discrete Cosine Transform, 2D Inverse (IDCT) 4 CAST, Inc.
memories, storage elements, math functions
Discrete Cosine Transform, Combined 2D Forward/Inverse (DCT_FI) 4 CAST, Inc.
and a variety of basic elements. Evaluation
Discrete Cosine Transform, Forward 2D (DCT) 4 CAST, Inc.
versions of more complex system level cores,
Discrete Wavelet Transform, Combined 2D Forward/Inverse (RC_2DDWT) 4 CAST, Inc.
which can be purchased separately, are also
Discrete Wavelet Transform, Line-based programmable forward (LB_2DFDWT) 4 CAST, Inc.
included. Use Xilinx IP to accelerate your time Discrete Wavelet Transform (BA113FDWT) 4 Barco-Silex
to market with pre-verified IP core functions Discrete Cosine Transform, forward/inverse 2D (DCT/IDCT 2D) 4 Barco-Silex
optimized by expert designers. Discrete Wavelet Transform, Inverse (BA114IDWT) 4 Barco-Silex
AllianceCORE™ products are intellectual Radar Pulse Compression (4954-440) 4 Pentek, Inc.
property (IP) cores that are developed, sold
and supported by our third-party Global
Alliance Partners. AllianceCORE certification
provides a showcase for the most popular IP
cores offered.

Communication IP (Cont’d) LogiCORE AllianceCORE Vendor The Xilinx CORE

Error Correction
Additive White Gaussian Noise (noise source) 4 Generator is included
Convolutional Encoder 4
Interleaver / De-interleaver 4 in the ISE Foundation
Reed-Solomon Decoder 4
Reed-Solomon Encoder 4 Design Tool and
Turbo Convolutional Code Decoder, CDMA2000/3GPP2 4
Turbo Convolutional Code Encoder, CDMA2000/3GPP2 4 comes with an
UMTS/3GPP Turbo Convolutional Decoder 4
UMTS/3GPP Turbo Convolutional Encoder 4 extensive library
IEEE 802.16 TPC Encoder 4
IEEE 802.16 TPC Decoder 4 of Xilinx LogiCORE IP.
IEEE 802.16 CTC Encoder 4
IEEE 802.16 CTC Decoder 4
Viterbi Decoder 4
Viterbi Decoder, (IEEE 802-Compatible) 4
Reed Solomon Decoder (MC-XIL-RSDEC) 4 Avnet
Reed Solomon Encoder (MC-XIL-RSENC) 4 Avnet
Turbo Decoder, 3GPP 4 SysOnChip, Inc. CORE Generator software
Turbo Decoder, 3GPP (S3000) 4 iCoding Technology, Inc.
Turbo Decoder, DVB-RCS (S2000) 4 iCoding Technology, Inc. can be accessed from DSP
Turbo Decoder, DVB-RCS (TC1000) 4 TurboConcept
Turbo Encoder, DVB-RCS (S2001) 4 iCoding Technology, Inc. design tools such as
Turbo Product Code Decoder, 160 Mbps (TC3404) 4 TurboConcept
System Generator for DSP.
DVB-S.2 Forward Error Correction Encoder 4
Cable Modem
183 Universal Modulator Annex A/C 4 Multi Video Designs
183 Universal Modulator Annex B 4 Multi Video Designs
Arithmetic
Floating-Point Operator 4
Reference Design Matrix Digital Communication Reference Designs Xilinx Alliance Partners Vendor
Xilinx also provides “unsupported” Wireless
reference designs to help developers and Open Base Station Architecture Initiative (OBSAI) RP3 4
innovators implement solutions and test Common Public Radio Interface (CPRI) 4
concepts. Reference designs are deliv- External Memory Interface (EMIF) 4
ered in multiple formats such as System Random Access Channel (RACH) 4
Generator models or netlists. Searcher 4

High Speed Downlink Packet Access (HSDPA) 4
HSDPA-Symbol Rate HS-DSCH 4
Crest Factor Reduction (UMTS) 4
Digital Up Conversion (DUC) 4
Digital Down Conversion (DDC) 4
WCDMA/WiMax 4 Axis Network Tech.
Wired
MultiBERT 4
Gigabit System 4
Queue Manager 4
Ethernet Aggregation 4
Mesh Fabric 4

Wireless/Wired Application Notes Application Note Literature Number

Jump start your design with Xilinx application CDMA2000 and UMTS DUC/DDC implementations for Spartan3/3E XAPP569
WCDMA Reference Design XAPP921c
notes that describe specific design examples
Implementing an ADSL to USB Interface Using Spartan Devices XAPP171
and methodologies. These application Common Switch Interface CSIX-L1 Reference Design XAPP289
notes prove very helpful in saving valuable Implementing an ISDN PCMCIA Modem Using Spartan Devices XAPP170
time in the design process allowing you to CDMA Matched Filter Implementation in Virtex Devices XAPP212
concentrate on differentiating your product Configurable LocalLink CRC Reference Design XAPP562
in the marketplace. Mixed-Version IP Router (MIR) XAPP655

LFSRs as Functional Blocks in Wireless Applications XAPP220
Digital Up and Down Converters for the CDMA2000 and UMTS Base Stations XAPP569
XtremeDSP Development Kit High-Speed DES and Triple DES Encryptor/Decryptor XAPP270
with System Generator for DSP Mesh Fabric Reference Design XAPP698
Developed in collaboration with Nallatech, MultiBERT IP Toolkit for Serial Backplane Signal Integrity Validation XAPP537
the FPGA computing solutions company, the Queue Manager Reference Design XAPP511
SONET Rate Conversion in Virtex-II Pro Devices XAPP649
XtremeDSP Development Kit provides a
SONET and OTN Scramblers/Descramblers XAPP651
complete platform for high-performance Word Alignment and SONET/SDH Deframing XAPP652
signal processing applications such as Dynamic Reconfiguration of RocketIO MGT Attributes XAPP660
Software Defined Radio, 3G Wireless, etc. RocketIO Transceiver Bit-Error Rate Tester XAPP661
The development board works seamlessly In-Circuit Partial Reconfiguration of RocketIO Attributes XAPP662
with the Xilinx System Generator for DSP An Overview of Multiple CAM Designs in Virtex Family Devices XAPP201
Content Addressable Memory (CAM) in ATM Applications XAPP202
tool and allows you to perform hardware-
Designing Flexible, Fast CAMs with Virtex Family FPGAs XAPP203
in-the-loop co-simulation so that you can Using Block RAM for High Performance Read/Write CAMs XAPP204
verify your design running on the FPGA High Performance TCP/IP on Xilinx FPGA Devices Using the Treck Embedded TCP/IP Stack XAPP546
itself. Interface to the PC is via PCI bus Virtex-II SiberBridge XAPP254
allowing for high bandwidth co-simulation. High Performance Multi-Port Memory Controller XAPP535
Gigabit System Reference Design XAPP536
644-Mhz SDR LVDS Transmitter/Receiver XAPP622
FPGA Interface to the TMSC6000 DSP Platform Using EMIF XAPP753
Gigabit Ethernet Aggregation to SPI-4.2 with Optional GFP-F Adaptation XAPP695
Configurable Physical Coding Sublayer XAPP759
PN Generators Using the SRL Macro XAPP211
Hardware Acceleration of 3GPP Turbo Encoder/Decoder BER Measurement Using System Generator XAPP948
PowerPC Processor with Floating Point Unit for Virtex-4 FX Devices XAPP547
Continuously Variable Fractional Rate Decimator – Under Literature Column XAPP936
Description Part Number

Hardware Development Tools
HW-AFX-FF672-300 Proto Board HW-AFX-FF672-300
HW-AFX-FF1152-300 Proto Board HW-AFX-FF1152-300
XtremeDSP Development Kit for Virtex-4 DO-DI-DSP-DK4
Hardware and Software
XtremeDSP Development Kit for Virtex-II Pro DO-DI-DSP-DK2PRO
Development Tools Virtex-II Pro ML300 Evaluation Platform DO-V2P-ML300
Xilinx has a wide range of development tools Virtex-4 ML403 Embedded Platform HW-V4-ML403
Virtex-4 ML402 SX XtremeDSP Evaluation Platform HW-V4-ML402
available that enable quick movement through Virtex-4 ML461 Advanced memory Development System HW-V4-ML461
the DSP-based application design process. Spartan-3 Starter Kit DO-SPAR3-DK
These development tools are designed to 2VP50 PICMG ATCA Design Kit ADS-XLX-ATCA-DEVP50
2VP70 PICMG ATCA Design Kit ADS-XLX-ATCA-DEVP70
enable developers and innovators to bring
JTAG Emulators
new products to market fast and turn ideas Parallel Cable IV HW-PC4
into reality. Platform Cable USB HW-USB
Software Development Tools
ISE Foundation
System Generator for DSP DS-SYSGEN-4SL-PC
2VP70 PICMG ATCA Design Kit ADS-XLX-ATCA-DEVP50
AccelDSP Synthesis
Development Option, AccelDSP Synthesis DO-ACDSP-F-PC
Development Option, AccelWare Communications Toolkit DO-AWCMT-F-PC
Development Option, AccelWare Advanced Math Toolkit DO-AWAMT-F-PC
Development Option, AccelDSP Synthesis with AccelWare DSP IP Toolkits DO-ACALL-F-PC

Multimedia Video and Imaging (MVI)

MVI Systems Overview
Target Applications Digital Video Systems Overview Performance and flexibility allow
• AV Professional Broadcast The MVI market is enjoying enormous developers to future-proof designs now, to
• Medical Imaging growth as video and imaging technologies meet the challenges of the future simply as
are becoming pervasive in all aspects of life. well as opportunities to beat competition to
• IP TV set-top boxes From digital TV to video conferencing to market.
• Home media gateways video on mobile phones, MVI technologies Xilinx offers a number of products
• Video on Demand servers are enabling new applications everywhere. including hardware, IP and integrated system
The growth is fuelled by the emergence of solutions that are perfect for digital video
• Multi-channel digital video
new compression and encryption standards applications. Numerous hardware boards
recorder (DVR)
which make it possible to securely trans- are available to get you jump started. These
• Video conference gateways mit video from producer to consumer over boards allow you to create designs even
• Digital TV and servers head-ends broadband or wireless services. These new before the actual hardware board is ready.
standards come at a price however. The new In addition, these boards provide the flex-
• Set-top boxes
generation of CODECs require vastly more ibility to upgrade evolving digital video
• Video surveillance processing power than the existing legacy standards during field test and reduce the
• IP-based Video conferencing systems and constantly evolving standards development time.
end-points and server increase the risk of product obsolescence.
Xilinx FPGAs provide the DSP performance Video Frame Buffer Controller
• Video Streaming
needed to address these markets within a Xilinx provides a Video Frame Buffer
future proof programmable architecture. Controller (VFBC) core that can be used
For example, the Virtex™-5 SXT plat- in video applications where the hardware
form can perform up to 352 GMACs, which control of 2D data is needed to achieve real
enables it to perform high quality/definition time operation. This is typical of motion
and multi-channel digital video system. estimation, video scaling, on-screen displays
and video capture used in video surveillance,
video conferencing and video broadcast.
DSP for MVI Applications

MVI technologies provide the
foundation to serve applications
in many markets. Whether you are
designing CAT scanners for imaging
or head-ends for broadcast systems,
Xilinx FPGAs provide the perfor-
mance you need.

Xilinx DSP Benefits for MVI Video & Imaging IP LogiCORE AllianceCORE Venue
Applications Color Space Conversion, RGB2YCrCb 4 CAST, Inc.

NTSC Color Separator (NTSC-COSEP) 4 Pinpoint Solutions, Inc.
• Solutions capable of handling high PCI to HDTV using FPGA and shared RAM 4 Colorado Electroni Product Design, Inc.
performance needed for real-time video SDVO: Next Generation High-Speed Serial Digital Video Interface 4 ExaLinx, Inc.
applications. Examples include high UXGA Video Controller, 1600x1200 4 Synchronous Design, Inc.
definition encoding, multiple video MPEG-2 HDTV I & P Encoder (DV1 HDTV) 4 Duma Video, Inc.
streaming channels and support for MPEG-2 SDTV I & P Encoder (DV1 SDTV) 4 Duma Video, Inc.
very high frame rates MPEG-2 Video Decoder (CS6651) 4 Amphion Semiconductor, Ltd
MPEG-4 Video Compression Decoder 4 4i2i Communications Ltd
• Very low power and cost per channel
MPEG-4 Video Compression Encoder 4 4i2i Communications Ltd
• Low risk through reprogrammability MPEG-4 Video Compression Decoder 4
that provides flexibility for faster time- MPEG-4 Video Compression Encoder 4
to-market and longer time-in-market MPEG-2 HD Decoder
JPEG Encoder
• Product differentiation through integrating
JPEG 2000 Decoder (BA111JPEG2000D) 4 Barco-Silex
other system features such as SDI interfaces
JPEG 2000 Encoder (BA112JPEG2000E) 4 Barco-Silex
for broadcast and Serial Rapid IO
JPEG Fast Codec (JPEG_FAST_C) 4 CAST, Inc.
JPEG 2000 Encoder (JPEG2K_E) 4 CAST, Inc.
JPEG, Fast color image decoder (FASTJPEG C DECODER) 4 Barco-Silex
MVI DSP Algorithms
JPEG, Fast Decoder (JPEG_FAST_D) 4 CAST, Inc.
The Xilinx CORE Generator software gener- JPEG, Fast Encoder (JPEG_FAST_E) 4 CAST, Inc.
ates parameterizable algorithms (delivered JPEG, Fast gray scale image decoder (FASTJPEG BW DECODER) 4 Barco-Silex
as IP cores) that are optimized for Xilinx JPEG, Motion Codec V1.0 (CS6190) 4 Amphion Semiconductor, Ltd
FPGAs. Exploiting these parameters allows JPEG, Motion Decoder (CS6150) 4 Amphion Semiconductor, Ltd
you to make tradeoffs between performance JPEG, Motion Encoder (CS6100) 4 Amphion Semiconductor, Ltd
and silicon area so that you can develop the Motion JPEG Decoder (JPEG Decoder) 4 4i2i Communications Ltd
ideal architecture to suit your algorithms. Motion JPEG Encoder (JPEG Encoder) 4 4i2i Communications Ltd
Use the Xilinx CORE Generator to design 1-D Discrete Cosine Transform 4
high-density designs in Xilinx FPGAs and 2-D Discrete Cosine Transform 4
achieve high-performance results while also 2-D Inverse Discrete Cosine Transform 4 CAST, Inc.
cutting your design time. Combined 2-D Forward/Inverse Discrete Cosine Transform 4 CAST, Inc.
The Xilinx CORE Generator system is 2-D Forward/Inverse Discrete Cosine Transform 4 Barco-Silex
included in the ISE Foundation Design Tool Discrete Cosine Transform (eDCT) 4 eInfochips Inc.
and comes with an extensive library of Xilinx Combined 2-D Forward/Inverse Discrete Wavelet Transform (RC_2DDWT) 4 CAST, Inc.
LogiCORE IP. These include DSP functions, Discrete Wavelet Transform (BA113FDWT) 4 Barco-Silex
memories, storage elements, math functions Discrete Wavelet Transform Inverse (BA114IDWT) 4 Barco-Silex
and a variety of basic elements. Evaluation Discrete Wavelet Transform Line-based programmable forward (LB 2DFDWT) 4 CAST, Inc.
H.264 Video Compression-MPEG-4/AVC Encoding 4 Ateme SA
versions of more complex system level cores,
Huffman Decoder (HUFFD) 4 CAST, Inc.
which can be purchased separately, are also
Compact Video Controller 4 Xylon d.o.o
included. Use Xilinx IP to accelerate your
time to market with pre-verified IP core
functions optimized by expert designers.
AllianceCORE products are intellectual
property (IP) cores that are developed, sold
and supported by our third-party Global
Alliance Partners. AllianceCORE certification
A rich library of algorithms
provides a showcase for the most popular IP
cores offered. for MVI applications

MVI Application Notes

Jump start your design with Xilinx application notes that describe
specific design examples and methodologies. These applications prove
very helpful in saving valuable time in the design process allowing you
to concentrate on differentiating your product in the marketplace.
Application Note Literature Number Description Part Number
Serial Digital Interface (SDI) Video Encoder XAPP298 Hardware Development Tools
Serial Digital Interface (SDI) Video Decoder XAPP288 Virtex-II XLVDS Demonstration Board HW-V2-XLVDS
I2C Video Peripheral Loader XAPP293
Virtex-4 ML403 Embedded Platform HW-V4-ML403
SDI : Ancillary Data & EDH Processor XAPP299
SDI : Physical Layer Implementation XAPP247
Spartan-3 Starter Kit DO-SPAR3-DK
DVB-ASI Physical Layer Implementation XAPP509 Video co-processing Kit XEVM642 HW-XEVM642-SX35
10 Gb/s Serial Digital Video Aggregation XAPP543 Video Starter Kit Virtex-4SX35 HW-V4SX35-VIDEO-SK1
Digital Video Test Pattern Generators XAPP248 JTAG Emulators
Virtex-EM FIR Filter for Video Applications v1.1 (10/00) XAPP241 Parallel Cable IV HW-PC4
Platform Cable USB HW-USB
Efficient Math for Video in Virtex Devices XAPP249
The Design of a Video Capture Board Using the Spartan Series XAPP172
ISE Foundation
Color Space Conversion: YCrCb to RGB XAPP283
Color Space Converter: RGB to YCbCr XAPP637 AccelChip DSP Synthesis
DCT - Transforming Image Blocks from Spatial Domain to Transform Domain XAPP610 Development Option, AccelDSP Synthesis DO-ACDSP-F-PC
IDCT - Transforming Image Blocks from Transform Domain to Spatial Domain XAPP611 Development Option, AccelWare Communications Toolkit DO-AWCMT-F-PC
HDTV Video Pattern Generator XAPP682 Development Option, AccelWare Advanced Math Toolkit DO-AWAMT-F-PC
Color-Space Converter: RGB to YCrCb XAPP930
Color-Space Converter: YCrCb to RGB XAPP931
Chroma Resampler XAPP932
Two-Dimensional Linear Filtering (2D FIR) XAPP933
Video Virtual Socket Architecture XAPP919
PowerPC Processor with Floating Point Unit for Virtex-4 Device XAPP547
MVI White Papers

The Digital Video White Papers provide a system level overview of
various end-equipment. The White papers contain supporting infor-
mation to aid your development process when using Xilinx products.
White Papers
Wavelet Characteristics – What Wavelet Should I Use
Minimum Multiplicative Complexity Implementation of the 2-D DCT using Xilinx FPGAs
Multirate Filters and Wavelets: From Theory to Implementation
Filtering in the Wavelet Transform Domain
Real Time Image Rotation and Resizing Algorithms and Implementations
FPGA Implementation of Adaptive Temporal Kalman Filter for Real Time Video Filtering
FPGA Implementation of a Nonlinear Two Dimensional Fuzzy Filter
FPGA Interpolators Using Polynomial Filters
Issues on Medical Image Enhancement
MVI Systems Hardware and Software Development Tools

Xilinx has a wide range of development tools available that enable
quick movement through the DSP-based application design process.
These development tools are designed to enable developers and inno-
vators to bring new products to market fast and turn ideas into reality.

XtremeDSP Video Starter Kit — Spartan-3A DSP Edition

The XtremeDSP Video Starter Kit — Spartan-3A Edition is a The Video Starter Kit includes the Xilinx design software tools
video development platform consisting of the Spartan-3A DSP Embedded Development Kit (EDK) and System Generator
3400 Development Platform, the FMC-Video daughter card and a for DSP that can be used to create video applications without
VGA camera. The Spartan-3A DSP 3400A development Platform, prior RTL knowledge or experience. Three reference designs
which can be purchased separately, is built around the Spartan- and a library of video IP are provided to jumpstart the devel-
3A DSP XC3SD3400A device that provides 126 embedded DSP opment process.
blocks for implementing high performance video processing
systems and co-processors and DVI in and DVI out video ports.
An FMC-Video daughter card is included and extends the video
capabilities of the Spartan-3A DSP 3400A development platform
to also include the following additional interfaces:
• DVI-I Input, both digital and analog
• Composite input
• S-video input
• 2 camera inputs
• Composite output
• S-video output
Performance Acceleration for DSP Video Processors

FPGAs are being used in many ways to complement DSP processors.
Examples include:
• Performance acceleration in the signal chain
• Connect directly to TI DSP Processor via EMIF or serial RapidIO
interface
• Consolidate system logic into FPGA
• Implement New Peripheral or bus interface using FPGA
ith over 350 GMACs of horsepower, Xilinx FPGAs can also be used
W
as pre-processors or post-processors for DSP processors like the Texas
Instruments DM642.
sing an FPGA co-processor, you can enhance the capabilities of your
U
DSP video co-processor in many ways including:
• Integrating more video channels
Benefits of using FPGAs as DSP co-processors
• Building advanced codecs (e.g. H.264) for video applications
• Increasing the resolution to support SD or HD rates
• Integrating more modes

Defense Systems
Defense Systems Overview
Defense Systems Overview to their parallel processing ability, thereby
Target Markets Defense communication and intelligence significantly reducing system cost and power
• Military Communications systems are migrating from legacy stovepipe consumption.
architectures to Software Defined Radios Electronics Countermeasures (EC) sys-
• Intelligence
(SDR) that can be dynamically reconfigured tems need to identify the signal of interest
• Electronic Warfare based on mission requirements. These SDR and jam it. These systems are required to
• Sensors platforms must support both legacy waveforms perform wideband digital down conver-
for voice and low-speed data as well as new sion, FFTs, signal detection, and target cor-
Target Applications wideband waveforms providing high-speed relation and may include electronic beam
data and multimedia content. This is enabled steering to optimize the jamming energy at
• Cognitive & Software Defined Radio
by new and extremely fast FPGAs, such as the the target receiver. Xilinx FPGAs are uniquely
• Military Satellite Terminals Virtex family, that are designed for reprogram- positioned to meet the DSP requirements
• Smart Antenna (Direction Finding/ mable, high performance, signal processing. demanded by EC.
Beam-forming) Phased Array Radar systems are required to With advanced process technology, Xilinx
• Communications Infrastructure perform many sophisticated signal processing high-density Virtex-5 FPGA devices makes
tasks, including wideband digital down conver- them low in static, dynamic and inrush
• Wideband Analysis
sion, channel equalization, beamforming and power, enabling customers to design systems
• Electronic Countermeasures pulse compression. While there are various with smaller supply circuitry and simpler sys-
• Radar silicon alternatives available for implement- tem thermal design, resulting in lower power
• Sonar ing these functions, such as DSP processors and system cost.
and General Purpose Processors (GPPs), often
Xilinx FPGAs are the preferred solution due
Building Cost and Power Efficient SDR

Xilinx FPGAs are commonly used in demanding applications such as these devices are highly suitable for many of today’s demanding
software defined radio (SDR). SDR solutions require high data sample real-time defense applications.
rates and channel integration, creating the need for very high- Xilinx has a wide range of enabling technologies that can help reduce
performance, yet fully programmable, digital signal processing designs the power consumption and cost of your system, an example of which
that are enabled by Virtex-5, Virtex-4, and Virtex-II Pro FPGAs. With is illustrated below.
over 350 GMACs of performance, the signal processing capability of
The dedicated resources model pictured above results in: The shared resources model pictured above is a more desirable
• Higher Power Cost modem architecture
• Limited Scalability • Lower Power Cost

• Greater Efficiency, Scalability

The SFF SDR Development Platform
The Small Form Factor (SFF) Software-defined Radio (SDR) • SFF SDR Evaluation module: a limited feature version of the SFF
Development Platform is a unique new product that addresses the SDR Development Platform for digital processing only, without
special portable SDR needs of military, public safety, and commer- conversion capabilities, the SCA framework, CORBA nor the
cial markets. It was designed around the TI TMS320DM6446 digital model-based design kit board support package.
media processor DSP and Xilinx Virtex-4 SX35 FPGA as a low-cost,
off-the-shelf, integrated hardware and software development solu- • SFF SCA Development Platform: SCA-enabled version of the SFF
tion for engineers who need a SCA-compliant low power coprocess- SDR Development Platform, with the first CORBA-enabled FPGA
ing modem development platform. This platform enables users to on an SCA platform.
experiment and make educated waveform partitioning decisions
based on power and performance while abstracting the complexities
of of the DSP/FPGA coprocessing interface.
The SFF SDR Development Platform is separated into three dis-

tinct modules — the Digital Processing Module, Data Conversion
Module, and RF Module — offering developers highly flexible devel-
opment capabilities.
The SFF SDR Development Platform is part of the SFF SDR family,
which also includes:
ITAR Compliance
Xilinx compliance with International Traffic in Capital Arms
Regulations (ITARs) meaning we can accept, develop and market
designs and products that meet the requirements as set out in the
Federal Code of Regulations. ITARs products can be handled by
U.S. citizens.

Xilinx DSP Benefits for Defense Systems Xilinx Algorithms

With 15+ years uninterrupted experience in the Defense The Xilinx CORE Generator software generates parameterizable
Industry, Xilinx understands the various dynamics and risks algorithms (delivered as fully supported IP cores) that are opti-
facing designers in the industry, including longer life cycles as mized for Xilinx FPGAs. Exploiting these parameters allows you to
well as substantial costs and loss of reputation associated with make tradeoffs between performance and silicon area so that
mission failure. you can develop the ideal architecture to suit your algorithms. Use
Xilinx’s focus is on providing solutions that address your the Xilinx CORE Generator System to design high-density designs in
SWAPC concerns - Size, Weight, And Power, and Cost. Xilinx Xilinx FPGAs and achieve high performance results while also
is combining innovative technologies, such as partial recon- cutting your design time.
figuration and SCA-enabled SoCs, with systems-level domain The Xilinx CORE Generator system is included in the ISE
expertise to identify ways to reduce SWAPC in your MILCOM, Foundation Design Tool and comes with an extensive library of
Intelligence, EW, radar or sonar system. Xilinx LogiCORE IP. These include DSP functions, memories,
The Xilinx XtremeDSP solution provides the performance, storage elements, math functions and a variety of basic elements.
flexibility, productivity as well as lower costs for long life cycle Evaluation versions of more complex system level cores, which can
applications you need. Parameterizable algorithms and third be purchased separately, are also included. Use Xilinx IP to acceler-
party development boards enable you to get to market quickly ate your time to market with pre-verified IP core functions optimized
by using proven technologies. by expert designers.
Elements of the XtremeDSP Solution that are particularly AllianceCORE products are intellectual property (IP) cores
suited for defense applications include: that are developed, sold and supported by our third-party Global
Alliance Partners. AllianceCORE certification provides a showcase
• Advanced FPGAs for signal processing that support
for the most popular IP cores offered.
- High-sample rate applications such as multi-channel
DUC/DDC for radar
- A combination of complex and real data types
- Integer and floating point data representa- Defense Systems IP LogiCORE AllianceCORE Vendor
tions and computation Filters
- Low enough power for handheld and Cascaded Integrator Comb (CIC) 4
manpack wideband SDR radios Distributed Arithmetic FIR Filter 4
- Partial reconfiguration that allows for MAC FIR Filter 4
more functionality to be time shared in FIR Filter using DPRAM 4 eInfochips Inc.
a smaller device, thus reducing system FIR Filter, Parallel Distributed Arithmetic 4 eInfochips Inc.
cost and power Building Blocks

Complex Multiplier 4
- Easy and efficient support for floating
CORDIC 4
point operations using 18x25 DSP48E
Multiplier Accumulator 4
slices (Virtex-5 only) algorithms
Multiply Generator 4
- Reprogramabality to reduce design risk Pipelined Divider 4
and lower field upgrade costs Sine Cosine Look Up Table 4
• World Class Development tools Transform
- Algorithms and IP cores for advanced 2-D Discrete Cosine Transform (DCT) 4
functions such as floating point FFTs for FFT up to 64K points 4
expanding dynamic range, working in FFT, Pipelined (Vectis-QuadSpeed) 4 RF Engines, Ltd.
high noise environments and sensitive FFT, Pipelined (Vectis HiSpeed) 4 RF Engines, Ltd.
processing applications Modulation/Demodulation

Digital Down Converter (DDC) 4
- Software tools that let you design in the
Digital Up Converter 4
language that best tackles the problem at
Direct Digital Synthesizer 4
hand. Examples include MATLAB®,
Digital Down Converter, High-Speed Wideband (4954-422) 4 Pentek, Inc.
Simulink®, VHDL, Verilog, RTL, C or a
Digital Down Converter, Wideband (4954-421) 4 Pentek, Inc.
combination of these
DVB Satellite Modulator (MC-XIL-DVBMOD) 4 Memec Design
- Development platforms such as JTRS SDR
kits that let you move rapidly from prototype
to production

Defense Systems IP (cont.) LogiCORE AllianceCORE Vendor

Compression
1-D Discrete Cosine Transform 4
2-D Discrete Cosine Transform (DCT) 4
ADPCM, 512 Channel Duplex (CS4180)
Discrete Cosine Transform (eDCT)
4
4
Amphion Semiconductor, Ltd.
eInfochips Inc.
Parameterizable
Discrete Cosine Transform, 2D Inverse (IDCT) 4 CAST, Inc.
Discrete Cosine Transform, Combined 2D Forward/Inverse (DCT_FI)
Discrete Cosine Transform, Forward 2D (DCT)
4
4
CAST, Inc.
CAST, Inc.
algorithms,
iscrete Wavelet Transform, Combined 2D
D
Forward/Inverse (RC_2DDWT)
iscrete Wavelet Transform, Line-based programmable
D
4 CAST, Inc.
and third party
forward (LB_2DFDWT) 4 CAST, Inc.
Discrete Wavelet Transform (BA113FDWT)
Discrete Cosine Transform, forward/inverse 2D (DCT/IDCT 2D)
4
4
Barco-Silex
Barco-Silex
development boards
Discrete Wavelet Transform, Inverse (BA114IDWT) 4 Barco-Silex
Radar Pulse Compression (4954-440)
Error Correction
4 Pentek, Inc.
enable you to
Additive White Gaussian Noise 4
Convolutional Encoder
Interleaver / De-interleaver
4
4
get to market
Reed-Solomon Decoder 4
Reed-Solomon Encoder
AEHF Turbo Convolutional Code Decoder
4
4
quickly by using
AEHF Turbo Convolutional Code Encoder 4
UMTS/3GPP Turbo Convolutional Decoder 4 proven technologies.
UMTS/3GPP Turbo Convolutional Encoder 4
IEEE 802.16 TPC Encoder 4
IEEE 802.16 TPC Decoder 4
Turbo Product Code (TPC) Decoder 4
Turbo Product Code (TPC) Encoder 4
Viterbi Decoder 4
Viterbi Decoder, (IEEE 802-Compatible) 4
Reed Solomon Decoder (MC-XIL-RSDEC) 4 Memec Design
Reed Solomon Encoder (MC-XIL-RSENC) 4 Memec Design
Turbo Decoder, 3GPP 4 SysOnChip, Inc.
Turbo Decoder, 3GPP (S3000) 4 iCoding Technology, Inc.
Turbo Decoder, DVB-RCS (S2000) 4 iCoding Technology, Inc.
Turbo Decoder, DVB-RCS (TC1000) 4 TurboConcept
Turbo Encoder, DVB-RCS (S2001) 4 iCoding Technology, Inc.
Arithmetic
Floating-Point Operator 4

Reference Designs Matrix Xilinx Everywhere Product Grades

Xilinx also provides unsupported reference designs to help developers and innovators imple- Xilinx supports the widest range of FPGAs
ment solutions quickly. Our reference designs include the documentation you need to reproduce for Aerospace and Defense in the industry.
designs. These reference designs have been built and tested as documented. Xilinx has solutions for the challenges facing
designers of aerospace and defense systems
Defense Systems Reference Designs Xilinx Alliance Partners Vendor
from space to base.
Analog and Signal Integrity Analysis for Flight Simulator 4 NUVATION
External Memory Interface (EMIF) 4 Xilinx offers a wide range of product
Complete Radar processing on single FPGA 4 Dillon Engineering, Inc grades: from commercial to Mil-Temp QPRO
devices. The Xilinx QPRO family addresses
Defense Systems Application Notes the issues that are critical to the aerospace
Jump start your design with Xilinx application notes that describe a specific design examples and and defense market:
methodologies. These applications prove very helpful in saving valuable time in the design process
• QML/Best commercial practices.
allowing you to concentrate on differentiating your product in the marketplace.
Commercial manufacturing strengths
Application Notes Literature Number result in more efficient process flows
Implementing an ADSL to USB Interface Using Spartan Devices XAPP171
Common Switch Interface CSIX-L1 Reference Design XAPP289 • Performance-based solutions, including
Implementing an ISDN PCMCIA Modem Using Spartan Devices XAPP170 cost-effective plastic packages
Gigabit System Reference Design XAPP536
PN Generators Using the SRL Macro XAPP211 • Reliability of supply. Controlled mask
CDMA Matched Filter Implementation in Virtex Devices XAPP212
sets and processes insure the same qual-
Configurable LocalLink CRC Reference Design XAPP562
Gold Code Generators in Virtex Devices XAPP217 ity devices, every time, without varia-
Mixed-Version IP Router (MIR) XAPP655 tion, which remain in production for an
LFSRs as Functional Blocks in Wireless Applications XAPP220 extended time
Digital Up and Down Converters for the CDMA2000 and UMTS Base Stations XAPP569
Two Flows for Partial Reconfiguration: Module Based or Difference Based XAPP290 • Off-the-shelf ASIC solutions. Standard
FPGA Interface to the TMSC6000 DSP Platform Using EMIF XAPP753
devices readily available, no need for
High –Speed DES and Triple DES Encryptor/Decryptor XAPP270
Partial Reconfiguration XAPP746 custom logic and gate arrays
RLDRAMII Memory Interface for Virtex-5 FPGAs XAPP852
Defense Systems Hardware and Software Development Tools

Xilinx has a wide range of development tools available that enable quick movement through
the DSP-based application design process. These development tools are designed to enable
developers and innovators to bring new products to market fast and turn ideas into reality.
XtremeDSP Development Kit for Virtex-II Pro DO-DI-DSP-DK2PRO
Virtex-II Pro ML300 Evaluation Platform DO-V2P-ML300
Virtex-4 ML403 Embedded Platform HW-V4-ML403
Virtex-5 SXT ML506 Evaluation Platform HW-V5-ML506-UNI-G
Virtex-4 ML461 Advanced Memory Development System HW-V4-ML461
Spartan-3 Starter Kit DO-SPAR3-DK
XtremeDSP Development Platform – Spartan-3A DSP 3400A Edition HW-SD3400A-DSP-DB-UNI-G
XtremeDSP Starter Platform – Spartan-3A DSP 1800A Edition HW-SD1800A-DSP-SB-UNI-GP
JTAG Emulators
Parallel Cable IV HW-PC4
ISE Foundation
AccelDSP Synthesis
Development Option, AccelWare Communications Toolkit DO-AWCMT-F-PC
Development Option, AccelWare Advanced Math Toolkit DO-AWAMT-F-PC

D S P D e v iC e s
XtremeDSP Devices
Overview
XtremeDSP Device portfolio fills the
performance gap created by the growth in
algorithmic complexity and limitation of
sequential processors in wireless, multimedia,
video imaging, and defense systems markets.
The XtremeDSP platform portfolio,
comprised of two series - Virtex-DSP and
Spartan-DSP, provides the range of price,
performance, power efficiency, bandwidth
and I/O to satisfy a broad spectrum of appli-
cation requirements within the communica-
tions, MVI (multimedia, video and imaging)
and Defense Systems.
*Algorithmic Complexity: - As demand for processing power rapidly increases, sequential processing cannot
Industry-Proven Highest
support algorithmic complexities within required response times. To overcome these architectural limita-
Performance DSP tions, the parallel processing offered by XtremeDSP devices is essential.
• Over 580 billion multiply-accumulate
operations per second (GMAC/s)
• Parallelism with distributed memory
enables sample rate to equal the clock rate -
up to 550 mega samples per second (MSPS)
in Virtex-5 SXT devices and 250 MSPS in
Spartan-3A DSP devices (slow speed grade)
• High internal memory bandwidth - 1.5 to
19.3 Gbps (not including distributed
memory)

D S P D e v iC e s
Virtex _ DSP Series Spartan _ DSP Series

Virtex _ DSP Series • Implements highly parallel architectures Spartan-DSP series includes the new
Virtex-DSP series includes recently for astounding DSP performance with Spartan-3A DSP platform consisting of 2
announced Virtex -5 platform based Virtex-5 the lowest cost and power per channel devices, the 3SD3400A and the SD1800A.
SXT family of devices, and Virtex-4 platform for complex systems Each device will be offered in 2 packages –
based Virtex- 4 SX based family of devices. • Incorporates up to 11.6 Mbits of embedded a space saving CS484 and a FG676 in both
BlockRAM and distributed RAM for the Pb and Pb-free.
Virtex-5 Platform Devices - Industry- highest memory-to-logic ratio for efficient
leading Performance and Connectivity memory-intensive functions required in Spartan-3A DSP Devices - Breakthrough
video processing and medical imaging. Price for High-Performance DSP
The new XtremeDSP DSP48E slice in our
flagship Virtex-5 SXT series facilitates faster The Spartan™-3A DSP device efficiently
• Includes low-power RocketIO™ GTP
and more optimized DSP functions. Virtex-5 balances three critical values - price,
transceivers (<100mW typical @ 3.2 Gbps),
SXT devices deliver the highest performance performance, and - for a host of
built-in PCI Express® endpoints and
for performance-centric or multi-channel applications.
Ethernet MAC blocks
solutions. It targets price and power efficiency-
The Virtex™-5 platforms meets the • Supports all major serial I/O protocols sensitive applications such as digital front-end
ultra-high digital signal processing (DSP) (PCIe®, CPRI, OBSAI, SRIO, GbE, and (DFE) and baseband solutions in a single-
bandwidth and lower system-cost require- XAUI) to provide the lowest power channel pico-cell wireless base station,military
ments of next-generation wireless, military/ solutions for building high-speed, high- mobile software-defined radios (SDRs),
aerospace and multi-media video applications: bandwidth connections between chips, ultrasound systems, driver assistance/media
boards, and boxes. systems, HD video and Smart IP cameras:
• Delivers over 528 GMACs at 550 MHz with
up to 1056 user-configurable DSP48E slices • Provides up to:
- Provides over 30 GMACS of performance
• Consumes 35 percent less dynamic power Virtex-4 Devices
enabled by up to 126 XtremeDSP
as compared to previous 90-nm devices. With up to 512 (18x18, 48-bit add) MACs
DSP48A Slices in a single device.
• Offers serial connectivity with low power each capable of operating at 500MHz, Virtex-4
- Up to 2,200 Mbps memory bandwidth
transceivers that operate up to 3.2 Gbps - FPGAs provide a 256 GMACs/s performance.
an industry first! In addition with a power of only 2.3 mW - Up to 53K logic cells
per 100 MHz per DSP slice, Virtex-4 FPGAs - Robust Memory:
• Boosts logic performance with 65-nm
ExpressFabric technology comprised of are ideal for applications that require many - Up to 2,268 Kb of Block RAM
up to 95K logic cells channels but have an imposed power budget. - Up to 373 Kb of Distributed RAM
- Power efficient devices
XtremeDSP Device Portfolio

Spartan-DSP Virtex-DSP
Spartan-3A DSP Virtex-4 SX Virtex-5 SXT
3SD1800A 3SD3400A 4VSX25 4VSX35 4VSX55 5VSX35T 5VSX50T 5VSX95T 5VSX240T

DSP Performance
(GMACS) 211 321 642 962 2562 1062 1582 3522 580
Max Block RAM Memory
Bandwidth (Gbps) 1,5121 2,2681 4,6082 6,9122 11,5202 6,6532 10,4542 19,3252 40,862
Max DSP
Frequency (MHz) 2501 2501 500 2 500 2 500 2 550 2 550 2 550 2 500
XtremeDSP
DSP48* Slices 84 126 128 192 512 192 288 640 1,056
Min Footprint (mm) 19x19 19x19 27x27 27x27 27x27 27x27 27x27 27x27 42.5x42.5
Distributed RAM (Kb) 260 373 160 240 384 520 780 1,520 4,200
Block RAM (Kb) 1,512 2,268 2,304 3,456 5,760 3,024 4,752 8,784 18,576
Logic Cells 37,440 53,712 23,040 34,560 55,296 34,816 52,224 94,208 239,616
180 x 1.25 Gb/s 240 x 1.25 Gb/s 320 x 1.25 Gb/s 320 x 1.25 Gb/s
High Speed
227 x 622+ Mb/s
213 x 622+ Mb/s 120 x 1+ Gb/s 224 x 1+ Gb/s 360 x 1+ Gb/s LVDS pairs, LVDS pairs, LVDS pairs LVDS pairs
Connectivity
LVDS pairs LVDS pairs LVDS pairs LVDS pairs LVDS pairs 8 x 3.2 Gb/s 12 x 3.2 Gb/s 16 x 3.2 Gb/s 16 x 3.2 Gb/s
Transceivers Transceivers Transceivers Transceivers
1
In Slow Speed Grade
2
In Fast Speed Grade
*
DSP48A, DSP48E, DSP48

D S P D e v iC e s
Virtex _ DSP Series for Signal Processing

Ultra High-Performance DSP
High Performance DSP
Virtex-5 SXT Devices Virtex-4 SX Family

Target Applications
The Virtex-5 SXT platform is ideal for designs The Xilinx Virtex-4 family has revolutionizing
•W
ireless Infrastructure (Smart antenna, that need ultra high performance DSP capa- the fundamentals of FPGA economics. With
Base-stations, Gateways) bility coupled with highest memory to logic three application-domain-optimized platforms
•W
ired Infrastructure (RAS, IPDSLAM, ratio. The Virtex-5 SXT platform features and a selection of seventeen devices, Virtex-4
VoIP, Soft switches) new DSP 48E platform features new DSP48E FPGAs deliver breakthrough perfor-
slices that comprise 18x25 multipliers that mance at the lowest cost.
•D
igital Video (Video surveillance,
Video conferencing, H.264 SD/HD provide expanded dynamic range and easier The Virtex-4 SX Platform provides blaz-
encode/decode) support for floating point operations. These ing DSP performance with unrivaled econo-
new slices also feature 48-bit adders and are my, with up to 512 DSP 48 slices, each capable
• Imaging (Medical, Machine) cascadable for building higher order filters of operating at 500 MHz throughput, for 256
•D
efense (Radar, Sonar, Military without utilizing fabric resources. DSP48E GMAC/second (18x18) performance. The
Communication Systems) slices also provide the best power efficiency Xilinx XtremeDSP solution helps accelerate
(only 1.38 mW per 100 MHz per slice) for your products to market with state-of-the-art
implementing scalable high-performance devices, design tools, intellectual property
Virtex-5 Family DSP structures in FPGAs. cores, and design services. This powerful
The Virtex-5 family of FPGAs offers a choice combination gives you the fastest means of
of four new platforms, each delivering an designing, verifying, and deploying your DSP
optimized balance of high-performance logic, algorithms and systems in FPGAs.
serial connectivity, signal processing, and
embedded processing. Three platforms are
available now:
• LX Optimized for high-performance logic
• LXT Optimized for high-performance
logic with low-power serial connectivity Virtex-4 & 5 Platforms
• SXT Optimized for DSP and memory Based on your system requirements, choose the
intensive applications with low-power platform that best fits the application.
serial connectivity .

DSP Devices
Spartan-3A DSP
Breakthrough Price for High-Performance DSP
Spartan-3A DSP
Target Applications
Breakthrough in Price for
High Performance DSP • Picocell /Femto Basestations
The new Spartan-3A DSP platform is • Video Surveillance
ideal for cost sensitive DSP algorithmic • Consumer Video
and co-processing applications requiring • Milcom Portable
significant DSP performance. The new
• Mounted Software Defined Radio
Spartan-3A DSP platform consists of
2 devices, the 3SD3400A and the
3SD1800A. The 3SD3400A delivers Spartan-3A DSP Product Table
over 30 GMAC/s (30 billion multiply
Spartan-3A DSP
accumulate operations per second) and XC3SD1800A XC3SD3400A
up to 2,200 Mbps memory bandwidth XtremeDSP DSP48A Slices 84 126
at a volume price starting at under $45* Dedicated Multipliers DSP48As DSP48As
Block RAM Blocks 84 126
while the 3SD1800A delivers over 20
Block RAM (Kb) 1,512 2,268
GMAC/s for under $30* in a small-foot- Distributed RAM (Kb) 260 373
print package. FFs/LUTs 33,280 47,744
Logic Cells 37,440 53,712
DCMs 8 8
Now Power Efficient Max Diff I/O Pairs 227 213
Introducing Spartan 3A DSP power CS484 19x19mm (0.8mm pitch) 309 309
efficient line of devices, these devices FG676 27x27mm (1.0mm pitch) 309 469
High Speed Connectivity 176 x 622+Mb/s LVDS pairs 208x622+ Mb/s LVDS pairs
deliver 4.06 GMACs per mW of high Low Power 4.06GMACs/mW 4.06GMACs/mW
performance signal processing capabil-
ity to competing devices in this class. Spartan-3A DSP Hardware, IP and Software
Spartan 3A DSP power efficient devices
deliver a 50% static power savings, and Hardware Development Tools
a 70% savings while in suspend mode, XtremeDSP Spartan-3A DSP development kit HW-S3-DSP-SK-UNI-G
compared to the non-low power devices. Parallel Cable IV HW-PC4
Dynamic power in Spartan-3A DSP Software Development Tools
devices is inherently low because of the ISE Foundation DS-ISE-FND
dedicated DSP 48A slices. AccelChip DSP Synthesis
Development option, AccelDSP Synthesis DO-ACDSP-F-PC
This represents an unprecedented
Development option, AccelWare Signal Communications Toolkit DO-AWCMT-F-PC
price/performance and power efficiency Development option, AccelWare Advanced Math Toolkit DO-AWAMT-F-PC
breakthrough that hits the mark for price Development option, AccelDSP Synthesis Tool with Accelware DSP IP Toolkits DO-ACALL-F-PC
and energy sensitive applications such
as digital front-end (DFE) and baseband
solutions in a single-channel pico-cell Spartan-3A DSP Literature and related
wireless base station, mobile tactical Technical documentation
radios, MILCOM portable, portable Data Sheets Literature Number
medical systems, driver assistance/media Spartan-3A DSP Data Sheet DS610
User’s Guides
systems, HD video and Smart IP cameras
XtremeDSP for Spartan-3A DSP users guide UG431
and motor/motion control. Product Brochures
XtremeDSP Portfolio Brochure
*25K units/yr in late 2008 Spartan 3 Generation Brochure PN 0010829 -1

D S P D e v iC e s
XtremeDSP DSP48 Slices
Overview
High performance XtremeDSP™ DSP48 slices XtremeDSP DSP48s brief comparison:
allow designers to implement multiple slower Function\Device family XtremeDSP DSP48A XtremeDSP DSP48 XtremeDSP DSP48E
operations using time-multiplexing methods. Spartan-3A DSP Virtex-4 Virtex-5
They provide: Multiplier 18 x 18 18 x 18 25 x 18
• Improved flexibility and utilization. Pre-adder Yes No No
Cascade inputs One One Two
• Improved application efficiency.
Cascade output Yes Yes Yes
• Reduced overall power consumption. Dedicated C input Yes No Yes
• Increased maximum frequency. Adder 2 input 48 bit 3 input 48 bit 3 input 48 bit
ALU logic functions No No Yes
• Reduced set-up plus clock-to-out time. Pattern detect No No Yes
• Support for many independent functions, SIMD ALU support No No Yes
including multiply, multiply accumulate Carry signals Carry in Carry in Carry in and out
(MACC), multiply add, three-input add, RTL support Main functions + pre-add Main functions Main functions
barrel shift, wide-bus multiplexing, magn-
tude comparator, bit-wise logic functions,
pattern detect, and wide counter.
• Support for cascading multiple XtremeDSP
DSP48 slices to form wide math functions, DSP XtremeDSP DSP48E Slice
filters, and complex arithmetic without
the use of general FPGA fabric.
XtremeDSP DSP48E Slices for the

Virtex-5 family:
DSP48E slices, available in all Virtex™-5
devices, accelerate algorithms and enable
higher levels of DSP integration and lower
power consumption than previous-generation
Virtex devices. They:
• Support over 40 dynamically controlled
operating modes including: multiplier,
multiplier-accumulator, multiplier
adder/subtractor, three input adder, barrel
shifter, wide bus multiplexers, wide counters,
and comparators.
• Enable efficient adder-chain architectures
for implementing high-performance filters
and complex math efficiently.
• Draw only 1.38 mW/100 MHz at a toggle
rate of 38% - a 40% reduction from
prevous-generation slices.

DSP Devices
XtremeDSP DSP48 Slices for the XtremeDSP DSP48E Feature Benefits

Virtex-4 family Feature Benefit
DSP48 slices are available in all Virtex-4
25-bit by 18-bit, two’s complement Enable higher precision for greater dynamic
family members to accelerate algorithms and
multiplier with full precision 48-bit result range, single-precision floating-point math,
solve complex DSP challenges. They provide: and wide filters with fewer slices.
• 500MHz performance independently or Enable three input, flexible 48-bit adder/

subtracter with optional registered
when combined within a column to imple- accumulation feedback.
ment DSP functions Enhanced second stage
Implement pattern detector for convergent rounding,
underflow/overflow detection for saturation arithmetic,
• 2.3 mW/100 MHz power consumption per and auto-resetting counters/accumulators.
slice, at a typical toggle rate of 38% Support SIMD operations.
• Support for over 40 dynamically controlled Adapt DSPE slice functions from clock cycle to
Over 40 dynamic user-controller operating modes
clock cycle.
operating modes including; multiplier,
18-bit B cascade routing Support input sample propagation.
multiplier-accumulator, multiplier adder/
subtracter, three input adder, barrel shifter, Enable advanced filter implementations and
New 30-bit A cascade routing
wide bus multiplexers, or wide counters reduce power.
Multiply, add, use large three-operand addition,

• DSP48 slice cascading without using device Independent, 48-bit C input or flexible rounding mode. Increase usability by
fabric or routing resources to perform wide eliminating sharing of C input across slices to
simplify design and increase performance.
math functions, DSP filters, and complex
arithmetic Cascading, 48-bit P bus Support output propagation of partial results.
XtremeDSP DSP48 Slice Highlights

• 18-bit by 18-bit, two’s complement
multiplier with full precision 36-bit result, XtremeDSP DSP48 Slice
sign extended to 48 bits
• Three input, flexible 48-bit adder/subtracter
with optional registered accumulation
feedback
• Over 40 dynamic user-controller operating
modes to adapt XtremeDSP Slice functions
from clock cycle to clock cycle
• Cascading, 18-bit B bus, supporting input
sample propagation
• Cascading, 48-bit P bus, supporting output
propagation of partial results
• Multi-precision multiplier and arithmetic
support with 17-bit operand right shift to
align wide multiplier partial products
(parallel or sequential multiplication)
• Symmetric intelligent rounding support
for greater computational accuracy
• Performance-enhancing pipeline options
for control and data signals are selectable
by configuration bits
• Input port “C” typically used for multiply,
add, large three-operand addition or flexible
rounding mode
• Separate reset and clock enable for control
and data registers

D S P D e v iC e s
XtremeDSP DSP48A Slice for the Spartan-3A DSP family
XtremeDSP DSP48A Slices for the XtremeDSP DSP48A Slice with Pre-adder
Spartan-3A DSP family
The 250 MHZ DSP48A Slice provides an
18-bit x 18-bit multiplier, 18-bit pre-adder,
48-bit post-adder/accumulator, and cascade
capabilities for various DSP applications.
XtremeDSP Slice Highlights

• 18-bit by 18-bit, two’s complement mult-
plier with full precision 36-bit result, sign
extended to 48 bits
• Pre-adder saves 9 logic slices per DSP48A used
• Two input, flexible 48-bit adder/subtracter
with optional registered accumulation
feedback
• Cascading, 18-bit B bus, supporting input Design Optimal FIR Filters Quickly
sample propagation The easiest way to implement designs to
• Cascading, 48-bit P bus, supporting output exploit the full power of the XtremeDSP
propagation of partial results Slices is to use the new FIR compiler or
the Xilinx System Generator for DSP design
• Multi-precision multiplier and arithmetic tool. The FIR compiler will help you to opti-
support with 17-bit operand right shift to mize performance, power and cost.
align wide multiplier partial products
(parallel or sequential multiplication)
• Symmetric intelligent rounding support for
greater computational accuracy
• Performance-enhancing pipeline options for
control and data signals are selectable by
configuration bits
• Input port “C” typically used for multiply,
add, large three-operand addition or flexible
rounding mode
• Separate reset and clock enable for control
and data registers

DSP Devices
Tools, Software and Support

Virtex-4 and Virtex-5 Platform Hardware and Virtex-5 & Virtex-4 Platform Literature and
Software Development Tools Related Technical Documentation
Xilinx has a wide range of development tools available that enable Data Sheets Literature Number
quick movement through the DSP-based application design process. Virtex-5 Family Overview DS100
These development tools are designed to enable developers and Virtex-5 DC and Switching Characteristics DS202
Virtex-4 Family Overview DS112
innovators to bring new products to market fast and turn ideas
Virtex-4 Data Sheet: DC and Switching Characteristics DS302
into reality. User’s Guides
Virtex-5 User Guide UG190
Description Part Number Virtex-5 XtremeDSP User Guide UG193
Virtex-5 Configuration User Guide UG191
Virtex-5 Packaging and Pinout Specification UG195
Virtex-5 RocketIO GTP Transceiver User Guide UG196
Virtex-5 ML506 Development Kit HW-V5-ML506-UNI-G
Virtex-5 PCI Express Endpoint Block User Guide UG197
Virtex-4 ML403 Embedded Platform HW-V4-ML403 Virtex-5 Embedded Tri-Mode Ethernet MAC User Guide UG194
Virtex-4 ML402 SX XtremeDSP Evaluation Platform HW-V4-ML402 Virtex-5 PCB Designer’s Guide UG203
JTAG Emulators Virtex-4 User Guide UG070
Parallel Cable IV HW-PC4 XtremeDSP Design Considerations User Guide UG073
Platform Cable USB HW-USB Virtex-4 Configuration Guide UG071
Software Development Tools Virtex-4 PCB Designer’s Guide UG072
ISE Foundation Virtex-4 Packaging and Pinout Specification UG075
Product Brochures
Virtex-5 Brochure pn0010938-3
AccelChip DSP Synthesis
Virtex-4 Brochure pn0010798
Virtex-4 EasyPath Brochure pn0010639
Development Option, AccelWare Communications Toolkit DO-AWCMT-F-PC DSP Solutions pn0010801
Development Option, AccelWare Signal Processing Toolkit DO-AWSPT-F-PC Virtex-4 Product Selector Guide Virtex4_color
Development Option, AccelWare Advanced Math Toolkit DO-AWAMT-F-PC Application Notes
Development Option, AccelDSP Synthesis with AccelWare DSP IP Toolkits DO-ACALL-F-PC Viterbi Decoder Block Decoding- Trellis Termination and Tail Biting XAPP551
Development Option, AccelDSP Synthesis with AccelWare DSP IP DO-ACALL-F-PC-EVAL Single Error Correction and Double Error Detection XAPP645
Toolkits Evaluation 3.3V PCI Design Guidelines XAPP653
Dynamic Phase Alignment for Networking Applications XAPP700
Memory Interface Data Capture Using Direct Clocking Technique XAPP701
DDR2 Controller Using Virtex-4 Devices XAPP702
QDR II SRAM Interface XAPP703
Virtex-4 High-Speed Single Data Rate LVDS Transceiver XAPP704
Virtex-4 High-Speed Dual Data Rate LVDS Transceiver XAPP705
Alpha Blending Two Data Streams Using a DSP48 DDR Technique XAPP706
DDR SDRAM Controller Using Virtex-4 Devices XAPP709
Synthesizable CIO DDR RLDRAM II Controller for Virtex-4 FPGAs XAPP710
Multiple Bit Error Correction XAPP715
Accelerated System Performance with the APU Controller and XAPP717
XtremeDSP Slices
Memory Interface Application Notes Overview XAPP802
Leveraging “In-System ECO” Capability of Spartan-3 and XAPP803
Virtex-4 EasyPath FPGAs

D E V ELO P MENT TOOL S _ H A R D W A R E
Hardware Development Kits

XtremeDSP Development Kit — Virtex-5 Edition
The Development Kit includes Xilinx System Generator for DSP that can be
used to create DSP designs using Simulink® from The Mathworks™ and to per-
form hardware-in-the-loop co-simulation so that you can verify your design
running on the FPGA itself. Interface to the PC is via PCI Express interface,
allowing for high bandwidth co-simulation
The development board works seamlessly with the Xilinx System
Generator for DSP Tool and allows you to perform hardware-in the- loop
co-simulation so that you can verify your design running on the FPGA itself.
Interface to the PC is via PCI Express interface, allowing for high bandwidth
co-simulation. XtremeDSP Virtex-5 SXT Development Kit -ML506
XtremeDSP Starter Kit — Spartan 3A DSP 1800A Edition

This low cost introductory design solution includes Xilinx System Generator
for DSP, reference designs and ISE™ design tools supporting industry-standard
peripherals, connectors and interfaces. Designed for use with the Xilinx System
Generator for DSP development platform, the Spartan-3A DSP Development
Platform provides a ideal environment for developing signal processing designs
based on the Spartan-3A DSP device.
XtremeDSP Development Platform – Spartan-3A DSP 1800A Edition
XtremeDSP Development Platform — Spartan-3A DSP 3400A Edition

This low cost development platform is designed for use with the Xilinx System
Generator for DSP and ISE™ design tools supporting industry-standard peripherals,
connectors and interfaces. This platform delivers instant access to the Spartan-
3A DSP family capabilities and is ideal for General Prototyping, Embedded
Processing, Digital Video, DSP Co-Processing and Digital Communications
applications. It was developed to help designers and system architects deal with
the design challenges in a wide variety of markets including wireless, automotive,
consumer, multimedia, video imaging, industrial, medical, military/aerospace,
servers, storage and telecom/datacom.
XtremeDSP Starter Platform – Spartan-3A DSP 3400A Edition

D E V ELO P MENT TOOL S _ H A R D W A R E
Xilinx DSP Development Boards

Xilinx Part Number Tool Description Devices Supported Supports High Bandwidth Hardware in the Loop
Digital Communication (Wired/Wireless)
DO-DI-DSP-DK2PRO XtremeDSP Development Kit for Virtex-II Pro Virtex-II Pro 4
DO-DI-DSP-DK2PRO-SG XtremeDSP Development Kit for Virtex-II Pro with System Generator tool Virtex-II Pro 4
DO-DI-DSP-DK4 XtremeDSP Development Kit for Virtex-4 Virtex-4 4
DO-DI-DSP-DK4-SG XtremeDSP Development Kit for Virtex-4 with System Generator tool Virtex-4 4
HW-AFX-FF672-300 HW-AFX-FF672-300 Proto Board Virtex-4
DO-V2P-ML300 Virtex-II Pro ML300 Evaluation Platform Virtex-II Pro
HW-V4-ML403 Virtex-4 ML403 Embedded Platform Virtex-4
HW-V4-ML402 Virtex-4 ML402 SX XtremeDSP Evaluation Platform Virtex-4
ADS-XLX-ATCA-DEVP50 2VP50 PICMG ATCA Design Kit Virtex-II Pro
ADS-XLX-ATCA-DEVP70 2VP70 PICMG ATCA Design Kit Virtex-II Pro
Multimedia, Video and Imaging
HW-V2-XLVDS Virtex-II XLVDS Demonstration Board Virtex-II
DO-SPAR3-DK Spartan-3 Starter Kit Spartan-3/3E
HW-V4SX35-VIDEO-SK Virtex-4 Video Starter Kit Virtex-4
HW-X61-VIDEO VIDEO 10 Daughter Card Virtex-4
Aerospace and Defense
DO-V2P-ML300 Virtex-II Pro ML300 Evaluation Platform Virtex-II Pro
General Purpose Signal Processing
HW-V4-ML402 ML402 XtremeDSP Evaluation Platform Virtex-4
HW-V5-ML506-UNI-G Virtex-5 XST Evaluation Platform Virtex-5 SXT
DO-SPAR3-DK Spartan-3 Starter Kit Spartan-3/3E
HW-SD3400A-DSP-DB-UNI-G XtremeDSP Development Platform – Spartan-3A DSP 3400A Edition Spartan-3A DSP
HW-SD1800A-DSP-SB-UNI-G XtremeDSP Starter Platform – Spartan-3A DSP 1800A Edition Spartan-3A DSP
DSP Development Boards from Third-Parties

Third Parties
Digital Communications (Wired/Wireless)
DSP Systems www.dspsystems.com Virtex-II/II Pro
Elite Innovations www.eliteinnovations.com Virtex 4 4
Innovative DSP www.innovative-dsp.com Virtex-II/II Pro 4 4
Lyrtech www.lyrtech.com Virtex-II/II Pro and Virtex-4 4 4
Multiple Access Comms www.macled.com Virtex-II/II Pro
Nallatech www.nallatech.com Virtex-II/II Pro and Virtex 4 4
Pentek www.pentek.com Virtex-II/II Pro 4
Sundance www.sundance.com Virtex-II/II Pro and Virtex 4 4
Spectrum Digital www.spectrumdigital.com Virtex-II/II Pro
Spectrum Signal www.spectrumsignal.com Virtex-II/II Pro 4
Traquair www.traquair.com Virtex-II/II Pro and Spartan-3/3E 4
Multimedia, Video and Imaging
Lyrtech www.lyrtech.com Virtex-II/II Pro 4 4
Spectrum Digital www.spectrumdigital.com Virtex-II/II Pro
Aerospace and Defense
DSP Systems www.dspsystems.com Virtex-II/II Pro
Elite Innovations www.eliteinnovations.com Virtex 4 4
Innovative DSP www.innovative-dsp.com Virtex-II/II Pro 4 4
Lyrtech www.lyrtech.com Virtex-II/II Pro 4 4
Multiple Access Comms www.macled.com Virtex-II/II Pro
Nallatech www.nallatech.com Virtex-II/II Pro and Virtex 4 4
Pentek www.pentek.com Virtex-II/II Pro 4
Spectrum Digital www.spectrumdigital.com Virtex-II/II Pro and Virtex-4
Spectrum Signal www.spectrumsignal.com Virtex-II/II Pro 4
Traquair www.traquair.com Virtex-II/II Pro and Spartan-3/3E 4
General Purpose Signal Processing
Alpha Data www.alpha-data.com Virtex-II/II Pro and Virtex 4 4
Annapolis Microsystems www.annapmicro.com Virtex-II/II Pro and Virtex-4 4
Anzus www.anzus.com Virtex-II/II Pro 4
Avnet www.avnet.com Virtex-II/II Pro, Virtex 4 and Spartan-3/3E 4 4
Bittware www.bittware.com Virtex-II/II Pro 4
Nu Horizons www.nu-horizons.com Virtex-II/II Pro and Spartan-3/3E 4
VMETRO Transtech www.vmetro.com Virtex-II/II Pro 4

D e v e l o p m e n t T o o l s – S O F T W A RE
DSP Design Environment

Xilinx DSP design tools accelerate system level verification
using hardware prototyping and help you to increase the
performance of your DSP system while lowering the cost.
Algorithm, hardware and system designers each receive
the benefits that FPGAs have to offer and our design tools
address the unique requirements for each designer. Our
DSP design philosophy is based on letting you design using
the tool that best solves the problem at hand and not dictate
a one-size-fits-all design flow. Whether you are designing in
C/C++, MATLAB®, Simulink®, HDL or a combination of
these, Xilinx offers best-in-class tools to help you get the job
done both optimally and faster.
Supported DSP Design flows
System Generator for DSP™ Tool
Based on the defacto standard for Model-Based Design,

Simulink from The MathWorks, Xilinx System Generator for
System Design
DSP (System Generator) is an FPGA design environment that
Improve system Performance
is tailored to the unique needs of system, algorithm and hard- through FPGA co-processing
ware developers designing DSP systems. Each design discipline
has different skills and problems to solve. Unique feature sets
within System Generator allow each developer to realize the
Algorithm Design
benefits that FPGAs offer using a design methodology that is Hardware Design
Accelerate Simulink algorithms in
familiar and productive for them. Automated verification
FPGAs without knowledge of
and debug environment for
Hardware design techniques
DSP FPGAs
System Design System Generator for DSP

DSP hardware platforms, traditionally based on processors Solving Problems for Multiple Disciplines
running algorithms developed in C, have been migrating

towards the use of FPGA co-processors in order to increase
performance while reducing power and cost. System design of
this hardware involves the partitioning of the main components
into software running on DSP or embedded processors and the
FPGA.
Support for Embedded Processing through Shared Memories

System Generator facilitates hardware/software partitioning by
offering tight integration to the Xilinx Platform Studio tool for
embedded processing (available through EDK, the Embedded
Development Kit). A shared memory interface is available
for targeting the Xilinx MicroBlaze™ embedded processor. This
abstracts away the hardware implementation details for both the
C programmer and DSP designer.
Shared Memory Interface to Xilinx Embedded Processors

D e v e l o p m e n t T o o l s – S o f t wa r e
Resource Estimation Design Exploration through IP Parameterization

System Generator’s “Resource Estimator” provides a quick Different hardware architectures for a DSP algorithm can be
FPGA resource utilization estimate prior to performing the quickly explored through parameterization of the IP building
synthesis and place and route implementation steps. blocks. Each block can be customized through a unique set
These estimates can be used to guide the hardware/ of hardware implementation parameters that effect hardware
software partitioning process. features, pipelining, sample rate and resource sharing. These
effects can be quickly analyzed using the Simulink cycle
accurate simulation environment.
Boost Simulation Performance using Hardware

Co-Simulation
Exploring and verifying mathematical approaches to system
requirements, often requires test and refinement of DSP
algorithms using real world data. This can result in large vector
sets and the need for real-time verification performance. System
Generator enables designs captured in Simulink, MATLAB, and
RTL to be accelerated up to 1000x using hardware-in-the-loop
co-simulation on a variety of Xilinx provided and 3rd party
hardware platforms.
MATLAB Support
Floating-point MATLAB is supported for model generation,
via the Xilinx AccelDSP Synthesis tool. MATLAB provides an
System Generator Resource Estimator efficient DSP modeling language through native support for
vector and matrix operations and an extensive set of built-in
functions. User defined DSP blocks can be generated from
Algorithm Design AccelDSP Synthesis and used within the System Generator
System Generator comes complete with an optimized, bit modeling and hardware generation environment. AccelWare™
and cycle accurate library for assembling sophisticated signal parameterized DSP IP can be used with the floating-point
processing systems. Xilinx algorithmic IP is an integral part MATLAB for hardware representations of linear algebra opera-
of this library and is used to rapidly create efficient implemen- tions such as adaptive filtering, matrix inversion, matrix factor-
tations of common DSP building blocks such as FIR filters, ization and MIMO.
FFTs and forward error correction (FEC) blocks.
Hardware Design
Hardware engineers developing production FPGAs need to
maximize the performance and minimize the cost of their final
implementation. For these designers VHDL or Verilog is often
their design creation method of choice.
System Generator bridges a verification gap by allow-
ing RTL models to be simulated and verified from within the
Simulink DSP modeling environment. Inputs created using
the Simulink standard blocksets can be used to drive the RTL
simulation and outputs generated from RTL simulation can
be viewed using the standard Simulink plotting functions.
Using Algorithmic IP blocks in Simulink/System Generator Hardware in the loop co-simulation is supported for this flow
providing up to a 1000x simulation performance increase.

Explore Multiple Design Implementations Using

System Generator for DSP Product Features Single Golden Source
• Tight integration to the Xilinx EDK for adding embedded Algorithms written in the MATLAB language become the
processors to the DSP hardware golden design source driving the entire AccelDSP design and
• Fixed-point RTL generation verification flow. All major design tasks, from floating-point
• FPGA resource estimation definition to gate-level implementation, are derived from the
• Integration to 3rd partly ESL C-synthesis tools MATLAB golden source. Speed and area tradeoffs can be
explored by setting system-level requirements and using
• 1000x simulation performance improvement through
the tool’s IP-Explorer technology to rapidly select optimal
hardware co-simulation
silicon implementations of key DSP building blocks. AccelDSP
• Xilinx optimized DSP blockset for Simulink MATLAB
reports make it easy to evaluate the effects of design changes on
language support through AccelDSP
resource utilization, throughput and latency.
• FIR Filter compiler
• Black box support for VHDL and Verilog Automated Floating- to Fixed-point Generation
• RTL testbench generation MATLAB algorithms must be implemented in fixed-point
Major Benefits hardware to achieve higher performance in FPGAs. This
requires the scaling and precision of each variable to be defined
• Assists system designers in partitioning operations between
to avoid overflow/underflow conditions – a tedious, error-
processors and FPGA logic
prone process.
• Accelerates the verification of RTL within a DSP modeling AccelDSP Synthesis assists in this process by using the
environment by up to 1000x floating-point source and stimulus to determine the dynamic
• Enables the use of the algorithm friendly MATLAB/ range of each variable and input/output port. Once determined,
Simulink modeling environment for FPGA design quantization directives are set throughout the design and a
fixed-point MATLAB or C++ model is generated that is
optimized for fast execution in MATLAB. These
AccelDSP Synthesis Tool quantization values can be re-defined by the user.
The AccelDSP™ Synthesis Tool automates the generation Scalable and Synthesizable Cores
of synthesizable RTL directly from floating point MATLAB AccelWare™ toolkits are hardware optimized DSP IP core generators
models. A Model-Based Design environment is provided from for use with AccelDSP Synthesis that provide essential signal
which high-performance DSP designs can be rapidly imple- processing components. These generators support multiple
mented in Xilinx FPGAs through a highly productive, top- macro-architectures to let designers craft a design for the
down flow integrated with third party and Xilinx design tools. specific requirements. Toolkits are available for:
• Communications, Reed-Solomon encoding/decoding, Viterbi
decoding, etc.
• Advanced Math – SVD/QR/Cholesky matrix factorization,
QR & Cholesky/triangular matrix inversion, etc.
AccelWare toolkits are functionally equivalent to their

MATLAB toolbox counterparts supporting the same input
parameters. The hardware parameterization of AccelWare IP
far exceeds that of RTL-level intellectual property, providing
synthesizable cores with the flexibility to precisely meet require-
ments with optimal hardware.
IP-Explorer Technology for Heuristic-Driven Optimization

IP-Explorer automatically replaces standard function calls
used in a MATLAB model with hardware accurate architec-
tures from the AccelWare IP library. This process is heuristic-
AccelDSP Synthesis Tool driven based on bit widths and system constraints such as
area and performance. Statistical methods are then used to
select the best

AccelWare architecture for each use of a function to produce

an overall optimized design. This technology elevates hard- AccelDSP Synthesis Product Features
ware design to a higher abstraction increasing productivity and
• MATLAB-based algorithmic synthesis generates technology-
reducing the time to implement designs.
optimized RTL
• Automated floating-to-fixed-point conversion
Optimize Hardware Implementation through Directives
AccelDSP offers a set of synthesis directives that guide deci- • IP-Explorer technology enables heuristic-driven selection
sions about resource utilization and alternative implementa- of hardware architecture at algorithmic level
tions that cannot be inferred from the high-level MATLAB • Complete automated verification flow with automatic
language constructs. Supported directives include loop rolling/ testbench generation
unrolling, quantization, matrix multiplication expansion, RAM/ • Hardware optimizations including loop rolling/unrolling,
ROM memory mapping, pipeline insertion, and shift register matrix multiplication expansion, RAM/ROM memory
mapping. Using these directives enables hardware-based mapping, pipeline insertion, and shift register mapping
design exploration without code rewrites. • Model generators for Simulink and Xilinx System
Generator for DSP
Correct-by-Construction DSP Design
• Easy-to-use graphical user interface integrates with
Developing and maintaining verification suites that check
downstream tools
equivalency of algorithmic, RTL, and gate-level designs is a
resource-intensive task that must be done to ensure that the
Major Benefits
hardware matches the original algorithm. AccelDSP automates
this process by generating a simulation testbench using test • Single, golden source drives synthesis and verification flow
vectors created from the MATLAB fixed-point simulation. for all Xilinx FPGAs,
AccelDSP is integrated with leading 3rd party simulation • Provides flexibility to use both algorithmic synthesis and
tool providers. DSP intellectual property
• Works with MATLAB and Simulink products from The
Generate Models for System Validation and Integration MathWorks
inside System Generator for DSP. • Provides device neutrality
MATLAB algorithms synthesized by AccelDSP can be incorpo- • Proven to increase productivity up to 20x
rated into larger DSP systems using Simulink. AccelDSP
generates bit and cycle accurate models for use with the stan-
dard Simulink blockset or with the Xilinx DSP blockset pro-
vided as part of System Generator. This allows rapid validation
of MATLAB algorithms in a hardware system through
System Generator’s hardware co-simulation.
The Xilinx ESL Initiative

Adding an FPGA co-processor to a DSP hardware
system provides new implementation options, including
FPGA logic and embedded processing that can be used
to dramatically increase the performance and lower the
cost of the hardware system. Taking advantage of these
new options, however, can be a daunting task for DSP
designers accustomed to working in a C development
environment. To ease the adoption of FPGA co-processors
Xilinx has created the “ESL Initiative” which is a partner- ESL Initiative Capabilities
ship between Xilinx and the industries leading providers of • Includes industry-leading ESL tool providers
Electronic System Level (ESL) design solutions. Through this • Focus on C-to-FPGA design flows
initiative innovative solutions are being developed to map C • Flows Support the MicroBlaze and PowerPC 405 embedded
routines directly onto the hardware resources of the Xilinx processors
FPGAs from a software friendly development environment. • C-to-FPGA logic flows support both module creation and
hardware accelerators

Complementary Software Design Tools
System Modeling and Design Simulink Simulink (from The MathWorks) is a platform for multidomain
simulation and Model-Based Design of dynamic systems. It pro-
vides an interactive graphical environment and a customizable set
of block libraries that let you accurately model and simulate signal
processing, communications, and other time-varying systems.
Platform Studio Platform Studio (from Xilinx) is an integrated development envi-

ronment containing a wide variety of embedded design tools, IP,
libraries, wizards, and design generators to quickly facilitate the
creation of your custom embedded platform. The tool supports
all Xilinx 32 bit microprocessors and can be invoked from System
Generator for DSP.
Algorithm Development MATLAB ATLAB (from The Mathworks) is a high-level technical computing
M
language and interactive environment for algorithm development,
data visualization, data analysis, and numerical computation. Using
MATLAB, you can solve technical computing problems faster
than with traditional programming languages, such as C, C++
AccelDSP™ Synthesis Tool is a high-level MATLAB® language based

tool for designing DSP blocks for Xilinx FPGAs. The tool automates
floating- to fixed-point conversion, generates synthesizable VHDL
or Verilog, and creates a testbench for verification. You can also
generate a fixed-point C++ model or System Generator block
from a MATLAB algorithm.
HDL Simulation and Generation ISE I SE Foundation software (from Xilinx) allows you to essentially
program the FPGA. Hardware designers can design using VHDL
or Verilog. When using System Generator, ISE design tools can be
invoked in batch mode.
Synthesis XST from Xilinx and Synplify Pro from Synplicity are synthesis
tools that allow low cost and highly efficient mapping to Xilinx
hardware, respectively. When used in conjunction with System
Generator, you have the option to use these tools in batch mode.

ModelSim If you already have legacy or production ready HDL then System
Generator provides the necessary interfaces to allow you to
interface to Mentor Graphics’ ModelSim simulator. You can co-
simulate your HDL using ModelSim and import simulated results
to the Simulink/System Generator simulation in real-time.
Verification and Debug ChipScope Pro onitor internal nodes in the FPGA to expedite the debug stage
M
of your design. ChipScope probes can be inserted from within
Simulink/System Generator. They are automatically inserted into
the hardware during the HDL generation stage.

System Generator Reference Designs Digital Communications & Video/Imaging Reference Designs
Ask your local Xilinx or Xilinx Distributor FAE • 16-QAM receiver, including LMS based equalizer • Gamma Correction
about one of the many DSP reference designs and carrier recovery loop
• Soft Focus
for System Generator. These documented • A/D and delta-sigma D/A conversion
• CORDIC reference design
designs will help you accelerate your learning. • Concatenated FEC codec for DVB
• Polyphase MAC-based FIR
• Custom FIR filter reference library
• Streaming FFT/IFFT
• Digital down converter for GSM
• BER Tester using AWGN model
• 2D discrete wavelet transform
• DWT
Free Online DSP Demos on Demand (DWT) filter
• Others
• 2D filtering using a 5x5 operator
See how System Generator can accelerate • Color space conversion
development of your next high-performance • Scaling: e.g. 4.2.2 > 4.2.0
signal processing design by viewing one of
• Image rotation
the many DSP Demos on Demand available
• Floating Point FFT
on Xilinx DSP Central at www.xilinx.com/dsp.
These hour-long lectures are broken down
into easily digestible, 10 minute modules.
These documented designs

will help you accelerate
DSP Design Flow Class
You can also get on the fast track by taking
the Xilinx DSP Design Flow Class. In this
your learning.
three-day class, you will learn how to build
a design, generate hardware and debug it, all
from within Simulink/System Generator for
DSP. See the DSP Resources section at the
back of this selection guide.

COM P LEMENT A RY S o l u t i o n s
DDSSP P SSyysst te emm SSool luut ti o
i onnss
Xilinx FPGAs _ The Ideal Complement for DSPs Processors

Xilinx FPGAs are used as complementary devices for DSP
processors and can complement DSP processors in many ways.
Interfacing Buses
FPGAs support many interface standards and are ideal for
bus-bridging applications. Whether you are connecting
serial interfaces such as Serial RapidIO and PCI Express or
parallel interfaces such as PCI, PCI-X, and VLYNQ, FPGAs can
handle your interfacing and bridging needs.
Interfacing Memory
XtremeDSP Co-Processing
No doubt you will have memory in your system so with FPGAs
The combination of reconfigurable hardware and a program-
you can also bridge different memories using DDR, DDR2 and
mable DSP provides a very good fit for handling highly
DDR3. In addition, Xilinx FPGAs support popular memory
complex signal processing algorithms. With Xilinx XtremeDSP
interfaces to DSP processors such as EMIF for TI DSPs.
co-processing, you can migrate computationally intensive DSP
tasks to the FPGA and free up programmable DSP processors
Consolidating System Logic
to perform other value-added software features.
Reducing system cost is frequently an important aspect to
Xilinx FPGAs extend the capabilities of DSP and media
prolonging the life of your product in the market. By consoli-
processors in many ways as shown.
dating your system glue logic into the FPGA you can reduce
bill of materials and form factor and save costs as a result.
Implementing New Peripherals

While DSP processor vendors go to lengths to include the
right mix of peripherals on their devices, you will often need
to include your own custom peripheral. An FPGA next to
your processor will provide you the flexibility to include and
upgrade your peripherals.
DSP Performance Acceleration

With over 350 GMACs (18 x 25 multiply, 48-bit add) of
performance, Xilinx FPGAs are increasingly being used as
co-processors for DSP processors in the signal chain. FPGA-
based co-processing provides the performance, scalability and
flexibility to tackle the most demanding DSP applications.
Xilinx Spartan-3/3E/3A and Spartan-3A DSP FPGAs are the
An example is a H.264 digital video encoding/decoding system
world’s lowest-cost FPGAs, ideally suited for co-processing
with transrating and transcoding capabilities. You can offload
in high-volume applications.
compute-intensive algorithms into the FPGA or extend the number
The Xilinx Virtex-5 FPGA family is the highest perfor-
of channels that can be processed or tackle higher resolutions and
mance DSP family from Xilinx. With up to 640 XtremeDSP
rates.
slices operating at 550MHz, these devices can implement
complex tasks such as:
Fast Time to Market with Xilinx DSP Co-Processing System
• High-definition (HD) H.264 and MPEG-4 encode/decode Design Tools
algorithms Xilinx and its partners provide complete solutions for rapid DSP
co-processing development and implementation. Hardware and
• Many IF-to-baseband down-conversion channels
software development tools allow you to model your FPGA-DSP
• 128X chip-rate processing for spread-spectrum systems system, design the FPGA portion even if you cannot write HDL,
and allow you to test and debug your design on the FPGA itself.
COM P LEMENT A RY S o l u t i o n s
Software Development Tools Coprocessing Designation
Xilinx provides two software tools that

make it easy for DSP developers to build
FPGA-based co-processors.
System Generator for DSP

System Generator for DSP is the indus-
try’s leading high-level tool for designing
high-performance DSP systems using
FPGAs. The tool interfaces seamlessly
with The MathWorks Simulink tool. It
provides abstractions that enable you to
develop highly parallel systems with the
industry’s most advanced FPGAs, pro-
viding system modeling, automatic code
generation and design verification using
high bandwidth hardware co-simulation.
AccelDSP (MATLAB) Synthesis

AccelDSP Synthesis is now part of
the Xilinx DSP software tool suite.
The tool automates the generation of Building FPGA Co-Processors for DSPs
synthesizable RTL or System Generator Building FPGA co-processors for traditional DSP processors has become
IP blocks directly from floating-point much simpler using The MathWorks Simulink tool. You can first design your
MATLAB M-files. There is a tight complete system in floating point and verify the functionality. Then by replac-
integration with System Generator for ing floating point blocks with bit-true and cycle-true library blocks from the
mixed graphical-and language-based Xilinx blockset you can also introduce quantization to verify accuracy.
design flow.
For the DSP processor portion of the design The MathWorks and Partners offer
tools such as Real-Time Workshop and Embedded Target that allow you to
Interfaces automatically generate code.
A number of interfaces to TI™ DSPs
are available as IP cores including:
• Serial RapidIO™
• VLYNQ™
• EMIF™

Xilinx and third party venders offer a
wide variety of co-processing hardware
boards for DSP accelerator based designs.
• Avnet
• Hunt Engineering
• Innovative Integration
• Lyrtech
• Spectrum Digital
• Spectrum Signal Processing
• Sundance
• Traquair
• VITEC Multimedia
• VMETRO Transtech

RE S OURCE S
i onnss
Xilinx Education Services -

the source for Xilinx education
Xilinx provides targeted, high-quality DSP education services DSP Specific Classes include:
designed by experts in programmable logic design, and delivered
by Xilinx-qualified trainers. Our courses are developed to create Introduction to AccelDSP
an engaging learning environment by blending lecture, hands-on Learn how to use AccelDSP and MATLAB to create designs
labs, interactive discussion, tips and best practices. The training optimized for Xilinx FPGAs. Highlights MATLAB coding styles
is delivered when and where you need it by leveraging a global that improve area and performance; and the use of floating-
network of Authorized Training Providers and online learning to-fixed-point and design exploration features of AccelDSP to
systems. achieve optimal results.
Knowledge gained through Xilinx Education Services on the DSP Design Using System Generator
use of Programmable Logic Devices, design techniques, and Teaches how to implement DSP functions using System
methodologies will enable you to take full advantage of all the Generator for DSP, design implementation tools, and hard-
capabilities of today’s advanced FPGAs when building your ware-in-the-loop verification.
next DSP design. Equipped with this know-how, you can bet-
ter innovate when developing products for your market, reduce DSP Implementation Techniques for Xilinx FPGAs
R&D costs through a more efficient design process, and reduce Instructs how to take advantage of the features available in the
production costs through the use of smaller and slower-speed- Xilinx FPGA architectures and most efficiently implement DSP
grade devices. algorithms. Techniques also demonstrate which decisions at the
system level have the greatest impact on the implementation
Xilinx DSP Curriculum Path is for developers who need to process and product costs.
build a DSP system. The Courses within this curriculum path
include lab sessions to apply the techniques and skills discussed
in the class. For details on the DSP Curriculum path, and the
courses that comprise it, please visit:
http://www.xilinx.com/support/training/cur_paths/atp-dsp.htm

RE S OURCE S
DSP Design Services

Xilinx DSP Design Services provide you the supplementary sup-
port you may need to meet your market requirements. Our team of
experts is available to help you conduct turn-key designs and ensure
that you have the most optimized FPGA-DSP design for your target
application. Here are some ways in which our DSP Design Services
team can help you with your next design:
Create a Simulink/System Generator design – our designers will
design and model all or part of your system to your specification,
generate the code and verify that the design works in hardware.
Algorithm development – Some designs require the develop-
ment of performance or area optimized algorithms. Use our Design
Services team to develop highly optimized filters, transforms, FFTs,
demodulators, error correction algorithms (e.g. Viterbi decoders)
wireless designs (e.g. Rake receivers, searchers) or video codecs
(e.g. MPEG 4).
Modify DSP IP cores – While our library of DSP IP cores can be
parameterized, there may still cases when you need additional features
that require modification to our cores. Use our Design Services team
On-Demand Webcasts to modify these cores rather then develop them from scratch.
On-Demand webcasts are 60 minutes, were recorded live and now
made available online. These lectures range from beginner overviews to DSP Support / Packaged Solutions
advanced, highly technical design information. Learn more about how XPA Packaged Solutions – The Xilinx Productivity Advantage (XPA)
to design Digital Signal Processsing (DSP) applications from FPGAs. offers all of Xilinx world class Software, Education, Support Services,
• Introducing Virtex-5 FPGA and IP cores in one easy to buy package. Custom tailored to your
specific needs, the scalable XPA solution is the best way to get
• Virtex-4 FPGA Design Techniques and Tools Settings for
everything you or your design team need to make your next design
MaximumPerformance
your best.
• Virtex-5 FPGAs and PlanAhead Delvier Maximum Performance The DSP XPA Seat is your ticket to productivity, providing
you with the advanced tools and expertise you need to develop
advanced, low-cost DSP designs in Xilinx industry-leading FPGAs.
Save 20% when you purchase this predefined value bundle, which
includes the System Generator for DSP software tools and 15
training credits.

i onnss
www.xilinx.com/dsp/

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Xilinx, Inc.
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San Jose, CA 95124
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Tel: 408-559-7778
Web: www.xilinx.com
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Ireland
Tel: +353-1-464-0311
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Tel: +65-6407-3000
Web: www.xilinx.com
www.xilinx.com
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and other designated brands included herein are trademarks of Xilinx, Inc.
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XtremeDSP Solutions

2 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

A New Era of Signal Processing

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 3

Example: Wireless Base Station

Wireless/Wired DSP for Digital Communications

4 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

Xilinx DSP Benefits for Digital Communication IP LogiCORE AllianceCORE Vendor

• Solutions capable of handling sample FIR Filter Compiler 4

of transmit and receive chains MAC FIR Filter 4

• Very low power and cost per channel Multiplier Accumulator 4

that you can develop the ideal architecture to Compression

Generator to design high-density designs in 2-D Discrete Cosine Transform (DCT) 4

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 5

Communication IP (Cont’d) LogiCORE AllianceCORE Vendor The Xilinx CORE

ered in multiple formats such as System Random Access Channel (RACH) 4

Generator models or netlists. Searcher 4

6 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

Wireless/Wired Application Notes Application Note Literature Number

in the marketplace. Mixed-Version IP Router (MIR) XAPP655

Description Part Number

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 7

Multimedia Video and Imaging (MVI)

DSP for MVI Applications

8 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

Applications Color Space Conversion, RGB2YCrCb 4 CAST, Inc.

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 9

MVI Application Notes

MVI White Papers

MVI Systems Hardware and Software Development Tools

10 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

XtremeDSP Video Starter Kit — Spartan-3A DSP Edition

Performance Acceleration for DSP Video Processors

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 11

Building Cost and Power Efficient SDR

• Limited Scalability • Lower Power Cost

12 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

The SFF SDR Development Platform

The SFF SDR Development Platform is separated into three dis-

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 13

Xilinx DSP Benefits for Defense Systems Xilinx Algorithms

- Partial reconfiguration that allows for MAC FIR Filter 4

cost and power Building Blocks

functions such as floating point FFTs for FFT up to 64K points 4

expanding dynamic range, working in FFT, Pipelined (Vectis-QuadSpeed) 4 RF Engines, Ltd.

processing applications Modulation/Demodulation

14 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

Defense Systems IP (cont.) LogiCORE AllianceCORE Vendor

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 15

Reference Designs Matrix Xilinx Everywhere Product Grades

Defense Systems Hardware and Software Development Tools

16 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 17

Virtex _ DSP Series Spartan _ DSP Series

XtremeDSP Device Portfolio

3SD1800A 3SD3400A 4VSX25 4VSX35 4VSX55 5VSX35T 5VSX50T 5VSX95T 5VSX240T

18 XtremeDSP Selection Guide www.xilinx.com/dsp June 2008

Virtex _ DSP Series for Signal Processing

Virtex-5 SXT Devices Virtex-4 SX Family

June 2008 www.xilinx.com/dsp XtremeDSP Selection Guide 19

• Solutions capable of handling sample FIR Filter Compiler 4

Platform Studio Platform Studio (from Xilinx) is an integrated development envi-