Geh 6005

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...... ... ........................ . .. .. .. ... ....................... ..............
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...... .... . ... .... ... .. ...... ... .... .... . .. . .. ............... ........ ..........
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GEH-6005
x
4? I
i
Instructions
A
DC2000
Digital Adjustable Spee
d Drive
C, CX, G, J , K , and M
Frames
Operation and Mainten

ance
nu
DC2000
Digital Adjustable Speed Drive
C, CX, G, J, K, and M Frames
Gperation and Maintenance
GEI-I-6005
Issue Date: September 1995
These instructions do not purpon to cover all details or variations in equipment, not to provide for every possible con-
tingency to be met during installation, operation, and maintenance. Should further information be desired or should
paracularproblems arise that are not covered sufficiently for the purchaser's purpose, the matter should be refereed to
GE Drive Systems & Turbine Contwls.
Iris docmnent contains proprietary information of General Electric Company, USA and is furnished to its customer
solely to assist that customer in the installation, testing, and/or maintenance of the equipment described This document
shall not be reproduced in whole or in part nor shall its contents be disclosed to any third panty without the written
approval of GE Drive Systems & Turbine Controls.
©1995 by General Electric Company, USA
AH rights reserved.
Printed in the United States of America.
ARCNET is a registered trademark of Datapolmt Corporation.

DIRECTOR-MATIC, Lexan, and VERSILUBE are registered trademarks of General Electric Company, USA.
Genius is a trademark of GE Fanuc Automation North America, Inc.
GLASTIC is a registered trademark of Glastic Corporation, a subsidiary of Kobe Steel.
IBM, IBM PC, and PC AT are registered trademarks of International Business Machines Corporation.
LynxOS is a registered trademark of Lynx Real-Time Systems, Incorporated.
MS-DOS is a registered trademark of Microsoft Corporation.
Muffin and Tarzan are registered trademarks of COMAIR ROTRON, a KLI Company.
DC2000 Digital Adjustable Speed Drive GEI-I-6005
SAFETY SYMBOL LEGEND
WARNING
I
Commands attention to an operating procedure, practice, condition, or statement which, if not strictly observed,
could result 'm personal injury or death.
CAUTION
Commands attention to an operating procedure, practice, condition, or statement which, if not strictly observed,
could result in damage to or destruction of equipment.
NOTE
Commands attention to an essential operating or maintenance procedure, condition, or statement that must be
highlighted.
a
GEH-6005 DC2000 Digital Adjustable Speed Drive
WARNING
This equipment contains a potential hazard of electric shock or burn. Only personnel who are adequately
trained and thoroughly familiar with the equipment and the instructions should install, operate, or main-
tain this equipment.
Isolation of test equipment from the equipment under test presents potential electrical hazards. If the test
equipment cannot be grounded to the equipment under test, the test equipment's case must be shielded to
prevent contact by personnel.
To minimize hazard of electrical shock or burn, approved grounding practices and procedures must be
strictly followed.
WARNING
To prevent personal injury or equipment damage caused by equipment malfunction, only adequately
trained personnel should modify any programmable machine.
b
DC2000 Digital Adjustable Speed Drive GEH-6005
TABLE OF CONTENTS
Section/Subject Page Section/Subject Page
CHAPTER 1. OVERVIEW 4-4. Controller Operation.......................... ......4-2 .

1-1. Definition and Scope .... .. . ... . .. . . . . . . .. . ... . .. . ... 1-1 4 5 Power Converter Operation 4-4
1-2. Eqmlpment Overview .... ... . . .. .. . . . ... .. . . . . . .. . .. . 1-2 4 5 1 Ac Line Fuses (FUI FU3) 4-4
1-2.1. Communications Interfaces. .. . . . .. . .. .. .. ... .... 1-2 4-5.2. Dc Leg L`me Fuses (FU1 FU12) 4-4
1-2.2. Software Design. .. . . .. .. .. .. . .. . . . . .. . . . .. . . .. . .. . 1-2 . . . . . .. .. . . . . . . . .. .. . . . .. . . . . ........4-4
4-5.3. Ac Reactors...--.--..-..
1-2.3. Hardware Design.. . . ... . . . .. ... .. ... .. . ... . .... ... 1-2 4-5.4. Main Contactor (MA or MD) 4-4
1-3. Related Documents . . . .. . .. . . .. . .. . .. . .... .. . . .. . . ... 1-3 4-5.5. Control Power Transformer (CPT) 4-4
4-5.6. Dc Line Fuse (FU4) ..........................4-4
CHAPTER 2. RECEIVING, HANDLING, AND .
4-5.7. Shllll[.................. ..............................4-4
STORAGE 4-5.8. Current Transformer (CT) Assembly ..........4-5
2-1. I n t r o d u c t i.o..n..,...._....,.,............................. . 2-1 .. 4-6. Drive Connection Drawings....--------- ........................4-5
2-2. Receiving and Handling ............................ 2-1
CHAPTER 5. PRINTED WIRING BOARD
2-3. Storage ................................................ 2-1
DESCRIPTIONS
2-4. Unpacldng ............................................ 2-2
2-5. Time Limitations .................................... 2-2 5-1. Introduction.............. ..5-1
5-2. Board Identification................................5-1
CHAPTER 3. INSTALLATION AND INITIAL 5-3. Adjustable Hardware ......................... .... .5-1
STARTUP 5-3.1. Initial Hardware Settings .........................5-2
........................................... 3-1 5-3.1.1. Potentiometers ..... ........................ 5-2
3-1. Introduction 5 3 1 2 Switches ..................................5-2
3-2. Operating Environment............................. 3-1
( 5-3.1.3. Jumpers.......... .................................5-2
3-3. Mounting.............................................. 3-1
5-3.2. Adjusting Replacement Boards .......5-2
3-4. Cabling and Wiring ................................. 3-1 5-4. Printed Wiring Boards...............................5-2
3-4.1. Ac Power Requirements ......................... 3-2
5-4.1. ARCNET Connect Board (DS200ACNA).....5-3
3-4.2. Connections ........................................ 3-2 5-4.2. Contactor Driver Board (DSZOOCDBA) .......5-3
3-4.2.1. Power Connections............................. 3-2 5-4.2.1. Configurable Hardware ........................5-4
3-4.2.2. Control Connections ........................... 3-2 5-4.3. Contactor Pilot Card (DS200CPCA) 5-4
3-4.3. Wiring Level Separations........................ 3-2 5-4.4. Power Supply Board (DS200DCFB) ...........5-6
.............................................. 3-3
3-4.4. Spacing., 5-4.4.1. Power Supplies ..................................5-6
3-4.5. Grounding .......................................... 3-3 5-4.4.2. Voltage and Current Feedback VCO
3-4.6. Commons........................................... 3-3 Circuits... .................................. ......5-6
3-4.7. Suppression ........................................ 3-3 5-4.4.3. Motor Voltage Attenuation Circuit.... .......5-6
3-5. Service and Parts Instruction ...................... 3-3 5-4.4.4. Ac Line Magnitude and Zero Crossing......5-6
3-6. Power-offCheck..................................... 3-3 5-4.4.5. Ac Line Current Transformer
3-6.1. Wiring and Circuit Checks .. . .. ... . . . . . . . . .. . . . . 3-4 ...................................5-7
I.I1[C1'faCC........,.,,_.,.__-_
3-6.2. Motor and Device Checks . . . .. . . .. . . ... .. . .. . . .. 3-4 5-4.4.6. Contactor Drive Circuits.......................5-7
3-7. Power Application and Startup.................... 3-4 5-4.4.7. Field/Armature SCR Firing Control
Circm'ts .....................................5-7
CHAPTER 4. FUNCTIONAL DESCRIPTION 5-4.4.8. Configurable Hardware ........................5-7
4-1. Introduction........................................... 4-1 5-4.5. LAN Current Source Board
4-2. Drive Software Structure 4-1 (531X207LCS) .............................. .... 5-11
.
4-2.1. Block System ..................................... 4-1 5-4.6. LAN I/O Terminal Board (531X307LTB) 5-11
4 2 2 Building Block Architecture 41 5-4 6 1 LTB Board Specriications 5 11
4-2.3. Diagnostics . . . . . . . . . . . . . .... . .. . . . . . . .. . .. .. . . .. . . . . 4-1 5-4.7. Multi-bridge Hub Communications Board
4-2.4. Configuring Blocks . .. . ... ... . . . .. .. .... ... . ...... 4-2 (DS200MBHA)...................................5-13
4-3. Drive Hardware Stnicture 4-2 5-4.7.1. Power Supply ..................................5-13
4-3.1. Control Section . .. . . . .. . . .. . .. . . . . . .. ... . . . . . ... . . . 4-2 5-4.7.2. Fiber-optic Transmitter/Receiver Pairs 5-13
.
4-3.2. Power Converter ................................. 4-2 5-4.7.3. Mode Control..................................5-13
i
GEI-I-6005 DC2000 Digital Adjustable Speed Drive
TABLE OF CONTENTS Continued
Section/Subject Page SeetionlSubject Page
5-4.7.4. System Logic ................................... 5-13 5-4.17.1. Encoder Follower Circuits................. 5-45
5-4 7 5 Configurable Hardware 5-13 5-4.17.2. Process Control Signal Inputs .. 5-45.
5-4.8. Drive Terminal Board (531X305NTB).... 5-14 5-4.17.3. Configurable Hardware 5-45
5-4.8.1. Power Supplies ................................ 5-14 5-4.18. Basic Drive Terminal Board
5-4.8.2. Encoder Interface ............................. 5-14 (DS2,00STBA) .................................. 5-49
5-4.8.3. RS-232C Interface ............................ 5-14 5-4.18.1. Power Supplies. .......... . ................... 5-49
5-4.8.4. Special Purpose RS-422 Interface .. .5-14 5-4 18 2 Encoder Interface 5-49
5-4.8.5. Relay Outputs .................................. 5-14 5-4,18.3. RS-232C Interface.. ......................... 5-50
5-4.8.6. Analog Tack and Reference Coarse 5-4.18.4. Configurable Control Inputs .5-50
Scaling .......................................... 5-14 5-4.18.5. Relay Outputs ................................ 5-50
5-4.8.7. Low-level Analog I/O ........................ 5-14 5-4.18.6. Configurable Hardware .................... 5-50
5-4.8.8. Digital Control inputs .5-14
5-4.8.9. Configurable Hardware 5-14 CHAPTER 6. IIO DEFINITIONS
5-4.9. Power Connect Boards (DS200PCCA, 6-1. Introduction .................... . ..... .... ............. 6-1
531X122PCN, and 531X121PCR) C . 5-19 6-2. Types of Connectors. . ............................... 6-1
5-4.9.1. Configurable Hardware . 5-19 6-2.1. Plug-in Connectors . . . .. . . . . . . . .... . .. . .......... .. 6-1
5-4.10. Relay Terminal Board (DSZOORTBA) ... 5-24 6-2.2. Terminal Board Connectors ........... .. . . . ..... 6-1
5-4.11. Drive Control Card (DS215SDCC) .. 5-26 6-2.3. Stab Connections (Stabs) .. . . ..................... 6-1
5-4.11.1. Reset Circuits .... .. .... . .. .. . . . ................ 5-26 6-3. LED and Neon Indicators ..6-1
5-4.11.2. Configurable Hardware...... . 5-26 6-4. ACNA Board I/O . ... . . . .... . ....... . .. .............. 6-2
5-4.11.3. Replacing/Inserting Software .. 5-26 6-5. CDBA Board UO.......................... . .. . . . . . . . . 6-3
5-4.12. Dc Power Supply and Instrumentation 6-6. CPCA Card I/O .. . . .. . .... ... ...... ... ............... 6-4
Board (DS200SDCI)........................... 5-29 6-7. DCFB and SDCI Board I/O ................ . . ......6-5
5-4.12.1. Power Supplies............................. 5-29 . 0
6-8. LCS Board I/O .. . . . . . . . . . ..... . . . . .... . . . . . . ... . . . . 6-12
5-4.12.2. Field Power Circuitry and Current 6-9. LTB Board I/O ..................................... 6-13
VCO ........................................... 5-29 6-10. MBI-IA Board I/O . 6-16
5-4.12.3. Do Armature Voltage VCO .. 5-29 6-11. NTB/3TB Board I/O ............................. 6-18
5-4 12 4 Armature Current VCO 5-30 6-12. PCCA, PCN, and PCR Board I/O........ 6-25
5-4.12.5. Ac Line Zero Crossing, Magnitude, 6-13. RTBA Board I/O.............................. .... 6-27
and Phase Sequence 5-30 6-14. SDCC Card I/O.. . .. . . ... ....... . ....... .. ... .. ... 6-29
5-4.12.6. Ac Line Instrumentation....... 5-30 .
6-15 sHvl and sHvm Board I/O.................... 6-31
5-4.12.7. Contactor Drive Circuits .. 5-30 6-16. SLCC Card I/O ....... .. .. .. ...... . ............... 6-33
5-4.12.8. Armature and Field Firing Circuits... .. 5-30 6-17. SPC and SPCB Card I/O . . ...... . . . . .. . . . . . .. . . . 6-34
5-4.12.9. Delayed Firing Power...... ¢ 5-30
¢
6-18. STBA Board I/O .................................. 6-36

5-4.12.10. Configurable Hardware 5-30
5-4.13. SCR High Voltage Interface Board CHAPTER 7. FUSES AND TESTPOINTS
(DS200SI-M) ................................... 5-32
5-4.13.1. Configurable Hardware............. . . 5-32 7-1. Line Fuses.................................... ......... 7-1
5-4.14. SCR High Voltage M Frame Interface 7-2. CDBA Onboard Fuse................................7-1
Board (DSZOOSHVM) ......................... 5-35 7-3. DCFB Onboard Fuses ...............................7-4
5-4.14.1. Configurable Hardware..................... 5-35 7-4. LCS Onboard Fuse .................................. 7-5
5-4.15. LAN Communications Card 7-5. SDCI Onboard Fuses ................................ 7,6
(DS2I5SLCC) .................................. 5-37 7-6. Testpoints.................... .......................... 7-7
5-4.15 1. Configurable Hardware..................... 5-37
. 7-6.1. CDBA Board Testpoints..........................7-7
5-4.15.2. Replacing/Inserting Software ...._ . 5-37 . 7-6-2. CPCA Card Testpoints ......... . ................. 7-8
5-4.16. Signal Processor Card (531X309SPC).. 5-40 . 7-6.3. DCFB Board Testpoints ..........................7-8
7-6.4. MBI-IA Board Testpolmt.s .......... .. . ............ 7-8
i
5-4.16.1. Configurable Hardware............... 5-40

5-4.17. Multi-bridge Signal Processing Card 7-6.5. NTB/3TB Board Testpoints ......................7-8
(DSZOOSPCB)................................... 5-45 7-6.6. SDCC Card Testpoints ......................... 7-11
of
II
s
Section/Subject Page Section/Subject Page
7-6.7 SDCI Board Testpoints..........................7-14

. CHAPTER 10. DIAGNOSTIC LISTS
7-6.8. SPC Card Testpoints ............................7-14
,
10-1. Introduction.................................
...........................7-14 10-1
7-6.9. SPCB Card Testpoints.~~ 10-2. MCP Diagnostic Circular List .................. 10-1
7-6.10. STBA Board Testpoints........................7-16 10-2.1. Circular List Content .......................... 10-1
10-2.2. MCP Diagnostic Circular List Operation.. 10-1
CHAPTER 8. SOFTWARE ADJUSTMENTS 10-2.3. Circular List Display .......................... 10-1
8-1. Introduction........................................... 8-1 10-3. DCP Circular List Blocks .• ... 10-2
8-2. ST2000 Toolkit ...................................... 8-1
. C
10-3.1. CLST Blocks .......... .. . 10-2

on .
8-2.1. Equipment Requirements ........................ 8-1 10 3 1 1 CLST1 (Basic) Block ..• 10-2 u O
8-2.2. Using the ST2000 Toolkit 8-1 10-3.1.2. CLST2 (Intermediate) Block.......... . 10-2 an c »
8-3. Drive ConNgurator, LynxOS Version 8-2 10-3.1.3. CLST3 (Advanced) Block .. . . . . . .. . . . ... . . . 10-3
8-3.1. Eqtu'pment Requirements ........................ 8-2 10-3.2. Circular List Display..................._ . • . 10-3.. s
10-4. LCP History Buffer .............................. 10-4

8
8-3.2. Using the Drive Contigurator........... 8-2

8-4. Programmer Module ............................... 8-2
.
8-4.1. Keypad. ............................................. 8-4 CHAPTER 1 1. PARTS REPLACEMENT
8-4.2. Disp1ay .............................................. 8-4
8 8
..............................
11-1. Introduction..---_,_ 11-1
8-4.3. Operating Modes .. . . . . . . .. . . .. .. . . .. ... . . . . . .. . . .. 8-4
l .
11-2. Replacing Boards .............................. 11-1

8-4.3.1. Operate Mode ................................... 8-4 11-3. Replacing Bridge Components ................. 11-2
8-4.3.2. Parameter Mode ................................ 8-6 11-3.1. SCR Module Repair/Replacement -
8-4.3.3. Diagnostic Mode................................ 8-8 G, C, and CX Frame Dives.................11-2
8-4.4. Drive Diagnostics ................................. 8-8 11-3.2. SCR Module Repair/Replacement -
8-4.4.1. Running the Diagnostic Tests................ . 8-8 J, K, and M Frame Drives .....,11-3
8-4.4.2. Diagnostic Test Definitions ................... 8-9
on
11-3.2.1. Removing Defective SCR .................. 11-3

8-4.4.3. DAC1, DAC2, MET1, MET2, and 11-3.2.2. Installing New SCR ......................... 11~4
MET3 ............................................8-11
CHAPTER 12. SPARE AND RENEWAL PARTS
CHAPTER 9. TROUBLESHOOTING
12-1. Introduction........................................ 12-1
.
9-1. Introduction........... ............................... 9-1 12-2. Custom Renewal Parts Listing.................. 12-1
.
9-2. Tools and Instruments ............................. 9-1 12-3. Ordering Renewal Parts ......................... 12-1
9-3. General Troubleshooting ........................... 9-1 12-4. Part Number Structure........................... 12-1
9-4. Stability Problem Troubleshooting ............... 9-6 12-4.1. Order-speciiic Assembly Part Numbers 12-1 .
9-4.1. Cyclical Stability Problems ..................... 9-6 12-4.2. Common Assembly Part Numbers ....
12-2
9-4.2. Mechanical Oscillation Problems .............. 9-7 12-4.3. Component Part Numbers .................... 12-2
9-4.3. Erratic Operation Problems ..................... 9-7 12-4.4. Board Part Numbers ........................... 12-2
9-4.4. Troubleshooting Procedures..................... 9-7 12-5. DC2000 Digital Adjustable Speed Drive
9-4.4.1. Initial Checks....................... 9-7 . Parts Lists ....... ................................... 12-2
9-4.4.2. Problem Determination........................ 9-7
9-4.5. Ac Line Phase Problems ......................... 9-7 APPENDIX A. GLOSSARY OF TERMS
9-5. Specific Fault Troubleshooting.................... 9-9
9-5.1. Fault Indication.................................... 9-9 APPENDIX B. HARDWARE DRAWINGS,
9-5.l . 1. Programmer Display ........................... 9-9
9-5.1.2. LED Display..................................... 9-9
c, CX,
AND G FRAME DRIVES
9-5.2. Types of Faults 9-9 B-1. Introduction.................................. ... B-1
9-5.3. Clearing the Fault................................ 9-10
9-6. Troubleshooting SCR Bridge Failures ..........9-11 APPENDIX C. HARDWARE DRAWINGS,
9-6.1. C, CX, and G Frame Troubleshooting ... •.9-11 . u
J AND K FRAME DRIVES
9-6.2. J, K, and M Frame Troubleshooting..........9-12 C-1. Introduction...... .. ................................. C-1
iii
SectionlSubiect Page Section/Subject Page
APPENDIX D. HARDWARE DRAWINGS, APPENDIX K. ELEMENTARY DIAGRAM,

M FRAME DRIVES K FRAME DRIVE
D-1. Introduction...... .. ........ .. ............. ........... D-1 K-1. Introduction . . . . . .. . . . . . . . .. .. . . . . .. . . . . . . . . . .... . . K-1
APPENDIX E. ELEMENTARY DIAGRAM, APPENDIX L. ELEMENTARY DIAGRAM,

c OR CX FRAME DRIVE WITH DCFB BOARD M FRAME DRIVE WITH DCFB BOARD
E-1. Introduction .......................................... E-1 L-1. Introduction......... . .................................L-1
APPENDIX F. ELEMENTARY DIAGRAM, APPENDIX M. ELEMENTARY DIAGRAM,

C OR CX FRAME DRIVE WITH SDCI BOARD M FRAME DRIVE WITH SDCI BOARD
F-1. Introduction...... . . .. . . . . . .... . ......... .. ..... . .. F-1 M-1. Introduction......................... . ...............M-1
APPENDIX G. ELEMENTARY DIAGRAM, APPENDIX n. PERIODIC MAINTENANCE

G FRAME DRIVE WITH DCFB BOARD N-1. Introduction .... .. .. ................................. N-1
G-1. Introduction.......................................... G-1 N-2. Preventive Maintenance... .. . ..................... N-1
N-3. Cooling Fans ........................................ N-2
APPENDIX H. ELEMENTARY DIAGRAM,
G FRAME DRIVE WITH SDCI BOARD APPENDIX 0. WARRANTY PARTS AND SERVICE
H-1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H-1 O-1. Warranty Terms ................... . . . . ......... . ... O-1
O-2. Obtaining Parts and Service Under
APPENDIX |. ELEMENTARY DIAGRAM. Warranty . . . .. . . ............................ . . . . . ... . . O-1
J FRAME DRIVE WITH DCFB BOARD
1-1. Introduction .................................. ........ .. 1-1
APPENDIX J. ELEMENTARY DIAGRAM,

J FRAME DRIVE WITH SDCI BOARD
1-1. Introduction............................................ J-1
iv
LIST OF FIGURES
l
Figure Page Figure Page
5-1. Sample Board Part Number, DS Series..........5-1 7-15. Sync Signal (SDCC Card TP29) Square u-
5-2. Pot Set at Default Position ..................•...... 5-2 Wave Synchronized to Ac Line Frequency 7-13 ..
5-3. ACNA Board Layout....................... ....5-3 7-16. SPC Card Layout ................................~.7 . -15
5-4. CDBA Board Layout......................
.. .
5-4 .
7-17 SPCB Card Layout . .............................. . 7-16
5-5. CPCA Card Layout ... . .......................... 5-4 7-18. STBA Board Layout ........................ 1-17
.
5-6• DCFB Board Layout ...................... ...... 5.7 8-1. Programmer Module......................... .......8-3
5-7. LCS Board Layout......................... . .. .. ..5-11 .
8-2. Changing Modes of Operation . ...................8-6
5-8. LTB Board Layout.......................... .. . 5-12 ..
9-1. BCD-coded LED Display . ........................9-9
- v
5-9. MBHA Board Layout . . . .. . . . .. . . . . .. .. . .. . 5-13 9-2. Binary-coded LED Display .........................9-9
5-10. NTB/3TB Board Layout .........................5-15 9-3. SCR Badge Assemblies, C Frame Drive 9-11
5-11, PCCA Card Layout ............................... 5-20 9-4. SCR Bridge Assemblies, CX Frame Drive .. 9-11 no
5-12. PCN Board Layout................................5-22 9-5. SCR Bridge Assemblies, G Frame Drive 9-12
...
a s
5-13. PCR Board Layout............................. 5-23 9-6. SCR Stack Connections, J and K Frame
5-14. RTBA Board Layout ......................... 5-24 Drives ........................................ . .9-13
5-15. SDCC Card Layout ...............................5-27 9-7. SCR Stack Assemblies, J and K Frame
5-16. SDCI Board Layout...............................5-31 .
Drives ........................... . ...... .. .
. .. . . ..
9-14
5-17. SHVI Board Layout...............................5-33 9-8. SCR Stack Connections, M Frame Drive.. ..9-15 .
5-18. SHVM Board Layout .............................5-35 9-9. SCR Stack Assemblies, M Frame Drive ..9-16
5-19. SLCC Card Layout ...............................5-38 B-1. C, CX, and G Frame Hardware Drawing
5-20. SPC Cad Layout .................................5-40 336A3511....................... .. U B-2 me
5-21• SPCB Card Layout................................5-46 C-1. J and K Frame Hardware Drawing

5-22. STBA Board Layout ................. ............5-49 ..
............................ ............. C-2
336A3508-..-
7-1. CDBA Board Layout..... .......................... 7-1
a s
D-1. M Frame Hardware Drawing 336A3509 D-2

7-2. DCFB Board Layout ................................ 7.5 E-1. Sample Elementary Diagram, C or CX
7-3. LCS Board Layout................................... 7-5 Frame Drive With DCFB Board ..._ .... ....... E-3
7-4. SDCI Board Layout ................................. 7.7
I
F-l. Sample Elementary Diagram, C or CX

...
7.5. CPCA Card Layout ... ........................... 7-8 Frame Drive With SDCI Board ........... F-3
7-6 • MBHA Board Layout ..............................7-10 G-1. Sample Elementary Diagram, G Frame
7-7 • NTB/3TB Board Layout ........... .......... ....7-10 Drive With DCFB Board .._........................ G-3
7-8• SDCC Card layout ................................7-12 H-1. Sample Elementary Diagram, G Frame
1-9. Current Feedback (SDCC Card.TPS) in Drive With SDC] Board............................H-3
.. .
Discontinuous Current.. .. .... .................. 7-12 1-1. Sample Elementary Diagram, J Frame Drive
7-10. Current Feedback (SDCC Card TP8) in With DCFB Board....................................1-3
Continuous Current............................... 7-12 J-1. Sample Elementary Diagram, J Frame Drive
7-11. Voltage Feedback (SDCC Card TP37) in With SDCI Board..................................... J-3
Discontinuous Current ...........................7-13 K-1. Sample Elementary Diagram, K Frame
7-12. Voltage Feedback (SDCC Card TP37) in .
Drive ... ..............................................K-2
Continuous Current ...............................7-13 L-1. Sample Elementary Diagram, M Frame
7-13. Current Feedback (SDCC Card TP8) With Drive With DCFB Board.......................... L-3
One SCR Open or Disconnected ...............1-13 M-1. Sample Elementary Diagram, M Frame
7-14. Voltage Feedback (SDCC Card TP37) Drive With SDCI Board ......................... M-3
With One SCR Open or Disconnected . . . .. . . . 7-13
v
LIST OF TABLES
Table Page Table Page
4-1. DC2000 Frame Size Specifications ........4-3 6-16. Connector TB1, LCS Board Power
5-1. CDBA Board Adjustable Hardware ...............5-5 Connections .................................. .. ... 6-12
5-2. CDBA Calibration Information .
. .....5-5 6-17. Connector 8PL, I/O Between LTB,
5-3. DCFB Board Adjustable Hardware ...............5-8 NTB/3TB, and SDCC Boards ..... . ............ 6~13
5-4. NTB/3TB Board Adjustable Hardware .... . 5-16 6-18. Connectors IN1 Through INS, Inputs to
5-5. Power Connect Board Applications ............. 5-19 LTB Board..................... .. ...... . ........... 6-14
5-6. PCCA Card Adjustable Hardware............... 5-20 6-19. Connector IOPL, I/O Between LTB Board
5-7. PCN Board Adjustable Hardware ............... 5-22 and SLCC Card ................................. . 6-14
.
5-8. PCR Board Adjustable Hardware .............. 5-23 6-20. Connector OPTPL, I/O Between LTB
5-9. RTBA Board Adjustable Hardware ......... . .. . 5-25 Board and nTB/3TB Board..................... 6-14
5-10. SDCC Card Adjustable Hardware ............. 5-27 6-21. Connectors OT1 Through oT7, LTB Board
5-11. SDCI Board Adjustable Hardware ............. 5-31 Connnections from Form C Relay Contacts .. 6-15
5-12. SHVI Board Adjustable Hardware............. 5-34 6-22. Connector RPL, I/O Between LTB Board
5-13. SHVM Board Adjustable Hardware ........... 5-36 and RTBA Board................................. 6-15
5-14. SLCC Card Adjustable Hardware .............5-39 6-23. LEDs on LTB Board ............................. 6-15
W
5-15. SPC Card Adjustable Hardware................ 5-41 6-24. MBHA Fiber-optic Connectors ................ 6-16
5-16. SPCB Card Adjustable Hardware .............. 5-46 6-25. Connectors TBPSA and TBPSB, Power
5-17. STBA Board Adjustable Hardware ............ 5-50 Supply Inputs to MBHA Board ................ 6-17
6-1. Connector ARCPL, I/O Between ACNA 6-26. Connector 3TB, I/O Between NTBI3TB
Board and SLCC Card ..............................6-2 Board and External Connections............... 6-18
6-2. Connector ITB, CDBA Board Contactor .
6-27 Connector 6PL, I/O Between NTB/3TB
Control Connections .................................6-3 Board and SDCC Card ................... ...... . 6-22
6-3. Connector ITB, CPCA Card Contactor 6-28. Connector COMPL, RS-232C I/O Between
Control Connections .................................6-3 NTB/3TB Board and User Interface .......... 6-24
6-4. Connector 1PL, I/O Between DCFB Board 6-29. Connectors IFPL Through 61=pL and
and SDCC Card......................................6-5 IRPL Through 6RPL, Output from PCCA,
6-5. Connector 1PL, I/O Between SDCI Board PCN, or PCR Board to SCR Bridge .......... 6-25
and SDCC Card......................................6-6 6-30. PCCA Card Stab Tenxninal Connections . 6-25
6-6. Connector 2PL, I/O Between DCFB or SDCI 6-31. PCN and PCR Board Stab Terminal
Board and NTB/3TB or STBA, SDCC, and Connections ...... . .. . .. .. . ......... . ..... . . . .. . ... 6-26
SLCC Boards .........................................6-7 6-32. Connector RTBA, I/O Between RTBA
6-7, Connector 4PL, I/O Between DCFB or SDCI Board and External Connections............ . .. 6-27
Board and NTB/3TB or STBA Board .. . .. .......6-7 6-33. Connectors CP1PL Through CP5PL and
6-8. Connector SPL, I/O Between DCPB or SDCI Y9PL Through Y35PL, RTBA Pluggable
Board 2I1d PCCA, PCN, or PCR Board .........6-8 Circuits...................... . ...................... 6-28
6-9. Connectors ICPL, CNPL, CPTPL, FAPL, 6-34. LEDs on Relays of RTBA Board .............. 6-28
NPL, PPL, and sopL, I/O Between DCFB 6-35. Connector 3PL, SDCC Card Output to
or SDCI Board and Components ..................6-9 SLCC Card........................................ 6-29
6-10. Connectors IAIPL, IA2PL, 11=1pL, and 6-36. Connector 7PL, I/O Between SDCC Card
IF2PL, I/O Between DCFB OI SDCI Board and SPC or SPCB Card ......................... 6-30
and Shunts ......................................... 6-10 .
6-37 Connector 11PL, SDCC Output to Meters... 6-30
6-11. Connector MACPL, I/O Between DCFB 6-38. LEDs on SDCC Card ........ . . .. . ............... 6-30
or SDCI Board and Contactor Driver 6-39. Connectors CTIPL, CT3PL, DCIPL, and
Circuits ............................................. 6-10 DC2PL, CT and Shunt Inputs to SHVI or
6-12. DCFB Board Stab Terminal Connections ....6-10 SHVM Board ................ ........... ........... 6-31
6-13. Neon Lamp and LEDs on DCFB Board ......6-11 6-40. Connectors MPL and RMPL, SHVI Board
6-14. SDCI Board Stab Terminal Connections ....6-11 . Contactor Driver Circuit Connections........ 6-31
6-15. Neon Lamps and LEDs on SDCI Board ......6-11 6-41. SHVI and SHVM Board Stab Terminal
Connections ................... . . .. .... ............ 6-32
vi
LIST OF TABLES Continued
Table Page Table Page
6-42. Neon Lamps on SHVI Board....................6-32 12-1. DC2000 C and CX Frame Drive Parts
6-43. Connector KPPL, I/O Between SLCC Card List........................... .
. ..................... 12-3
and Keypad.........................................6-33 12-2. DC2000 G Frame Drive Parts List 12-11
6-44. Connectors 16PL and ITB, I/O Between 12-3. DC2000 J and K Frame Drive Parts List ...12-18 .
SPC or SPCB Card and External ...........12-27
12-4. DC2000 M Frame Drive Parts List.........
Connections ........................................6-34 C-1. Hardware Drawing 336A3508_, J and K
6-45. Connector SYTB, I/O Between SPCB Card Frame Drive Applications ......................... C-1
and External Connections ....................... 6-35 E-1. C or CX Frame Drive With DCFB Board
6-46. SPCB Card Fiber-optic Connectors............6-35 Elementary Diagram Sheet Summary .. E-1
6-47. Connector STBA, I/O Between STBA E-2. Terminal Board 2TB Connections, C or CX
Board and External Connections ...............6-36 Frame Drive With DCFB Board E-2
6-48. Connector COMPL, RS-232C I/O Between F-1. C or CX Frame Drive With SDCI Board
STBA Board and User Interface................6-41 Elementary Diagram Sheet Summary ........... F-1
7-1. DC2000 Line Fuse Values ......................... 7-2 F-2. Terminal Board 2TB Connections, C or CX
7-2. DCFB Board Fuses .................................. 7-4 Frame Drive With SDCI Board .. F-2
7-3. SDCI Board Fuses ................................... 7-6 G-1. G Frame Drive With DCFB Board
7.4. CDBA Board Testpoints ............................ 7-7 Elementary Diagram Sheet Summary G-1
7-5. CPCA Card Testpoints ............................. 7-8 G-2. Terminal Board 2TB Connections, G Frame
7-6. DCFB Board Testpoints .................... 7-8 ..........
Drive With DCFB Board,,,---,---................G-2
7-7. MBHA Board Testpoints ........................... 7-9 H-1. G Frame Drive With SDCI Board
7-8. NTB/3TB Board Testpoints... 7-9.. Elementary Diagram Sheet Summary . H-1
7-9. SDCC Card Testpoints ............................7-11 H-2. Terminal Board 2TB Connections, G Frame
.
7-10. SDCI Board Testpoints.. ........................7-14 Drive With SDCI Board......... ..... ..H-2
7-11. SPC Card Testpoints ............................. 7-14 1-1. J Frame Drive With DCFB Board
7-12. SPCB Card Testpoints............................7-15
6
Elementary Diagram Sheet Summary 1-1

7-13. STBA Board Testpoints ..........................7-16
6
1-2. Terminal Board 2TB Connections, J Frame

8-1. Standard Diagnostic Tests.......................... 8-9 Drive WithDCFB Board .... ..... .... .
6
1-2
8-2. RAM Addresses for Analog Signals._ .. ._ .......... 8-10 6 6 6 J-1. .T Frame Drive With SDCI Board Elementary
8-3. Diagnostic Mode Analog Output Points ..8-12 Diagraln Sheet Sun1rnary ............................ J-1
9-1. Troubleshooting Quick Reference Guide .. ... 9-2 . o f J-2. Terminal Board 2TB Connections, I Frame
9-2. General Troubleshooting Chart ................ 9-3 Drive With SDCI Board .............................J-2
9-3. Stability Troubleshooting ........................... 9-8 L-1. M Frame Drive With DCFB Board
9-4. Summary of Fault Types ..........................9-10
6 6 6 6 6 Elementary Diagram Sheet Summary ........... L-1
9-5. Specific Fault Troubleshooting Using L-2. Terminal Board 2TB Connections, M Frame
Fault Numbers ......................................9-17 Drive With DCFB Board.......................... L-2
10-L MCP Circular List Software Jumpers M-1. M Frame Drive With SDCI Board
EE.6282 (MDGNJP)..............................10-5 Elementary Diagram Sheet Summary ......._.. M-1 . _
10-2. DCP Circular List Software Jumpers.... ... 10-7 M-2. Terminal Board 2TB Connections, M Frame
.
u. c
10-3. LCP History Buffer Software Jumpers .......10-9 6 , 6 Drive With SDCI Board ......................... M-2
11-1. SCR Module Mounting and Connecting
Torque Requirements.. ...........................11-2
vii
Notes:
viii
CHAPTER 1
OVERVIEW
1-1. DEFINITION AND SCOPE Chapter 8 - Software Adjustments

Defines the adjustable software used to customize
This manual describes the DC2000 Digital Adjustable and fine-tune the DC2000 drive. Includes informa-
Speed Drive. The DC2000 drive is a microprocessor- tion on operating the Programmer, the module used
based power converter that provides a controlled do to make software adjustments and to perform diag-
output for customer application. nostic testing.
This manual is intended to assist applications and Chapter 9 - Troubleshooting
maintenance personnel in understanding the equipment
Provides information to detect and correct prob-
hardware and software . lems with the DC2000 drive, including general
problems, stability problems, and problems indi-
The manual is organized as follows:
cated by diagnostic test error codes.
Chapter 1 - Overview Chapter 10 - Diagnostic Lists
Briefly defines the DC2000 drive, with an overview
Describes the DC2000 drive's Diagnostic Lists and
of the hardware and software design.
how to use them for troubleshooting.
Chapter 2 - Receiving, Handling, and Storage
Chapter 11 - Parts Replacement
Provides guidelines for handling and storing the
Provides instructions for replacing printed wiring
DC2000 drive upon receipt.
1 boards and silicon-controlled rectifiers (SCRs) used
' the DC2000 drive.
m
Chapter 3 - Installation and Initial Startup
Contains environmental, mounting, and electrical Chapter 12 - Spare and Renewal Parts
guidelines for installing the DC2000 drive, includ-
Contains ordering information for DC2000 drive
ing pre-startup checks . parts, including part numbers.
Chapter 4 - lhnctional Description
Appendix A - Glossary of Terms
Describes the DC2000 drive software and hardware
Defines acronyms and terms used in this manual.
structure, including overall operation.
Appendix B - Hardware Drawings, c, cx, and G
Chapter 5 - Printed Wiring Board Descriptions
Frame Drives
Describes the function and operation of boards
Includes the hardware drawings provided in the
within the drive, including descriptions of the ad-
door pocket of DC2000 C, C Extension (CX), and
justable hardware included on each board.
G frame drives.
Chapter 6 - I/O Definitions
Appendix C - Hardware Drawings, J and K Frame
Lists and defines I/O connector points, stabs, and Drives
LEDs for the DC2000 drive.
Chapter 7 - Fuses and Testpoints
door pocket of DC2000 J and K frame drives .
Lists and defines the fuses and signal testpoints Appendix D - Hardware Drawings, M Frame Drives
available in the drive and on some boards.
door pocket of DC2000 M frame drives.
1-1
Appendix E - Elementary Diagiram, C or CX Frame Appendix 0 - Warranty Parts and Service

Drive With DCFB Board Explains procedures for obtaining warranty infor-
Provides a sample elemental diagram for a C or mation and service .
CX frame drive that contains a DS200DCFB Power
Supply Board (DCFB). Refer to the Table of Contents for the organization of
these chapters and appendices.
Appendix F - Elementary Diagram, C or CX Frame
Drive With SDCI Board
Provides a sample elementary diagram for a C or 1-2. EQUIPMENT OVERVIEW
CX frame drive that contains a DS200SDCI Do
Power Supply and Instrumentation Board (SDCI). The DC2000 Digital Adjustable Speed Drive uses a
basic digital hardware design with powerful application
Appendix G - Elementary Diagram, G Frame Drive software. The user interface consists of a 10-character
With DCFB Board alphanumeric display and a keypad for simplified
monitoring, diagnostics, and tuneup.
Provides a sample elementary diagram for a
G frame drive that contains a DCFB board.
1-2.1. Communications Interfaces
Appendix H - Elementary Diagram, G Frame Drive
With SDCI Board
The DC2000 drive provides local area network (LAN)
Provides a sample elementary diagram for a and RS-422 interfaces for external communications. An
G frame drive that contains an SDCI board. RS-232C interface is also provided for use with Me
ST2000 Toolkit or Drive Configurator, LynxOS® Ver-
Appendix I - Elementary Diagram, J Frame Drive sion.
With DCFB Board
J frame drive that contains a DCFB board. 1-2.2. Software Design
Appendix J - Elementary Diagram, J Frame Drive The drive application program consists of functional
With SDCI Board software modules (building blocks), which are com-
Provides a sample elementary diagram for a bined to perform to system requirements. Block dehni-
.T frame drive that contains an SDCI board. tions and contiguradon parameters are stored in ROM
(read-only memory), while variables are stored in RAM
Appendix K - Elementary Diagram, K Frame Drive (random-access memory). Microcontrollers execute the
code. See Chapter 4 for details.
K frame drive . Tuneup and diagnostic software is transparent to the
user. A Programmer module with a digital display and
Appendix L - Elementary Diagram, M Frame Drive keypad allows an operator to request parameter values
With DCFB Board and self-checks. See Chapter 8 for details.
Provides a sample elementary diagram for an
M frame drive that contains a DCFB board.
1-2.3. Hardware Design
Appendix M - Elementary Diagram, M Frame Drive
With SDCI Board A DC2000 drive consists of a control section and a
Provides a sample elementary diagram for an power converter section, described in Chapter 4.
M frame drive that contains an SDCI board.
The control section, or controller, includes printed
Appendix N - Periodic Maintenance wiring boards containing microprocessors with compan-
ion circuits, including EEPROM (electrically erasable
Provides recommended periodic maintenance for
programmable read-only memory). Additional boards
the equipment.
provide optional fear res. Chapter 5 describes the
boards.
1-2
The power converter section consists of an SCR bridge -

GEH-6203 Drive Configurator, LynxOS Version,
rectifier and control circuitry. The components and User's Manual
frame size vary for the do output required.
GEH-6328 DS2020FIEAN 50 100 Amp NRX/NRP
Chapter 4 defines the frame sizes available for the Field Exciter Module
DC2000 drive.
GEH-6329 - DS2020FEBN 75 Amp NRX/NRP Field
Exciter Module
1-3. RELATED DOCUMENTS
_
GEH-6330 DSZOZOFECN 24 Amp NRX/NRP Field
The following documents also apply to the DC2000 Exciter Module
drive, and may assist 'minstallation and troubleshoot-
ing: Custom software (if applicable)
Hardware summary - located in the drive door pocket, GEH-6011 - Installation Guidance Service for
includes drawings showing the locations of termi- DIRECTOR-MATIC° 2000 Equipment
nal board points, printed wiring boards, connec-
tors, plugs, and power fuses within the drive (see GE Drive Systems & Turbine Controls supplies the
Appendices B through D for examples) applicable documents to customers as needed to support
the equipment.
GEH-5860 - ST2000 Toolkit User's Manual
1-3
Notes:
1-4
I CHAPTER 2
RECEIVING, HANDLING, AND STORAGE
2-1. INTRODUCTION If assistance is needed, contact:
This chapter contains guidelines and precautions for Industrial Systems-

handling and storing the DC2000 Digital Adjustable Drive Systems & Turbine Controls
Speed Drive upon receipt. General Electric Company
Product Service Engineering
1501 Roanoke Boulevard
2-2. RECEIVING AND HANDLING Salem, VA 24153-6492 USA
Phone 001-540-387-7595
Fax 001-540-387-8606
CAUTION
2-3. STORAGE
Possible danger of damage to equipment.
Immediately upon receiving the DC2000 If the drive is not installed immediately upon receipt, it
drive, place it under adequate cover to pro- must be stored properly to prevent corrosion and dete-
tect it from adverse conditions. Packing rioration. Since packing cases do not protect the equip-
cases are not suitable for outdoor or unpro- ment for outdoor storage, the customer must provide a
tected storage. clean, dry place free of temperature variations, high
humidity, and dust .
Shock caused by rough handling can damage
electrical equipment. To prevent such dam- Use the following guidelines when storing eqmlpment:
age when moving the equipment, be sure to
observe normal precautions along with all 1. Place the equipment under adequate cover with the
handling instructions printed on the case. following requirements:
General Electric Company (GE) carefully inspects and a. Keep the equipment clean and dry, protected
packs all equipment before shipping it from the factory. from precipitation and flooding .
A packing list, which itemizes the contents of each
package, is attached to the side of each case of the b. Use only breathable (canvas type) covering
equipment. -
material do not use plastic .
GE provides handling guidelines to the carrier. During 2. Unpack the equipment as described in section 2-4,
shipment, the equipment should not be exposed to ex- and label it.
cess moisture or humidity, extreme temperatures, ex-
cess temperature changes, or rough handling . 3. Maintain the following environment in the storage
enclosure:
Upon receipt, carefully examine the contents of each
shipment, and check them with the pacldng List. Imme- a. Ambient storage temperature limits from
diately report any shortage, damage, or visual indica- -20 °C (-4 °F) to 55 °C (131 °F).
tion of rough handling to the carrier. Then notify both
the transportation company and GE. Include the serial b. Surrounding air free of dust and corrosive ele-
number, part (model) number, drive code, GE requisi- ments, such as salt spray, or chemical and
tion number, and case number when identifying the electrically conductive contaminants .
missing or damaged part.
c. Ambient relative humidity from 5 to 95% with
provisions to prevent corrosion.
2-1
d. No rodents. 2-4. UNPACKING
e. Limit temperature variations that can cause It is good practice to not completely unpack the equip-
moisture condensation on the equipment. ment until it has been placed as near as possible to its
permanent location. If the equipment has been exposed
to low temperatures for an extended period of dine, do
CAUTION not unpack it until it has reached room temperature.
When unpacldng, check the contents of each case
Moisture on certain internal parts can cause against the pacldng list. Report any shortage to GE
electrical failure. Drive Systems & Turbine Controls.
Condensation occurs with temperature drops of 15 °C Use standard unpacldng tools, including a nail puller .
(27 °F) at 50% humidity over a 4-hour period, and with Carefully move the equipment from its container to
smaller temperature variations at higher humidity. avoid damaging or marring the part. Wipe off any par-
ticles of pacldng materials or foreign substances that
If the storage room temperature varies in such a way, may be lodged in or between the parts.
install a reliable heating system that keeps the equip-
.
ment temperature slightly above that of the ambient air Small parts (such as bolts and screws) are packed in
This can include space heaters or panel space heaters special containers to keep them together. However, they
(when supplied) inside each enclosure. A 100 W lamp may become separated. Therefore, carefully inspect
can sometimes serve as a substitute source of heat. pacldng material for loose parts before discarding.
CAUTION 2-5. TIME LIMITATIONS
The above specifications apply to shipping and storage

To prevent fire hazard, remove all cartons durations of up to one year. Longer times may require
and other such flammable materials packed additional treatment. For warranty information, refer to
inside units before energizing any heaters. Appendix O.
2-2
CHAPTER 3
(
INSTALLATION AND INITIAL STARTUP
3-1 . INTRODUCTION . Electromagnetic radiation or noise introduced by:
This chapter contains environmental, mounting, and Radio frequency signals, typically from port-
electrical guidelines for installing the DC2000 Digital able transmitters used near the equipment or its
Adjustable Speed Drive. The information presented wiring.
includes basic circuit checks needed after installation
and before the drive is started up. Stray high voltage or high frequency signals,
typically produced by arc welders, unsup-
Before starting installation, consult and study all fur- pressed relays, contactors, or brake coils op-
nished drawings. These should include arrangement erating near drive control circuits.
drawings, connection diagrams, elementary diagrams,
and a summary of the equipment.
3-3. MOUNTING
3-2. OPERATING ENVIRONMENT The system outline drawing (included with the system
documentation) contains the drive dimensions and
DC2000 drives are suited to most industrial environ- mounting diagrams.
ments. To CIISUIC proper performance and normal op-
erational life, the environment should be maintained as Use the following mounting guidelines:
I
follows:
Ambient temperature range: 0 °C (32 °F) to

. Position an enclosed drive to permit heat radiation
from all surfaces.
50 °C (122 °F)
A wall-mounted drive can be mounted on any firm,
Maximum operating temperature: 50 °C (122 °F) .
reasonably flat, vertical surface
Maximum relative humidzlyz 95% non-condensing . A wall-mounted enclosure can be placed side-by-
side with another enclosure.
Environments that include excessive amounts of any of
the following elements reduce drive performance and • Provide front clearance of at least the width of the
life :
enclosure door so that the door may be fully opened
for easy access.
• Dust, dirt, or foreign matter
Vibration or shock 3-4. CABLING AND WIRING

. Moisture or vapors All installations should meet the requirements of both
. Rapid temperature changes

the National Electrical Code (NEC) and any applicable
local codes. Use these codes to determine such factors
. Caustic fumes
as wire size, insulation type, conduit sizing, and enclo-
sures.
. Power line fluctuations
3-1
GEH-6005 DC2000 Digital Adiustable Speed Drive
NOTE
WARNING
Elementary diagrams may change with
product upgrades and revision. The elemen-
Danger of electric shock or burn. Before tary diagrams presented in Appendices E
handling and connecting any power cables to through M are current as of the issue date of
the equipment, €IlSl1I'€ that all input power is this manual.
turned off. Then check voltage levels on the
wiring to ensure that it is not carrying haz- Ac input power connects to either a breaker or discon-
ardous voltages. nect switch, which is connected to L1, L2, and L3 OH
the line side of fuses 1=U1, FU2, and FU3 .
3-4.1. Ac Power Requirements Control power may be fed from the ac input, or may be
supplied externally by connection to fuses CPTFU1 and
The DC2000 drive is normally configured with the fol- CPTFU2.
lowing power requirements:
Motor connections are to output terminals PI and P2.
Voltage: 230, 460, or 575 V ac, +10% and -5%
3-4.2.2. CONTROL CONNECTIONS. Control connec-
Phase: 3-phase tions to the DC2000 drive are made by wiring the Drive
Terminal Board (NTB/3TB) or Basic Drive Terminal
Nominal line frequency: 50 or 60 Hz, i2% Board (STBA). Chapter 5 describes these boards and
includes layout drawings to identify the connectors on
Input power to the control power transformer (cpT), the board. Chapter 6 defines the UO connections.
which provides 115 V ac and 40 V ac to the power
supply board, may be supplied by the ac input, or by an For the LAN I/O Terminal Board (LTB), connect all
external control power source. The requirements for I/O to the LTB's screw terminals. The terminals are
externally fed control power are: identified by onboard labels (name and number) .
Voltage: 230, 460 or 575, + 10% and -5 % The optional Relay Terminal Board (RTBA) provides
screw terminal connections to the relays, as labeled.
Phase: 3-phase
Nominal line frequency: 50 or 60 Hz, i2% 3-4.3. Wiring Level Separations
To prevent signal interference caused by electrical

3-4.2. Connections noise, installation must consider the type of voltages on
the wiring. These types must be separated and spaced as
Cabling and wiring connections include: described below.
• Incoming ac line connections There are four levels of wiring, which must be run in
separate conduits or wireways:
. Power connections to the motor Held
. Low-level signals (Level L, see system level draw-
ings to identify), which consist of analog signals up
• A11 terminal board connections
to £0 V do and digital signals of 0 through 15 V do
When connecting any wiring/cabling, ensure that all
connections are tight.
• Medium-level signals (Level M), which consist of
analog signals greater than 50 V do with less than
28 V ac ripple, and 28 V do light and switching cir-
3-4.2.1. POWER CONNECTIONS. Refer to the system cuits
elementary diagram provided with the drive. Sample
elementary diagrams for the available frame sizes of the
DC2000 drive are provided in Appendices E through
M.
3-2
• High-level signals (Level H), which consist of de 3-4.6. Commons

switching signals greater than 28 V, analog signals
greater than 50 V de with greater than 28 V ac External commons, including reference and meter, can
ripple, regulating signals of 50 V with less than 20 only be connected at the COM connector on the
A current, and ac feeders of up to 20 A NTB/3TB or STBA board, unless otherwise specified by
the system elementary diagrams,
• Power wiring (Level P), which consists of ac and
do buses up to 800 V with currents of more than 20
A 3-4.7. Suppression
For additional information O11 wiring level definitions Electrical noise transients caused by control system re-
and separation, refer to GEH-6011, Installation Guid- lays, solenoids, or brake coils can cause erratic drive
ance Servicefor DIRECTOR-MATIC 2000Equipment. behavior. To prevent this, add a series resistorlcapaci-
tor (RC) suppressor in parallel with the 115 V ac coils
of these devices. A 220 Q, 2 W resistor in series with a
3-4.4. Spacing 0.5 oF, 600 V capacitor can typically be used.
The following requirements ensure correct distance

between cabling and wiring: 3-5. SERVICE AND PARTS INSTRUCTION
Signal wiring and power wiring may cross at right Each DC2000 drive contains instructions placed inside
angles with a minimum 1-inch separation. the door to aid in connecting and troubleshooting the
drive. These insrrucdons contain the following infor-
Avoid parallel runs between signal-level wires and mation:
power or control wires. If signal wires must be run
parallel with power or control wires: Board locations
For distances up to 4 feet, maintain a minimum

separation of 3 inches.
. Power module locations
Fuse information and nomenclature

For distances over 4 feet, add 1/4 inch of
spacing for every foot of additional distance. Plug locations
• Within pillboxes and junction boxes, use grounded

barriers to maintain the level separations.
. Incoming control connections at the NTB/3TB or
STBA board
• Power connections
3-4.5. Grounding
1. Ground the drive common (COM) at only one 3-6. POWER-OFF CHECK
point. If the reference is supplied by a numerical
control or by a process instrument with a grounded A11DC2000 drives are factory-tested and operable
common, do not provide a separate ground for the when shipped to the installation site. However, it is not
dive common. uncommon for connections to loosen during shipping
and handling. Therefore, anal checks should be made
2. If an isolation transformer is used and must be after installation before starting the equipment.
grounded, use a high resistance ground, unless lo-
cal electrical codes direct otherwise . Before initial powerup, check the drive using the steps
listed in sections 3-6.1 and 3-6.2.
3. For shielded and twisted shielded wire, ground the
shields on one end only, preferably at the drive
end. Provisions have been made to tie shields to
chassis ground at the drive I/O.
3-3
3-6.1. Wiring and Circuit Checks 6. If a current transformer circlu't is not complete,
check that the shunt (used for shipping) is removed .
WARNING 7. With the drive disconnected from meggered cir-
cuits, check for grounds in the motor or leads by
meggering all terminals to ground.
This equipment contains a potential hazard
of electrical shock or burn. Extremely high
voltages are present on some circuitry. To 3-6.2. Motor and Device Checks
prevent accidental injury, do not touch any
circuitry without first ensuring that it does 1. Check mat the motor options are correctly installed
not carry these voltages . and connected per their device instructions .
1. Ensure that all electrical terminal connections are 2. Ensure that the motor shaft is free to rotate, and
tight. Unless otherwise directed in the system that the motor and moving devices are free to func-
documentation, electrical bus connection hardware tion.
should be torqued as defined below:
3. Verify the motor and controller nameplate data,
SAE Torque
such as motor maximum field current, rated Held
Thread (lb ft)
voltage, and maximum field voltage .
I
1/4-20 4 a. Check that the motor and controller voltages

3/8-16 14 match.
1/2-13 35
5/8-1 1 70 b. Check that the motor field current does not ex-
ceed controller current.
NOTE 4. Check that all fuses are installed, are the right size,
and make Firm contact in the householder .
To ensure that electrical connections remain
tight, they should he rechecked within three
to six months after initial powenxp, and an- 3-7. POWER APPLICATION AND STARTUP
nually thereafter, using screwdrivers and
wrenches or an infrared survey. After the previous power-off checks, complete the fol-
lowing steps to check the drive with the power on.
2. Ensure that all devices, modules, and boards are
secure and have not been damaged during shipping
and handling or installation. Boards may be held in WARNING
place by plastic snaps (holders) or mounted on
standoffs. Check that all holders are snapped into
position and all standoffs are securely tightened. Before any adjustments, servicing, or any
other act is performed requiring physical
3. Check that all incoming wiring agrees with the contact with electrical working components
elementary drawings supplied with the drive, and is or wiring of this eqLu°pment, ensure all power
complete and correct. supplies are turned off. Then ground and
discharge the equipment.
4. Ensure that the incoming wiring conforms to ap-
proved wiring practices, as described previously 1. Check that incoming power is the correct voltage
(section 3-4). and frequency.
5. Ensure that no wiring has been damaged or frayed 2. Apply power to the drive.
during installation. Replace if necessary.
3-4
3. Check for correct rotation of the 3-phase blower in b. If a fault occurs at powerup, the display blinks
the drive (if used). If 'mcorrectz and shows the fault name and number. (For
fault code definitions, see Chapter 9.)
a. Turn power off. Ensure that the circuit is dead
before touching it. 5. Using the system elementary diagram, ensure that
all permissive, start, and stop circuits are function-
b. Interchange any two leads to the blower motor . ing properly .
c. Re-apply power and check for proper rotation. 6. Call the local GE Service Office for additional
checks and startup .
4. Check the display on the Programmer (described in
Chapter 8) for error indication: NOTE
a. If the drive powers up with no faults, the Pro- The DC2000 drive software architecture re
grammer indicates ready-to-run by displaying quires that a trained specialist conduct addi-
M S 0% I 0% (Manual Mode) or A s 0% I tional checks and startup using the ST2000
0% (Automatic Mode). Toolkit or Drive Configurator, LynxOS
Version, developed for that purpose.
3-S
Notes:
3-6
CHAPTER 4
FUNCTIONAL DESCRIPTION
4-1. INTRODUCTION 4-2.2. Building Block Architecture
This chapter describes the DC2000 Digital Adjustable The block programming scheme is an open architec-
Speed Drive software and hardware structure, and ture programming method that combines pre-existing
overall operation of the drive. Refer to the sample ele- blocks of code for a variety of applications. The drive
mentary diagrams contained in Appendices E through software is configured from a library of functional
M. Chapter 5 contains descriptions of the printed wiring blocks. The blocks are then connected by a mechanism
boards contained in the drive. that schedules and controls their execution.
The DC2000 dive stores programming data as follows:

4-2. DRIVE SOFTWARE STRUCTURE
• Block library (block definitions) in the Drive Con-
The DC2000 drive stores most configuration and ad- trol Processor (DCP) ROM
justment data in EEPROM O11 the Drive Control Card
(SDCC). This data is organized into 16-bit words, and
is stored and checksummed. The SDCC's Drive Control
. Block variables i11 RAM
Processor (DCP) controls memory access. • Block configuration parameters in EEPROM
Four major elements of the software configuration are: An operator can examine and adjust parameters stored
. Generic interface to inner motor control loops
in EEPROM in one of three ways: using the Program-
mer .on the LAN Communications Card (SLCC), or
. Pointer-based selection of inputs to functional

using the ST2000 Toolldt (see GEH-5860) or Drive
Configurator, LynxOS Version (see GEH-6203), 011 a
modules serially connected computer .
• Logical addressing of primary variables
. Use of functional building blocks for primary

regulator structures
4-2.3. Diagnostics
The DC2000 drive provides built-in diagnostics for

automatic selftest at powerup and for troubleshooting. It
tests circuitry down to the board level, generating diag-
4-2.1 . Block System nostic messages. There are three ways to decode these
messages:
The DC2000 dive application software is a structure of
software modules that define data flow and function . Using the LED diagnostic readout on the SDCC
(see Chapter 9)
execution. These modules are pre-deiined blocks of
code that perform specific functions.
.As
The software includes simple blocks, such as summing

. Using the Programmer's alphanumeric readout (see
Chapter 8)
junctions, and complex blocks, such as speed regula-
tors. These functions are applied using the building
block architecture described below.
. Reading diagnostic messages over an optional
RS-232C communication link.
4-1
4-2.4. Configuring Blocks . Multi-bridge Signal Processing Card (SPCB)
A block source list is the program schedule. It defines . Multi-bridge Hub Communications Board (MBHA)
which blocks are to be executed and their rate and rela-
tive order of execution. This list consists of a linear • LAN I/O Terminal Board (LTB)
sequence of source words stored in EEPROM.
Relay Terminal Board (RTBA)
The block compiler translates this source information
into a set of run lists. These lists point to run-time code Section 4-4 describes the d_rive's overall control opera-
and data blocks. The block interpreter reads the run tion. Chapter 5 describes the function and operation of
lists. It uses a compact Next Block instruction sequence the control section's printed wiring boards.
to thread the execution of compiled blocks.
The ST2000 Toolkit and Drive Configurator, LynxOS 4-3.2. Power Converter
Version, display the blocks as configured for the par-
ticular application. The DC2000 drive's power converter section includes
SCR bridge rectifiers, snubber circuits, and control
circuitry. The components vary for the power output
4-3. DRIVE HARDWARE STRUCTURE required. Section 4-5 describes these components and
their operation.
The DC2000 hardware consists of the control section
and the power converter section.
4-4. CONTROLLER OPERATION
The power conversion hardware is defined by the appli-
cation requirements, and therefore determines the The DC2000 drive provides microprocessor regulation
drive's frame size (see Table 4-1). The control section for de motor control. The drive combines programma-
is basically the same for the different frame sizes. ble de drive control with power circuitry. Drive pa-
rameters are stored in EEPROM, keeping them accurate
and drift free .
4-3.1. Control Section
Three-phase ac input power is fed into the DC2000
The control section, or controller, contains powerful drive through ac line fuses, current transformers (CTs),
programmable microprocessors with companion cir- and the MA contactor (up to 300 hp). The input power
cnitry, including EEPROM, to process the application enters the power conversion SCR modules, which con-
software. The controller includes the following printed vert the ac input to an adjustable de output. The do out-
wiring boards: put current is fed through a shunt, a de link thse, and an
. Drive Control Card (SDCC), which contains mi-

croprocessor circuitry
MD contactor (greater than 300 hp) to the de motor
armature 4
Motor field control (MFC) can be provided either by

Drive Terminal Board (NTB/3TB) or Basic Drive an internal 10 A mandmum field supply or by the fol-
Terminal Board (STBA) lowing optional external field supplies:
. LAN Communications Card (SLCC), which in- . DS2020FEAN 50 - 100 A NRX/NRP Field Exciter
Module (FEAN)
cludes the Programmer
. Power Supply Board (DCFB) or Dc Power Supply

and Instrumentation Board (SDCI)
• DS2020FEBN 75 A NRXlNRP Field Exciter
Module (FEBN)
. Power Connect Board (PCN, PCR, or PCCA) DS2020FECN 24 A NRX/NRP Field Exciter
Module (FECN)
Optional boards includel
Refer to publication GEH-6328 for the FEAN module,
• Signal Processor Card (SPC) GEI-I-6329 for the FEBN module, or GEH-6330 for the
FECN module »
4-2
Table 4- 7. DC2000 Frame Size Specifications
Ac Input Maximum Dc Maximum Dc

Frame Size Voltage Output Voltage Output Current
(V acl (v de} (A) 1
C 230 240 2602

460 500 2602
575 600 2602
C Extension (CX) 230 240 4902
460 500 4,902
575 600 3922
G 230 240 1273
460 500 1273
575 600 99
J4 700 800 25112
1000 1 100 20782
1300 1400 18712
M 230 240 14552

460 500 14552
700 800 14552
1000 1100 15002
Notes:
1. Output current ratings at 60 Hz ac input, include 150% overload for 60 seconds at 40 °C.
2. Derate 10% for 50 Hz ac input.
3. Rated for CSA applications at 125 A.
4. The K frame drive consists of multiple J frame drives, one of which is configured as the
master drive, the rest of which are configured as follower drives.
DC2000 drives that contain 2.11 SDCI board can provide Field power is supplied through fuses on the SDCIG1
only non-reversing, non-plugging (NRX) motor Held board or on the external field exciter module. A thyris-
control. The G1 version of the SDCI board provides tor-diode bridge (on the SDCIG1) or thyristor bridge (in
internal 10 A NRX motor field control, the G2 version the external field exciter module) controls the field cur-
is used to control an external field supply. rent. The SDCI or DCFB decodes Held Ering signals
from the SDCC to direct firing pulses to gate pulse
Drives that contain a DCFB board can provide either .
transformer drivers for the thyristors in the bridge
NRX or non-reversing, plugging (NRP) motor field
control. The DCFB board can control up to two ex- The field power is applied through a shunt. A voltage-
ternal field supplies. controlled oscillator (VCO) circuit on the SDCI or
DCFB board converts the voltage across the shunt into a
For 10 A internal motor Held control, the SDCIG1 frequency signal representing field current. The fre-
board provides 15 A fused field outputs, a .line reactor quency signal is sent to the SDCC card, which controls
to jilter the 'field current, and ac and do snubber cir- the phase angle of the thyristor firing.
cuits. Neon lights are used to indicate blown fuses.
(These components are omitted on the SDCIG2 board The SCR power conversion bridge receives 3-phase
used with external field supplies.) A field power module power. G, C, and C Extension (CX) frame drives in-
is mounted on the main controller heatsink. clude fuses FU1, FU2, and FU3 on the incoming ac
power lines. J, K, L, and M frame drives include fuses
The external field exciter modules include incoming FU1 through FUl2 on the de leg lines. The SCR bridge
line fuses, metal-oxide varistor (MQV) voltage suppres- is made up of SCR modules, sized for the drive's cur-
sors, ac and de line jilters, a thyristor bridge, and a . rent rating. The hardware drawings and elementary
DS200FSAA Field Supply Gate Amplifier Board diagrams included in the appendices show the SCR
(FSAA). The FEAN module also includes a cooling fan. bridges for each frame size .
4-3
GEH-6005 DC2000 Digital Acliustable Speed Drive
A regenerative drive includes two current transform- 4-5.3. Ac Reactors

ers, designated CT1 and CT3, on the L1 and L3 lines to
the SCR bridge. (A regenerative drive has the ability to Ac reactors are included on the ac power lines between
return power from the motor armature to the ac line, the ac line fuses and the SCR bridge. The reactors limit
creating a braldng effect on the motor.) The CTs pro- the rate of change in line current when the bridge cur-
vide current feedback signals that are scaled by the rent commutates from one leg to another.
SDCI or DC1=B board and sent to the SDCC card to
indicate commutation failure. The SDCC uses the cur- 4-5.4. Main Contactor (MA or MD)
rent feedback to control the ac instantaneous overcur-
rent (IOC) protection feature. The SDCC compares the The MA contactor provides a controllable disconnect
current feedback to the limit programmed into between the ac power line and the SCR power conver-
EEPROM location EE.580 (ACIOCT). The default set- sion bridge. The MD contactor provides a disconnect in
ting for the ac IOC trip level is 400%. the de armamre circuit.
The SDCC card provides SCR bridge firing signals to The contactor picks up when the running mode is se-
the power supply board (DCFB or SDCI). The power lected (see the description of the Programmer in Chap-
supply board decodes the signals to prow'de tiring ter 8) and no fault exists in the drive. The contactor
pulses to the gate pulse transformers on the Power Con- drops out under any of the following conditions:
nect Board (PCN, PCR) or Power Connect Card
(PCCA) ¢ 1. Coast Stop is initiated.
Dc power is applied to the motor armature from the P1 2. STOP is selected and the motor slows to near zero
bus through a shunt. The power returns to the P2 bus . speed on regenerative drives.
Regenerative G, C, and CX frame drives include a do
line fuse FU4 on the return line. The output voltage 3. A fault condition occurs.
feedback signal is derived across the armature output.
The output current feedback signal is derived across
the shunt. 4-5.5. Control Power Transformer (CPT)
The CPT is energized either from the ac input lines, or

4-5. POWER CONVERTER OPERATION from an external control power source. The secondary
winding provides two isolated voltages:
The following sections describe the power convener
circuitry associated with the DC2000 drive. These cir- • 115 V ac to operate the enclosure cooling fans and
c1u`ts are shown in the sample elementary diagrams SCR bridge cooling fan (if used)
contained in Appendices E through M.
. 38 V ac center-tapped for the power supply board
to generate the do control voltages necessary for
4-5.1. Ac Line Fuses (FU 1 - FU3) controller operation
In G, C, and CX frame drives. ac line fuses protect the

power SCRs, internal wiring, and output wiring from 4-5.6. Do Line Fuse (FU4)
short circuits. These fuses are not included in J, K, and
M frame drives. This fuse is used in regenerative G, C, and CX frame
drives only. It is located on the de output line to the
Instantaneous and timed overcurrent functions in the motor armature, and protects the SCR bridge against
control software also protect against excess current. overcurrent sourced at the motor.
4-5.2. Dc Leg Line Fuses (FU1 - FU12) 4-5.7. Shunt
In J, K, and M frame drives, do leg line fuses protect The shunt provides the armature current feedback signal
the power SCRs, internal wiring, and output wiring to the power supply board. The shunt generates a nomi-
from short circuits. These fuses are not included in G, nal 100 mV output signal at the current rating stamped
\
C, and CX frame drives. on it.
4-4
: _ _ -
4-5.8. Current Transformer (CT) Assembly NOTE
I Regenerative drives include CT assemblies that provide Elementary diagrams may change with
ac line current feedback signals used for circulating ac product upgrades and revisions. The infor-
current fault detection. mation presented in this manual is current as
of the issue date.
4-6. DRIVE CONNECTION DRAWINGS
Appendices E through M contain sample elementary

diagrams for the available frame sizes of the DC2000
drive, with DCF-B and SDCI boards.
4-5
Notes:
4-6
CHAPTER 5
PRINTED WIRING BOARD DESCRIPTIONS
5-1 . INTRODUCTION board, in this case, the Drive Terminal Board. The c
dgit can be A or B, depending on the configuration, the
This chapter describes the printed wiring boards used 'm r digit is an alphabetic character that indicates the revi-
the DC2000 Digital Adjustable Speed Drive and their sion level of the printed wiring board. The G# identities
operation. Chapter 6 defines the I/O connections for a group, which is a variation of a particular board.
these boards. Chapter 7 lists and defines the fuses and
testpoints contained on some of these boards . A11 digits are important when ordering or replacing any
board. Chapter 13 contains spare and renewal parts in-
formation.
5-2. BOARD IDENTIFICATION
NOTE
A printed wiring board is designated by an alphanu-
meric part (catalog) number. Two parts numbering The terms card and board both apply to
series are commonly used for printed wiring boards at printed wiring boards. In this manual, board
GE Drive Systems & Turbine Controls. is the preferred term. However, card is used
in some drawings and when it is part of a
Most of the boards contained in the DC2000 drive are board's pre-established nomenclature - for
designated with part numbers beginning with the digits example, the Drive Control Card (SDCC).
DS200 or DS215. For example, the Drive Control Card
is identified by part number DS215SDCCG#AAA. The
digits in the part number provide information about the 5-3. ADJUSTABLE HARDWARE
board, as shown in Figure 5-1.
Some printed wiring boards used in the DC2000 drive
Other boards contained in the DC2000 drive are desig- include adjustable potentiometers (pots), switches, and
nated with part numbers beginning with the digits 53IX. jumpers for setting and fine-tuning functions. The board
For example, the Drive Terminal Board is identified by layout drawings in this chapter show their locations on
part number 531X305NTBcrG#. The 53IX305N18 por- the boards. The board adjustable hardware tables list
tion is the base number that identifies the printed wiring and describe the adjustments.
DS 215 SDCC G# A A A
M a l l _
A board revision (artwork change) that is backward compatible.
A board revision (functional change) that is backward compatible.
A board revision (functional change) that is not backward compatible.

Essentially a new catalog number.
A group, or variation, of a particular board.
Board functional acronym .

Indicates that the board is a higher level assembly that can contain
firmware and/or other components added to the base level board (200
indicates that the board is a base level board and can contain firm ware).
Identifies GE Drive Systems & Turbine Controls.
Figure 5- 1. Sample Board Part Number, DS Series

5-1
I
- I It
-`
WARNING ii
u
.r
l
.A
_,r
'I
|-
l
.
4.. |.
f;
1.
1-1 . 1
;_
-"in
.I-
| . 1
.f - l
Potentially hazardous voltages are present in .e".» _ 11

-r
L
a
the drive circuits. Ensure that power is off

before touching a board or any connected
Figure 5-2. Pot Set at Default Position
circuits.
cAuTion 5-3.1 .3. JUMPERS. The drive uses Berg-type

(manually moveable) jumpers for both manufacturing
test and customer options. Typically these jumpers are
Some boards contain static-sensitive compo- designated with a JP nomenclature.
nents. To prevent component damage caused
by static electricity, use static-sensitive The drive uses hard-wired jumpers to configure boards
handing techniques with all boards. for component substitutions or upgrades. Typically
these jumpers are designated with a WJ nomenclature .
NOTE
The jumpers are deaned 'm the board adjustable hard-
Board adjustable hardware may change with ware tables contained in this chapter .
product upgrades and revisions. The infor-
mation presented in this manual is current as NOTE
of the issue date. The ST2000 Toolkit or
Drive Configurator, if purchased with the Before moving any jumper, compare its ac-
drive, contains information current as of the tual position with the as shipped position
date the equipment was manufactured. shown on the hardware drawings located in
the drive door pocket.
.
5-3. 1 Initial Hardware Settings
5-3.2. Adjusting Replacement Boards
The factory sets most adjustable hardware when manu-
facturing and testing the drive. For adjustments that are When replacing a board, set the pots, switches, and
not factory-set, refer to the tables in this chapter and the jumpers on the new board to match the settings on the
drive's Custom Software . board being replaced. Chapter 11 provides instructions
for replacing a board.
5-3.1.1. POTENTIOMETERS. Potentiometers (pots)
may be adjusted during startup to optimize drive per-
formance. The initial (default) setting is the straight-up 5-4. PRINTED WIRING BOARDS
position (see Figure 5-2). These pots are defined in the
board adjustable hardware tables contained in this This section describes the printed wiring boards that
chapter. may be used in the DC2000 drive. These include:
NOTE . ARCN'ET'*° Connect Board (ACNA) - optional
Use only high-impedance digital voltmeters . Contactor Driver Board (CDBA) - optional, J, K,
and M frame drives only
or the optional onboard DVM to make indi-
cated adjustments.
. Contactor Pilot Card (CPCA) - optional, J, K, and
M frame drives only
5-3.1 .2. SWITCHES. Some boards contain DIP
switches for configuring I/O options. Switch settings are
defined in the board adjustable hardware tables con-
tained in this chapter.
. Power Supply Board (DCFB) - the drive contains
either a DCFB or SDCI board
. LAN Current Source Board (LCS) - optional
5-2
• LAN I/O Terminal Board (LTB) - optional Figure 5~3 shows the layout of the ACNA board. Sec-
don 6-4 defines I/O points for the board.
• Multi-bridge Hub Communications Board (MBHA)
- optional
• Drive Terminal Board (NTB/3TB) - the drive C011- J
tains either an NTB/3TB or STBA board. I
I
. Power Connect Board (PCCA, PCN, or PCR)
__ m
-
I
I
I
_
_
I
JI
.J N
o. o <.
l
D D
o
Relay Terminal Board (RTBA) - optional
O
• 5 §
o
no
as
<
<
o z
m
z
O
©
o
©
n¢ r.>
< z
o <
• Drive Control Card (SDCC) RX2 o RX1
• Do Power Supply and Instrumentation Board

DS200
AGNA
G1A
IN 3 2
o
o
o o
o
o
o
o
o
o
o I
.
(SDCI) - the drive contains either an SDCI or

DC1=B board Figure 5-3. ACNA Board Layout
SCR High Voltage Interface Board (SHVI) -Jand

K frame drives only
5-4.2. Contactor Driver Board (DSZOOCDBA)
. SCR High Voltage M Frame Interface Board
(SHVM) - M frame drives only The DS200CDBA Contactor Driver Board (CDBA)
provides power to open and close a contactor under
control of the DS200DCFB Power Supply Board
LAN Communications Card (SLCC) - optional
(DCFB) or DS200SDCI Do Power Supply and Instru-
mentation Board (SDCI). Contactors used with the
• Signal Processor Card (SPC) - optional CDBA have coil voltages of 30 to 40 V do. To close a
contactor, the CDBA applies 105 V de for 250 msec to
• Multi-bridge Signal Processing Card (SPCB) - K force the contactor closed. The CDBA then regulates
frame drives only the contactor drive current at the level set using pot
. Basic Drive Terminal Board (STBA) - the drive

contains either an STBA or NTB/3TB board
RV1 to keep the contactor closed. Directions for setting
pot RV1 are contained in section 5-4.2.1.
The hardware drawings included in Appendices B CAUTION

through D show the locations of these boards in the
DC2000 drive. The sample elementary diagrams in-
cluded in Appendices E through M include board inter- When replacing the CDBA board, pot RV1
.
connection information for the drive on the new (replacement) board must be set
to the same position as on the board being
replaced. For DS304-type contactors, failure
5-4.1. ARCNET Connect Board (DSZOOACNA) to adjust the pot as described in the following
section may cause the contactor coil to fail.
The DSZOOACNA ARCNET Connect Board (ACNA)
provides the connection for an ARCNET data link be- Section 6-5 defines I/O points for the CDBA board.
tween the drive and other devices. The ACNA connects Section 7-2 defines the CDBA fuse FU1, and section 7-
to the DS215SLCC LAN Communications Card 6.1 defines CDBA onboard testpoints.
(SLCC) via connector ARCPL, and provides two BNC
connections (channels A and B) for communications
with other equipment.
5-3
5-4.2.1. CONFIGURABLE HARDWARE. The CDBA 5-4.3. Contactor Pilot Card (DSZOOCPCA)
board includes two Berg-type jumpers, designated .TP1
and J?2, and one adjustable pot, designated RV1. The The DSZOOCPCA Contactor Pilot Card (CPCA) is
jumpers are used for manufacturing test or customer similar to the CDBA board in that it also provides
options. Pot RV1 is used to set the contactor dive cur- power to control the opening and closing of a contactor.
rent. Figure 5-4 shows the layout of the CDBA board, The contactors used with the CPCA have a coil voltage
including the locations of the jumpers and pot. Table of 115 v do. The CPCA recdies incoming 115 V ac
5-1 lists and defines these items. into 105 V de to drive the contactor coil. Unlike the
CDBA board, the CPCA card does not force the contac-
Pot RV1 is typically ser to regulate the contactor drive tor closed, rather, it applies full voltage to close the
current at 1.5 A. For DS304-type contactors, the con- contactor and keep it closed.
tactor drive current must be set to 0.75 A. Refer to Ta-
bles 5-1 and 5-2 for instructions on setting the contactor The CPCA card contains no adjustable hardware. Fig-
drive current using RV1. ure 5-5 shows the layout of the CPCA, including the
locations of onboard testpoints. Section 6-6 defines I/O
points for the CPCA card. Section 7-6.3 defines CPCA
testpoints.
DS200CDBAG1B
DS200CPCAG1A
'D
Ln
pa
'U
LN
RVS 1 s IZ
0S
ACOMA
REFA
z
>
z re
'u
J:
(1
19
2:
C l
'U
r'
F 15A
3
LED1
FE
U l
z
I:
1
P z
I I
MPL
0 r
1 2 3 4- 5 6 7 8 9
I
10 11 12 l
I
JP1
-*
-4
nu 1 TBA ITBE 1 TBC 1TED
FU1 1
l I I
MPL
m
>:
ID
N4
'-v I ,I 1 2 5 4 5 6 7 B 9 1D1112
JP2
1
TBA ITBB ITBC 1TBD 1 2 1 2 4 5 6 7 B g 11 12
1 1
RMPL MACPL
iTs Figure 5-5. CPCA Card Layout
Figure 5-4. CDBA Board Layout
5-4
Table 5- 1. CDBA Board Acyustab/e Hardware
( Revision Name Description
All JP1 Factory test jumper

JP1 = 2-3 allows the current output scaling to be lowered for factory card test purposes. If not in factory
card test; JP1 must be 1-2.
1.2 Normal operation
2.3 Special setting for factory card test
BAA-Pres JP2 Allow coordinated operation of multiple CDBA boards
For coordinated operation (2.3 position). apply parallel voltage to 1 TB~9 and -10. This circuit was designed
for 12 circuits using 340 ohms in series with the 24 volt supply. All 12 CDBA inputs can be connected
together so all contactors will pick up and drop out together.
1.2 Normal non-coordinated CDBA operation
2.3 Coordinated operation
All RV1 Coil current reference pot
Pot RV1 controls the amount of current which will drive the contactor coil, as measured using testpoints
REFA and ACOM. This pot is set at the factory and varies depending on the particular contactor to be
driven. Table 5-2 presents calibration information for the CDBA. Consult the factory for the proper setting
if it is suspected to be set incorrectly.
Table 5-2. CDBA Calibration information
REFA to ACOM Coil Position of Pot RV1

Voltage (V de) Current (A)
o.oo 0.60 Full couruterclockwise

0.12 0.75 ____
0.70 1 .50 Approximately 11 o' clock
l 1 .so 2.50 Full clockwise
NOTE
All CDBA testpoints are referenced at CDBA common (ACOM), which is different from drive common.
Therefore, all test measurements must be performed using isolated test equipment that is suitable for
measuring floating potentials.
5-5
5-4.4. Power Supply Board (DSZOODCFB) 5-4.4.2. VOLTAGE AND CURRENT FEEDBACK VCO
CIRCUITS. The DCFB includes voltage-controlled oscil-
The DSZOODCFB Power Supply Board (DCFB) re- lator (VCO) circuits that convert input voltages to fre-
ceives 38 and 115 V ac input power from the control quency signals. Each VCO has a nominal output fre-
power transformer (CPT), and provides control-level quency of 250 kHz. The output frequency varies from 0
power to the drive and 115 V ac to the enclosure fans. to 500 kHz, depending upon the input voltage. VCO
The DCFB board includes the following circuits: outputs are sent to the SDCC through connector lPL to
. Control-level power supplies (+5 , i15, and 1:24

V do)
provide feedback of the following:
. SCR bridge ac input voltage

. Motor field power circuits (except the SCR mod-
ule)
Output bridge voltage
• Motor voltage
Driver circuits for the motor field SCR gate pulse
Millivolt signals from field shunts
generators
Circuits to monitor numerous ac line and do motor

. Millivolt signals from armature shunts
signals, including:
The output bridge VCO circuit provides feedback to the
Armature cuIrent(s) and voltage(s) SDCC through connector IPL, pin 13 (IPL-13). DIP
Motor field currents switch SW4 is used to scale the voltage applied to the
circuit. A frequency-to-voltage reconstruction circuit
Ac line current provides a diagnostic signal for testpoint TP37 on the
Ac line voltage magnitude and phase sequence SDCC through IPL-37 . The diagnostic bridge voltage
signal can be viewed using an ac-coupled oscilloscope .
Section 6-7 defines I/O points for the DCFB board.
Section 7-3 defines DCFB onboard fuses and section 7- The second VCO provides feedback of the motor volt-
6.3 defines DCFB testpoints. age to the SDCC through IPL-39. DIP switch SW5 is
used to scale the voltage applied to the circuit.
5-4.4.1 . POWER SUPPLIES. The DCFB board receives
38 V ac (;4-.10%) from the CPT. This voltage is fuu- Two other VCO circuits provide feedback of the input
wave rectified and Filtered to produce the unregulated voltage from a shunt. The VCO output frequency sig-
+_24 V de outputs. The +24 V do output is rated at 3 nals are sent to the SDCC through connector 1PL.
A, the -24 V de output is rated at 1 A.
The DCFB also includes two motor armature VCO cir-
Regulators on the DCFB derive i15 V de from the cuits. The frequency output signals from these VCOs
i2A V do supplies. The i15 V do outputs are each are sent to the SDCC through IPL-8 and IPL-10. These
rated at 0.8 A, of which 0.25 A is available for external VCOs are at the potential of the armature bus, and are
loading . fed by an isolator.
The DCFB also generates a +5 V do, 4 A output from 5-4.4.3. MOTOR VOLTAGE ATTENUATION CIRCUIT.
the +24 V do supply. The /PSEN signal on 2PL goes to The DCFB includes a motor voltage attenuation circuit
a TTL low stare when the +5 V do supply is in regula- that provides an analog representation of the motor
tion, the signal goes high if the supply goes out of voltage. This signal is sent to the SDCC through 1PL-6 _
regulation. When high, /PSEN generates a microproc- The attenuation circuit is biased at 2.5 v, and can vary
essor reset on the Drive Control Card (SDCC) . from 0 to 5 V depending on the motor voltage. DIP
switch SW6 is used to scale the motor voltage feedback.
The DCFB provides isolated +5 and i15 V de supplies
to power the armature current feedback circuits. 5-4.4.4. AC LINE MAGNITUDE AND ZERO
CROSSING. The DCFB contains amplifier circuits that
The power supply outputs are protected against short process the ac line-to-line voltages. The voltage signals
circuits by fuses FU2 and FU3 (7 A, 2AG). Light- are sent to the SDCC through IPL-11, 1PL-12, and
emitting diodes (LEDs) CR51 and CR55 provide blown IPL-29. These signals are used to detect power bridge
fuse indications for these fuses. The 115 V ac output is
protected by fuse FU1 (1/2 A, 2AG). Neon light LT1
provides blown fuse indication for FU1.
5-6
L
SCR failures and may also be used to derive the syn- 5-4.4.7. FIELDIARMATURE SCR FIRING CONTROL
chronization signal for the Bring of the SCRs. DIP CIRCUITS. The DCFB contains a gate array circuit that
switches SW1, SW2, and SW3 are used to scale the ac controls the firing of the SCRs in the bridge based upon
line voltage feedback. control signals received from the SDCC through con-
nector 1PL. The gate array is programmed at powerup
5-4.4.5. AC LINE CURRENT TRANSFORMER by a sepal PROM.
INTERFACE. In some applications, the d.dve's ac input
lines L1 and L3 include ac line current transformers The 5 V outputs of the gate array are converted by gate
(ACCTs). Switch SW7 on the DCFB is used to select pulse amplifier circuits into the power level required to
the burden resistance as a function of rated 1 per unit feed the forward and reverse gate pulse transformers on
(pu) de output current. (The rated 1 pu de output cur- the PCCA card. These signals are sent to the PCCA
rent is defined as 0.5 V across the DCFB's ACCT bur- through SPL. To prevent spurious tiring signals, the
den resistors.) The DCFB sends the ACCT signals to firing power is removed from the gating circuits until
the SDCC through 1PL. The SDCC uses the ACCT the gate array is programmed and the 5 V power is be-
signals to check for commutation failure and ac instan- ing regulated.
taneous overcurrent HOC). Testpoint ACCT on the
DCFB may be used to view the ACCT signals. 5-4.4.8. CONFIGURABLE HARDWARE. The DCFB
board includes Berg-type jumpers and DIP switches,
5-4.4.6. CONTACTOR DRIVE CIRCUITS. The DCFB used for customer options. Figure 5-6 shows the layout
includes relay K2, which serves as a pilot relay to the of the DCFB board, including the locations of the
MD contactor. The SDCC drives the coil of this relay jumpers and switches. Table 5-3 lists and defines these
through 1PL-34, IPL-35, and IPL-36. Connector items.
MACPL provides 24 V de FET output to the MD COI1-
tacror driver.
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1
Figure 5-6. DCFB Board Layout

5_7
Table 5-3. DCF8 Board Acvirstable Hardware
Revision Name Description
All JP1 Select source of ac line sync signal passed to the SDCC
Proper synchronization to the ac line is critical to the operation of the drive, and 1.2 is the only valid
setting of this jumper for DC2000s.
1.2 Generated by DCFB using line voltage 2-3 lDC2000 applications)
2.3 Generated by the TCCB card (EX2000 applications)
All JP2 Decrease ac contactor drop-out time
Normally, this circuit delays opening of the ac contactor to ensure all load current has been extinguished.
Removal of this jumper during can cause the Control-on circuit to drop out the MA relay before the current
has been brought to zero.
1 .2 Normal operation. gives about 100 ms delay
O Minimum delay, (and manufacturing test)
All JP3 Configuration of armature shunt #1 input circuit
Jumpers JP3 through JP7 must be set together for proper operation of the voltage controlled oscillator
(VCO) which converts the shunt current to a frequency signal which is then read by the SDCC.
Application JP3, JF4 JP5-JP7
G, C or D frame DC2000 1.2 1.2
M, J or K frame DCZ000/EX2000 1.2 2.3
GFZOOO or ME2000 with svlA card 2.3 1.2
M frame CBZOOO 1 .2 1.2
J frame CB2000 with SHVI card 1 .2 2.3
When JP3 & 4 are in position 1.2, no attenuation affects the IA1 PL input signal which may come from
either a TOO mV (1 pu) shunt or a an external VCO. The local VCO will produce O Hz at -5 pu and 500
kHz at + 5 pu from a shunt signal. A frequency input signal from an external VCO must be bypassed
around the local VCO (See JP5 and JP6). Putting JP3 and JP4 in position 2.3 rescales the input to receive
an analog isolator (SVIA) signal such that the local VCO produces a frequency output of 12 kHz with -5.0
V input and 488 kHz with +5.0 V input (IV = 1 pu).
Jumpers JP5-7 select and enable the local (DCFB) VCO when in position 1.2. When in position 2.3 the
local VCO is disabled and bypassed to allow use of an up stream VCO circuit.
1.2 Direct input of shunt or external VCO signal
2.3 Input rescaled for analog isolator signal
All JP4 Configuration of armature shunt #1 input circuit (see JP3)

1 .2 Direct input of shunt or external VCO signal
All JP5 Configuration of armature shunt #1 VCO circuit (see JP3)
1.2 Local VCO circuit selected
2.3 Local VCO circuit bypassed
1 .2 Local VCO circuit enabled
2.3 Local VCO circuit disabled
All JPB Configuration of armature shunt # 2 input circuit
Jumpers JP8 through JP12 must be set together for proper operation of the voltage controlled oscillator
(VCO) which converts the shunt current to a frequency signal which is then read by the SDCC.
Application JP8, JP9 JP10-JP72
, or frame C2000 1.2 1 .2
M, J of K frame DC2000/EX2000 1 .2 2.3
GFZOOO or MEZOOO with SVIA card 2.3 1 .2
M frame CBZOOO 1.2 1 .2
J frame CBZOOO with SHVI card 1.2 2.3
When JP8 & 9 are in position 1.2, no attenuation affects the IA2PL input signal which may come from
either a 100 mV (1 pu) shunt or a an external VCO. The local VCO will produce o Hz at -5 pu and 500
kHz at + 5 pu from a shunt signal. A frequency input signal from an external VCO must be bypassed
around the local VCO (See JP1O and JP1 1). Putting JP8 and JP9 in position 2.3 rescales the input to re-
ceive an analog isolator (SVIA) signal such that the local VCO produces a frequency output of 1 2 kHz with
-5.0 V input and 488 kHz with +5.0 V input (IV = 1 pu).
Jumpers JP10-12 select and enable the local (DCFB) VCO when in position 1.2. When in position 2.3 the
local VCO is disabled and bypassed to allow use of an up stream VCO circuit.
/*
2.3 input rescaled for analog isolator signal
5_8
Table 5-3. DCF8 Board Acyustable Hardware - Continued

All JP9 Configuration of armature shunt #2 input circuit (see JP8)

All JP1O Configuration of armature shunt #2 VCO circuit (see JP8)
1.2 Local VCO circuit enabled
2.3 Local VCO circuit disabled
All SW1 Select the ac line voltage applied to the line voltage 1-2 circuit
SW1 and SW3 scale the V1 -2 and V1-3 line voltage feedbacks into VCOs used to provide the SDCC with
a frequency signal proportional to instantaneous line voltages. These are used for phase loss and sequence
detection, and for line sync via the bi-phase PLL. SW2 scales the V2-3 voltage applied to the circuit used
to generate the ac line synchronization and frequency measurement signal via the zero-crossing detector.
Scaling of SW1 -SW3 is in conjunction with the SHVI/M card voltage attenuators, if used.
The maximum nominal V ac is the maximum ac input voltage which may be 15% high without saturating
the instrumentation circuitry.
For DCZOOO/EXZOOO applications, switches SW1 , 2, 3, 4, 5, and 6 must all be set to the same position.
Above 617 V ac, SHVI/M attenuators must be used (refer to SHVI JP9 through JP17). For
GFZ000/ME2000 applications, switches SW1 through SW4 must be set to the same position; switches
SW5 and SW6 may be set to different positions than SW1-SW4, depending upon the application.
For the DCZOOO, the settings of these switches affect the scaling of VAR.1 O8 (ACLINMAG), which affects
the phase loss protective fault (see EE.582). For each of the maximum nominal runs line-line voltage
selections, if the input is at the maximum nominal, VAR.108 will be approximately 25700 counts. For the
EXZOOO, these switches have a similar effect on the phase loss function provided by EE.576, PUATHR. For
both drive types, a scale factor, EE.VLL_SF allows these voltages to be scaled to a 1 pu = 20000 basis
prior to being applied to the phase loss function.
O (All off) 308 max nominal V ac (762 V ac using SHVI attenuators)
8 (4 on) 364 max nominal v ac (901 V ac using SHVI attenuators)
1 (1 on) 488 max nominal V ac (1214 V ac using SHVI attenuators)
9 (1 & 4 on) 545 max nominal V ae (1353 V ac using SHVI attenuators)
All SW2 Select the ac line voltage applied to the line sync circuit (see SW1)
O (All off) 308 max nominal V ac (762 V ac using SHVI attenuators)
8 (4 on) 364 max nominal V ac (901 V ac using SHVl attenuators)
9 (1 & 4 on) 545 max nominal v ac (1353 v ac using SHVI attenuators)
All SW3 Select the ac line voltage applied to the line voltage 1-3 circuit (see SW1 )
O All off) 308 max nominal V ac (762 V ac using SHVI attenuators)
8 4 on) 364 max nominal V ac (901 V ac using SHVl attenuators)
1 1 on) 488 max nominal V ac (1214 V ac using SHVI attenuators)
9 1 & 4 on) 545 max nominal v ac (1 353 v ac using SHVI attenuators)
2 2 on) 617 max nominal v ac (1535 v ac using SHVI attenuators)
All SW4 Select the voltage applied to the do bridge voltage feedback VCO circuit
SW4 scales the voltage applied to the circuit used to generate the frequency representation of do bridge
voltage (P1 to P2) feedback passed to the SDCC. SW5 scales the voltage applied to the circuit used to
generate the frequency representation of do motor voltage feedback passed to the SDCC. SW6 scales the
voltage applied to the circuit used to generate the analog representation of do motor voltage feedback
passed to the SDCC. Scaling of SW4 through SW6 is in conjunction with the SHVI/M card voltage
attenuators, if used.
The voltages listed in the selection table are maximum nominal V ac and nominal V do. The maximum
nominal v ac is the maximum ac input voltage which may be 15% high without saturating the VCO
channel instrumentation circuitry. For the do VCO channels, nominal V do is the do voltage which results in
20,000 counts raw voltage feedback (VFBRAW) before scaling by EE.1503 (VFBSFn).
For DC2000/EX2000 applications, switches SW1 , 2. 3, 4, and 5 should be set to the same position.
Above 617 v ac, SHVI/M attenuators must be used (refer to SHVI JP9 through JP17). For
GF2000/MEZOOO applications switches SW1 through SW4 should be set to the same position; switches
SW5 and SW6 may be set to different positions than SW1 -SW4, depending upon the application.
5-9
Table 5-3. DCF8 Beard Aayustab/e Hardware - Continued
o (All off) 30B V ac, 341 V do (762 v ac, 843 V do using SHVIIM attenuators)
8 (4 on) 364 V ac, 403 V do (901 V ac, 996 V do using SHVI/M attenuators)
S (1 & 4 on) 545 V ac, 602 V de (1353 V ac, 1496 V do using SHVl/M attenuators)
All SW5 Select the voltage applied to the do motor voltage feedback VCO circuit
O (All off) 308 V ac, 341 V do (782 V ac, 843 V do using SHVUM attenuators)
8 (4 on) 364 V ac, 403 V do (901 V ac, 996 V de using SHVI/M attenuators)
1 (1 on) 488 V ac, 541 V de (1214 V ac, 1342 V do using SHVI/M attenuators)
9 (1 & 4 on) 545 V ac, 602 V do (1353 V ac, 1496 V do using SHVI/'M attenuators
2 ( 2 on) 617 V ac, 683 V do (1 535 V ac, 1698 V do using SHVI/M attenuators)
All SW6 Select the voltage applied to the analog de motor voltage feedback circuit
SW6 is an analog instrumentation channel. The channel feeds a an A/D converter on the SDCC card. A 2.5
V bias added on the DCFB card allows the unipolar A/D converter to "read" bipolar instrumentation signals.
A change of :t 1 pu for a de voltage results in a 1 1 .7 V swing about the +2.5 V bias. A i t pu change
for an ac voltage results in a i 1 .535 V swing about the +2.5 v bias.
o (All off) 154 V ac, 171 V do (380 V ac, 422 V do using SHVI/M attenuators)
2 ( 2 on) 308 v ac, 341 V do (766 v ac, 849 V do using SHVIIM attenuators)
4 (3 on) 385 V ac, 427 V de (959 V ac, 1062 V do using SHVIIM attenuators)
11 (1,2,4 on) 426 V ac, 472 V de (1061 V ac, 1175 V do using SHVI/M attenuators)
5 (1 ,3 on) 475 V ac, 526 V do (1 184 V ac, 1312 V do using SHVI/M attenuators)
6 (2,3 on) 540 v ac, 598 V do (1345 V ac, 1489 V do using SHVI/M attenuators)
7 (1,2,3 on) 630 V ac, 697 V do (1570 V ac, 1739 V do using SHVI/M attenuators)
All SW7 Select ac line CT burdens as a function of rated drive hp and voltage
These switch settings scale the ac line current transformers as a function of do amps. Correct scaling is
essential for proper operation of the ac IOC protective feature. These CTs are mounted on lines 1 and 3 of
the power converter, and are wired through plug 1CPL to a common burden resistor. Select the proper
setting as a function of drive current and CT turns ratio. The CT ratio can be determined from its part
number and the following table.
Part Number Turns Ratio
104X157AB O23 1000:1
104X157AB O25 2000:1
104x15'/AB O20 400021
104x157AB 013 5000:1
104X15'/AB 024 5000:1
104x157AB O26 800011
When set properly, the current magnitude read in VAR.1019 (CTCFB) should be scaled within 1 5 % of the
current magnitude in VAR.1 O4 (CFB). Above 144 mA ACCT secondary current, the CTs are routed through
a set of 10:1 step down CTs on the SHVI/SHVM card, using JP1 through JP8 on the SHVI/SHVM card.
The enumerations listed are in terms of the mA input to the DCFB card (ACCT secondary milliamps
attenuated by 10:1 SHVI/SHVM attenuation if selected). At present, the SHVI/SHVM cards are used on M,
J, K, and L frames only, and then 10:1 CTs are used only if the ACCT secondary current is > 144 mA.
The CT secondary current (in milliamps) is approximated by:
7 pu rated current x 1000
/ct, mA
Combined CT turns ratio
o (All off) o.o s Ict, mA < 6.0
1 (1 on) 6.0 s let, mA < 13.4
2 (2 on) 13.4 S Ict, mA < 21.1
3 (1 ,2 on) 21.1 S let, mA < 28.4
4 ( 3 on) 28.4 S let, mA < 39.3
5 (1 ,3 on) 39.3 s jct, mA < 46.7
6 1z,3 on) 46.7 s Ict, mA < 54.4
7 (1,2,3 on) 54.4 S let, mA < 61.8
8 (4 on) 61.8 S let, mA < 88.7
9 (1,4 on) 88.7 S let, mA < 96.0
10 (2.4 on) 96.0 S Ict, mA < 103.0
11 (1 ,2,4 on) 103.0 <_ let, mA < 111.0
12 (3,4 on) 1 t1.o Slot, mA < 122.0
13 (1 ,3,4 on) 122.0 _< Ict, mA < 129.0
14 (2,3,4 on) 129.0 S let, mA < 137.0
15 (AI1 on) 137.0 S Ict, mA < 144.0
5-10
DC2000 Digita] Adjustable Speed Drive GEH-6005
5-4_5_ LAN Current Source Board (531X207LCS)
The 531X207LCS LAN Current Source Board (LCS)

provides a jumper-selectable 5 or 15 V do power supply
and a voltage-limited 0.3 A current source. For LAN 1
I
z
installations, the LCS power supply should be config-
g |_
ured for 15 V de output. |-
>
z
o PI
c
z
Berg-type jumper JP1 is used to select the output volt- z
m
age of the de power supply: z
-"l JP1 I 121
.
m
o 1 2 3
:
x
Connect pins 1 and 2 to enable 5 V do operation n
m
. Connect pins 2 and 3 to enable 15 V de operation

UP
UI
-n
X
N
o
>O
up
Pot P1 is used to adjust the output voltage of the 5/15 V >
'q
c>
do power, as follows: 1 2 3 4 5 s 7 8 9 10 1 1 12
FU 1
1' '\
I .25 AMP
1 I £°1 I I TB1
L
1. Position jumper JP1 for the desired de output volt- | _I
age (5 or 15 V de).
Apply 115 V ac input power to the LCS board at Figure 5-7. LCS Board Layout
TB1-1 and TBI-3 •
3. Using a voltmeter, measure the output voltage

across TB1~8 (V +) and TB1-7 (COM) for the
power supply output, and TB1-11 (-) and TB1-12 The LTB is available in two group numbers: G1 and
(+) for the current source output. G2. The G1 version contains eight 24 V de input plugs,
designated CI1PL through CISPL, which are configur-
4. Adjust pot P1 for nominal output voltage . able control inputs (see Figure 5-8). These inputs con-
nect to 8PL, which connects to terminal board points
Figure 5-7 shows the LCS board layout, including the and to the SDCC.
locations of jumper JP1 and pot P1 . The G2 version omits control inputs CIIPL through
Section 6-8 defines I/O points for the LCS. Section 7-4 CISPL and connector SPL, and can only be used with
defines LCS fuse FU1 . de inputs.
5-4.6. LAN IIO Terminal Board (531X307LTB) CAUTION
The 531X307LTB LAN I/O Terminal Board (LTB) Do not connect the input across an inductive de-
provides an interface between control devices (such as vice, as this can damage the circuit.
drives or exciters) and external devices, such as contac-
tors, indicator lights, pushbuttons, and interlocks. Figure 5-8 shows the layout of the LTB board, includ-
ing the locations of connector points and LEDs C011-
The LTB control outputs consist of seven low-voltage, tained on the board.
low-current, form C relay contact connections. The
LTB also provides pilot contact connections that func- Section 6-9 defines I/O points for the LTB board.
tion to actuate up to seven high-voltage, high-current
relays, such as those on the DS200RTBA Relay Termi- 5-4.6.1. LTB BOARD SPECIFICATIONS. This section
nal Board (RTBA). When the LTB and RTBA are used contains input and output specifications for the LTB
together, contacts from both are available. board.
5-11
Input Specyicadons. The input specifications for the • Relay Outputs - Form C contacts (non-fused):
LTB are as follows:
0.6 A at 125 V ac
Nominal Voltage Range Current Range
24 -. 230 V ac, 60 Hz 4-10mApeak 0.6 A a t 110Vdc
115 230 V ac, 50 Hz 4-10mApeak
24-250V do 4-8mA 2.0 Aat30vdc
NOTE RTBA Pilot Outputs - Form A contacts
For revision 531X307LTBAGG1 boards and . I/O Terminal Wire - Size must be 28 - 14 AWG.
The maximum length of a 26-conductor intercon-
above, devices connected in series with an
input that has a de leakage current greater nection ribbon cable is 20 feet. The maximum
than 1.0 mA or ac peak leakage current lengths of input and output wiring depends upon the
greater than 4.0 mA can cause the input to application s
be continuously in the ON state.

NOTE
For all other revision boards, devices con-
nected in series with an input that has an Do not route I/O ribbon cables with power
ac/dc leakage current greater than 0.05 mA cables. In ac applications, capacitive cou-
can cause the input to be continuously in the pling of connection wires can cause I/O input
ON state. (IN1 through INX) leakage.
Output Specifications. The output specifications for the

LTB board are as follows:
Cl2PL C!1PL
BPL l 10PL 531 X3077TB I/O TERMINAL BOARD
V
l - I ' - \
z 20 sz
Eli
:
1 I L j 19
-;
so z
LE08
LEDS
LED1
N 1 I"
r'1
|-
f'1
|-
m
|"'
m
|-
r"1
2 i D Q o o a
n RPL ~l o> A u N
l
a'U
L/
\ /
f\
O
A
\J
/ '\
p' C) C) C) C)
LED22 LED21 LED20 LE01S LED18 LED17
OPTPL nLEo2s r"\ f'\ A /'\ Ra
-./ \./ \J v v w v
Cl7PL RX7 Rxs Rxs Rx4 lzxs RX2 RX1

1.
- I
L
OT87
I.
ores
L
I OTB5
I
oTa4
I
I DTB3
\
DTB2 DTBI
L
ITBB
L
ITBT
I
ITBS
l
ITB5
l
i ITB4
II
l ITE5
|.'
ITB2
l
ITB1
l
1
Cl8PL
I
F l | 1 L
Figure 5-8. LTB Board Layout
S-12
5-4.7. Multi-bridge Hub Communications Board 5-4.7.5. CONFIGURABLE HARDWARE. The MBHA
(DSZOOMBHA) board contains one Berg-type jumper, designated IP1 .
This jumper is used for manufacturing test purposes
The DSZOOMBHA Multi-bridge Hub Communications only, for normal operation, pins 1 and 2 must be con-
Board (MBHA) is the 6ber-optic communications link nected. Figure 5-9 shows the MBHA board layout, in-
between the member drives of a multi-bridge system. cluding the location of JP1.
The MBHA includes an internal +5 V de power supply,
seven fiber-optic data links consisting of receiver/
transmitter pairs, optically coupled logic inputs for
control of local/broadcast modes, and a programmable
logic device to provide system logic.
Section 6-10 defines I/O points for the MBI-IA board.
rE .J*.
I
!
Lusr-:'nl " : :
. '| .
I
I
I
Section 7-6.4 defines MBHA testpoints . I

2
r£»'El
_ - - H - %
gl I
5-4.7.1. POWER SUPPLY. The MBHA contains a 100 x
kHz + 5 V de switching power supply that provides
canon:
internal power for the MBHA only. The power supply
f ZAK
a
U22
DS200MBHAG1A
is typically powered from an unregulated 24 V de
source, and can operate with an input voltage of be-
, |
cznovt
U21
L.
Irzo
a
TP19
L
tween 15 and 30 V do. Power consumption is approxi-
mately 5 w.
cnkovz
U20
I Zell
s
The power supply includes redundant inputs, wired in a
3 l1_1
'E
| L--
BROADCAST RIGHT
,.L
diode OR configuration so that only the higher of the
\ .J
us
s
?I§§W:
- -1
sun
two input voltages is used by the power supply. If one
In
1ps
of the two inputs is lost, the power supply can continue
U15
c
Lldl
TP2
to operate.
.
-
IPI
I
5-4.7.2. FIBER-OPTIC TRANSMITTER/RECEIVER
runs
\nl§§
PAIRS. The MBHA includes seven 5-Mbaud WEber-optic

data links, located along one edge of the board. The
TP15
5:.1»2
data links are grouped in transmitter (gray) and receiver
neon I:;r=.I is
ms TPI4
(blue) pairs so that they may be accessed via duplex
JP1
|
2
fiber-optic cables. The CONTROL 1 thru oh
CONTROL 5 data links are used to communicate with § 3
S up
the DS200SPCB Multi-bridge Signal Processing Card
TP12
TP22
(SPCB) in each of the follower dr es in a system con- In " Qin

sisting of up to six drives. The BROADCAST LEFT a
E
and BROADCAST RIGHT data links are used to com- g
lldl.
N
o u-
:
municate with the MBHA boards in the master drives of
adjacent systems.
Oldl
'
5-4.7.3. MODE CONTROL. The MBHA also includes
»*'
--;______ Q u:
Sal
three fiber-optic receivers (designated CIMODE,

CZMODE, and C3MODE) used to receive mode control
TP8
1- .fig 3
information (local/broadcast) Hom individual drives. o
E
The CIMODE and C2MODE receivers are 5 Mbaud s o
TP7
u 9.-
"
data links; the C3MODE link includes circm'ts to reduce A :a
its bandwidth to 100 kbaud .

1:31 lsvanvoua
is
zn
S-4.7.4. SYSTEM LOGIC. The MBHA includes a

rps
sn
»/
5C060 programmable logic device that provides system

logic.
Figure 5-9. MBHA 8oard Layout
5-13
5-4.8. Drive Terminal Board (531X305NTB) 5-4.8.5. RELAY OUTPUTS. The NTB/3TB board pro-
vides the following outputs from seven relays with a
The 531X305NTB Drive Terminal Board (NTB/3TB) 120 V, 0.5 A contact rating:
contains customer connection terminals for most signal-
level I/O. This board also includes most of the hardware
customizing jumpers and pots required in the DC2000
. Form C output from Eve relays controlled by the
SDCC
drive, along with some passive interface circuits.
• One form A output and one side of the coil from a
The NTB/3TB board connects to the SDCC via 6PL and sixth relay controlled by the SDCC. This enables
SPL, tO the DCFB OI SDCI via 2PL and 4PL; and [0 the the coil to be controlled by the SDCC or a cus-
customer/system via COMPL and terminal points . tomer 24 V do signal. It also allows the SDCC coil
diver output to be accessed by Me customer for
The NTB/3TB board's 3TB connector contains 90 ter- applications that cannot tolerate the time delay as-
minal board points in two rows or screw-type terminals . sociated with the relay pickup.
The terminals are numbered sequentially, with odd
numbers in the top row and even numbers in the bottom • Two form C contacts and both sides of the coil of a
row. These points provide the following 'interfaces to seventh relay for general purpose use. A hardware
the drive, primarily to the SDCC. jumper is used to select whether this coil is driven
by 24 V do or 120 V ac.
Section 6-11 defines I/O points for the NTB/3TB board.
Section 7-6.5 defines NTB/3TB testpoints . The NTB/3TB also provides form C contacts from the
MA contactor pilot relay on the power supply board.
5-4.8.1. POWER SUPPLIES. The NTB/3TB board pro- These contacts are rated at 120 V ac, 2.0 A.
vides the following power outputs for external use:
5-4.8.6. ANALOG TACH AND REFERENCE COARSE
• Regulated +5 V de and :t15 V do, each with a cur- SCALING. The NTB/3TB board includes DIP switches
rent capacity of 300 mA that allow coarse scaling of analog tech (25 to 380 V)
and analog reference (9 to 29 V) inputs. The SDCC
• Unregulated i24 V do, with a current capacity of card provides Ene scaling of these signals.
500 mA.
. 120 V ac, with a current capacity of 0.4 A

5-4.8.7. LOW-LEVEL ANALOG I/O. The NTB/3TB in-
cludes four pots to scale (5 to 50 V) 10-bit, general-
purpose, medium-resolution inputs to the SDCC. The
Hardware jumpers allow distribution of the encoder NTB/3TB transfers two high-resolution analog VCO
loads among the +5 and _+15 V do supplies to balance inputs to the SDCC, and receives two 12-bit, i10 V
loading . analog outputs (DAC1 and DAC2) and three 8-bit, il0
V analog outputs (MET1, MET2, and MET3) from the
5-4.8.2. ENCODER INTERFACE. The NTB/3TB board SDCC. The outputs drive functions such as other
includes a differential A-quad-B encoder interface, in- drives, analog meters, and diagnostics.
cluding a marker channel, that can be connected to the
drive. This circuit is optically isolated on the SDCC. 5-4.8.8. DIGITAL CONTROL INPUTS. Various control
Jumpers on the NTB/3TB are used to configure the in- inputs pass through the NTB/3TB to the SDCC. These
terface for 5 V or 15 V encoders. inputs include special-puipose digital inputs, such as
RESET and CONTROL ON, and 12 general-purpose
5-4.8.3. RS-232C INTERFACE. Connector COMPL control inputs (up to :l:24 V do). Jumpers are used to
included on the NTB/3TB board provides an RS-232C bias unconnected inputs to +24 or -24 V do, depending
serial link for use with the ST2000 Toolkit (see upon whether positive or negative logic is used.
GEH-5860) or Drive Coniigurator, LynxOS Version
(see GEH-6203). 5-4.8.9. CONFIGURABLE HARDWARE. The NTB/3TB
includes Berg-type jumpers, DIP switches, identified by
5-4.8.4. SPECIAL PURPOSE RS-422 INTERFACE. The an SW nomenclature, and pots, identified by a P no-
NTB/3TB provides line termination resistors for a half- menclature. Figure 5-10 shows the layout of the
duplex, RS-422 compatible, serial interface to the Mo- NTB/3TB, including the locations of the jumpers, DIP
tor Control Processor (MCP) on the SDCC. switches, and pots. Table 5-4 lists and defines these
items.
5-14
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I-7gure 5- 10. NTB/3T8 Board Layout
5-15
Table 5-4. NTB/3TB Board Awustab/e Hardware
All JP1 Termination resistors for the MCP RS-422 interface (see also JP2)
RS-42.2 termination resistors should only be installed at the physical first and last drops (ends of the cable
runs).
1.2 Not installed
2.3 Installed (Must also put JP2 2.3)
All JP2 Termination resistors for the MCP RS-422 interface (See also JP1 l
1.2 Not installed
2.3 Installed (Must also put JP1 2.3)
All JP4 Swap RS232C RxD and TxD data lines, COMPL pins 2 and 3 (see also JP5)
Note many PCs can be bumpered to either the DCE or DTE configuration, and many cables are wired with
pins 2 and 3 interchanged. If communication is not established with JP4 and JP5 in the default position,
the alternate position may be necessary.
1 .2 DCE mode for PC/term interface. Drive transmits on pin 3.
1 .3 DTE mode for modem interface. Drive transmits on pin 2.
All JP5 Swap RS232C RxD and TxD data lines, COMPL pins 2 and 3 (see also JP4)
3.4 DCE mode for PC/term interface. Drive transmits on pin 3.
2.4 DTE mode for modem interface. Drive transmits on pin 2.
All JP6 RS232C RTS (COMPL-4)/CTS (-5) handshake line options (see also JP7)
3.7 DCE mode forced true handshaking
3.4 DCE mode full handshaking
2.4 DTE mode full handshaking
2.6 DTE mode forced true handshaking
All JP7 RS232C RTS (COMPL-4)/CTS (-5) handshake line options (see also JP6)
The default position bypasses handshaking, generally allowing satisfactory serial communication
independent of whether COMPL pins 4 and 5 are connected to a DTE or DCE port, or not connected at all.
1 .5 DCE or DTE forced true handshaking
1 .2 DCE mode full handshaking
1.3 DTE mode full handshaking
AI1 JP8 RS232C DSR (coMpLy) and DTR (COMPL-20) handshake options (see JP9)
The default position bypasses handshaking, generally allowing satisfactory serial communication, inde-
pendent of whether COMPL pins 6 and 20 are connected to a DTE or DCE port, or not connected at all.
1 .2 DSR and DTR both tied to + 1 5 V do (forced true)
1 .3 DSR connected to DTR (loopback)
All JP9 RS232C DSR {CQMPL-6) and DTR (COMPL-20) handshake options (see JP8)
3.4 DSR and DTR both tied to +15 V de (forced true)
2.4 DSR connected to DTR (loopback)
AD-Pres JP1O RF24 polarity for digital control inputs (see also JP1 1 )
Note on early prototypes of this card JP1 O and JP1 1 were identified as JP3A and JP3B.
1.2 RF24 = -24 V (negative logic)
1 .3 RF24 = + 2 4 V (Positive logic)
AD-Pres JPG 1 RF24 polarity for digital control inputs (see also JP10)
3.4 RF24 = -24 V (negative logic)
2.4 RF24 = + 2 4 V (positive logic)
All JP1 2 Voltage to encoder supply (EOV1, EOV2)

1.2 EOV1 = + 1 5 V d c
2.3 EOV 1 = + 5 V d c
All JP13 Voltage to encoder supply (E1V1, E1V2)

1.2 E l v t = EOV1 per JP12
2.3 E1V1 = -15 V do
5-16
Table 5-4. NTB/3T8 Board Aoyustab/e Hardware - Continued

AL-pres JP14, Coarse voltage range select for VCO #3, V3VCO
JP15 JP14 & JP15 settings determine the gain of the first stage of the analog interface circuitry for the (VCSP,
VC3N) analog inputs to the vavco channel. per the following table.
Max/inum Nominal
JP14 JP15 Input Voltage Input Voltage
2.3 2.3 16.9 10.0
1.2 2.3 23.3 13.8
2.3 1.2 34.9 20.6
1.2 1.2 41 .3 24.4
Maximum and Nominal values represent differential input voltages at the 3TB inputs with the following
significances:
Second Max: Max voltage for which the first stage will provide linear transfer function independent of the
V3SCLE setting.
Nominal: Voltage which will produce 20000 counts in VSVCOVAR (VAR.184) with the EE.V3SCLE
(EE.484) programmed to 10000. This is the optimum "rated reference" voltage, allowing 25% overrange.
Note that VCO #3 is only available on drives having SDCC control cards, not DCC control cards.
2.3 1o.o V Nom (with JPt5 2.3); or 20.6 v Nom (JP15 1.21
1.2 13.8 V Nom (With JP15 2.31: or 24.4 V Nom (JP15 1.2)
All JP17 Encoder o optically isolated receiver voltage drive level (EOA)
1.2 15 v do
2.3 5 V do
All JP18 Encoder O optically isolated receiver voltage drive level (EOB)
1.2 15 V do
2.3 5 V do
All JP19 Encoder O optically isolated receiver voltage drive level (EOM)
1.2 15 v de
2.3 5 V de
All JP2O Voltage level of external drive for general purpose relay (GR + and GR-)
1.2 120 volts
2.3 24 volts
All JP21 Supply -24 volts on COMPL-25

1.2. COMPL-25 is open
2.3 COMPL-25 is connected to -24 v do
AL-Pres JP22, Coarse voltage range select for VCO #4, V4VCO
JP23 JP22 & JP23 settings determine the gain of the first stage of the analog interface circuitry for the (VC4P.
VC4N) analog inputs to the V4VCO channel. per the following table.
Maximum Nominal
JP22 JP23 Input Voltage Input Voltage
2.3 2.3 16.9 10.0
1.2 2.3 23.3 13.8
2.3 1.2 34.9 2o.6
1.2 1.2 41 .3 24.4
Maximum and Nominal values represent differential input voltages at the 3TB inputs with the following
significances:
V4SCLE setting.
Nominal: Voltage which will produce 20000 counts in V4VCOVAR (VAR.185) with the EE.V4SCLE
(EE.488) programmed to 10000. This is the optimum "rated reference" voltage, allowing 25% overrange.
Note that VCO #4 is only available on drives having SDCC control cards, not DCC cards.
2.3 1o.o v Nom (with JP23 2.3): or 20.6 v Nom (JP22 1.2)
1.2 13.8 V Nom (with JP23 2.3); or 24.4 V Nom (JP22 1.2)
AL-Pres JP24 Enable 4-20 mA current loop input to the feedback VCO (FDBP, FDBN)
When the current loop mode is enabled (2.3), a 500-ohm burden resistor is inserted. yielding 10 volts at
20 mA.
1.2 Voltage input mode. scaled via SW1-5
2.3 Current loop input mode, SW1 -5 should be open
5-17
GEH-6005 DC2000 Digital Aqiustable Speed Drive
Table 5-4. NTB/3TB Board Aw:/stab/e Hardware - Continued
AA-AC JP3A RF24 polarity for digital control inputs (see also JP3B)
Note JP3A and JP3B were renamed JP1O and JP1 1 on subsequent revisions.
1 .2 RF24 = -24V (negative logic)
1 .3 RF24 = +24V (positive logic)
AA-AC JP3B RF24 polarity for digital control inputs. (See also JP3A).
3.4 RF24 = -24V (negative logic)
2.4 RF24 = +24V (positive logic)
All SW1 -5 Feedback VCO Channel/Analog Tach Feedback (FDBP, FDBN) Voltage Range Select
These switch settings determine the gain of the first stage of the analog interface circuitry for the (FDBP,
FDBN) analog inputs to the FBVCO channel. Maxima and Nominal values represent differential input
voltages at the 3TB inputs with the following significances:
First Max: Voltage for which the VCO stage will saturate with the FBSCL (DCC P6, if present) scaling
potentiometer set to the maximum gain (full CCW) position.
FBSCL setting.
Nominal: Voltage which will produce 20000 counts in FBVCOVAR (VAR.183) with the FBSCL scaling pot
set to maximum gain (full CCW) and the EE.FVSCL# (EE.1386ml -programmed to 10000. This is the
optimum "rated feedback" voltage, allowing 25% overrange.
Note that the software scaling function on the VCO channels is only available on DCP Rev 1.24 & later.
ALSO NOTE: When JP7 on the DCC/SDCC card is in the 2.3 position, each voltage range in the chart
should be divided by 6 (these values are shown in braces { } in the list of choices). For use with 4-20 mA
current inputs, set all switches off and see JP24 (REV AL and later).
O (All off) 25-33 Volts Max, 20.0 Volts Nom or 4-20 mA {4.2/3.3}
1 (1 on) 32-42 Volts Max, 25.1 Volts Nominal {5.3/4.2}
2 (2 on) 39-52 Volts Max, 30.9 Volts Nominal {6.515.2}
3 (1 ,2 on) 45-60 Volts Max, 35.9 Volts Nominal {7.5/6.0}
4 (3 on) 55-74 Volts Max, 44.0 Volts Nominal {9.2/7.3}
6 (2.3 on) 69-92 Volts Max, 54.9 Volts Nominal {11 .5/9.2}
a (4 on) 89-119 Volts Max, 70.5 Volts Nominal {14.8/11 .8}
1 2 (3,4 on) 11a-159 Volts Max, 94.5 Volts Nominal {19.7/15.8}
14 (2-4 on) 132-177 Volts Max, 105 Volts Nominal {22.0/17.5}
16 (5 on) 175-236 Volts Max, 140 Volts Nominal
20 (3,5 on) 205-276 Volts Max, 164 Volts Nominal
24 (4,5 on) 239-321 Volts Max, 191 Volts Nominal
28 (3-5 on) 268-362 Volts Max, 215 Volts Nominal
31 (All on) 300-390 Volts Max, 231 Volts Nominal
All SW6-7 Reference VCO Channel/Analog Reference (REFP, REFN) Voltage Range Select
These switch settings determine the gain of the first stage of the analog interface circuitry for the (REFP,
REFN) analog inputs to the RFVCO channel. Maxima and Nominal values represent differential input
voltages at the 3TB inputs with the following significances:
First Max: Voltage for which the VCO stage will saturate with the RFSCL (DCC P5, if present) scaling
potentiometer set to the maximum gain (full CW) position.
RFSCL setting .
Nominal: Voltage which will produce 20000 counts in RFVCOVAR (VAR.182l with the RFSCL scaling pot
set to maximum gain (full CW) and the EE.RVSCL# (EE.1281m) programmed to 10000. This is the
optimum "rated reference" voltage, allowing 25% overrange.
Note that the software scaling function on the VCO channels is only available on DCP Rev 1.24 & later.
O (All off) 12.5-16.9 Volts Max, 10.0 Volts Nominal
2 (7 on) 17.3-23.3 Volts Max, 13.8 Volts Nominal
1 (6 on) 25.8-34.9 Volts Max, 20.6 Volts Nominal
3 (All on) 30.6-41.3 Volts Max, 24.4 Volts Nominal
All PI Provides scaling of analog input P1 from 8 volts to 50 volts maximum.
All P2 Provides scaling of analog input P2 from 8 volts to 50 volts maximum.
5-18
5-4.9. Power Connect Boards (DSZOOPCCA. Section 6-12 defines I/O points for the PCCA, PCN,
531X122PCN, and 531X121PCR) and PCR boards.
The DS200PCCA Power Connect Card (PCCA), and 5-4.9.1. CONFIGURABLE HARDWARE. The PCCA has
the 531X122PCN and 531X121PCR Power Connect four wire jumpers, designated JP1, JP2, WP3, and
Boards (PCN, PCR) provide an interface between the WP4. Jumpers JP1 and JP2 must be connected to the
DC2000 drive's control circuitry and the SCR power appropriate stab terminals P3 through P10, as deter-
bridge. mined by the card group number and system voltage.
Jumpers WP3 and WP4 are used to connect stab termi-
Table 5-5 summarizes the applications of the various nals P2A to P2B, and P1A to P1B, respectively. These
PCCA group numbers and the PCN and PCR boards. jumpers are used to select whether the PCCA snubber
capacitors are connected to the same point on the power
The PCCA uses pulse transformers to provide gate bridge as the voltage feedback channel.
drive to the SCR bridge. For low-to-medium horse-
power controllers, the PCCA also includes snubber cir- Figure 5-11 shows the layout of the PCCA card, includ-
cuits to control spikes across the ac lines, do bus, and ing the locations of the stab terminals. Table 5-6 lists
gate drivers. For higher horsepower controllers, some and defines the placement of the wire jumpers for vari-
or all of the snubber circuits are omitted from the ous PCCA group numbers and system voltages .
PCCA, and are located elsewhere in the system.
Both the PCN and PCR boards also include wire jump-
The PCCA has ten group numbers. The group number ers that are connected between stab terminals on the
used 'm a system is determined by the system voltage, boards to select the de armature voltage.
frame size, and whether the system uses regenerative or
non-regenerative power conversion. Figure 5-12 shows the layout of the PCN board, includ-
ing the locations of these jumpers. Table 5-7 lists and
The armamre voltage scaling depends on which PCCA defines the PCN board jumpers.
group number is used:
Figure 5-13 shows the layout of the PCR board. Table
G1, G7, G9 - Regenerative, 240 - 630 volts 5-8 lists and defines the PCR board jumpers.
G2, G8, G10 - Non-regenerative, 240 - 700 volts
The PCN board is used in non-regenerative drives, the

PCR board is used in regenerative drives. Both board
types contain snubber circuits.
Table 5-5. Power Connect Board Applications

H
Board PCN, PCR PCCA PCCA PCCA PCCA

Group G1 - G 3 G1,G2 G5, G6 G7, G8 G9, G1 0
Scrubbers Ac&dc Ac&dc None & no Ac & do Do only
attenuation
string
Frames c, G c, G J, K, M c, G J, M
Power Supply SDCI DCFB DCFB SDCI SDCI
Board
Ac Volts $480 V runs $600 V runs $1500 V runs $600 V runs $600 V runs
Fuses Line Line Leg Line Leg
Reactors Line Line Leg Line Leg
Bus Transformer Separate Separate or Separate or Separate or Separate or
common common common common
5-19
1 RPL 2RPL 5RPL

..-
L
II
P R - 5RPL
4 L P R 6
Ii | EJ] [1]
,_ ,.. ,.
. .
5PL
L...- I I
2 25
1 0
'j
I 25
_
I ,..
4FPL
I
5FPL
,.
I ,..
6FPL
DSZOOPCCAG A
[j] 1 FPL
El]
l
2FPL
El]
3FPL
PA P7
- n
--
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P2 P2B PA -- pg
.II-
un- -- ',. _ . . . ..`

wp5 PB
P5 P10
--
P2A
\
P6
nu!
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DCS
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--
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-nn
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2ACS
nn:-
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-in
ann-
4»ACS
--
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5ACS
- n
SACS
un:
P1B\\WP4_____/I
Figure 5-1 1. PCCA Card Layout
Table 5-6. PCCA Card Aoyustab/e Hardware
All JP1 Groups 1, 3, 7, 9 only -

Selects do armature voltage range
3.8 240 V do, Also connect JP2 P6-P9
3.4 290 V do; Also connect JP2 P5-P6
7.8 500 V de; Also connect JP2 P9-P10
4_7 550 V do; Also connect JP2 P5-P10
o 630 v do; Leave all P3-P10 open
All JP2 -
Groups 1, 3, 7, 9 only Selects do armature voltage range (see JP1 , Groups 1,3,7)
6.9 24-O V do; Also connect JP1 P3-P8
10.9 500 V do, Also connect JP1 P7-P8
10.6 370 V do; Also connect JP1 P3-F'7
O 630 V do; Leave all P3-P1O open
All JP1 -
Groups 2, 4, 8, 70 only Selects do armature voltage range
3.7 550 V do; Also connect JP2 P6--P1O
o 700 V do; Leave all P3-P1 o open
5-20
Table 5-6. PCCA Card Acyustab/e Hardware - Continued

I Revision Name Description
All JP2 Groups 2, 4, 8, 10 only - Selects do armature voltage range (see JP1 , Groups 2, 4, 8)
10.9 390 V de: Also connect JP1 P7-P8
O 700 V do; Leave all P3-P10 open
AAA-AAZ JP1 Group 5 only - Selects do armature voltage range

3.4 290 v do; Also connect JP2 P5-P6
4.7 550 V do: Also connect JP2 P5-P1 O
O 630 V do; Leave all P3-P1 O open
AAA-AAZ JP2 Group 5 only - Seleets do armature voltage range (see JP1, Group 5 )
6.9 . 240 V do: Also connect JP1 P3-P8
10.5 550 V do; Also connect JP1 p4-p7
O 630 v do; Leave all P3-P1 o open
ABA-Pres JP1, JP2 Group 5 only - Jumpers deleted. Voltage attenuator string and jumpers no longer on Group 5.
AAA-AAZ JP1 Group 6 only - Selects do armature voltage range

7.8 390 V do; Also connect JP2 P9-P1o
4.7 500 V de; Also connect JP2 P5-P1O
3.7 550 v de; Also connect JP2 P6-P1 O
4.8 595 V do: Also connect JP2 P5-P9
O 700 V do; Leave all P3-P10 open
AAA-AAZ JP2 Group 6 only - Selects de armature voltage range (see JP1, Group 6)
'lO.9 390 v do; Also connect JP1 P7-P8
o 700 V do; Leave all P3-P10 open
ABA-Pres JP1,JP2 Group 6 only - Jumper deleted. Voltage attenuator strings and jumpers no longer on Group 6
All WP3 Groups 1-4, 7-10 only - Separate/tie card snubbers and VFBK to same/different point(s)
WP3 and WP4 are wire jumpers on the PCCA card which are connected between stab terminals P2A-
P2B and P1A-P1 B. respectively. If these jumpers are present the card snubber capacitors are at-
tached to the same point on the bridge as the voltage feedback channel. WP3 & WP4 may be re-
moved if the card snubbers and voltage feedback channel need to be connected to different bridge
points.
1 .2 Jumper IN - Connect scrubbers & voltage feedback channel to same point
o Jumper OUT - Separate scrubbers & voltage feedback channel
All WP4 Groups 1-4, 7- 10 only - Separate/tie card snubbers and VFBK to same/different point(s)
1.2 Jumper IN - Connect scrubbers & voltage feedback channel to same point
O Jumper OUT - Separate scrubbers & voltage feedback channel
5-21
__
531 x122PCNA_C1
POWER CONNECT CARD
5PL
4RPL 5RPL 6RPL 1RPL 2RPL 3RPL

2 2 2 1 1 1
1 ) 1 l 1 2 2 2
NOTE: REMOVE W1 AND W2 FOR 500V

DC DRIVES
PA P4 P5 t P6
I l
I F I I
W1-1 W1-2 W2- 1 w2-2
P2
PI
2AC sAc
I I I
Figure 5- 12. PCN Board Layout
Table 5- 7. PCN Eoard Acyustab/e Hardware
AE-Pres JP1 Selects de armature voltage range (see JP2)

JP1 and JP2 are wire jumpers which must be connected between the appropriate stab terminals, P3-P6.
The armature voltage scaling ranges depend upon which board group (G1 or G2) is being used. G1 is stan-
dard and G2 is used only with high voltage "D" frame drives only.
G1 Only:
3.4 240 V do; Also connect JP2 between stab terminals P5 and P6
O 500 v do; Leave stab terminals P5 to P6 open
G2 Only:
O 700 V de, Leave stab terminals P 5 to P6 open.
AE-Pres JP2 Selects do armature voltage range (see JP1 I
G1 Only:
O 500 V do; Leave stab terminals P3 to P4 open
G2 Only:
5.6 500 V do, Also connect JP1 between stab terminals P3 and P4
O 700 V do; Leave stab terminals P3 to P4 open
5-22
I 4RPL 5RPL SRPL 531X121PCRA_G1 1 NIL 2RPL SRPL
rV O
POWER CONNECT CARD
2
1
2
1 1
2
1 \
1
2
1
2
1
2 1-;1
z 26
25
I I
5PL
4FPL 5FPL SFPL 1 FPL 2FPL 3FPL

2 .
2 2 CHECK DRNE VOLTAGE 1 1 1
t 1 1 l OUTPUT FOR PROPER
JUMPER LOCAUON 2 2 2
IIP2
I1~
\
II P7 ]lp4 IIPB I IPS 1 IPS l[plo
P6
IH
AC 2AC :Ac
PI
II P2A
III AAC III SAC ::: SAC

(
I-Tgure 5- 13. PCR Board Layout
Table 5-8. PCR Board Adjustable Hardware
AF-pres JP1 Selects do armature voltage range (see JP2)

JP1 and JP2 are wire jumpers which must be connected between the appropriate stab terminals, P3-P10.
The armature voltage scaling ranges depend upon which board group number (G1, G2, G3, or G4) is being
used. GO is standard, G2 is used only with high voltage "D" frame drives only, G3 is used for low voltage
DFMs, and G4 is for single quadrant common bus drives. Note JP1 and JP2 must be installed in corre-
sponding positions.
Setting G1, G4 G2 G3
3.8 190 V do 350 V do 5ovdc
3.4 240 V do 420 v do 8OVdc
7.8 290 v do 500 V do 120 v do
4.7 340 V do 550 v de 15ovdc
3.7 400 V de 570 v do 170 V de
4.B 450 v do 630 v do 2 1 o v do
o 500 V do 700 v de 24OVdc
AF-Pres JP2 Selects do armature voltage range (See JP1)

Setting G1, G4 G2 G3
3.8 190 V do 350 V do 5OVdc
3.4 240 v de 420 V do 8OVdc
7.8 290 V do 500 V do 12OVdC
4.1 340 V de 550 V do 150 V do
3.7 400 V do 570 V do 17ovdc
4_8 450 V de 630 V do 210 V do
o 500 V do 700 v do 24oVdc
5-23
5-4.10. Relay Terminal Board (DSZOORTBA)
ZS
N
m
DFTPL
|-
or
z
Y25PL Y2SPL Y27PL Y2BFL Y29PL YJDPL Y31PL Y32PL Y33PL Y34PL Y35PL Y36PL Y57PL
The DS200RTBA Relay Terminal Board (RTBA) is an ad >-
I
optional board that is sometimes referred to as a Relay soZ
.-
Card. The RTBA provides ten relays, seven of which
z
*
I
m
z
have two form C contacts rated at 10 A, the other three I
C
z[
1-
L
L
.-
have four form C contacts rated at 5 A. These relays °»
g
are relays are driven directly from the relays on the
z
I
'E
I ,
LTB board, or remotely by the user. The RTBA relays I'
z
l
are available Mth three coil voltages, depending on the LET ..
En
or
z
group number of the board. The coil voltages available
l
are 110 v de (RTBAG1); 24 V do (RTBAG2); ally 115 ngl
C
of
I
V ac, 50/60 Hz (RTBAG3). u
I !
If
c
z[
E E
no
Section 6-13 defines I/O points for the RTBA board.
of al
E
D.
l
1
C
QL
l
The RTBA board includes Berg-type jumpers. Figure
5-14 shows the RTBA board layout, including the loca-
1
r.
z
l
- _go
r
~!.l-Iu
tions of these jumpers. Table 5-9 lists and defines tlle ..

n
2z
I
Y24PL Y25PL
jumpers N 1
J1
z
Y2:PL Y24PL
I I
u"
m
L
1 i
I
Y22PL Y2:PL
QQ
c
LJ
I.
Il f
- 1
z
Y21PL Y22PL
¥2cPL Y21PL
z[
2[
l
l
c C
[Lu Miaz-.I
m
JI
I I r-
V19PL ¥2cPL
l_II'! as
-v
l
-a
ll
z
YlaPL V19PL
l
Yl1PL YlaPL
.l
[r
Yl6Pi. Yl1PL
u as
rc
[
a.
'a
YISFL Yl6Pi.
1-
051
z
l
Y14PL YISFL
I I
LJ:-5
z
l
Y15PL Y14PL
to
o.
Bl
1
§=
c
of
Ir
z
Y9PL YIOPL Y11PL YIZPL Y15PL
_l~
EEE?3;
z:
I I
E
I
L.n
m
o.
1
z
I
EO 0~ §
ac
L
a
I I
LIE
*
9,"'[-"
_ §
E
z
I
n
=.
u
I
r
In
m
2
.J |-
L z
16
iN
L
u .-
sor D
m
h
z
L
o N
s O33
4-
" o
m
o. PA N | - .
u z
Fd
[QE 11533 __ -v
C333
§ldl' her .-
E
u ~ [ : :1 E321-= m
m
d :jar ZldF E
a II-_ E :I;]»» .-
.*
a'
x
° - N
z
G.
udr oldr
:
Q.
a
E (-
u u
.II
VLSVELHOOZS
Figure 5-74. RTBA Board Layout
5-24
Table 5-9. RTBA Board Aayustable Hardware
All JP1 Relay #20 coil voltage source

Each RTBA relay may be picked-up by either an internal control voltage source supplied through plug RPL
from LTB or an external voltage source connected on the terminal board between KnA (n = 20-26) and
KCM. (Note that additional options are available for K20-K22 via JP8 and JP9).
1.2 Use external power source (RTBA.TB.K2OA)
2.3 Use power source from LTB through plug RPL

1 .2 Use external power source (RTBA.TB.K21A)

1.2 Use external power source (RTBA.TB.K22A)

1 .2 Use external power source {RTBA.TB.K23A)



All JP8 K20-22 coil neutral source

In the 1.2 position, the coil neutrals of K20-K26 are all tied to RTB.5O (KCM). In the 2.3 position, the coil
neutrals of K20-K22 are isolated from RTB.50: JP9 must be set to position 2.3 to connect the coil neu-
trals to RPL.1 and LTB.
1.2 K20-K22 coil neutrals connected to RTB.50, KCM
2.3 K20-K22 coil neutrals isolated from RTB.5O
All JP9 RPL.1 connection

1.2 Ties RPL.1 to RTB.51 & OPTPL.2
2.3 Ties RPL.1 to K20-K22 coil neutrals
All JP1O Select whether pluggable circuit Y25PL-Y28PL is powered from CPH
1.2 Pluggable circuit using Y25PL-Y28PL, not connected to CPH
2.3 Pluggable circuit using Y25PL-Y28PL powered from CPH
All JP11 Select whether pluggable circuit Y25PL-Y28PL is powered from CPN
1.2 Pluggable circuit using Y25PL-Y28PL, not connected to CPN
2.3 Pluggable circuit using Y25PL-Y28PL powered from CPN
All JP12 Select whether pluggable circuit Y31 PL-Y34PL is powered from CPH
1.2 Pluggable circuit using Y31 PL-Y34PL, not connected to CPH
2.3 Pluggable circuit using Y31 PL-Y34PL powered from CPH
All JP13 Select whether pluggable circuit Y31 PL-Y34PL is powered from CPN
1.2 Pluggable circuit using Y31 PL-Y34PL, not connected to CPN
2.3 Pluggable circuit using Y31 PL-Y34PL powered from CPN
All JP14 Select whether pluggable circuit Y1 SPL-Y22PL is powered from CPH
1.2 Pluggable circuit using Y19PL-Y22PL, not connected to CPH
2.3 Pluggable circuit using Y1 SPL-Y22PL powered from CPH
All JP15 Select whether pluggable circuit Y19PL-Y22PL is powered from CPN
1.2 Pluggable circuit using Y19PL-Y22PL, not connected to CPN
2.3 Pluggable circuit using Y19PL-Y22PL powered from CPN
5-25
5-4.11. Drive Control Card (DS215SDCC) 5-4.11.2. CONFIGURABLE HARDWARE. The SDCC
contains Berg-type hardware jumpers, identified with a
The DS215SDCC Drive Control Card (SDCC) contains JP nomenclature, and hard-wired jumpers, identified
the drive's primary control circuits and software. The with a WJ nomenclature. Figure 5-15 shows the loca-
SDCC also contains general-purpose interface circuits tions of these jumpers on the SDCC card. Table 5-10
that connect with other boards to form various types of lists and deNies these jumpers.
ac and do motor drives. The interface circuits control
and process drive and motor signals, and customer I/O. 5-4.11.3. REPLACING/INSERTING SOFTWARE. The
SDCC must include the onboard software stored in
The SDCC contains three microprocessors: the Drive EPROMs U11, U 12, U22, and U23, and in EEPROM
Control Processor (DCP) at location U1, the Motor U9 to function in the drive. When replacing an SDCC,
Control Processor (MCP) at location U21, and the Co- transfer the onboard software from the old card to the
motor Processor (CMP) at location U35 . new as follows:
The SDCC card uses onboard software stored in Ive

memory chips: four EPROMs (U11, U12, U22, and CAUTION
U23), which contain configuration data programmed at
the factory; and one EEPROM (U9), which contains
field-adjustable parameters. These memory chips are To prevent component damage caused by
contained in sockets on the SDCC. static electricity, treat all boards with static
sensitive handling techniques. Use a
NOTE grounding strap when handling boards or
components. Store boards in anti-static bags
The DS200SDCC card does not include the or boxes.
five memory chips mentioned above (the
sockets are empty). To order a replacement To prevent damage to components, use the
card including the five memory chips, spec- proper chip extraction/insertion tool when
ify a DS215SDCC card. performing the following procedure.
Section 6-14 defines I/O points for the SDCC card. 1. Carefully remove one of the EPROM chips (U11,
Section 7-6.6 defines SDCC onboard testpoints. U12, U22, or U23) from the old card and insert it
into the same socket on the new card.
5-4.11.1. RESET CIRCUITS. The SDCC includes four
reset circuits, including a RESET pushbutton.
CAUTION
CAUTION
To prevent damage to memory chips, ensure
that chips are properly oriented when insert-
The system trips when a hard reset is initi- ing them into sockets.
ated; do not reset when running.
2. Repeat the previous step one chip at a time for
A reset can be generated in four ways: each of the remaining EPROM chips.
. By pressing the RESET pushbutton on the SDCC. 3. Remove the EEPROM chip (U9) from the old card
and insert it into the correct socket on the new
• card.
By applying +5 to +24 V do to customer interface
point 3TB pin 58 on the NTB/3TB board.
4. If the same failure symptoms still exist, install the
new (blank) EEPROM shipped with the new card.
The board generating a reset by programmed soft- Program the new EEPROM per the customer soft-
ware control• ware adjustment values using the ST2000 Toolkit
(see GEH-5860) or Drive Configurator, LynxOS
• The board generating a reset by automatic internal Version (see GEH-6203).
hardware watchdog protection.
5-26
:PL
312°
T' T
| I
34 |
31
I
N
an 7PL
:
f |
is \ | 19
JP12
CLKC 2 : ]
CP5 BM 1 2 5 5
CCM
CDX 0 l-D
FSR
CMP U35
XF 2 N15 P15 TP4 TPS TPE
Fsx
CLX
0 U 0 0 0 0
CLR
CDR ca
;
E
'2
3
Es D
DACS ..._
V_
- - _ -.
.ill
02
L
J
.-'~
0 I ' = - - - <_»-
N
N . r~ EEROM
ii
2 _
3
. _
._._,.
-.-1-- .. . _ _-. g
g
in
h
TP12
D
3 :za JP1
F :J QNMI
IH 3;
MTPNT
3
DCP
IJJP14
1 2 3 g JPB :zz
JP22 U1
9 JP23 JP7
PL :za 3:3
MCP I JP15
; 3 : ]
D.
El RESET
U21
Q O
D FCLK
QHHHUHHBHHU g
DCOM2 go
0 TP37
0
TV- BPL
nr; vi
1
I
1PL
CII
39
0 TP29
Q TPB 2PL
1
'E 6PL
4.o
2
1
V 11PL
10
s
1 1
DS215SDCCG1A 39
Figure 5-15. SDCC Card Layout
Table 5- 10. SDCC Card Acyustable Hardware
All JP1 EEPROM parameter write protect

1 .2 Writes inhibited, safe mode
2.3 Writes enabled (required to modify EEPROM)
All JP7 Enable 6:1 gain increase for feedback VCO circuitry
1.2 Normal gain
2.3 Increase gain 6:1 (see NTB SW1)
All JP8 Enable absolute value circuit for feedback VCO circuitry
Note that, due to the 10-volt maximum voltage available on the STBA card, the FB VCO is not normally
suitable for analog tacks unless the NTB/3TB board is used.
1 .2 Bipolar mode, for DC tachometers
2.3 Absolute mode, for analog AC AN tachometers
AFD-Pres JP12 DCP PROM high page enable
This jumper provides for future access to the full address space of 4 Mbit DCP program memory. It is
currently not used and should be left in the 1.2 position.
1.2 U12 and U11 are EPROM or FLASH memories up to 2 Mbit
2.3 Reserved for 4 Mbit FLASH memory (29F040) applications
AFD-Pres JP14 MCP PROM high page enable
This jumper provides for future access to the full address space of 4 Mbit MCP program memory. It is
currently not used and should be left in the 1.2 position.
1.2 U22/U23 are EPROM or FLASH memories up to 2 Mbit
2.3 Reserved for 4 Mbit FLASH memory (29F040) applications
S-27
Table 5- 10. SDCC Card Acyustable Hardware - Continued
O-ACZ JP15 Enable for DCP crystal

1 .2 Enabled (required for normal operation)
O Manufacturing test only
ADB-Pres JP16 Enables FLASH electrically erasable program memory erase/reprogram mode
JP16 is required to be in the 2.3 position only for in-house reprogramming of 12 V FLASH memory such
as the AM28F020. JP16 applies + 12 V do to the VPP pin of the DCP and MCP program memory.
EPROM memory and 5 V FLASH memory (such as the 29F04»O) do not require + 12 V do, so for these
types of Ut 2, U1 1, U22, and U23 memory, JP16 should be left in the default 1 .2 position.
1 .2 Normal mode for EPROM or FLASH memory read only
2.3 Reserved for FLASH memory reprogramming mode
All JP22 Enable for MCP crystal
1.2 Enabled (required for normal operation)
All JP23 Signal source into DCP's external DMA channel, used for time tagged inputs
1.2 From NTB/3TB analog feedback input (for AC AN tech interfaces)
2.3 From the NTB/STB encoder marker track input, EOM.
o-Acz JP33 Enable for CMP crystal
1.2 Enabled (required for normal operation)
ADB-Pres WJ1 Remap MET3 D/A to DAC1 output for SDCCG3
SDCCG3 omits the 12-bit DIA converter used for DAC 1 and DAC2, and instead drives DAC1 and DAC2
outputs with the 8-bit D-A used to drive MET3 and MET4 on SDCCG1 . MET3 and MET4 are not available
on SDCCG3. If this jumper is erroneously present on an SDCCG1 card, the D/A outputs will be corrupted;
if this jumper is missing on an SDCCG3 card, the DAC1/DAC2 output will not function.
O SDCCG1 , jumper omitted
1.2 SDCCG3, jumper installed
ADB-Pres WJ2 Remap MET4 D/A to DAC2 output for SDCCG3
O SDCCG1, jumper omitted
1 .2 SDCCG3, jumper installed
ADB-Pres WJ3 Provide 10-volt full scale reference for DIA outputs on SDCCG3
If this jumper is incorrectly set for the SDCC group number, the DIA converters will operate improperly.
O SDCCG1 , uses internal reference from 12-bit D/A
1.2 SDCCG3, develops reference from + 5 V do power supply
ADB-Pres WJ4 Identify card group number to firmware
The firmware uses this jumper to identify whether the card contains GO or G3 components. Incorrect
setting of this jumper will cause malfunction of the DCP, including the inability of the processor to power
up and configure card logic cell arrays, and possible loss of EEPROM drive configuration memory.
O Omit jumper, identifies card as group G1
1 .2 Install jumper. identifies card as group G3
ADB-Pres WJ5 Configure card for logic cell array size
Incorrect setting of this jumper may damage or cause unreliable operation of LCA U32.
O Jumper omitted on SDCC G3 (LCA is 3042 device)
1.2 Jumper installed on SDCC G1 (LCA is 3OB4 device)
ADB-Pres WJ7 Configure card for EEPROM size

In all present drive applications, WJ7 and WJ9 must be omitted and WJ8 and WJ1 O must be installed.
The alternate setting allows for future expansion of EEPROM size from 32K to 64K. Incorrect setting of
these jumpers will result in incorrect reading and configuration of the drive EEPROM.
O SDCCG 1 and G3, jumper omitted
1.2 Reserved for future expansion
O Reserved for future expansion
1.2 SDCCG1 and G3, jumper installed
O SDCCG1 and G3, jumper omitted
1.2 Reserved for future expansion
ADB-Pres WJ1O Configure card for EEPROM size
O Reserved for future expansion
1.2 SDCCG1 and G3, jumper installed
5-28
5-4.12. Dc Power Supply and Instrumentation circuit. This circuit is at the potential of the motor ar-
Board (DSZOOSDCI) manure since it connects to the armature current sensing
shunt.
The DS200SDCI Dc Power Supply and Instrumentation
Board (SDCI) provides logic power and interface cir- The outputs of the SDCI power supplies are protected
cuimry for the DC2000 drive. The board includes the by fuses FU2 and FU3 (7A, 2AG). Light-emitting di-
following circuits: odes (LEDs) CR51 and CR55 provide blown fuse indi-
cations for FU2 and FU3, respectively .
• +5 V do, 4 A, i15 V de, 0.4 A, -L24 V do, and 115
V ac, 0.4 A power supplies 5-4.12.2. FIELD POWER CIRCUITRY AND CURRENT
VCO. The G1 version of the SDCI board includes a
. Motor Held power circuits (except the SCR mod-
ule)
field supply circuit for fields up to 10 A. The SDCIG1
board contains all field power circuitry, except the SCR
module .
Driver circuits for the armature SCR gating
The field power circuit contained 011 the SDCIGl board
Circuits to monitor numerous ac line and do motor includes snubbers and a reactor. Field power is input at
stab terminals ACl through AC3. The field current is
signals, including:
'filtered by the reactor. The field is connected to stab
terminals FAC2 and FAC3. Depending on drive frame
Armature current and voltage
size, a 3-phase MOV may be attached to stab terminals
MOV1 through MOV3. The field outputs and MOV
Field current outputs are protected by fuses FU5 and FU6. Neon
lights LT5 and LT6 indicate if FU5 or FU6, respec-
Ac line currents, voltage magnitude, and phase tively is blown. For more information on the fuses, re-
SSQUCIICC fer to Chapter 9.
There are two group numbers of the SDCI. The G1 The SDCIG2 board is used in applications greater than
version of the board includes circlu'ts for an internal $10 10 A. These applications require a field power circuit
A field exciter, the G2 version is used with external that is external to the SDCI board. The SDCIG2 board
field exciters. omits the field power circuit described above .
Section 6-7 defines I/O points for the SDCI board. Sec- Both group numbers of the SDCI board include a volt-
tion 7-5 defines SDCI onboard fuses, and section 7-6.7 age-controlled oscillator (VCO) circuit for feedback
defines SDCI testpoints. signals from the field shunt. The VCO converts the in-
put voltage from the field shunt to a frequency signal.
5-4.12.1 . POWER SUPPLIES. The SDCI board receives The nominal output frequency of the VCO is 250 kHz;
38 V ac (i~10%) from the control power transformer the output frequency varies from 0 to 500 kHz, depend-
(CPT). This voltage is rectified and Eltered to produce ing upon the input voltage. The frequency signal is sent
the unregulated £4 V de outputs. The +24 V do output to the SDCC card through lPL-9. The field shunt VCO
is rated at 3 A, the -24 V do output is rated at 1 A. Of circuit is isolated (up to 600 V) from drive common
these, 0.5 A is available for external loading . (DCOM) and from the armature VCO described in the
following section.
Regulators on the SDCI derive i-15 V do from the 1124
V do supplies. The £15 V de outputs are rated at 0.4 A, 5-4.12.3. DC ARMATURE VOLTAGE VCO. The motor
of which 0.25 A is available for external loading . armamre voltage is attenuated, and then brought into
the SDC1 board as a differential input on connector
The SDCI also generates a +5 V do, 4 A output Hom SPL. The armature voltage VCO circuit converts the
the +24 V de supply. The /PSEN signal on connector voltage to a i5 V frequency signal, which is sent to the
2PL goes to a TTL low state when the +5 V do supply SDCC card through 1PL-13. The armature voltage
is in regulation: the signal goes high if the supply goes VCO circuit also provides an analog representation of
out of regulation. When high, /PSEN is used to gener- the armature voltage (VFBB), which is sent to the
ated a microprocessor reset on the SDCC card. SDCC through lPL-37, and can be measured at SDCC
testpoint TP37 .
The DCFB also provides isolated +5 and i15 V do
supplies used to power the armature current feedback
5-29
6-4.12.4. ARMATURE CURRENT vco. A third VCO Connector CNPL provides 115 V ac to the MA contac-
circuit, which floats at the armature bus potential (up to tor, connector MACPL provides a 24 V do FET output
600 V above DCOM), instruments motor current de- to the MD contactor driver. Jumper JP1 is used to select
tected from a shunt. The shunt voltage is converted to a whether the MD contactor is controlled independently
frequency and is sent to a counter circuit on the SDCC of the MA contactor by the SDCC MCP. Jumper JP2
through 1PL-8 c selects the dropout time for the MA contactor (see Ta-
ble 5-7).
5-4.12.5. Ac LINE ZERO CROSSING, MAGNITUDE,
AND PHASE SEQUENCE. A 3~phase filter and amplifier 5-4.12.8. ARMATURE AND FIELD FIRING CIRCUITS.
circuit processes the ac line-to-line voltages. These The SDCI board contains two programmable array
voltages are logically ORed to derive the VMAG and logic (PAL) circuits that decode armamre and field fir-
VSEQ signals, which are sent to the SDCC through ing signals from the SDCC card. Based upon these Hr-
lPL-5 and 1PL-6, respectively. One of the amplifier ing signals, the PALs direct tiring pulses to the appro-
circuit outputs is also filtered, processed by a zero- priate SCR bridge or field gate pulse transformer driv-
crossing detector, and made TTL-compatible to produce ers. The SDCI includes transformers that isolate the
the SYNC signal sent to the SDCC through IPL-29. .
field gate firing outputs
The SDCC uses these signals to determine the magni- The SDCC provides a 25 kHz, 10% duty cycle pulse
tude and phasing of the ac line-to-line voltages. VMAG train (SYOSC) through connector 1pL-14. This pulse
represents the average voltage on the incoming ac lines. HaM, along with the enable and initial pulse (IPU) sig-
VSEQ is used with the SYNC signal to determine if the nals from the SDCC, are used to form the firing bursts.
ac line phasing is correct. SYNC is the V2-V3 zero- The SDCC also generates signals to select which SCR
crossing synchronization signal. pair is enabled, and to indicate when the Cell Test
Mode is active .
5.4.12.6. AC LINE INSTRUMENTATION. The drive's 1
and 3 ac lines include current transformers CT1 and 5-4.12.9. DELAYED FIRING POWER. A delayed firing
CT2. DIP switch SW1 is used to select burden resis- power circuit on the SDCI board provides power to the
tance as a function of the nominal de output current of SCR bridge gate-pulse transformer outputs. As a pro-
the CTs (see Table 5-7). The SDC1board sends the tection, the power remains off until gating is required.
ACCT output current signals IL3 and ]].,l to the SDCC As an additional protection, this circuit removes gate
through lpL-l and lPL-2, respectively. The SDCC uses Bring power in the event of a failure.
these two signals to check for commutation failure and
ac instantaneous overcurrent GOC). 5-4.12.10. CONFIGURABLE HARDWARE. The SDCI
board includes Berg-type jumpers and a DIP switch
5-4.12.7. CONTACTOR DRIVE CIRCUITS. The SDCI used for customer options. Figure 5-16 shows the layout
board includes relay K2, which serves as a pilot relay to of the SDCI board, including the locations of the jump-
the MA or MD contactor. The SDCC drives the coil of ers and switch. Table 5-11 lists and defines these items .
K2 through IPL-34 and IPL-35 C
5-30
»
VI vz vs 1A1PL 1F1PL
II II II p
l 1
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FFS
II
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R w
NPL
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as
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'mum
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<
A. I FUS 5 ru:
|Q I -G
r CNPL
I
|
Act
. I
I VI
.SA
2 I
Los I
A02
II
DS200SDCIG1A
Ac:
II 1
SPL
- ZPL
I- CPTPL FAPL urL
I
Figure 5- 16. SDC/ Board Layout
Table 5-7 7. SDC/ Board Adjustable Hardware
All JP1 MD control source

This jumper allows the MD contactor drive hardware output to be slaved to the MA contactor drive hard-
ware output. Normally the MD contactor drive output is controlled independently by MCP software (JP1 =
1-2).
1.2 MD controlled by MCP (Normal Operation)
2.3 MD hardware slaved to MA operation
All JP2 MA ac contactor drop-out time

Normally, this circuit delays opening of the ac contactor to ensure all load current has been extinguished.
Removal of this jumper during normal running can cause the control-on circuit to drop out the MA relay
before the current has been brought to zero.
1.2 Normal operation, gives about 1 oo ms delay
2.3 Minimum delay, (and manufacturing test)
All swf Select ac line CT burdens as a function of nominal do output current

These switch settings scale the ac line current transformers as a function of do amps. Correct scaling is
essential for proper operation of the ac IOC protective feature. These CTS are mounted on ac lines 1 and 3
of the power bridge and are wired through connector 1CPL to a burden resistor network. Select the proper
setting as a function of drive current and CT turns ratio. The CT ratio can be determined from its part
number and the following table.
Part Number Turns Ratio
104x157AB O23 1 OOO:1
104X157AB 025 2000:1
104x157AB O20 4000:1
104X157AB O13 500021
104X157AB O24 5000:1
104x157AB O26 8000:1
5-31
Table 5-1 1, soc/ Board Adjustable Hardware - Continued

When set properly, the current magnitude read in VAR.1019 (CTCFB) should be scaled within 15% of the
current magnitude in VAR.1 O4 (CFB). Above 144 mA ACCT secondary current, the CTs are routed through
a set of 10:1 step down CTS on the SHVI/SHVM card, using JP1 -JP8 on the SHVI/SHVM card. The enu-
merations listed are in terms of the mA input to the DCFB card (ACCT secondary mA attenuated by 10:1
SHVI/SHVM attenuation if selected). At present the SHVI/SHVM cards are used on M, J, K, and L frames
only, and then 10:1 CTs are used only if the ACCT secondary current is > 144 mA.
The CT secondary current (in mA) is approximated by:

1 pu rated current x 1000
/ct, mA
Combined CT turns ratio
o (All off) 0.0 s let, mA < 6.1
1 (1 on) 6.1 S let, mA < 13.4
2 ( 2 on) 13.4 s let, mA < 21 .1
3 (1 ,2 on) 21.1 s let, mA < 28.4
4 ( s on) 28.4 s let, mA < 39.3
5 (1,3 on) 39.3 s lot, mA
< 46.7
6 (2,3 on) 46.7 _< let, mA
< 54.4
7 (1,2,3 on) 54.4 S lot, mA
< 61 .s
8 (4 on) 6t.8 S lot, mA
< 88.7
9 (1 ,4 on) 88.7 s lot, mA
< 96.0
10 (2.4 on) 96.0 < 103.0
S let, mA
11 (1,2,4 on) 103.0 < 1 1 1.o
s let, mA
12 (3,4 on) 111.0 $lct,mA < 122.0
13 (1,3,4 on) 122.0 s let, mA < 129.0
14 (2,3,4 on) 129.0 s let, mA < 137.0
15 (All on) 137.0 S let, mA < 144.0
5-4.13. SCR High Voltage Interface Board Incorporates three neon `mdicator lights to provide
(DS200SHVI) visual indication of a blown line filter fuse
The DS200SHVI SCR High Voltage Interface Board Includes driver circuits for both standard and fast
(SHVI) provides an interface for signals from the contactors
DC2000 drive's SCR bridge to the DCFB or SDCI
board and PCCA card. The SHVI performs the follow- Section 6-15 defines I/O ports for the SHVI board.
ing functions:
5-4.13.1. CONFIGURABLE HARDWARE. The SHVI
Converts shunt signals (-500 my to +500 mV) 'into board includes Berg-type jumpers. Revision AAA of the
differential-frequency outputs (0 to 500 kHz) that board also included hard-wired jumpers that were con-
are sent to the DCFB or SDCI board nected to stab terminals to connect or bypass the
board's attenuation circuits. Figure 5-17 shows the
Incorporates hardware jumper-selectable 10:1 cur- SHVI board layout, including the locations of the Berg-
rent transformers to provide additional current at- type jumpers. Table 5-12 lists and defines the Berg-type
tenuation capability and hard-wired jumpers.
Provides attenuation of line and bridge voltages
5-32
L1 H L2 II LE II PI II P2 II
<[1§"° <g1"'2
JP9 JP11 an?)
<§¥ L.: LJ LJ
H II H II II
VI V2 V5 P1A
JP14 P2A
FA
II I I VM1A
v11AII n
FB
II JPE§ll: II VM1 B
JP16 m1EI I OD
II
LT1
@ m2AII -13
J
|| Q
VM2A >
FC
LT2
© JP17
:=@J
I
y)
o
LTD
@ M2BII | | VM2B o
N
m
O
SDPL
w
R EI
..
no
DC1PL
UP
G
DC1COM HI"wN
1A1PL
l::J
ACNCOM
no N
1A2PL
w
II
CONTACT
+ll
. B1
M1
1
N
w
CI
EI
R
.¢
I I MI
DC2pL CONTACT .2
E
DCZCOM
I I sz
MPL
RMPL
4
2
'H 0 HzH 0 go0 0 go0'0

1
5:2 Q2
1
$2
1
h-2 m
sLI"s.J":}J":Jls}J";sU"sLl%51J%
1 1 1
cT PL 1 CPL clapL
2 U R w
4
w R R w
I
1 z
w R
I; II
cAcl CAC2
II
Figure 5- 77. SHV/ Board Layout
5-33
Table 5- 12. SHV/ Board Acyustable Hardware
AAA-AAA JP1-JP12 Select 10:1 attenuation for phase A (JP1 -JP4), phase B (JP5-JP8}, and phase C (JP9-JP12) cur-
rent transformers
Jumpers JP1 -JP1 2 should all be set to the same position, either selecting or bypassing the 10:1
attenuation for the ac line current transformers. The attenuation is required if the ACCT secondary
current feeding the SDCI, DCI, or DCFB power supply boards is > 144 mA (rated do currentlACCT
ratio). Burden resistor circuits on these boards canhot handle > 144 mA inputs. Be sure to com-
pensate for the 10:1 current attenuation when setting the burden scaling jumpers or switches on
the DCI, SDCI, or DCFB board, whichever is used.
1.2 Bypass 10:1 attenuator, ACCT current < 144 mA
2.3 Insert 10:1 attenuator, ACCT current 2 144 mA
BAA-Pres JP1-JP8 Select 10:1 attenuation for phase A (JP1 -JP4) and phase C (JP5-JP8) current transformers
1.2 insert 10:1 attenuator, ACCT current > 144 m A
2.3 Bypass 10:1 attenuator, ACCT current s 144 mA
BAA-Pres JP9-JP11 Bypass line voltage phase L1 (JP9), L2 (JP10), and L3 (JP11) attenuator strings for 240 - $00 V ac
JP9, JP10, and JP1 1 together are used to scale the ac line voltage feedbacks.
1.2 Main ac = 601 - 1500 volts
2.3 Main ac = 240 - 600 volts (bypass attenuators)
BAA-Pres JP12 Bypass do + bus attenuation
Bypass voltage attenuator string for do + bus for 240-600 V ac (P1). JP12 and JP13 are used to
scale the do bus voltage feedback.
1.2 Main ac = 601 - 1500 volts
2.3 Main ac = 240 - 600 volts (bypass attenuators)
BAA-Pres JP13 Bypass dc- bus attenuation
Bypass voltage attenuator string for dc- bus for 240 - 600 V ac (P2).
1.2 Main ac = 601 - 1500 volts
-
2.3 Main ac = 240 600 volts (bypass attenuators)
BAA-Pres JP14 Bypass motor voltage #1 M1A attenuator string for 240 - 600 volts
JP14 and JP15 together are used to scale the motor voltage #1 voltage feedback. However, the
settings for JP14 and JP1 5 are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 - 1500 volts
2.3 Main ac = 240 - 600 volts (bypass attenuator)
BAA-Pres JP15 Bypass motor voltage #1 M1 B attenuator string for 240 - 600 volts
-
1.2 Main ac = 601 1500 volts
-
2.3 Main ac = 240 600 volts (bypass attenuator)
BAA-Pres JP16 -
Bypass motor voltage #2 M2A attenuator string for 240 $00 volts
JP16 and JP1 7 together are used to scale the user-defined voltage for customer-specific applica-
tions. However, the JP16 and JP17 settings are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 1500 volts
-
2.3 Main ac = 240 600 volts (bypass attenuator)
BAA-Pres JP17 Bypass motor voltage #2 M2B attenuator string for 240 - 600 volts
1.2 Main ac = 601 -
1500 volts
AAA-AAA BYP1A/B, Bypass line voltage attenuator strings for phase L1 lBYP1A/B). L2 (BYP2AlB), and L3 (BYP3A/B) for
BYP2A/B, 240 - $00 volts
BYP3A/B BYP1A/B, BYP2A/B, and BYP3A/B together are used to scale the ac line voltage feedbacks.
O Greater than $00 volts (BYP1 A - BYP1B, BYP2A - BYP2B, and BYP3A - BYPBB open)
1 .2 240 _ 600 volts (Stab BYP1 A - BYP1B, BYP2A - BYP2a, and BYP3A - BYP3Bl
AAA-AAA BYP4A/B, Bypass voltage attenuator strings for do (BYP4AlB) and dc- (BYP5A/B) buses for 240 - 600 volts
BYP5A/B BYP4A/B and BYP5A/B together are used to scale the do bus voltage feedback.
o Greater than 600 volts (BYP4A - BYP4B and BYP5A - BYP5B open)
_
1.2 240 600 volts (Stab BYP4A - BYP4B and BYP5A - BYP5B)
AAA-AAA BYPSA/B, -
Bypass voltage attenuator strings for motor voltage for 240 600 volts
BYP7A/B BYPSA/B and BYP'/A/B together are used to scale the motor voltage feedback.
O -
Greater than 600 volts (BYP6A - BYP6B and BYP7A BYP7B open)
_
1 .2 240 600 volts (Stab BYP6A - BYP6B and BYP7A - BYP7B)
AAA-AAA BYP8A/B, Bypass voltage attenuator strings for user-specific voltage for 240 -
600 volts
BYP9A/B BYP8A/B and BYP8A/B together are used to scale the user-defined voltage for customer-specific
applications.
O Greater than 600 volts (BYP8A - -
BYPBB and BYP9A BYP9B open)
1 .2 240 - 600 volts (Stab BYP8A - BYP8B and BYP9A BYPSB) -
5-34
5-4.14. SCR High Voltage M Frame Interface Incorporates hardware jumper-selectable 10:1 cur-
Board (DSZOOSHVM) rent transformers to provide additional current at-
tenuation capability
The DS200SHVM SCR High Voltage M Frame Inter-
face Board (SHVM) provides an interface for signals
from an M frame drive's SCR bridge to the DCFB or
. Provides attenuation of ac line, motor armature,
and SCR bridge voltages
SDCI board and PCCA card. The SHVM performs the
following functions: Section 6-15 defines I/O points for the SHVM board.
. Converts shunt signals (-500 mV to 500 my) into

differential-frequency outputs (0 to 500 kHz) that
5-4.14-.1. CONFIGURABLE HARDWARE. The SHVM
board 'includes Berg-type jumpers used for manufactur-
are sent to the DCFB or SDCI board ing test or customer options. Figure 5-18 shows the
SHVM board layout, including the locations of these
jumpers. Table 5-13 lists and defines these items.
II Ll IIL2 11 L5 II PI II P2 H »A1A
1 JPS
1 JP10 1 .IP11 'Jp12 1 Jpls 1 Jp14 M1B II
2 2 z 2 2
2
JP15
1.J5 L J ; LJ 5 L.: 5 LJ: 1
1..15
z
: I
I
1..13
II V1 llv2 llvs II P1A II P2A II VM1A

vo
VOLTAGE
LTAGE ATTENUATDR JP1-9 SETTINGS
II
via <
JUMpeas
JUMPERS AÌTEN.
USE SHVM AÌTEN . BY-PASS SHVM 1-
o
STRING
STRING ATTEN. STR
I
JP16 JP9-1 T
JP9-17 1-2
1-2 2-5 >
M2A I
1 2 5 m
1 s'I o
II . J II II 1 2
J
II o
N
vmzs pa
JP17
G
_ Q
R
w
II
R _J
DClPL
1AIPL
u-
w
.I
w
R _ SDPL
DCZPL
R
ACCT EXTRA 10:1 ATTENUATIDN CT'S w
JUMPERS USE 10:1 BY-PASS IO: 1 1AZPL
STEP-DWN CT'5 STEP-DWN CT'S
JP1-B
JP1-B 1-2 2-5
JP1 JP2 JPG JP4 JP5 JP6 JP7 JPB
HHUHUUHU
1 1 1 1 1 1 1
2 2 2 2 z 2 2 2
I I I I
LJ3 LJ 3 LJ3 LJ3 LJ3 LJ 3 L J 3 L J 5
i Hi
1CPL
r'
R w w R R w w R
Figure 5~ 78. SHVM Board Layout
5-35
Table 5- 13. SHVM 8oard A¢#ustable Hardware
All JP1 - JP8 - -

Select 10:1 attenuation for phase A (JP1 JP4) and phase C (JP5 JP8) current transformers
Jumpers JP1 -JP8 should be set to the same position, either selecting or bypassing the SHVM 10:1 CT
attenuation for the ac line currents. Attenuation is required above 144 mA main line ACCT secondary
current (Rated do current/ACCT ratio), because the CT burden resistors on the SDCI board are not
rated to handle > 144 mA. Be sure to compensate for the 10:1 current attenuation when setting the
burden scaling switches on the SDCI board.
1 .2 Insert 10:1 attenuator, ACCT current > 144 mA
2.3 Bypass 10:1 attenuator, ACCT current s 144 mA
All JP9 Bypass line voltage phase L1 attenuator string for 240 - 600 V ac
JP9, JP10, and JP1 1 together are used to scale the ac line voltage feedbacks.
1.2 Main ac = 601 .. 1000 volts
All Jpto Bypass line voltage phase L2 attenuator string for 240 -
$00 V ac
-
1.2 Main ac = 601 1000 volts
All JP11 Bypass line voltage phase L3 attenuator string for 240 - 600 V ac
_
1.2 Main ac = 601 1000 volts
2.3 Main ac = 240 - $00 volts (bypass attenuator)
All JP12 -
Bypass de + bus voltage attenuator string for 240 600 volts (PI)
JP12 and JP13 together are used to scale the do bus voltage feedback. However, the settings for
JP12 and JP13 are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 - 1000 volts
All JP13 Bypass dc- bus voltage attenuator string for 240 - 600 volts (P2)
-
1.2 Main ac = 601 1000 volts
2.3 Main ac = 240 - BOO volts (bypass attenuator)
All JP14 Bypass motor voltage #1 M1A attenuator string for 240 -
600 volts
JP14 and JP15 together are used to scale the motor voltage #1 voltage feedback. However, the set-
tings for JP14 and JP15 are based on the nominal main ac runs input voltage.
t . 2 Main ac = 601 1000 volts
¢.

All JP15 Bypass motor voltage #1 M1 B attenuator string for 240-600 volts (M1 B)
1.2 Main ac = 601 - 1000 volts
2.3 Main ac = 240 -
600 volts (bypass attenuator)
All JP16 Bypass motor voltage # 2 M2A attenuator string for 240 - GOO volts
JP16 and JP17 together are used to scale the motor voltage #2 voltage feedback. However, the set-
tings for JP16 and JP17 are based on the nominal main ac runs input voltage.
1.2 Main ac = 601 - 1000 volts
All JP17 Bypass motor voltage #2 M2B attenuator string for 240 -
600 volts
-
1.2 Main ac = 601 1000 volts
5-36
*Pi*
DC2000 Digital Adjustable SpeedDrive GEI-I-6005
5-4.15. LAN Communications Card 5-4.15.1. CONFIGURABLE HARDWARE. The SLCC

(DS215SLCC) includes Berg-type jumpers and hard-wired jumpers.
Figure 5-19 shows the locations of the SLCC card
The DS215SLCC LAN Communications Card (SLCC) jumpers. Table 5-14 lists and defines these items.
provides isolated and non-isolated input circuits for
communications to the drive. The SLCC connects to the 5-4.15.2. REPLACING/INSERTING SOFTWARE. The
NTB/3TB or STBA, SDCC, and DCFB or SDCI boards SLCC must include the onboard software stored in
via 2PL, to the SDCC card via 3PL; and to the optional EPROMs U6 and U7 to function in the drive. When
LTB board via IOPL. The SLCC also connects to the replacing the SLCC card, the onboard software must be
Programmer. transferred from the old card to the new. Carefully re-
move each of the two EPROM chips from the old card
The SLCC features an alphanumeric display controller and insert it into the same socket on the new card.
that connects to the Programmer. Refer to Chapter 8 for
information about the Programmer.
CAUTION
The SLCC also includes onboard software contained 'm
two EPROMs, designated U6 and U7 . To prevent component damage caused by
NOTE static electricity, treat all boards with static
sensitive handling techniques. Use a
The DS200SLCC card does not include grounding strap when handling boards or
EPROMs U6 and U7 (the sockets are empty). components. Store boards in anti-static bags
To order a replacement board including or boxes•
these two memory chips, specify a
DS215SLCC card. To prevent damage to components, use the
proper chip extraction/insertion tool when
The SLCC has three group numbers. The G1 version of performing the following procedure.
the SLCC includes circuits used to connect the drive to
DLAN (drive local area network) or DLAN + To prevent damage to memory chips, ensure
(ARCNET) networks; the G2 version includes only the that chips are properly oriented when insert-
DLAN interface circuits, and the G4 version includes ing them into sockets.
neither the DLAN nor the ARCNET circuits.
Section 6-16 defines I/O points for the SLCC card.
S-37 "»
DEVICE TOWARD THIS END

Ds215sLccc;1A
10PL
DPL
I I
.3
L=1:J
JPZO
1
1 I
I U5 U7
u1 I
_
-O LJ U WJ4 2PL
I:-1
6ldf`
O (J
WJ5
`ldd>l
LJ LJ n
nEI n
HE
WJ2 WJ1 D
O U
* 0 0 1-
if:
pa
n
I I
ID
D-
pa
l"l
- 01.
I I
or
-v-
"J
ARCPL
WJ3 LJ LJ
Figure 5- 7.9. SLCC Card Layout
S-38
Table 5- 74. SLCC Card Aayustab/e Hardware
Jumpers JP14 through JP18 are not present on DS21 SSLCCG4 cards.
All JP14 Groups 1 and 2 only - This jumper selects the RS-422 DLAN drivers or the isolated DLAN circuit
1 .2 Isolated DLAN circuit
2.3 RS422 drivers and receivers
All JP15 -
Groups 7 and 2 only This jumper selects the RS-422 DLAN drivers or the isolated DLAN circuit
1.2 Isolated DLAN circuit
2.3 RS-422 drivers and receivers
All JP16 Groups 1 and 2 only - This jumper selects the RS-422 DLAN drivers or the isolated DLAN circuit
1.2 Isolated DLAN circuit
2.3 RS422 drivers and receivers
All JP17 Groups 1 and 2 only - This jumper puts the DLAN termination resistors in the DLAN circuit
The termination jumpers should be added to the drives located at the end of a daisy~chain 422 LAN.
Never exceed 5 sets of termination resistors in a 422 DLAN circuit.
1.2 Termination resistors in
2.3 Termination resistors out
Ali JP18 Groups 1 and 2 only - This jumper puts the DLAN termination resistors in the DLAN circuit
The termination jumpers should be added to the drives located at the end of a daisy-chain 422 LAN.
Never exceed 5 sets of termination resistors in a 422 DLAN circuit.
1.2 Termination resistors in
2.3 Termination resistors out
All JP19 Groups 7, 2, and 4 - This jumper connects the crystal to the processor
This bumper should be in place except during manufacturing testing.
1.2 Normal running condition
2.3 Manufacturing testing
All JP2O Groups 7, 2, and 4 - This jumper sets up the EPROM sockets for either EPROMs or Flash PROMS
1.2 EPROM setting
2.3 Flash PROM setting
All WJ1 Groups 1, 2, and 4 - This jumper redirects the Ready Line when there is no ARCNET module
This jumper should be in place when there is no ARCNET module.
1.2 No ARCNET module (os215$LCCG2, G4)
O ARCNET module present (DS215$LCCG1)
ACC-Pres WJ2 Groups 1, 2, and 4 - This jumper connects the LRX signal to ground through a 470-ohm resistor
This jumper should be in place for G4 only.
o LRX signal is not connected to ground (DS21 5SLCCG1, G2)
1.2 LRX signal is connected to ground (DS21 SSLCCG4)
ACC-Pres WJ3 Groups 1, 2, and 4 - This jumper connects the T2CLK signal to ground through a 470-ohm resistor
O T2CLK signal is not connected to ground (DS21 SSLCCG1, G2)
1.2 T2CLK signal is connected to ground (DS21 5SLCCG4)
ACC-Pres WJ4 Groups 1, 2, and 4 - This jumper connects the input signal to ground through a 470-ohm resistor
O Input signal is not connected to ground (DS21ESLCCG1, G2)
1.2 Input signal is connected to ground (DS215SLCCG4)
ACC-Pres WJ5 Groups 1, 2, and 4 - This jumper connects the input signal to ground through a 470-ohm resistor
O Input signal is not connected to ground (DS21 5SLCCG1, G2)
1.2 Input signal is connected to ground (DS21BSLCCG4)
S-39
5-4.16. Signal Processor Card (531X309SPC) 5-4.16.1. CONFIGURABLE HARDWARE. The SPC card
includes Berg-type jumpers, a DIP switch (earlier revi-
The optional 531X309SPC Signal Processor Card (SPC) sions of the SPC card included two DIP switches); and
processes I/O for the SDCC card. The SPC includes six pots, designated P1 through P6. The jumpers are
two identical encoder interface circuits: Encoder #1 and used for manufacturing test or customer options. Figure
Encoder #2, Each encoder interface circuit interface 5-20 shows the SPC card layout, including the locations
with 5 to 15 V incremental encoders or digital tachome- of the jumpers, DIP switch, and pots. Table 5-15 lists
ters to supply position or speed feedback, or reference and defines these items .
instrumentation to the drive.
Section 6-17 defines I/O points for the SPC card. Sec-
tion 7-6.8 defines SPC onboard testpoims.
:m 531 X309SPC SIGNAL PROCESS TP2UP

'
* E..
no
EZAB TPZDN
..
-1
0 l-'M
:EP
/E2AB m i_l¢.r1
>- n
N -
1-
FE r 1
mr1
1-
N
Ezaa . o JP1
I I
I I
_
/E2BB SW1 I I
10
D.
m
W
l
._
EZMB m
-I
- n JP7 H'
2
I
m
U 21 11.4
|I n-
/EmMa . 5
1 2 3 TP27 1 2 5 TP1UP
I
PF1 N 3
I I-
-' -|
I .123 JP10
1
.I l"i
I
II
QA
JPG JP2 TP1DN : :l ____,, 4
PF1 P -|
zI
!I
m
n
iI .
m P
PF2N .
'0 T 1Z SP1TP1
7
7PL
-.I
I
|-
PF2P
r _20
I .-
20
I
ID
19
-I
TXP
_
|
co
U 3
JP9 l"l
SPITPZ
TXN l"* i t
2~ Il_.4 SP2TP2
RXN
1TBE
-L _n _n
RXP N N N N N N
w ld us up u be
PS p5"' P4 , FE pi PI
TX RX ZRESP 2SCALE ZZERO 1RESP 1 SCALE TZERO
Figure 5-20. SPC Card Layout

Table 5- 75. SPC Card Acyustable Hardware
All JP1 Encoder #1 clock inhibit, this is used for test purposes only.
1 .2 Enables encoder #1 logic array (normal operation)
o Inhibits clock to PAL (manufacturing test only)
All JP2 Encoder #1 marker channel enable to be used for absolute position.
1.2 Inhibit marker. for incremental position or speed only
2.3 Enable marker, for absolute position instrumentation
All JP3 Encoder #2 clock inhibit, this is used for test purposes only.
1.2 Enables encoder #2 logic array (normal operation)
O inhibits clock to PAL (manufacturing test only)
1.2 Inhibit marker, for incremental position or speed only
AA-AF JP5 Select biasing of input PF1N for the analog channel SPA1 (VAR.2S6)
-
Jumpers JP5 JP7 and pots P1 P3 on the SPC card control hardware options for the process follower
analog channel SPA1 (VAR.256), input from PF1P and PF1N on 1TB. This circuit is a general purpose am-
plifier which can accept either current loop or voltage inputs. JP5, JP7, and P1 (1 ZERO) control the offset
added to the input; P2 (SCALE) controls the gain of the amplifier, CCW = more gain; P3 (1 RESP) controls
the response of the low pass filter of the amplifier, CCW = more filtering; and JP6 controls input burden-
ing when this circuit is used for current loop inputs. JP5 and JP7 allow several options for the 1 ZERO off-
set pot. The most common configurations are as follows:
JP5 ./p7 MODE
1.2 1.2 No offset trimming, ZERO is disabled
1.2 1.3 Positive trimming, CCW = more offset
1.2 1.4 Negative trimming, CCW = more offset
For example, to set-up a 4-20 mA current loop, assuming PF1P positive with respect to PF1N, set JP5
1.2, JP6 1.3, and JP7 1 .4. Apply a 4 mA input. and adjust P1 until VAR.256 is o. Then apply a 20 mA
input, and adjust P2 to give the desired full scale (the amplifier saturates at a maximum value of + 51 1
counts). Note that currents less than 4 mA will produce negative values down to -512 counts at
VAR.256. If this is undesirable, feed VAR.256 into a limit block before using it in the drive.
1.2 Bias to common
1.3 Add negative bias, o to -8 V do
1.4 Add positive bias, O to + 8 V do
1.5 Add no bias
AG-Pres JP5 Select gain of amplifier for the analog channel SPA1 (VAR.256)
- -
Jumpers JP5 JP7 and pots P1 P3 on the SPC card control hardware options for the process follower
analog channel SPA1 (VAR.256). input from PF1P and PF1N on 1TB. This circuit is a general purpose am-
plifier which can accept either current loop or voltage inputs. JP7 and PI (ZERO) control the offset added
to the input; JP5 and P2 (SCALE) control the gain of the amplifier, CW = more gain; P3 (1 RESP) controls
ing when this circuit is used for current loop inputs. The most common configurations are as follows:
PHP/PF1N
MODE JF5 JP6 JP7
1-5 mA 1 .2 1 .3 1.3
4-20 mA 1.2 1.3 1.3
1o-so mA 1.2 1.4 1.3
O-30 V 1.2 1 .2 1.3
For example, to set-up a 4-20 mA current loop. assuming PF1P positive with respect to PF1N:
- Set JP5 1.2 and JP6 1.3. Temporarily set JP7 to 1.2.
- Apply a 20 mA input. and adjust P2 until Test point SP1TP2 is 6.25 V.
- Set JP7 to 1.3.
- Adjust P1 until SP1TP2 is 5.0 V and VAR.256 is +500 counts.
- Apply a 4 mA input, and verify that SP1TP2 and VAR.256 are both O.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP1TP2 for the second step
-
should be adjusted to (5 x max)/lmax min) V instead of 6.25 V. Note that VAR.256 saturates at a maxi-
mum value of +51 1 counts when SP1TP2 exceeds 5 V. Also note that currents less than 4 mA produce
negative values down to -512 counts at VAR.256. If this is undesirable, feed VAR.256 into a limit block
before using it in the drive.
1.2 Normal gain
2.3 10:1 gain boost for max input < 5 mA or < 2 V
5-41
Table 5- 75. SPC Card Aafustab/e Hardware - Continued
AA-AF JP6 Select input burdening for PF1 P/PF1N of the analog channel SPA1 (see JP5)
1.2 No burden, for 2-30 V do input signals
1 .3 Burden for 4-20 mA current loop input
1.4 Burden for 10-50 mA current loop input
AG-Pres JP6 Select input burdening for PF1P/PF1 N of the analog channel SPA1 (see JP5)
1 .2 No burden, for 2-30 V de input signals
1 .3 Burden for 1-5 or 4-20 mA current loop input
AA-AF JP7 Select biasing of input PF1P for the analog channel SPA 1 (see JP5)
1.2 Bias to common
1 .3 Add positive bias, O to + 8 V do
1 .4 Add negative bias, O to -8 V do
1.5 Add no bias
AG-Pres JP7 Select zero offset for the analog channel SPA1 (see JP5). Use PI for fine trim.
1 .2 No offset
1.3 Negative offset
1.4 Positive offset
AA-AF JP8 Select biasing of input PF2N for the analog channel SPA2 (VAR.257)
-
Jumpers JP8 - JP1 O and pots P4 P6 on the SPC card control hardware options for the process follower
plifier which can accept either current loop or voltage inputs. JP8, JP1 O, and P4 (ZZERO) control the offset
added to the input; P5 (ZSCALE) controls the gain of the amplifier, CCW = more gain; P6 (2RESP) controls
ing when this circuit is used for current loop inputs. JPB and JP1O allow several options for the 2ZERO
offset pot. The most common configurations are as follows:
JP8 J'P1O MODE
1.2 1.2 No offset trimming, ZZERO is disabled
1.2 1 .3 Positive trimming, CCW = more offset
1.2 1 .4 Negative trimming, CCW = more offset
For example, to set up a 4-20 mA current loop. assuming PF2P positive with respect to PF2N, set JP8
1.2, JP9 1.3, and JP1O 1.4. Apply a 4 mA input, and adjust P4 until VAR.257 is O. Then apply a 20 mA
input, and adjust P5 to give the desired full scale (the amplifier saturates at a maximum value of + 51 1
counts). Note that currents less than 4 mA will produce negative values down to -512 counts at
VAR.257. If this is undesirable, feed VAR.257 into a limit block before using it in the drive.
1.2 Bias to common
1.3 Add negative bias, O to -8 V do
1 .4 Add positive bias, O to + 8 V do
1.5 Add no bias
AG-Pres JP8 Select gain of amplifier for the analog channel SPA2
Jumpers JP8 - JP1 O and pots P4 - P6 on the SPC card control hardware options for the process follower
plifier that can accept either current loop or voltage inputs. JP1 O and P4 (ZZERO) control the offset added
to the input; JP8 and P5 (2SCALE) control the gain of the amplifier, CW = more gain; P6 (ZRESP) controls
the response of the low pass filter of the amplifier, CCW = more filtering, and JP9 controls input burden-
PF2P/PF2N
MODE JP8 JP9 ./p10
1-5 mA 1 .2 1 .3 1 .3
4-20 mA 1.2 1.3 1.3
1o-50 mA 1.2 1.4 1.3
O-30 V 1.2 1.2 1.3
For example, to set up a 1-5 mA current loop, assuming PF2P positive with respect to PF2N:
- Set JP8 to 1.2 and JP9 to 1.3. Temporarily set JP1 O to 1.2.
- Apply a 5 mA input, and adjust P5 until testpoint SP2TP2 is 6.25 V.
- Set JP1O to 1.3.
- Adjust P4 until SP2TP2 is 5.0 V, and VAR.257 is +500 counts.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP2TP2 for the second step
should be adjusted to 5 x max I (max - min) V instead of 6.25 V. Note that VAR.257 saturates at a maxi-
mum value of + 5 1 1 counts when SP2TP2 exceeds 5 V . Also note that currents less than 1 mA produce
negative values down to -512 counts at VAR.257. If this is undesirable, feed VAR.257 into a limit block
before using it in the drive.
1.2 Normal gain
2.3 10:1 gain boost for max input < 5 mA or < 2V
5-42
Table 5- 75. SPC Card Aoiustable Hardware - Continued
I Revision Name Description
AA-AF JP9 Select input burdening for PF2P/PF2N of the analog channel SPA2 (see JP8)
AG-Pres JP9 Select input burdening for PF2P/PF2N of the analog channel SPA2 (see JP8)
1.3 Burden for 1-5 or 4-20 mA current loop input
AA-AF JPG O Select biasing of input PF2P for the analog channel SPA2 (see JP8)
1.2 Bias to common
1.3 Add positive bias, O to + 8 V do
1.4 Add negative bias, O to -8 V do
1.5 Add no bias 1
AG-Pres JP1O Select biasing of input PF2P for the analog channel SPA2 (see JP8). Use PI for fine trim.
1.2 No offset
1.3 Negative offset
1.4 Positive offset
AA-AF SW1-1, Selects input attenuation resistors for channel A of encoder #1

SW1-2 Input attenuation resistors for channel A of encoder #1 can be selected as follows
O (All off) 15 volt encoder interface
1 (1 on) 5 volt encoder interface
2 12 on) 5 volt encoder (alternate setting)
3 II ,2 on) External attenuation
AG-Pres SW1-1 Selects input attenuation resistors for channel A of encoder #1

Input attenuation resistors for channel A of encoder #1 can be selected as follows
o (Of"f) 15 volt encoder interface
1 (On) 5 volt encoder interface
AG-Pres SW1 -2 Selects input attenuation resistors for channel B of encoder #1

Input attenuation resistors for channel B of encoder #1 can be selected as follows
O (Off) 15 volt encoder interface
AA AF SW1 -3, Selects input attenuation resistors for channel B of encoder #1

SW1 -4 Input attenuation resistors for channel B of encoder #1 can be selected as follows:
2 (4 on) 5 volt encoder (alternate setting)
3 (3.4 on) External attenuation
AG-Pres SWF -3 Selects input attenuation resistors for marker channel of encoder #1 __._.~
Input attenuation resistors for marker channel of encoder #1 can be selected as follows
AG-Pres SW1 -4 Selects input attenuation resistors for channel A of encoder #2

AA-AF SW1-5, Selects input attenuation resistors for marker channel of encoder #1
SW1-6 Input attenuation resistors for marker channel of encoder #1 can be selected as follows
O (Au off) 15 volt encoder interface
AG-Pres SW1 -5 Selects input attenuation resistors for channel B of encoder # 2

0 (Off) 15 volt encoder interface
5-43
Table 5- 75. SPC Card Acyustable Hardware - Continued
AG-Pres SW1 -6 Selects input attenuation resistors for marker channel of encoder #2
Input attenuation resistors for marker channel of encoder # 2 can be selected as follows
O (Of'f) 15 volt encoder interface
AG-Pres SW1-7 Selects input attenuation resistor for serial channel RXP/RXN (1TB-13)
RXP and RXN (1TB-13, 14) may be used either as the input from a BEI serial absolute encoder, or as the
receiver input of a full-duplex RS-422 serial channel to the motor control processor.
O (Off) 15 volt input (Serial encoder interface)
1 (On) 5 volt input (RS-422 serial communication)
AA-AF swz-1 | Selects input attenuation resistors for channel A of encoder #2

SW2-2 Input attenuation resistors for channel A of encoder #2 can be selected as follows
3 (1 ,2 on) External attenuation
AA-AF SW2-3, Selects input attenuation resistors for channel B of encoder # 2

SW2-4 Input attenuation resistors for channel B of encoder #2 can be selected as follows
AA-AF SW2-5, Selects input attenuation resistors for marker channel of encoder #2
SW2-6 Input attenuation resistors for marker channel of encoder #2 can be selected as follows
3 (5,6 on) External attenuation
All PI Full CCW = 0700. Provides zero adjust of SPA1 (see JP5).
(1 zERo)
All P2 Full CCW = 0700. Provides gain adjust of SPA1 (see JP5).
(1 SCALE)
All P3 Full CCW = 0700. Adjusts response of SPA1, from 1 to 1coo msec.
(1 RESP) Response #1 (P3) adjusts the response of analog channel #1 (SPA1 ). The response can be adjusted from 1
to 1coo msec.
All P4 Full CCW = 0700. Provides zero adjust of SPA2 (see JP8).
(ZZERO)
(2SCALEI
All P6 Full CCW = 0700. Adjusts response of SPA2, from 1 to 1000 msec.
(2RESP) Response # 2 (P6) adjusts the response of analog channel #2 (SPA2). The response can be adjusted from 1
to 1 coo msec.
5-44
5-4.17. Multi-bridge Signal Processing Card coded by PAL (programmable array logic) circuits to
(DS200SPCB) produce up/down and marker pulse output signals.
These output signals are fed to the SDCC via 7PL. The
The DS200SPCB Multi-bridge Signal Processing Card PAL inputs may be 5 V or 15 V differential signals.
(SPCB) provides an interface between dmc SDCC card
and the MBI-IA boards in multi-bridge drive systems . 5-4.17.2. PROCESS CONTROL SIGNAL INPUTS. The
The SPCB card performs the following functions: analog process control input channels SP1 and SP2 are
operational amplifier gain circuits. These circuits con-
• Processing encoder feedback signals to the SDCC vert 1-5 mA, 10-50 mA, or 2-30 V process control
input signals into -5 to + 15 V signals that are fed to the
Converting analog process control voltage/current SDCC.
signals to voltage signals (i5 V), and transmitting
the resulting voltage signals to the SDCC 5-4.17.3. CONFIGURABLE HARDWARE. The SPCB
card includes a DIP switch, designated SW1, Berg-type
Providing fiber-optic transmit and receive capabili- jumpers, and six pots, designated P1 through P6.
ties for bridge-to-bridge communications and a fi-
ber-optic mode transmission for master-master DIP switch SWf is used to configure the encoder inputs
systems for 5 or 15 V signals. Jumpers JP5 through IPl0 are
used to select the gain of the analog input channels
based upon the type of input process control signal. Pots
Transmitting and receiving synchronization signals,
P2 (ISCALE) and P5 (ZSCALE) are used to further
either through an isolated DLAN hardware archi-
adjust the gain of channel SP1 and SP2, respectively.
tecture or through Fiber-optic sync input and output
Pots Pl (IZERO) and P4 (ZZERO) are used to zero the
channels
input channels. Pots P3 (RESP) and P6 (2RESP) are
used to adjust the response of the input channels from 1
Section 6-17 defines I/O points for the SPCB card. Sec-
tion 7-6.9 de6nes SPCB onboard testpoints . to 1000 msec .
1 Figure 5-21 shows the layout of the SPCB board, in-
5-4.17.1. ENCODER FOLLOWER CIRCUITS. The [WO
cluding the locations of the jumpers, switch, and pots.
encoder follower circtUts include 3-channel opto-
Table 5-16 lists and defines these items.
coupled differential interfaces for channel A, channel B,
and marker pulse inputs from an incremental encoder or
digit tachometer. The input signals are de-
5-45
JP1 7PL 5P1TP1 SP1TP2
D V
\_ A
I 20 C] E]
19 SP2TP1 re
I I I a
EI TP2UP E1 U; F-
no 7P2Z 11 3
1. 3 o
o.
r-
EJ z
'E
°'n
<I 2:
,_
r »
cs
CD
a
1:
CJ
1 5 :
of
LJ El E] re D
P
2
CL JP2
LO 5
c: I
I
I
r'1 3
I i
1 3
a
CD 1? "Lu
co 2 :L
':
2
2
°°m F
of 1 1
CO
11 E5 g
"up
°Lr4
2 cu
.1 . .. 3--
s
E2AB
:_.-I
géééééé SPRS SPSYO
2
3'
UP
=a Co
1 3
/E2AB f _.
g
..»
JP11 £1 E] ¢%
laN
_ SPSYN 2
EWBB
_
N 1
-4
E] JPG .
go g 2 r'1 5 r°1 5 JP7
/Eze# I I 1 I JP5 2 I | _ 2 I |_
t
..
3 .
EZMB' .a
-4
-|
|
I1 2
:J3 I l_]4
JP9 Jp10
1-34
~»
m
CD
re 5 FE 3
/Ezmw *I
.. In
Ra
JPB _ 2 I l _ I |_
I I
3W
PF1 N 1_3 _j 4 1_1
1 2 3 2 1 4
PF1 P l
1SPL
__a 1 Ll
I r I \ I
PF2N zo
IB
PF2P |
|. I
| | I 11
I I
-1 DCOM
SYTB
1
B G B II I
\JIT ID
vi
:a
5 :n
D
2
:
ouT :
D
IN 8
:>
RX Rx
MODE SYNCH CDMM
Figure 5-27. SPCB Card Layout
Table 5- 16. SPCB Card Aayustable Hardware
All JP1 Encoder #1 and #2 clock inhibit, this is used for test purposes only.
1.2 Enables encoder #1 logic array (normal operation)
O inhibits clock to PAL (manufacturing test only)
All JP5 Select gain of amplifier for the analog channel SPA1 (VAR.256)
- -
Jumpers JP5 JP7 and pots P1 P3 on the SPCB card control hardware options for the process follower
plifier which can accept either current loop or voltage inputs. JP7 and P1 (1 ZERO) control the offset added
to the input; JP5 and P2 (1 SCALE) control the gain of the amplifier, CW = more gain; P3 (1 RESP) controls
PF1P/PF1N MODE JP5 JP6 JP7
1-5 mA 1 .2 1 .3 1 .s
4-20 mA 1.2 1.3 1.3
10-50 mA 1.2 1.4 1.3
O-30 V 1.2 1.2 1.3
5-46
Table 5-76. SPCB Card Aayustable Hardware - Continued
For example, to set-up a 4-20 mA current loop, assuming PF1P positive with respect to PF1 N:
- Set JP5 1.2 and JP6 1.3. Temporarily set JP7 to 1.2.
- Set JP7 to 1.3.
- Adjust P1 until SP1TP2 is 5.0 V and VAR.256 is +500 counts.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP1TP2 for the second
step should be adjusted to (5 X max)/(max -min) v instead of 6.25 V. Note that VAR.256 saturates at a
maximum value of +511 counts when SP1TP2 exceeds 5 V. Also note that currents less than 4 mA
produce negative values down to -512 counts at VAR.256. If this is undesirable, feed VAR.256 into a
limit block before using it in the drive.
1.2 Normal gain
2.3 10'1 gain boost for max input < 5 mA or < 2 V
All JP6 Select input burdening for PF1P/PF1N of the analog channel SPA1 (see JP5)
All JP7 Select zero offset for the analog channel SPA1 (see JP5). Use PI for fine trim .
1.2 No offset
1.3 Negative offset
1.4 Positive offset
All JP8 Select gain of amplifier for the analog channel SPA2 (VAR.257)
Jumpers JP8 - JP1O and pots P4 - P6 on the SPCB card control hardware options for the process fol-
lower analog channel SPA2 lVAR.257), input from PF2P and PF2N on 1TB. This circuit is a general pur-
pose amplifier which can accept either current loop or voltage inputs. JP1O and P4 (2ZERO) control the
offset added to the input; JP8 and P5 (2SCALE) control the gain of the amplifier, CW = more gain; P6
(2RESP) controls the response of the low pass filter of the amplifier, CCW = more filtering; and JP9
controls input burdening when this circuit is used for current loop inputs. The most common configura-
tions are as follows:
PF2P/FF2N MODE JP8 JP9 JP7O
1-5 mA 1.2 1.3 1.3
4-20 mA 1.2 1 .a 1.3
1O-50 mA 1 .2 1 .4 1.3
O-30 V 1.2 1 .2 1.3
For example, to set up a 1-5 mA current loop, assuming PF2P positive with respect to PF2N:
- Set JP8 to 1.2 and JP9 to 1.3. Temporarily set JP1O to 1.2.
-
-
_ Set JP1O to 1.3.
Adjust P4 until SP2TP2 is 5.0 v, and VAR.257 is +500 counts.
Apply a 1 mA input, and verify that SP2TP2 and VAR.257 are both o.
If the ratio between the maximum and minimum inputs is not 5, the voltage at SP2TP2 for the second
-
step should be adjusted to 5 x max / (max min) v instead of 6.25 V. Note that VAR.2.57 saturates at a
maximum value of + 511 counts when SP2TP2 exceeds 5 V. Also note that currents less than 1 mA
produce negative values down to -512 counts at VAR.257. If this is undesirable, feed VAR.257 into a
limit block before using it in the drive.
1.2 Normal gain
2.3 10:1 gain boost for max input < 5 mA or < 2 V
All JP9 Select input burdening for PF2P/PF2N of the analog channel SPA2 (see JP8)
All JP10 Select zero offset for the analog channel SPA2 (see JP8). Use P4 for fine trim .
1.2 No offset
1.3 Negative offset
1.4 Positive offset
ADA-Pres JP11 Listen to fiber-optic or hardware. (hardwired) sync signal

Jumper selects whether to listen to the fiber-optic channel or to the hardware channel for the synchroni-
zation signal.
1.2 Listen to hardware sync channel
2.3 Listen to fiber optic sync channel
5-47
Table 5- 76. SPCB Card Aciustable Hardware - Continued

ADA-Pres JP12 Enable or disable master sync derived from SDCC

Enable or disable master sync signal derived from SDCC. For DCZOOO DRVTYP=5, setting 1.2 must
be used for follower bridges. 1 .2 restricts the bridge to be a sync "listener." If drive is a master this
jumper must be 2.3. Setting 2.3 allows the synchronization signal to be transmitted on the fiber-optic
sync channel or the hardware (hardwired) sync channel. For DC2000 DRVTYP=85 multibridge, this
circuitry is not used, and JP12 may be left in either position.
1 .2 Dis ble master sync input (Drive is a multi-bridge FOLLOWER)
2.3 Enable master sync input (Drive is a multi-bridge MASTER)
All SW1-1 Selects input attenuation resistors for channel A of encoder #1

o (Off) 15 volt encoder interface
All SW1-2 Selects input attenuation resistors for channel B of encoder # 1

O (Off) 1 5 volt encoder interface
AG-PreS SW1-3 Selects input attenuation resistors for marker channel of encoder # 1
All SW1 -4 Selects input attenuation resistors for channel A of encoder # 2

All SW1 -5 Selects input attenuation resistors for channel B of encoder #2

Input attenuation resistors for channel B of encoder # 2 can be selected as follows
All sw1-6 Selects input attenuation resistors for marker channel of encoder #2
All SW1 -7 Spare switch, not used.
(ZERO)
Ali P2 Full CCW = 0700. Provides gain adjust of SPA1 (see JP5).
(1 SCALE)
(1 rEsp) Response #1 (P3) adjusts the response of analog channel # t (SPA1). The response can be adjusted
from 1 to 1000 msec.
l2zERo)
(ZSCALE)
(2.RESP) Response #2 (P6) adjusts the response of analog channel #2 (SPA2). The response can be adjusted
from 1 to 1000 msec.
5.48
DC2000 Digital Adjustable Speed Drive
5-4.18. Basic Drive Terminal Board (DSZOOSTBA) (
JP24
HLI02 3
I
The DS200STBA Basic Drive Terminal Board (STBA)
contains customer connection points for most signal-
2-""'
W
of
or
level I/O. The STBA also `mc1udes many of the custom- g noU
`ld9
1;
.
'
izing jumpers required in the system, and some passive
interface circuits.
I
"2 c-l:1
|\
nm-
_ UE
in _no
pa
:L :I
ldv
'7
z
al-In
I
WARNING _
P7
2 c.1::
¢
¢IZl-J[
n m -
~r
JI]
J JP15_
m .-Ra
JPI4
N
D. c::1
Potentially hazardous voltages are present in 1
nl-I N
'|:
I
the STBA board. Ensure that power is off
o
before touching the board or any connected m sg
1
3
n N 1
circuits.
1-
JP4
JP5
1
2
2 . - Hv
2
4
2PL
|
The STBA board connects to the SDCC via 6PL and o.
1
E
pg 1-1 N
8PL; to the DCFB or SDCI via 4PL, to the DCFB or

SDCI, SDCC, and SLCC boards via 2pL, and to the
LZdl'
u
1]»z
I Ip
I
customer/system via COMPL and terminal board
Y
L
oldr
l!dl°'
points. Figure 5-22 shows the layout of the STBA, in-
cluding connector locations.
z l::l::l
v' I l l
acer
The STBA board's STBA connector contains 60 termi-
I
nuA2
DA1
nal board points in two rows of screw-type terminals . I I
COM
The terminals are numbered sequentially, with odd i n
ml I
:
n N
numbers in the top row and even numbers in the bottom D.
-> I
LLJ
E
u
COMPL
.-
I I
2
row. The board's STBK connector contains three termi- 4-wma
nal board points numbered 62, 64, and 66. The terminal I _
board points provide the interfaces described in the n
ss l
:no _
C
l::l
l"l LE |.
I I ax I
following sections. se I
Qzdr
:we
ES I
new
LE I
L
to
Section 6-18 defines IlO points for the STBA board. NBCIJ
so F
veld
mo l_
lZJJP;S5
Section 7-6.10 defines STBA onboard tesrpoints. "in

I I
L*
t.*>1_-
"0 NB!
J
o.
I
-.r Co I
d:!3!l
C11PL
5-4.18.1. POWER SUPPLIES. The STBA board pro- L+ |

T '1
f1 "
Sd
so I
"u.
vides the following power outputs for external use: zum

2
L: I
C15PL
:pa
is: :
Regulated +5 V do and _+15 V de, each with a cur- fig N
Q8?
'II z
I
an
nwza
C17PL
Le '___
'it
rent capacity of 250 mA. US:-1

sz I
3N1'H _
2
I
LZ1'
NO
:we L
_
20
so I
19
Unregulated 124 V de, each with a current capacity

9ZdF
outs
cz |
us
of 500 mA LZ I
sum L
S
l
BPL
ELl_
QEZCD [ 2 2
sis
Ll I
120 V ac, with a current capacity of 0.4 A
Zldl'
1-1:>
su-
:na |-
Ell
L Q
zla
H
Hardware jumpers are used to balance encoder loads
tildI'
LID
sr
among the +5 and i-15 v do supplies. woo
L
B03
I
L
g |
N F YO3N u
o \
5-4.18.2. ENCODER INTERFACE. The STBA board V03

L . L
includes a differential A-quad-B encoder interface that

JPI 7
~lil =>u
can be connected to the system. Jumpers are used to

2
configure the interface for 5 V or 15 V encoders.

Figure 5-22. STBA Board Layout
5-4.18.3. RS-232C INTERFACE. Connector COMPL 5-4.18.5. RELAY OUTPUTS. The STBA board pro-
included on the STBA board provides an RS-232C se- vides seven relays, each with a contact rating of 120 v,
rial link for use with the ST2000 Toolldt (see 0.5 A. Two of these relays are controlled by a 24 V do
GEH-5860 for information) or Drive Configurator, input, one relay is controlled by a 115 V ac input.
LynxOS Version (see GEH-6203 for information).
The other four relays can be configured via hardware
5-4.18.4. CONFIGURABLE CONTROL INPUTS. The jumpers to be controlled via 115 V ac inputs or via 24
STBA board provides eight configurable control inputs V do software-controlled inputs. One set of contacts for
(CI1 through CI8), which enable the customer to inter- each of these relays can be directed via jumper to a
face to discrete (24 V do) signals. These inputs have a digital control input.
27 k§2 input impedance and 2 ms noise filtering .
The STBA board also provides form C contacts from
Hardware jumpers bias unconnected general-purpose the MA contactor pilot relay on the DCFB or SDCI
inputs to +24 or -24 V de, depending upon whether board. These contacts are rated at 120 V ac, 2 A.
positive or negative logic is used.
5-4.18.6. CONFIGURABLE HARDWARE. The STBA
Typically, inputs CI2, CI3, CI4, and CI6 monitor the board includes Berg-type jumpers used for manufactur-
stars of relays K2, K3, K4, and K6, respectively. Us- ing test and customer options. Figure 5-22 shows the
mg
' jumpers JP28, ]P31, JP35, and JP38, however, locations of the jumpers. Table 5-17 lists and defines
these inputs can be connected to customer input termi- these items.
nals to monitor external signals. Control inputs CI1,
CI5, CI7, and C18 are available at the STBA terminal
board for customer wiring .
Table 5- 77. STBA Board Acyustab/e Hardware
All JP4 Swap RS-232C RxD and TxD data lines, COMPL pins 2 and 3 (see also JP5)
Note that many PCs can be jumpered to either the DCE or DTE configuration, and many cables are wired
with pins 2 and 3 interchanged. If communication is not established with JP4 and JP5 in the default posi-
tion, the alternate position may be necessary.
1 .2 DCE mode for PC/term interface. Drive transmits on pin 3.
1 .3 DTE mode for modem interface. Drive transmits on pin 2.
All JP5 Swap RS-232C RXD and TxD data lines, COMPL pins 2 and 3 (see also JP4)
3.4 DCE mode for PC/term interface. Drive transmits on pin 3.
2.4 DTE mode for modem interface. Drive transmits on pin 2.
All JP1 O RF24 polarity for digital control inputs (see also JP1 1 l
In the negative logic position, control inputs C11-C18 must be pulled down to generate a TRUE Boolean logic
input variable. EE.1 .4 must be set consistent with this jumper.
1 .2 RF24 = -24 V (negative logic).
1.3 RF24 = + 2 4 V (positive logic).
All JP1 1 RF24 polarity for digital control inputs (see also JP1 O)
3.4 RF24 = -24 V (negative logic).
2.4 RF24 = +24 v (positive logic).
All JP12 Voltage to encoder supply (EOV1, EOV2)

1.2 EOV1 = +15 V do
2.3 EOV 1 = + 5 v do
5-50
Table 5-17. ST8A Board Aayusrabm Hardware - Continued
All JP14 Connects CPH power to panel control circuit

A generic control circuit formed with Y19PL, Y2OPL, Y21 PL, K5 (SW control) and K28 (hard-wired control)
contacts. The circuit is jumper configured to be dry or powered.
I-JP25"-1
I I Y20PL Y21PL
3 2 | K5 | K28 ext contact 1 load
CPH o A | II I
II '<"!I-°>> <<"'( ) ' -
1 I
JP14 o I
I
I
JP15 I
3 I
CPN O
JP14 MUST be in the same position as JPt 5 to complete the circuit.

1.2 Circuit unpowered
2.3 CPH powering circuit
All JP15 Connects CPN ( CPH return) to panel device control circuit (see JP14)
1.2 Circuit unpowered
2.3 CPN in circuit
All JP17 Encoder o optically isolated receiver voltage drive level (EOA)
1.2 15 v do
2.3 5 V do
All JP18 Encoder O optically isolated receiver voltage drive level (EOB)
1.2 15 v de
2.3 5 V de
All JP24 Enable 4-20 mA current loop input to the feedback VCO lFDBP, FDBN)
When the current loop input mode is enabled (position 2.3). a 500-ohm burden resistor is inserted, yielding
10 volts at 20 mA.
1.2 Voltage input mode ( + 10/-10 v do)
2.3 Current loop input mode (4-20 mA)
All JP25 K5 interlock in panel device control circuit

A K5 contact is in the generic control circuit formed with Y19PL, Y2OPL, & Y21 PL. The circuit is jumper
configured to be dry or powered (see JP14 & JP15). This circuit is a series string of K5 (SW control) and
K28 (hard-wired control) contacts. JP25 in position 2.3 bypasses K5 control, and K28 control is bypassed
by jumpering pins 1 & 2 of Y19PL. Y21 PL is the output pair, and Y2OPL is a connector input for additional
external interlocking into the circuit.
r-JP25-1
| | Y20PL Y21PL
| K5 1 K28 ext contact 1 load
H | II | I1 -'<--I l-->> /<___l )-- l
2 I
N f<----.....-... |
1 .2 K5 in circuit
2.3 K5 contact bypassed
All JP26 K2 coil control from 1 15 V ac input (see JP27)

JP26 & JP27 must both be in the 1.2 position to operate K2 as a 115 V ac input. If software controlled,
JP26 must be 3.4, and JP27 MUST be 2.3. Other combinations will result in drive misoperation.
1.2 K2 coil from 1 15 V ac source, JP27 must be 1.2
3.4 K2 coil from software (24 V de). JP27 must be 2.3
All JP27 K2 coil control from 115 V ac input (see JP26)

1.2 K2 coil from 115 V ac source, JP26 must be 1.2
2.3 K2 coil from software (24 V do), JP26 must be 3.4
All JP28 Jumper K2 contact (status) to CI2

1.2 K2 contact to CI2
2.3 CI2 connected to STBA terminal board point 1 1
S-51
Table 5-77. S'T$A Board Acfustab/e Hardware - Continued

JP29 & JP3O must both be in the t . 2 position to operate K3 as a 1 15 V ac input. If software controlled,
JP29 must be 3.4, and JP3O MUST be 2.3. Other combinations will result in drive misoperation.
1.2 K3 coil from 1 15 V ac source, JP3O must be 1.2
3.4 K3 coil from software (24 v do) , JP30 must be 2.3
All JP3O K3 coil control from 115 V ac input (see JP29)

All JP31 Jumper K3 contact (status) to CIS (see JP32)

1.2 K3 contact to Cl3
2.3 K3 contact connected to STBA terminal board point 23
All JP32 Wire K3 contact to RF24 (see JP31 )

JP31 & JP32 must be in the same position for circuits to operate correctly.
1.2 K3 contact to RF24
2.3 K3 contact connected to STBA terminal board point 2O

JP33 & JP34 must both be in the 1.2 position to operate K4 as a 1 15 V ac input. If software controlled,
JP33 must be 3.4, and JP34 MUST be 2.3. Other combinations will result in drive misoperation.
3.4 K4 coil from software (24 V do) , JP34 must be 2.3

1.2 K4 coil from 1 15 V ac source, JP33 must be 1.2
All JP35 Jumper K4 contact (status) to CI4

1 .2 K4 contact to CI4
2.3 CI4 connected to STBA terminal board point 1 5
All JP36 K6 coil control from 1 15 v ac input (see JP37)

JP36 & JP37 must both be in the 1.2 position to operate K6 as a 115 V ac input. If software controlled,
JP36 must be 3.4, and JP3l7 MUST be 2.3. Other combinations will result in drive misoperation.
3.4 K6 coil from software (24 V do) JP37 must be 2.3

2.3 K6 coil from software (24 V do) , JP36 must be 3.4
All JP38 Jumper K6 contact (status) to C16

1.2 K6 contact to CI6
2.3 Cl6 connected to STBA terminal board point 1 9
All JP39 K3 contact in series with K28 for CTLN1 & 2

1.2 K3 contact in CTLN1 & 2 string with K28
2.3 K3 interlock to CTLN bypassed
5-52
CHAPTER 6
I/O DEFINITIONS
6-1. INTRODUCTION -
User connections These CODDCCIOIS me located 011
boards in the drive. They carry I/O between these
This chapter lists and defines I/O connector points and boards and user connections outside the DC2000
LEDs for the DC2000 Adjustable Speed Drive. The drive.
connectors include plug-in cable type, terminal board
type, and stab terminals located on the printed wiring
boards. 6-2.2. Terminal Board Connectors
This chapter is organized alphabetically by board name: This type of connector is identified by a IB in its name.
section 6-4 covers the ACNA, section 6-5, the CDBA, It provides a connection point for individual wires that
section 6-6, the CPCA, and so 011. Each section con- carry signals or power. This I/O can be between a
tains tables of I/O definitions for each connector, stab board and components within or outside the drive. The
terminal, and LED on that board. The board layout fig- wires are secured in the terminal board by tightening
ures in Chapter 5 show the locations of these items on screws at each connection.
the boards.
6-2.3. Stab Connections (Stabs)

6-2. TYPES OF CONNECTORS
This type of COIIIICCIOI is a wide metal post that secures
6-2.1. Plug-in Connectors one side of a removable wire jumper. It provides OP-
tions for configuring drive I/O, such as power require-
The type of connector, typically identified by PL in its ments .
name, mates with a cable that plugs into it. The cable
carries signal and power UO within the drive and exter-
nally to customer equipment. Plug-in connectors pro- 6-3. LED AND NEON INDICATORS
vide three types of connections:
The DC2000 drive includes LEDs Gight-emitting di-
Internal board-to-board connections - Carry I/O be- odes) and/or neon lamps on some boards as indicators
tween boards in the drive. The connector typically of a board or drive condition. The indicators are located
has the same name and spinout assignments on each on I/O paths, and mm on or off with the signal condi-
board. tion.
Board-to-component connections - Carry I/O between

boards and components (for example, transformers
or semiconductors) within the drive. These connec-
tors are commonly 2-pin plugs.
6-1
6-4. ACNA BOARD I/O
This section defines I/O points for the ACNA board. Figure 5-3 shows connector locations on the board.
Table 6- 7. Connector ARCPL,

I/O Between ACNA Board and SLCC Card
Pin No. Nomenclature Description
1 TXA- Transmitting and receiving signals, channel A.
2 TXA+ Transmitting and receiving signals, channel A.
3 TXB- Transmitting and receiving signals, channel B.
4 TXB + Transmitting and receiving signals. channel B.
5 P5 +5 V do power.
6 DCOM Power digital common.
7 TXB Transmitting signal selected by JP15 on the SLCC card as isolated DLAN
circuit or RS-422.
8 TXA Receiving signal selected by JP15 on the SLCC card as isolated DLAN
circuit or RS-422.
J
6-2
6-5. CDBA BOARD I/O
This section defines I/O points for the CDBA board. Figure 5-4 shows connector locations on the board.
Table 6-2. Connector 1T8,

CDBA Board Contactor Control Connections
Pin No. Description
1 Coil Driver Series Interlock Input.

1TB-1 and 1 TB-2 provide a connection point for an interlock to be wired in series
with the coil driving signal from MACPL. MACPL is intended for factory wiring
only.
2 Coil Driver Series Interlock Input (see 1TB-1 ).
3 Contactor Normally Open Interlock.

1TB-3,1TB~4 and 1TB7,1TB-8 are normally open auxiliary contacts from the MD
contactor.
4 Contactor Normally Open Interlock (see 1TB-3).
5 Contactor Normally Closed Interlock.

1TB-5,1TB-6 and 1TB-9,1TB-10 are normally closed auxiliary contacts from the
MD contactor. The normally closed contact, 1TB-9,1TB»10, is internally wired to
the CDBA control circuitry, and should not be used.
6 Contactor Normally Closed Interlock (see 1TB-5).
11 Driver Card Input Power - CPH.

Hot (or + ) input power for the CDBA board. 1TB-11 and 1TB-12 are electrically
parallel with RMPL pins 1 and 2 respectively. RMPL is intended for factory daisy
chain wiring of control power.
12 -
Driver Card Input Power CPN.
Neutral (or -l input power for the CDBA board. 1TB-t 1 and 1TB-12 are electrically
chain wiring of control power.
6-3
6-6. CPCA CARD I/O
This section defines I/O points for the CPCA card. Figure 5-6 shows connector locations OH the card.
Table 6-3. Connector ITB,

CPCA Card Contactor Control Connections
Pin No. Description
1 Coil Driver Series Interlock Input.

1TB-1 and 1TB-2 provide a connection point for an interlock to be wired in series
with the coil driving signal from MACPL. MACPL is intended for factory wiring
only. PSP and PSN provide test points for coil control circuit integrity.
2 Coil Driver Series Interlock Input (see 1TB-1).
3 Contactor Normally Open Interlock.

1TB-3,1TB-4 and 1TB7,1TB-8 are normally open auxiliary contacts from the MD
contactor.
5 Contactor Normally Closed Interlock.

1TB-5,1TB-6 and 1TB-9,1TB-10 are normally closed auxiliary contacts from the
MD contactor.
11 CPCA Power + Input, CPH.

Hot (or + } input power for the CPCA card. 1TB-1 1 and 1TB-12 are electrically
chain wiring of control power. CPH and CPN provide test points for power circuit
integrity.
12 CPCA Power - input, CPN.

Neutral (or -) input power for the CPCA card. 1TB-1 1 and 1TB-12 are electrically
parallel with RMPL pins 1 and 2 respectively. RMPL is intended tor factory daisy
chain wiring of control power. CPH and CPN provide test points for power circuit
integrity.
6-4
DC2000 Digit Acliustable Speed Drive GEH-6005
6-7. DCFB AND SDCI BOARD IIO
Depending upon application requirements, the DC2000 drive contains either a DCFB or SDCI board. This section de-
fines I/O points, LEDs, and neon lamps for these boards. Figure 5-6 shows connector, LED, and neon lamp locations on
the DCFB board, Figure 5-16 shows the SDCI board.
Table 6-4. Connector 1PL,

//O Between DCF8 Board and SDCC Card
1 FANO ACCT current.

2-5 Not connected.
6 FAN5 Motor voltage #2 - analog output.
7 HG5 FlN5 counter control.
8 HNO Do armature shunt #1 VCO output.
9 HN1 Motor field current shunt #1 VCO output.
10 HN2 Do armature shunt #2 VCO output.
11 HN4 V1-V2 ac line voltage feedback.
12 HN5 V1-V3 ac line voltage feedback.
13 HN6 Do bridge voltage feedback.
14 _ . _ -
Not connected.
15 HG4 FIN4 counter control.
16 /ENREV Enable reverse armature SCRs.
17 /ENFVVD Enable forward armature SCRs.
18 /FF2 Field #2 SCR firing.
19 /FF1 Field #1 SCR firing.
20 A14R A14R cell decode signal.
23 _-___
Not connected.
24 A14F A14F cell decode signal.
27 SCRTST Short circuit SCR test mode select line.
28 xm XlLINX programmed (0 = Yes: 1 = No).
29 SYNC Ac line synchronization signal.
30 . - ;
Not connected.
31 /RST1 System reset.
32 FLD1 CTRL Field #1 control enable.
33 FLDZCTRL Field #2 control enable.
34 MAC 1 MA contactor drive.
35 MAC2 MD contactor #1 drive.
36 mAcs MD contactor #2 drive.
37 VFBB Dc voltage feedback testpoint.
38 DTYPE Drive type (1.8 - 2.2 v do for DC2000 drive).
39 HN7 Motor voltage feedback VCO output.
40 HN8 Shunt #2 VCO output.
6-5
Table 6-5. Connector cpL,

I/O Between SDC/ 8oard and SDCC Card
It
1 ms Line 3 ACCT current.

2 m1 Line 1 ACCT current.
3, 4 Not connected.
5 VMAG Ac voltage magnitude.
6 VSEQ Ac voltage sequence.
8 IDC Dc armature shunt VCO output.
9 W Field shunt VCO output.
1 0 - 12 Not connected.
13 VA Dc armature voltage VCO output.
14 SYOSC 25 kHz firing oscillator.
16 IENREV Enable reverse armature SCRs.
17 IENFVVD Enable forward armature SCRs.
18 IPU Initial firing pulse width.
19 /FLDF Field SCR firing.
21 A25R A25Fl cell decode signal.
23 ....... .I-
Not connected.
27 SCRTST Short circuit SCR test mode select line.
28 Not connected.
29 SYNC Ac line synchronization signal (V2-V3 zero crossing).
30 FHH Discontinuous current indicator.
31 /RST1 System reset.
32 DFPC Delayed firing power control.
33 ENFLD Field control enable.
34 MAC MA contactor drive.
35 MDC MD contactor drive.
36 l1~ -_ l1» 41»
Not connected.
37 VFBB Dc voltage feedback testpoint.
38 DTYPE Drive type (1 .8 - 2.2 V do for DC2000 drive).
39, 40 Not connected.
6-6

I/O Between DCF8 or SDC/ 8oard and NTB/3T8 or STBA, SDCC, and SLCC Boards
l
PI n NO Nomenclature Description
1 IPSEN Power supply enable (active low).

2 -15V -15 V do, i5%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
3 + 15V + 1 5 V do, :t5%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
4 DCOM Drive common to the NTBl3TB or STBA, SDCC, and SLCC boards.
5 6 +5V + 5 V do, ¢5%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
7 DCOM Drive common to the NTB/3TB or STBA, SDCC, and SLCC boards.
8 -24V -24 V do, i20%, to the NTB/3TB or STBA, SDCC, and SLCC boards.
9 + 24V + 24 V do, i-20%, to the NTB/3TB or STBA, SDCC, and SLCC
boards.

//O Between DCFB or SDC/ Board and NTB/STB or STBA Board
Pin no. NTB/3TB STBA Nomenclature Description

Terminal Terminal
1 85 55 X2 115 v ac output lunfused side).

2 83 54 FX1 115 V ac output (fused side).
3 81 53 MANC Form C normally closed contact from the MA pilot relay
lK2l.
4 79 52 MANO Form C normally open contact from the MA pilot relay (K2).
5 77 51 MACM Form C common contact from the MA pilot relay (K2).
6-7

//O Between DCFB or SDC/ Board and PCCA, PCN, or PCR Board
1 ASF Drives cell 6F gate pulse transformer.

2 P24 +24 volt output.
3 A5F Drives cell 5F gate pulse transformer.
4 P24 + 24 volt output.
5 A4F Drives cel! 4F gate pulse transformer.
11 A1 F Drives cell IF gate pulse transformer.
13 A1R* Drives cell 1R gate pulse transformer.
23 ABR* Drives cell 6R gate pulse transformer.
25 DCN(SDCU On S Cl, do bridge voltage (negative),
----(DCFB) On D FB, test attenuation.
26 DCP(SDCD On S cl, do bridge voltage (positive),
- - (DCFB) On DCFB, test attenuation.
* Reversing bridges only.
6-8
Table 6-9. Connectors CPL, CNPL, CPTPL, FAPL, NPL, PPL, and SOPL,
VO Between DCF8 or SDC/ Board and Components
Connector Pin No. Nomenclature Description
1 CPL 1 _ _ » _ _
L1 ACCT current input, white.
2 L1 ACCT current input, red.
3 L3 ACCT current input, red.
4 L3 ACCT current input, white.

CNPL 1 X1 MA contactor control output.
2 ____ MA contactor control output.

CPTPL 1 X2 1 15 V ac output (unused side).
2 XI 115 V ac output (fused side).
3 ....._ Not connected.
4 DCOM Common connection.
5 _ _ - _
38 V ac output.
6 _ _ - u _
38 V ac output.
FAPL 1 X2 115 V ac output for controller cooling fan.
2 X1 115 V ac Output for controller cooling fan.

NPL 1 _ _ _ ;
NRX N2 SCR cathode, red.
2 _ - »
NRX N2 SCR gate, white.
PPL 1 _-__
NRX PI SCR cathode, red.
2 --_u-»
NRX PI SCR gate, white.
SQPL* 1 ACNP 25 kHz power l + ) to SHVI/SHVM board.
2 ACNN 25 kHz power (-) to SHVI/SHVM board.
3 ACNACOM 25 kHz power common.
4 ACNACOM 25 kHz power common.
* DCFB board only.
6-9
Table 6-10. Connectors /A IPL, lA2PL, lF1PL, and lF2PL,

//O Between DCFB or SDC/ Board and Shunts
IA1 PL 1 Motor armature current shunt input ( + ), red.

2 Motor armature current shunt input (-). white.
IA2PL 1 _ - _
Motor #2 armature current shunt input ( + ) , red.
(DCFB only) 2 Motor #2 armature current shunt input (-), white.
- _ . » - . Q
IF PL 1 field current shunt input ( + ) , red.

o t o r
-»-_-
2 _ _ - M Motor field current shunt input (-). white.
IF2PL 1 - __ _
Motor #2 field current shunt input ( + ) , red-
(DCFB only) 2 Motor # 2 field current shunt input (-), white.
Table 6-7 1. Connector MACPL,

//O Between DCF8 or SDC/ Board and Contactor Driver Circuits
1 ._-__
MD #1 contactor control common output.
2 MD #1 contactor control 24 V do output.
3 - _ _
MD #2 contactor control common output.
Not connected on SDCL
4 MD #2 contactor control 24 V do output.
Not connected on SDCI.
Table 6- 72. DCF8 Board Stab Terminal Connections
Stab Description
I
VI Phase A ac line voltage.

V2 phase B ac line voltage.
V3 Phase C ac line voltage.
P1A Dc bridge voltage ( + ) .
P2A Do bridge voltage (-).
VM1A Motor armature voltage ( + ).
VM1B Motor armature voltage (-).
VM2A Motor #2 armature voltage ( + ).
VM2B Motor #2 armature voltage (-).
6-10
Table 6- 13. Neon Lamp and LEDs on DCFB Soard
I Name Indication
CR51 (Red LED) When lit, indicates that fuse FU2 in the +24 V do line
to the + 15 V do regulator is blown.
CR55 (Red LED) When lit, indicates that fuse FU3 in the -24 V do line
to the -15 V de regulator is blown.
LT1 (Neon lamp) When lit, indicates that fuse FUt in the 1 15 V ac
line to CNPL-1 , CPTPL-2 and FAPL-2 is blown.
Table 6- 14. SDC/ Board Stab Terminal Conn ections
Stab Description
ACT Input to internal < 10 A NRX/MOV.

AC2 Input to internal < 10 A NRXIMOV.
AC3 Input to internal < 10 A NRXIMOV.
FAC2 NRX < 10 A fused output.
FAC3 NRX <10 A fused output.
FPS NRX <10 A do snubber ( + L
FPN NRX <10 A de snubber (-).
MOV1 3-phase MOV output.
VI phase A ac line voltage.
V2 Phase B ac line voltage.
V3 Phase C ac line voltage.
Table 6- 15. Neon Lamps and LEDs on SDC/ Board
Name Indication
CR51 (Red LED) When lit, indicates that fuse FU2 in the +24 v do line
to the + 15 V de regulator is blown.
CR55 (Red LED) When lit, indicates that fuse FU3 in the -24 V do line
to the -15 V do regulator is blown.
LT1 (Neon lamp) When lit, indicates that fuse FU1 in the 1 15 V ac
external supply is blown.
LT5 (Neon lamp) When lit, indicates that fuse FU5 in the internal
NRX 10 A field and/or MOV assembly is blown.
LT6 (Neon lamp) When lit, indicates that fuse FU5 in the internal
NRX 10 A field and/or MOV assembly is blown.
6-11
6-8. LCS BOARD l/o
This section defines I/O points for the LCS board. Figure 5-7 shows connector locations on the board.
Table 6- 76. Connector TB 7,

LCS 8oard Power Connections
1 115 v ac input to LCS board.
2 __-__
Not connected.
3 115 V ac input to LCS board.
4 6 Not connected.
7 COM 5/15 V do power supply output, common.
8 +V 5/15 V do power supply output, positive.
9, 10 _ _ - _
Not connected.
11 TXA 0.3 A current source output (-).
12 TXB 0.3 A current source output ( + ) .
6-12
6-9. LTB BOARD I/O
This section defines I/O points and LEDs for the LTB board. Figure 5-8 shows connector and LED locations on the
board.
Table 6- 17. Connector 8PL,

VO Between LTB, NT8/3TB, and SDCC Boards
Pin No. NTB/3TB Nomenclature Description

Terminal
1 6 FA Non-inverting RS-422 half-duplex serial data line from the SDCC's Motor
Control Processor (MCP) UART.
2 8 FB inverting RS-422 half-duplex serial data line from MCP UART.
3 10 DCONI Signal return for EXSY (at COM potential).
4 12 EXSY External sync input to MCP.
5 Not connected .
6 1 EOAB Encoder interface Channel A non-inverted differential input.
7 3 /EOAB Encoder interface Channel A inverted differential input. (Tie to COM for
single-ended encoders.)
8 5 EOBB Encoder interface Channel B non-inverted differential input.
9 7 /EOBB Encoder interface Channel B inverted differential input. (Tie to COM for
single-ended encoders.)
10 9 EOMB Encoder interface marker channel non-inverted differential input.
11 11 /EOB Encoder interface marker channel inverted differential input. (Tie to COM
for single-ended encoders.)
12 .-».I»| -_
| -
Not connected.
13 14 CI1 -
CI1 C18 are general-purpose control inputs, i24 v do maximum with
27 kg input impedance.
14 16 cuz See CI1 (pin 13)-
15 18 cms See CI1 (pin 13)-
16 20 CM- See C11 (pin 13).
17 22 cw See CI1 (pin 13).
18 24 cue See CI1 (pin 13).
19 26 CW' See CI1 (pin 13)-
20 28 cm See CI1 (pin 13).
6-13
Table 6- 18. Connectors ln7 Through IN8,

Inputs to LT8 Board
1 INx-* 24 - 240 V ac or de input logic signal is brought in on INk and lNx- where + is
for the high or hot side and - is for the low or ground side. Each input draws 6 mA
maximum. The signal is converted to a 24 V do logic signal for the SDCC.
2 Not connected.
3 INK* 24 - 240 V ac or do input logic signal is brought in on lNG and INx- where + is
for the high or hot side and - is for the low or ground side. Each input draws 6 mA
maximum. The signal is converted to a 24 V do logic signal for the SDCC.
* Number here (x) corresponds to input circuit (IN) number.
Table 6- 19. Connector /OPL,

//O Between LT8 Board and SLCC Card
'I P24 +24 V do.
2- 8 112-118 i24 V logic lines to the drive.
9 16 Not connected.
17 N24 -24 V do.
18 111 +_24 V logic line to the drive.
19 - 25 101 - 107 Relay control lines 0 through 6.
26 P24 +24 V do.
Table 6-20. Connector OPTPL,

//O Eetween LTB Board and NT8/3TB Board
1 X2 Return for CFX1 120 V ac loads (isolated from COM). Same as NTB/3TB pin 85.
2 CFX1 120 V ac, it 5%, from NTB/3TB board, fused at 500 mA, including internal fans
(isolated from COM). Same as NTB/3TB pin 83.
6-14
Table 6-2 7. Connectors OT7 Through OT7,

LTB Board Connections from Form C Relay Contacts
1 OTxCM * Relay common connection; contact rating is 0.6 A @ 125 V ac, 0.6 A @
110 VdC, 2 . 0 A @ 30 V d c .
2 OTxNc * Relay normally closed (NC) connection; contact rating is 0.6 A @ 125 V
ac, 0.6 A @ 110 Vdc, 2.0 A @ 3OV do.
3 OTxNO * Relay normally open (NO) connection; contact rating is 0.6 A @ 125 V
ac, O . 6 A @ 11Ovdc, 2 . 0 A @ 3 O v d c .
* Number here (x) corresponds to relay output circuit (OT) number.
Table 6-22. Connector RPL,

//O Between LTB Board and RTBA Board
1 X2 Return for CFX1 120 v ac loads (isolated from COM). Same as OPTPL-1 .
2 - _ _ ¢ _
Not connected.
3 RX1 RTBA relay RX1 pilot output.
4 ; _ . -
Not connected.
6 _ - _ . ¢
Not connected.
8 Not connected.
9 RX4 RTBA relay RX4- pilot output.
10 _ _ _ - .
Not connected.
12 _..__ Not connected.
14 _ . -
Not connected.
16 ¢ _
Not connected.
Table 6-23. LEDs on LT8 Board
LED Name Indication
1 Q . 8 On when the source is applied to circuits IN through IN8, respectively.

17 - Q 23 On when Relay RX1 through RX7, respectively, is energized.
6-15
6-10. MBHA BOARD IIO
This section defines UO points for the MBHA board. Figure 5-9 shows connector locations OI1 the board.
Table 6-24. MBHA Fiber-optic Connectors
Connector Nomenclature Description

(Color)
U9 (Gray), BROADCAST Fiber-optic Broadcast Left Communications.

U2 (BIUB) LEFT 12-pulse or larger bridges use this fiber-optic channel to communicate between
masters of each 6-pulse lineup. The fiber-optic connection goes to the MBHA hub
communication board of each 6-pulse lineup master.
u1o (Gray), CONTROL 1 Fiber-optic Bridge #1 Communications.

U3 (Blue) This fiber-optic channel should connect to bridge #1 's SPCB card COMM
IN/COMM OUT channel. Bridge-to-bridge communications occur through this
channeL
U11 (Gray), ccn~rrRcn.2 Fiber-optic Bridge #2 Communications.

U4 (Blue) This fiber-optic channel should connect to bridge #2's SPCB card COMM
channel.
U12 (Gray), CONTROL 3 Fiber-optic Bridge #3 Communications.

channeL
U13 (Gray), cx3nrrR(JL 4 Fiber-optic Bridge #4 Communications.

channel.
U14 (Gray), cxJnrrRcJL 5 Fiber-optic Bridge #5 Communications.

channeL
U15 (Gray), BROADCAST Fiber-optic Broadcast Right Communications.

U8 (Blue) MGHT
U20 (Blue) C1MODE Fiber-optic Bridge #1 Mode Communications Input.

This fiber-optic channel should connect to bridge #1 's SPCB card MODE channel.
Master selection signal communications occur through this channel.
U21 (Blue) C2MODE Fiber-optic Bridge #2 Mode Communications Input.

This fiber-optic channel should connect to bridge #2's SPCB card MODE channel.
U22 (Blue) CSMODE Fiber-optic Bridge #3 Mode Communications Input.

This fiber-optic channel should connect to bridge #3's SPCB card MODE channel.
6-16
Table 6-25. Connectors TBPSA and TBPSB,

Power Supply Inputs to MBHA Board
Conneetor Pin No. Nomenclature Description
TBPSA 1 p20p Primary positive power supply input to the MBHA board.
P2OP, GNDP, P2OA, and GNDA are the primary and alternate power
supply inputs for the MBHA board, normally supplied from the P24 and
COM signals of 2 drives in the multi-bridge arrangement. GNDP and
GNDA are assumed to be nominally at the same potential. The alternate
inputs provide redundancy in case the master drive is shut down. As-
suming P20P is 24 V do, the MBHA board consumes approximately
200 mA of current.
2 GNDP Primary common power supply input to the MBHA board.
TBPSB 1 P20A Alternate positive power supply input to the MBHA board (see
TBPSA-1l.
2 GNDA Alternate common power supply input to the MBHA board.
6-17
6-11. NTBl3TB BOARD IIO
This section defines I/O points for the NTB/3TB board. Figure 5-10 shows connector locations on the board.
Previous tables define other NTB/3TB I/O: Table 6-6 for connector 2pL, Table 6-7 for 4PL, Table 6-17 for SPL, and
Table 6-20 for OPTPL.
Table 6-26. Connector 3T8,

I/O Between NTB/3TB and External Connections
I
3TB Nomenclature Description

Terminal
J
t EOA Non-inverting differential input for Encoder #0, channel A.

2 EOV1 Positive side of power supply with bal un choke for Encoder EOA/EOB. Either + 5 or + 15
V do as set by NTB/3TB jumper JP12.
3 /EOA Inverting differential input for Encoder #0, channel A.
4 EOV2 Return for EOV1 , basically at COM potential.
5 EOB Non-inverting differential input for Encoder #0, channel B.
6 FA Non-inverting RS-422 half-duplex serial data line. Provides a serial channel into the
SDCC's MCP (as opposed to the RS-232C channel into the SDCC's DCP). Jumpers JP1
and JP2 are used to connect line termination resistors to FA and FB (needed at each end
of an RS-422 network).
7 /EOB Inverting differential input for Encoder #0, channel B.
8 FB Inverting RS-422 half-duplex serial data line (see FA, 3TB point 6).
9 EOM Encoder interface marker pulse channel non-inverted differential input.
10 FCOM Signal return for EXSY (at COM potential).
11 /EOM Encoder interface marker pulse channel inverted differential input.
12 Exsy External sync input to SDCC's Motor Control Processor.
13 RE C Relay #1 common contact.
14- CI1 C11 - CI8 are general-purpose control inputs, $24 V de maximum with 27 kg input im-
pedance.
15 R1NC Relay #1 normally closed contact.
16 CQ See CI1 (3TB point 14).
17 R1NO Relay #1 normally open contact.
18 CB See CI1 (3TB Doint 14).
19 RZC Relay #2 common contact.
20 CM See CI1 (3TB point 14).
2t R2NC Relay #2 normally closed contact.
22 cm See CI1 (3TB point 14).
24 cm See CI1 (3TB point 14).
25 R3C Relay #3 common contact.
26 CW See CI1 (3TB point 14).
28 CB See CI1 (3TB point 14).
6-18
Table 6-26. Connector 3TB -

Continued,
//O Between NTB/3TB and External Connections

Terminal
I
30 RF24(1) Voltage reference for digital control inputs. Defaulted to -24 v do; changes to +24 V
de via NTB/3TB's jumpers JP10 and JP11. Each digital control input is active when
connected to RF24, inactive when open. Total _+24 v de load includes loading on RF24.
32 RF24(2) Voltage reference for digital control inputs (see RF24[1], 3TB point 30).
34 RUN General-purpose input. Defaulted to, but not limited to, RUN function.
36 JOG General-purpose if put. Defaulted to JOG function.
38 POL General-purpose input. Defaulted to the reference polarity function.
40 XSTP General-purpose input. Defaulted to the XSTOP function (normally closed).
42 CTLN1 Control on input 1. CTLN1 and CTLN2 l3TB point 44) form part of the circuit that picks
up the MA contactor pilot relay. They must be connected together for the drive to run.
Can also be used to connect external interlocks, providing a fail-safe (microprocessor
independent) way to stop the drive.
( 43 R6NO Relay #6 normally open contact.
44 CTLN2 Control on input 2 see CTLN1 , 3TB point 42).
45 RGC Relay #6 common contact.
46 PI P1 through P4 are medium-resolution analog input channels for voltages from i-5 V do to
1:50 V do. Scaled via respective pots P1 through P4 on the NTB/3TB. Input impedance z
10 kQ.
47 MSRF Relay #6 coil driver (Master Sync Reference output). open collector output. When inac-
tive, MSRP is pulled up to + 24 V do through 1400 Q maximum. When active, MSRF is
pulled down to 1.5 v do maximum through 200 Q, not including a maximum drop of
3.4 v across the 200 Q due to the relay #6 coil load. If internal control of this relay is
not required, relay #6 may be picked up by an external driver capable of pulling MSRF
down to 1.5 v do maximum sinking 17 mA.
48 P2 See PI (STB point 46).
49 DVM Medium resolution analog input channels, with fixed scaling for -:51 .O v do max (125.5
on early DCC cards). Input impedance and filtering is 511 kg and 100 ms. in conjunc-
tion with drive test 03, provides a digital voltmeter function with at least 0.5% accuracy
for diagnostic functions.
50 P3 See P1 (3TB point 46).
51 ASPO Medium-resolution analog input channel with fixed scaling for $5 V de maximum. Input
impedance and filtering is 10 kg and 1 ms.
52 P4 See P1 (3TB point 46).
53 DAC1 Output from 8-bit (DCC and SDCCG3l or 12-bit (SDCCG1) D/A converter. Can source
i-10 V do at no load or i8 V de at a 10 mA load (200 Q series impedance). Any drive
variable can be sent to this output and can be scaled to set the value corresponding to
10 V do output. If the variable attains a magnitude greater than this value, the output is
clamped to i10 V. rather than rolling over. (For diagnostics and system applications.)
6-19
Table 6-26.-Connector 3T8 - Continued,

I/O Between NT8/3TB and External Connections
I

Terminal
I
54 MET1 Output from 8~bit D/A converter. Can source iio V de at no load or i8 V do at a 10
mA load (200 Q series impedance). Any drive variable can be sent to this output and
can be scaled to set the value corresponding to tO V do output. If the variable attains a
magnitude greater than this value, the output is clamped to i o V, rather than rolling
over. (Provided for meter driver functions.)
55 DAC2 Same as DAC1 (see 3TB point 53).
56 MET2 Same as MET1 (see 3TB point 54).
57 MSSY Input to internal interrupt INTO of the SDCC's Drive Control Processor (DCP). Biased to
+24 V do though 27 kg, must be pulled to COM (less than + 1 .5 V do) to be recog-
nized by the DCP.
58 RESET Hard reset input to the drive. Connecting RESET to + 5 to +24 V do resets all proces-
sors in the drive. Leaving RESET open or connecting to COM allows drive operation. The
SDCC provides a 20 ms noise filter on this input.
59 TOW Input to internal timer/counter O of the SDCC's Drive Control Processor (DCP). Biased to
+24 V do through 27 kg, and must be pulled to COM (less than + 1 .5 V do) to be rec-
ognized by the DCP.
60 +5VDC + 5 V do source, i10%, 300 mA (including load on EOV1 and E1V1 ).
61 TOOUT TTL output through 200 Q from DCP's timer/counter O (on SDCC).
62 +15VDC + 15 V do source, i10%, 3OO mA (including load on EOV1 and E1V1).
63 REFP Non-inverting differential analog reference input. Maximum reference can be 9 to 29 V
do, coarsely selected by NTB/3TB's switches swf through SW7. Fine scaling provided
by EE.1281 (RVSCLn). This circuit uses a VCO similar to the one used by FDBP and
FDBN. Input impedance is at least 60 kQ with less than 1 ms of filtering. If this circuit is
not needed for the drive speed reference, the digitalization of this input is available for
other functions requiring high resolution.
64 -15VDC -15 V de source, :l:10%, 3OO mA (including load on E1 VI).
65 REFN Inverting differential analog reference input, with REFP, 3TB point 63.
66 COMH) 0 V common reference for all drive IlO. Should be used for signal level returns only.
67 RSVD U) Not used. Provides voltage clearance between signal-level points and points with poten-
tials above 50 V.
68 cow um O V common reference for all drive I/O, same as 3TB point 66.
69 FDBP Non inverting differential analog tech input (with 3TB point 73). Either ac AN or do ta-
chometers with a top speed voltage from 25 to 390 V (6 to 65 v if jumper JP7 on the
SDCC card is in the 2-3 position) can be connected to these differential inputs.
NTB/3TB's DIP switches SW1 through SW7 provide coarse scaling. SDCC'S jumper JP8
and EE.1386 (FVSCLn) provide fine scaling and analog ac AN tech rectification. Input
impedance of this circuit is at least 300 kQ, with less than 1.5 ms of filtering. If this
circuit is not needed for the drive speed feedback, the digitalization of this input is a
available for other functions requiring high resolution.
70 +24VDC + 24 V do source, i25%, unregulated, 500 mA (including load on RF24).
71 RSVDQJ Not used. Provides voltage clearance between signal-level points and points with poten-
tials above 50 v.
72 -24VDC -24 V do source, i25%, unregulated, 500 mA (including load on RF24).
73 FDBN inverting differential analog tech input (with 3TB point 69).
6-20
Table 6-26. Connector 3TB - Continued,

I/O Between NTB/3T8 and External Connections

Terminal
74 E1V1 Power supply with bal un line choke for encoders on SPC card. Either -15V do or same
voltage as EOV1 ( + 5 or +15 v de) as selected using NTB/3TB jumper JP13.
75 R$VD{3) Not used. Provides voltage clearance between signal~level points and points with poten-
tials above 50 v.
76 E1V2 Return for E1 vi , basically at COM potential.
77 MACM Form C common contact from MA pilot relay; auxiliary contact from the relay used to
pilot the MA contactor. Rated for 125 v ac, 2A.
78 RSVD(4) Not used. Provides voltage clearance between signal-level points and points with poten-
tials above 50 V.
79 MANO Form C normally open contact from the MA pilot relay; auxiliary contact from the relay
used to pilot the MA contactor. Rated for 125 V ac, 2A.
80 GRC1 General-purpose relay common contact of first form C. Rated for 120 V ac, 0.5 A.
81 MANC Form C normally closed contact from the MA pilot relay, auxiliary contact from the relay
used to pilot the MA contactor. Rated for 125 v ac, 2A.
82 GNC1 General-purpose normally closed contact.
83 CFX1 120 V ac source from drive, i15%, fused at 500 mA (isolated from COM).
84 GNO1 General-purpose relay normally open contact.
85 X2 Return for CFX1 120 v ac loads (CFX1 and X2 isolated from COM).
86 GRC2 General-purpose relay common contact of second from C. Rated 120 V ac, 0.5 A).
87 GR+ GR+ and GR- (3TB point 89) are coil inputs to a general purpose relay. This relay is not
internally connected to any drive circuitry, and may be used as required for customer
applications. The coil may be driven by 24 v or 120 v, either ac or do, as selected using
jumper JP20.
88 GNC2 General-purpose relay normally closed contact. Rated 120 V ac, 0.5 A.
89 GR~ See GR+ (3TB point 87).
90 GNO2 General-purpose relay normally .open contact. Rated 120 V ac, 0.5 A.
91 VC3N inverting differential analog input for auxiliary VCO #3. The top reference voltage may
be 9 to 29 V do. Jumpers JP14 and JP15 provide coarse scaling of the inputs. This
circuit uses a VCO similar to the one used by REFP and REFN. Input impedance is at
least 60 kg with less than 1 ms of filtering. The digitalization of this input is available at
VAR.184 for functions requiring a high-resolution analog input by using BLK.263
(V3VCO). (An SDCC card is required to support VCO #I-3; it is not available on the DCC
card.)
92 VC4N Inverting differential analog input for auxiliary VCO #4. The top reference voltage may
be 9 to 29 V do. Jumpers JP22 and JP23 provide coarse scaling of the inputs. This
circuit uses a VCO similar to the one used by REFP and REFN. Input impedance is at
least 60 kg with less than 1 ms of filtering. The digitalization of this input is available at
VAR.185 for functions requiring a high-resolution analog input by using BLK.264
(V4VCO). (An SDCC card is required to support VCO #4, it is not available on the DCC
card.)
93 VC3P Non-inverting differential analog input for auxiliary VCO #3.
94 VC4P Non-inverting differential analog input for auxiliary VCO #4.
95 MET3 i o V do analog output from an 8-bit D/A converter (see 3TB point 54).
J
6-21
CAUTION
The NTB/3TB board DAC and MET outputs (DA and MET testpoints) are not controlled during powerup
or powerdown of the drive. During these times, which may be as long as 3-4 seconds, the outputs may be as
high as ill) v de. If an output is used to control a process which might respond inappropriately to these
transient outputs, the process should be disabled during these times. One solution is to pass the output
through an NTB/3TB relay driven by SDCC relay outputs, which are always dropped out during powerup
and powerdown. The relay can be configured to pick up after powerup by pointing it at a drive variable
such as TRUEREG (VAR.10).

I/O Between NT8/3TB Board and SDCC Card
Pin No. NTBl3TB Nomenclature Description

Terminal
I
1 42 CTLN1 Control on input 1. CTLN1 and CTLN2 (3TB point 44) form part of the cir-
cuit that picks up the MA contactor pilot relay. They must be connected
together for the drive to run. Can also be used .to connect external inter-
locks, providing a fail-safe (microprocessor independent) way to stop the
drive.
2 44 CTLN2 See CTLN2 (pin 1).
3 LBIAS i24 V do bias for digital inputs from NTB/3TB (for + or - logic).
4 61 TOOUT TTL output through 200 Q from DCP's timer/counter O (on SDCC).
5 34 RUN General~purpose input. Defaulted to, but not limited to, RUN function.
6 36 JOG General-purpose input. Defaulted to JOG function.
7 38 POL General-purpose input. Defaulted to the reference polarity function.
8 40 XSTP General-purpose input. Defaulted to XSTP function (normally closed).
9 47 MSRF Relay #6 coil driver (Master Sync Reference output), open collector output.
10 14 RO1 - R05 NTB/3TB relay coil output driver lines 1 through 5.
15 P3B Scalable general-purpose analog input from NTB/3TB.
16 P4B Scalable general-purpose analog input from NTB/3TB.
17 51 ASPO Medium-resolution analog input channel with fixed scaling for i5 V do
maximum. Input impedance and filtering is 1O kg and 1 ms.
18 VC3NB inverting differential analog input to SDCC auxiliary VCO #3.
19 VC3PB Non-inverting differential analog input to SDCC auxiliary VCO #3.
20, 21 ; ¢
P1 A, PI B Scalable general-purpose analog inputs from NTB/3TB.
22 95 MET3 Same as MET1 (pin 26)-
23 49 DVM Medium resolution analog input channels, with fixed scaling for 151 .O V do
max (i25.5 on early DCC cards). Input impedance and filtering is 5 1 1 kQ
and 100 ms. In conjunction with drive test 03, provides a digital voltmeter
function with at least 0.5% accuracy for diagnostic functions.
24 53 DA1 Output from 8-bit (acc and SDCCG3) or 12-bit lsocccn) D/A converter.
Can source i o V do at no load or i8 V do at a 10 mA load (200 Q series
impedance). Any drive variable can be sent to this output and can be scaled
to set the value corresponding to 1O V do output. If the variable attains a
magnitude greater than this value, the output is clamped to i o V, rather
than rolling over. (For diagnostics and system applications.)
6-22
Table 6-27. Connector 6PL - Continued,

//O Between NT8/3T8 Board and SDCC Card
Pin No. NTB/3TB Nomenclature Description

Terminal
25 55 DA2 Same as DA1 (pin 24).
26 54 MET1 Output from 8-bit D/A converter. Can source i10 V do at no load or 18 V
do at a 10 mA load (200 Q series impedance). Any drive variable can be
sent to this output and can be scaled to set the value corresponding to 10 v
do output. If the variable attains a magnitude greater than this value, the
output is clamped to i-10 V, rather than rolling over. (Provided for meter
driver functions.)
27 56 MET2 Same as MET1 (pin 26)-
28 57 MSSY Input to internal interrupt INTO of the SDCC's Drive Control Processor
(DCP). Biased to +24 V do though 27 kQ, must be pulled to COM (less
than + 1 .5 V do) to be recognized by the DCP.
29 59 TOIN Input to internal timer/counter 0 of the SDCC's Drive Control Processor

(DCP). Biased to +24 v do through 27 kg, and must be pulled to COM
(less than + 1 .5 V do) to be recognized by the DCP.
30 58 RESET Hard reset input to the drive. Connecting RESET to + 5 to +24 V de resets
all processors in the drive. Leaving RESET open or connecting to COM al-
lows drive operation. The SDCC provides a 20 ms noise filter on this input.
31 nu
TDB RS-232C channel transmitted from DCP.
32 RDB RS-232C channel received by the DCP.
33 ; _
CTSB RS-232C channel clear-to-send handshake.
34 RTSB RS-232C channel clear-to-receive handshake.
35 _-_
VC4NB inverting differential analog input for SDCC auxiliary VCO #4.
36 VC4PB Non-inverting differential analog input for SDCC auxiliary VCO #4.
37 RFNB Differential analog input from NTB/3TB to reference VCO, negative line.
38 @ -
RFPB Same as pin 37, but positive line.
39 _ FBNB Differential analog input NTBl3TB to feedback VCO, negative line.
40 FBPB Same as pin 39, but negative line.
J
6-23
Table 6-28. Connector COMPL,

RS-232C //O Between NT8/3TB Board and User Interface
1 25 _ . _ _ The drive includes an RS-232C connection only for use as a serial link with the
ST2000 Toolkit or Drive Configurator, LynxOS Version. These software packages are
diagnostic and configuration programs used during installation, tuneup, and trouble-
shooting. GE does not intend this communications link to be used for any other pur-
pose.
CAUTION
Do not connect pin 25 of COMPL directly to a PC (personal computer) unless jumper JP21 is in the 1-2
position, or damage may occur.
NOTE
Although the RS-232C interface should work correctly with all 25 pins of COMPL connected, using the
minimum possible interface avoids incompatibility and noise problems.
6-24
6-12. PCCA, PCN, AND PCR BOARD IIO
This section defines I/O points for the PCCA, PCN, and PCR boards. Figure 5-11 shows connector locations for the
PCCA, Figure 5-12 shows the PCN, and Figure 5-13 shows the PCR.
For connector SPL, see Table 6-8.
Table 6-29. Connectors FPL Through 6FPL and 1RPL Through 6RPL*,
Output from PCCA, PCM or PCR Board to SCR Bridge
Connector Pin No. Description
1FPL - 6FPL 1 Forward gate pulse to corresponding SCR (red wire).
2 Forward gate pulse to corresponding SCR (white wire).

1RPL -_ GRPL* 1 Reverse gate pulse to corresponding SCR (red wire).
2 Reverse gate pulse to corresponding SCR (white wire).
* Reversing bridges only.
{
Table 6-30. PCCA Card Stab Terminal Connections
Stab Card Group No. Description
P1 G1-4,7-10 Positive do bus.
P1A , P1B G1 4,7-10 Positive do bus voltage feedback. When wire jumper WJ3 is connected be-
tween these terminals, the card snubber capacitors are connected to the
same point on the bridge as the voltage feedback channel (see Table 5-4).
P2 G 1 - 7 - 1 0 Negative do bus.
P2A, P2B G 1 - 7 - 1 0 Positive de bus voltage feedback. When wire jumper WJ4 is connected be-
tween these terminals, the card snubber capacitors are connected to the
same point on the bridge as the voltage feedback channel (see Table 5-4).
P3 - P10 G1-4,7-10 Voltage feedback scaling resistor connections (see Table 5-4).
DCS G1-4,7-10 To do snubber circuit.
1 ACS -- 6ACS G1, 2, 7, 8 To ac snubber circuits.
6-25
Table 6-31. PCN and PCR Board Stab Terminal Connections
Stab Board Description
P2A PCR Negative do bus voltage feedback.
P1 PCN, PCR Positive do bus.
P2 PCN,PCR Negative do bus.
P3 - P6 PCN,PCR Voltage feedback scaling resistor connections (see Tables 5-7 and 5-8).
P7 -- P10 PCR Voltage feedback scaling resistor connections (see Table 5-8).
SAC PCR Snubber resistor connection,
3A C
P C N , P C R 2 A C , Snubber resistor connections.
4AC q - 6AC PCR Snubber resistor connections.
6-26
6-13. RTBA BOARD uo
I This section defines I/O points and LEDs for the RTBA board. Figure 5-14 shows connector and LED locations.
For connector RPL, see Table 6-22.
Table 6-32. Connector RTBA,

VO Between RTBA Board and External Connections
RTBA Nomenclature* RTBA Nomenclature* RTBA Nomenclature*

Terminal Terminal Terminal
1 K20A 18 K221 NC 35 K242NC
2 K201 NO 19 K222NO 36 K25A
3 K201CM 20 K222CM 37 K251NO
4 K201 NC 21 K222NC 38 K251 CM
5 K202NO 22 K23A 39 K251 NC
6 K202CM 23 K231NO 40 K252NO
7 K202NC 24 K231CM 41 K252CM
8 K21A 25 K23tNC 42 K252NC
9 K21 1NO 26 K232NO 43 K26A
10 K21 1CM 27 K232CM 44 K261 NO
11 K21 1 NC 28 K232NC 45 K261CM
I 12 K212NO 29 K24A 46 K261NC
13 K212CM 30 K24-1NO 47 K262NO
14 K212NC 31 K241CM 48 K262CM
15 K22A 32 K241NC 49 K262NC
16 K221NO 33 K242NO 50 KCM
17 K221 CM 34 K242CM 51 115V
* The RTBA board contains seven relays that have two form C contacts. Nomenclature for the terminal
board points indicates the contact connection. For example, the terminal board point K2O NO: K =
relay; 20 = which of the seven relays (20 - 26), 7 = which of the two form C contacts; and NO =
normally open, as opposed to normally closed (NC) or common (CM).
6-27
Table 6-33. Connectors CPIPL Through CP5PL and Y.9PL Through Y35PL,
RTBA Pluggable Circuits
Connector Description
I
CPI PL - CP5PL, pin 1 Pluggable circuit control power, positive (hot) side (CPH).
CP1PL - CP5PL, pin 2 Pluggable circuit control power, negative side (CPN).
Y9PL-1 CPH.
Y9PL-2 Connected to Y10PL-1. Y9PL and Y1OPL form a powered pluggable cir-
cuit.
Y10pL-1 Connected to Y9PL-2.
Y1 OPL-2 CPN.
Y1 1pL-1 CPH.
Y1 1PL ...- v14PL Two-position plugs forming a series string to coil of relay K27.
Y15PL Jumpers Y1 SPL-2 to CPN.
Y16PL Relay K27 normally open contacts.
Y17PL Relays K27 and K28 dry contacts in series.
Y t 8PL Relays K28 and K29 coil leads.
Y19PL - Y22PL pluggable control circuit with K28 interlock.
Y23PL, Y24PL Dry circuit with K29 contact.
Y25PL - Y28PL Pluggable control circuit with K29 interlock.
Y29PL, Y3OPL Dry circuit with K29 contact.
Y31PL - Y34PL Pluggable control circuit with K29 interlock.
Y35PL - Y37PL Pluggable control circuit.
Table 6-34. LEDs on Relays of RTBA Board
LED on Indication
Relay's Name
K2O - K29 On when relays K2O though K29 (respectively) are energized.
6-28
6-14. SDCC CARD I/O
This section defines I/O points and LEDs for Lhe SDCC card. Figure 5-15 shows connector and LED locations .
Previous tables define other SDCC UO: Tables 6-4 and 6-5 for connector 1PL, Table 6-6 for 2PL, Table 6-27 for 6PL;
and Table 6-17 for 8PL.

SDCC Card Output to SLCC Card
Pin no. Nomenclature Description
1 - 8 BDO-BD7 Buffered, multiplexed SDCC Drive Control Processor (DCP) data bus lines O - 7.
9 DCOM Power supply return, common.
10 P5 +5 V do regulated power supply for digital circuits.
11 /RST3 System reset signal (active low)-
12 UNT Interrupt from SLCC/SDCC microapplication chip to DCP.
13 /LBSY Busy bus control handshake to DCP.
14 BA12 Buffered address latch enable from DCP.
16 IBCSL SLCC chip select.
17 /BRD Buffered read control line from CP.
18 nnwn Buffered write control line from DCP.
19 BA8 Buffered. demultiplexed DCP address line 8.
20 BA9 Buffered, demultiplexed DCP address line 9.
21 /BCSU SDCC microapplication chip select.
22 BA1O Buffered, demultiplexed DCP address line 10.
23 BA11 Buffered, demultiplexed DCP address line 11.
24, 25 DCOM Power supply return, common.
26 P5 +5 v do regulated power supply for digital circuits.
27 -. 34 BAO-BA7 Buffered, demultiplexed DCP address lines 0 through 7.

J
6-29
GEH-6005 DC2000 Digita] Adjustable Speed Drive

I/O Between SDCC Card and SPC or SPC8 Card
1 SPA1 i5 V do SPClSPCB analog channel #1 .

2 SPA2 i5 V do SPC/SPCB analog channel #2.
3 E12 Marker channel from encoder #1 interface.
4 E22 Marker channel from encoder #2 interface.
5 N15 -15 V do power supply for analog circuits on SPC/SPCB card.
6 pt5 + 15 V do power supply for analog circuits on SPC/SPCB card.
8 SPRS Digital output from DCP to SPC/SPCB card.
10 P5 + 5 V do power supply for digital circuits on SPC/SPCB card.
11 E1UP Up channel output from encoder #1 interface.
12 E1DN Down channel output from encoder # t interface.
13 E2UP Up channel output from encoder #2 interface.
14 E2DN Down channel output from encoder #2 interface.
15 ORST7 System reset (active low). Not connected on SPCB card.
17 SPSYN Not connected on SPC card. Sync pulse listener input to SDCC on SPCB card.
18 SPSYO Not connected on SPC card. Sync pulse listener output from SDCC on SPCB card.
19 SPTX + 5 V do output from SDCC's Motor Control Processor (MCP) UART.
20 SPRX + 5 V do input to MCP UART.
Table 6-37. Connector 7 IPL,

SDCC Output to Meters
1, 2 Not connected.
3 DCOM Drive common connection.
4 MTR1 MTR1 through MTR4 are outputs from an 8-bit DIA converter and can source i o V
do at no load or i8 V do at 10 mA load (200 Q series impedance). Any drive variable
can be steered to these D/A outputs and can be scaled to set what value corre-
sponds to the 10 v do output. These outputs are for meter driver functions.
5 MTR2 See MTR 1 (pin 4).
6 MTR3 See MTR1 (pin 4)-
7 MTR4 See MTR 1 (pin 4)-
8 DCOM Drive common connection.
9. 1 O ¢ . _ -
Not connected.
Table 6-38. LEDs on SDCC Card
LED Name Indication
1 Bar graph LED indicating fault patterns showing whether the drive is healthy, and stopped or run-
ning. When the drive has a fault, the graph displays the fault code number. For a detailed descrip-
tion of fault codes, see Chapter 10.
6-30
6-15. SHVI AND SHVM BOARD 110
This section defines I/O points for the SHVI and SHVM boards. Figure 5-17 shows connector and neon lamp locations
on the SI-IVI board, Figure 5-18 shows connector locations on the SHVM board.
Previous tables define other SHVI/SHVM I/O: Table 6-9 for connectors 1CPL and SQPL and Table 6-10 for IA1PL and
IA2PL.
Table 6-39. Connectors cTlp/., CT3PL, DC IPL, and DC2PL,

CT and Shunt Inputs to SHVI or SHVM Board
CT1PL 1 1 1 ;
L1 ACCT current input (-), white.
2
L 1 ACCT current input ( + ) , red.
1
CT3PL 1 - - L3 ACCT current input (-), white.
2 - 1
L3 ACCT current input ( + ) , red.
DC1 PL 1 Shunt 1 connection ( + L red.
2 Shunt 1 connection (-), white.
DC2PL 1 ___ Shunt 2 connection ( + ) , red.
2 _ _ S h u n t 2 connection (-), white.
Table 6-40. Connectors MPL and RA/IPL,

SHV/ Board Contactor Driver Circuit Connections
MPL 1 ; _ _
Contact driver #1 ( + ) , connected to stab terminal M1 .
2 1 ;
Contact driver #1 (-), connected to stab terminal B1.
3 ¢ - _ - n
Contact driver #2 ( + ) , connected to stab terminal M2.
4 _ - _ _
Contact driver #2 (-), connected to stab terminal B2.
RMPL 1 - _ ;
Contactor power ( +).
2 ; _ _
Contactor power (-).
3 1 ;
Contactor power ( + ).
4 . » ; -
Contactor power (-).
6-31
Table 6-47. SHV/ and SHVM Board

Stab Terminal Connections
Stab Description
I
B1 * Contact driver #1 (-).

B2* Contact driver #2 (-)-
CAC1 * 115 V ac control power.
CAC2 * 1 15 V ac control power.
FA* Phase A line filter.
FB* Phase B line filter.
FC* Phase C line filter.
Lt Ac voltage attenuator input.
L2 Ac voltage attenuator input.
L3 Ac voltage attenuator input.
M1 * Contact driver #1 ( + ) .
M1A Motor #1 attenuator input ( + ) .
M1 B Motor #1 attenuator input (-).
M2* Contact driver #2 ( + ) .
M2A Motor #2 attenuator input ( + ) .
M2B Motor #2 attenuator input (-).
P1 Dc bridge attenuator input ( + ) .
P1A Do bridge attenuator output ( + ) .
P2 Do bridge attenuator input (-).
P2A Do bridge attenuator output (-).
VI Ac voltage attenuator output.
V2 Ac voltage attenuator output.
V3 Ac voltage attenuator output.
VM1A Motor #1 attenuator output ( + ) .
VM1B Motor #1 attenuator output (-).
VM2A Motor #2 attenuator output ( + ).
VM2B Motor #2 attenuator output (-).
* SHVI board only.
Table 6-42. Neon Lamps on SHVI Board
Name Indication
LT1 Phase A line filter blown fuse indicator. LT1, LT2, and LT3 are
connected in a Y configuration. Therefore, a blown fuse is indi-
cated by a corresponding lamp being dimmer than the other two.
For example, LT1 dimmer than LT2 and LT3 indicates that the
phase A line filter fuse is blown.
LT2 Phase B line filter blown fuse indicator.
LT3 Phase C line filter blown fuse indicator.
6-32
6-16. SLCC CARD I/O
This section defines I/O points for the SLCC card. Figure 5-19 shows connector locations on the card.
Previous tables define other SLCC I/O: Table 6-6 for connector 2PL, Table 6-19 for IOPL, and Table 6-35 for 3PL.
Table 6-43. Connector KPPL,

//O Between SLCC Card and Keypad
1 -9 Keypad connectors to processor. Output from U1 to pins 19 - 32, respectively.
10 LODIN Display; Input to U1 pin 38.
11 LDCLK Display; Input to U1 pin 39.
6-33
6-17. SPC AND SPCB CARD l/o
This section defines IIO points for the SPC and SPCB cards. Figure 5-20 shows connector locations for the SPC card,
Figure 5-21 shows connector locations for the SPCB card.
For connector 7PL, see Table 6-36 .
Table 6-44. Connectors 76PL and 7 TB,

I/O Between SPC or SPCB Card and External Connections
t 6PL 1TB Nomenclature Description

Pin No. Terminal
1 E1AB Non-inverting input for encoder #1 channel A

2 -....._ -_
/E1AB inverting input for encoder #1 channel A.
3 E1BB Non-inverting input for encoder #1 channel B.
4 /ETBB Inverting input for encoder #1 channel B.
5 ......II!...
E1 MB Non-inverting input for encoder #1 marker channel.
6 -.<l.._.. /E1MB inverting input for encoder #1 marker channel.
7 1 E2AB Non-inverting input for encoder #2 channel A.
8 2 /E2AB Inverting input for encoder #2 channel A.
9 3 E2BB Non-inverting input for encoder #2 channel B.
10 4 /E2BB Inverting input for encoder #2 channel B.
11 5 E2MB Non-inverting input for encoder #2 marker channel.
12 6 /E2hAB inverting input for encoder #2 marker channel.
13 7 PF1 N Inverting input for analog channel SPA 1 (VAR.256).
14 8 PF1 P Non-inverting input for analog channel SPA1 (VAR.256).
15 9 PF2N Inverting input for analog channel SPA2 (VAR.257).
16 1o PF2P Non-inverting input for analog channel SPA2 (VAR.257).
17 11 TXP For SPC card, non-inverting RS-422 output from SDCC's Motor Control
Processor (MCP). Not connected on SPCB card.
18 12 TXN For SPC card, inverting RS-422 output from MCP. Not connected on
SPCB card.
19 13 RXN For SPC card, inverting RS~4-22 input to MCP. Not connected on SPCB
card.
20 14- RXP For SPC card, non-inverting RS-422 input to MCP. Not connected on
SPCB card.
6-34
Table 6-45. Connector SYT8,

VO Between SPCB Card and External Connections
1 SYNC Drive synchronization signal, non-inverting output.
2 /SYNC Drive synchronization signal, inverting output.
Table 6-46. SPC8 Card Fiber-optic Connectors
Connector Nomenclature Description

(Color)
U28 (Gray) MODE OUT Fiber-optic Mode Communications Output.
U27 (Blue), SYNCHIN, Fiber-optic Synchronization.

U26 (Gray) SYNCH OUT Bridge-to-bridge firing synchronization may (through the MBHA board) occur
through this channel. If it is used it should be connected to one of the following
fiber-optic channels on an MBHA board (depending on which drop the respective
bridge iS): CONTROL 1, CONTROL 2, CONTROL 3, CONTROL 4, or CONTROL
5. Blue is the receiver, gray is the transmitter.
U11 (Blue), COMM IN, Fiber-optic Bridge-to-Bridge Communications.

U20 (Gray) COMM OUT Bridge-to-bridge communications (COMM IN/COMM OUT) occur through this
fiber-optic channel (through the MBHA board). It should be connected to one of
the following fiber-optic channels on an MBHA board (depending on which drop
the respective bridge is): CONTROL 1, CONTROL 2, CONTROL 3, CONTROL 4,
or CONTROL 5. Blue is the receiver, gray is the transmitter.
6-35
6-18. STBA BOARD I/O

i
This section defines I/O points for the STBA board. Figure 5-22 shows connector locations on the board.
Previous tables define other STBA I/O: Table 6-6 for connector 2PL, Table 6-7 for 4PL, and Table 6-17 for 8PL.
Table 6-47. Connector STBA,

I/O Between STBA Board and External Connections
I
STBA Nomenclature Description

Terminal
J
1 EOA Encoder channel A non-inverted differential input.

2 Eovl Positive side of power supply with bal un choke for encoder EOA/EOB. Either +5 V do or
+ 15 v do, per jumper JP12.
3 NEOA Encoder channel A inverted differential input.
4 EOV2 Return for EOV1, basically at COM potential.
5 EOB Encoder channel B non-inverted differential input.
e NEOB Encoder channel B inverted differential input.
7 COM O volt common reference for all drive I/O, same as STBA-44.
8 R1 C Relay #1 common contact.
9 CI1 General-purpose control input.
C11-CI8 are general-purpose control inputs, :1:24 V do maximum, with 27 kQ input im-
pedance and a 2 ms hardware filter. Each is automatically sampled 45 times per second
by default. Beginning with DP revision 2.24, CI1-CIB may be sampled faster, at 90 to
720 times per second by scheduling a foreground block, BLK.372, CIINS, at the appro-
priate rate.
CI1 is also accessible through Cl1PL. Cl1PL is a 2-position plug, with pin 1 being RF24,
and pin 2 being on. The connector is mainly for factory use, where CI1 is wired as a
status input (feedback) of a local panel-mounted device.
10 MNC Relay #1 normally closed contact.
11 Cl2 General-purpose control input.
CI1-CI8 are general-purpose control inputs. £24 v do maximum, with 27 kQ input im-
by default. Beginning with DP revision 2.24, CI1 -CIS may be sampled faster, at 90 to
720 times per second by scheduling a foreground block, BLK.372, CllNS, at the appro-
priate rate. Cl2 is jumper configurable to be accessible to STBA-11 by placing JP28 in
the 2.3 position. By placing JP28 in the 1.2 position , C12 is directly driven by relay K2,
and IS NOT accessible to STBA-1 1 .
12 P1NO Relay #1 normally open contact.
13 CIS General-purpose control input.
CI1-CIS are general-purpose control inputs, _+24 V do maximum, with 27 kg input im-
by default. Beginning with DP revision 2.24, CI1-CIS may be sampled faster, at 90 to
priate rate. CI3 is jumper configurable to be accessible to STBA-13 by placing JP31 in
the 2.3 position. By placing JP32 in the 1.2 position and JP31 in the 1.2 position, Cl3
is directly driven by relay K3.
6-36
Table 6-47. Connector STBA - Continued,

//O Between ST8A Board and External Connections

Terminal
I

These relay contacts are rated for 120 V ac, 0.5 A maximum. EEPROM parameters al-
low this relay to be driven by any bit of any variable in the SDCC's Drive Control Proc-
essor WITH THE PROPER JUMPER CONFIGURATION l see JP26 and JP27 )-
This relay can also be configured to be driven from a dry external contact, powered from
STBA 115 V ac. The other K2 contact can be jumper configured to go to Cl2, a 24 v do
configurable input. This gives the relay the ability to be a software-configured output OR
a 115 v ac input to a CI, but not both.
(See EE.218 and following for software). When software-driven, relay status is updated
45 times per second. Beginning with DP revision 2.24, blocks RLYAL (373) and RLAYN
(374), allow any or all of these relays to be updated 90 to 720 times per second. These
relays have a typical mechanical delay of 3 to 4 ms.
C11-C18 are general-purpose control inputs, i24 v do maximum, with 27 kg input im-
by default. Beginning with DP revision 2.24, C11-C18 may be sampled faster, at 90 to
priate rate. CI4 is jumper configurable to be accessible to STBA-15 by placing JP35 in
the 2.3 position. By placing JP.35 in the 1.2 position , CI4 is directly driven by relay
K4, and IS NOT accessible to STBA-15.
CI1-Cl8 are general-purpose control inputs, 124 V do maximum, with 27 k§2 input im-
by default. Beginning with DP revision 2.24, CI1-CI8 may be sampled faster, at 90 to
720 times per second by scheduling a foreground block, BLK.372, CllNS, at the appro-
priate rate. Cl6 is jumper configurable to be accessible to STBA-'l 9 by placing JP38 in
the 2.3 position. By placing JP38 in the 1.2 position , Cl6 is directly driven by relay KB,
and IS NOT accessible to STBA-19.
20 RSC Relay #3 common contact.
These relay contacts are rated for 120 v ac. 0.5 A maximum. EEPROM parameters al-
essor WITH THE PROPER JUMPER CONFIGURATION (see JP29 and JP30}_
This relay can also be configured to be driven from dry external contacts (wired to
v11PL & Yt2PL), powered from STBA 115 v ac (CPH & CPN)_
The other K3 contact is wired in series with a K28 contact and wired to internal points
CTLN1 and CTLN2. CTLN1 and CTLN2 form part of the circuit for picking up the MA
contactor pilot relay, and must be connected together to allow the drive to run. They
provide a hard-wired, microprocessor-independent, means of stopping the drive. This
gives the K3 relay the ability to be a software-configured output OR a 1 15 V ac hard-
wired relay that can stop the drive on loss of contact closure in the contact string, and
loss of CPT power (CPT undervoltage detection). JP39 bypasses K3 interlock control to
CTLN1 and CTLN2. JP31 and JP32 configure a K3 contact to be used as a relay output,
or to feed to CI3 for K3 status (software-programmable action on status).
(See EE.220 and following for software). When software-driven, the relay status is up-
dated 45 times per second. Beginning with DP revision 2.24. blocks RLYAL (373) and
RLAYN (374) allow any or all of these relays to be updated 90 to 720 times per second.
These relays have a typical mechanical delay of 3 to 4 ms.
6-37

I/O Between STBA Board and External Connections

Terminal
I

24 RF24 Voltage reference for the digital control inputs.
Defaulted to -24 V do but may be changed to +24 V de via JP1O and JP1 1. Each digi-
tal control Input is considered active when it is connected to RF24 and inactive when it
is left open. Loading on RF24 must be included in the total i24 volt load.
25 R-4C Relay #4 common contact.
essor WITH THE PROPER JUMPER CONFIGURATION (see JP33 and JP34).
STBA 1 15 V ac. The other K4 contact can be jumper configured to go to CI4, a 24 V de
a 115 V ac input to CI4, but not both.
(374) allow any or all of these relays to be updated 90 to 720 times per second. These
26 RF24 Voltage reference for the digital control inputs.
29 REC Relay #5 common contact.
essor.
(See EE.224 and following for software). By default, the relay is updated 45 times per
second. Beginning with DP revision 2.24, blocks RLYAL (373) and RLAYN (374) allow
any or all of these relays to be updated 90 to 720 times per second. These relays have
a typical mechanical delay of 3 to 4 ms.
A K5 contact is in the generic control circuit formed with Y19PL, Y2OPL, and Y21 PL.
The circuit is jumper configured to be dry or powered (see JP14 and JP15). This circuit
is a series string of K5 (software control) and K28 (hard-wired control) contacts.
JP25 bypasses K5 control, and K28 control is bypassed by jumpering pins 1 and 2 of
Y19pL. Y21 PL is the output pair, and Y20PL is a connector input for additional external
interlocking into the circuit.
31 RENO Relay #5 normally open contact.
32 Rec Relay #6 common contact.
essor WITH THE PROPER JUMPER CONFIGURATION (see JP36 and JP37).
STBA 1 15 v ac. The other K6 contact can be jumper configured to go to Cl6, a 24 v do
a 1 15 v ac input to CI6, but not both.
(374) allow any or all of these relays to be updated 90 to 720 times per second. These
6-38

//O Between STBA Board and External Connections
I

Terminal

34 DAY 110 v do analog output from 8-bit or 12-bit D/A converter.
DAC1 and DAC2 (8-bit resolution on SDCCG3 cards and 12-bit on SDCCG1 cards) and
MET1, and MET2 (8-bit resolution), are outputs from D/A converters and can source
i o V do at no load or i8 V do at a 10 mA load (200 Q series impedance). Any drive
variable can be steered to these D/A outputs and can be scaled to set what value corre-
sponds to a 10-volt output. If the variable attains a magnitude greater than this value,
the D-A output is clamped to i-10 V do rather than rolling over. DAC1 and DAC2, in-
tended for diagnostics and system applications, are updated every 1.4 ms. MET1 and
MET2, intended primarily for meter driver functions, are updated every 2.8 ms.
35 DA2 i o V do analog output from 8-bit or 12-bit D/A converter (see STBA-34).
36 BAET1 i10 v do analog output from 8-bit D/A converter (see STBA-34).
37 IMET2 i10 V do analog output from 8-bit D/A converter (see STBA-34).
38 RESET Hard reset input to the drive.
39 p5 +5 v do source. i10%, 250 mA (including load on EOV 1 and E1V1 ).
4O P15 + 15 V do source, it O%, 250 mA (including load on EOV1 and E1 vi ).
41 REFP Non-inverting differential analog reference input.
Analog reference input. This circuit uses a VCO similar to the one used by FDBP and
FDBN. Input impedance is at least 60 kg ohms, with less than 1 ms of filtering. If this
circuit is not needed for the drive current reference, the digitalization of this input is
available for other functions requiring high resolution.
I 42 N15 -15 v do source, :.l:10%, 250 mA (including load on E1v1l.
43 REFN inverting differential analog reference input.
44 COM o volt common reference for all drive I/O, same as STBA-45. COM should be used for
signal-level returns only.
45 CONI O volt common reference for all drive I/O, same as STBA-44.
46 FDBP Non inverting differential analog tech input.
Analog +_1o V input. This signal is digitized by a voltage-controlled oscillator (VCO) on
the SDCC which yields a resolution of at least 14 bits over a sampling interval of at
least 65 ms. Because of the VCO integrator, note that long-term resolution is much
higher than attainable with an A/D converter due to discrete sampling aliasing. Input
impedance of this circuit is at least 40 kg, with less than 1.5 ms of filtering.
47 P24 +24 V do source, i-25%, unregulated, 500 mA (including RF24- load)-
48 N24 -24 V do source, i25%, unregulated, 500 mA (including RF24 load).
49 FDBN Inverting differential analog tech input.
50 cut General-purpose control input.
CI1-C18 are general-purpose control inputs, i24 V do maximum, with 27 kg input im-
by default. Beginning with DP revision 2.24, Cl1~cl8 may be sampled faster, at 90 to
priate rate.
51 RAACNI Form C common contact from MA pilot relay.
These contacts are auxiliary contacts from the relay used to pilot the MA contactor.
Ratings are 125 V ac, 2 A.
52 llAno MA auxiliary form C normally open contact.
53 IMANC MA auxiliary form "C" normally closed contact.
6-39
-
Table 6-47. Connector STBA Continued,
//O Between STBA Board and External Connections

Terminal
54 CFX1 12O V ac source from drive, i15%, fused at 500 mA.

55 X2 Return for CFX1 120 V ac loads (CFX1 and X2 isolated from COM).
56 CPH Control Power Hot side.
CPH is the control power supplied from a power source external to STBA, typically 115
V ac from a drive CPT. lt is supplied to TB points to be used as a power feed when a K
relay is configured to be used as a 1 1 5 V ac input, with relay status configured to go to
a Cl. This circuit has only enough amperage rating to power the K relay coil.
57 RLY2 + K2 , 115 V ac input.
When K2 is configured as a 115 V ac input, (see JP26 and JP27), its intended use is as
a 1 15 V ac pilot relay, with a contact feeding Cl2. A dry contact status, as from a mo-
tor overtemp switch, for instance, can be directly wired to STBA, using STBA-56 as the
power feed, and STBA-57 as the return wire. Also see STBA-14.
58 CPH Control Power Hot side (see STBA-56).
When K4 is configured as a 1 15 V ac input, (see JP33 and JP34), its intended use is as
a 115 V ac pilot relay, with a contact feeding CI4. A dry contact status, as from a mo-
tor overtemp switch, for instance, can be directly wired to STBA, using STBA-58 as the
power feed, and STBA-59 as the return wire. Also see STBA-25.
60 CPH Control Power Hot side (see STBA-56).
When K6 is configured as a 1 15 V ac input (see JP36 and JP37), its intended use is as
a 115 V ac pilot relay, with a contact feeding CIS. A dry contact status, as from an-
other drive's /FAULT contact. for instance. can be directly wired to STBA, using STBA-
60 as the power feed, and STBA-62 as the return wire. Also see STBA-32.
64 K28+ K28, 115 v ac input.
This relay coil is isolated, that is, it can be driven from any 115 V ac source. The K28
contact is internally connected to internal points CTLN1 and CTLN2. CTLN 1 and CTLN2
form part of the circuit for picking up the MA contactor pilot relay, and must be con-
nected together to allow the drive to run. They provide a hard-wired, microprocessor-
independent means of stopping the drive. For any drive to run, K28 must be picked up
(powered). Also check to see if K3 is jumpered in series with K28 contact to CTLN1 and
CTLN2. See STBA~20.
66 K28- K28, 1 15 V ac input.
J
CAUTION l
The STBA board DAC and MET outputs (DA and MET testpoints) are not controlled during powemp or
powerdown of the drive. During these times, which may be as long as 3-4 seconds, the outputs may be as
high as 110 V de. If an output is used to control a process which might respond inappropriately to these
transient outputs, Me process should be disabled during these times. One solution is to pass the output
through an STBA relay driven by SDCC relay outputs, which are always dropped out during powerup and
powerdown. The relay can be configured to pick up after powerup by pointing it at a drive variable such
as TRUEREG (VAR.10) .
\
6-40
- . L - - n u
- Table 6-48. Connector COMPL,

RS-232C //O Between STBA Board and User Interface
1 -_ 25 1 _ -
The drive includes an RS-232C connection only for use as a serial link with the
ST1000 Drive Configuration Tools. This software package is a diagnostic and con-
figuration program used during installation, tuneup, and troubleshooting. GE does not
intend this communications link to be used for any other purpose.
NOTE
Although the RS-232C interface should work correctly with all 25 pins of COMPL connected, using the
minimum possible interface avoids incompatibility and noise problems.
Notes:
H
v
~o
r
"\_
1
i
CHAPTER 7
FUSES AND TESTPOINTS
7-1. LINE FUSES 7-2. CDBA ONBOARD FUSE
A11DC2000 Adjustable Speed Drives include protective The .CDBA board contains protective fuse FU1 on the
fuses 011 various power lines to protect the equipment. 115 V ac input power to the board. FU1 is a 4 A, 125
V, 2AG, slow-blowing fuse. If FU1 continually blows,
C, CX, and G frame drives include fuses on the ac the CDBA board is probably defective, and should be
power lines and control power transformer (CPT) lines. replaced.
CX frame drives also include fuses on the blower motor
power lines. The ac power line fuses are typically des- See Figure 7-1 for the location of fuse FU1 on the
ignated FU1 through FU3; the CPT line fuses, CPTFUI CDBA board .
through CPTPU3, and the blower motor power line
fuses, BF1 through BF3.
DSZOOCDBAG1 B
J, K, and M 'frame drives include fuses on the ac input
power line alters, do leg lines, CPT lines, and the
blower motor power lines. For these frame sizes, the ac
input power line filter fuses are typically designated
FU2l, FU22, and FU23, the de leg line fuses are typi- \
Rv1 1 5
cally designated FU1 through FU12; the CPT fuses are
typically designated CPTFUl through CPTFU3 and 2
CPTAPU1 through CPTAFU3; and the blower motor s
power line fuses are typically designated B#FU1 S

REFA
through B#FU3, where # is a number from 1 through 3, ACOMA
corresponding to the number of the blower motor . P15A
O
Table 7-1 lists typical values for these fuses. Chapter 12 LED1
contains parts lists for the various frame sizes, including
the pan number for each fuse. O
The hardware drawings in the drive door pocket show
the locations of these fuses. Appendices B through D
E
JP1
e
contain sample hardware drawings for the various
DC2000 drive frame sizes. FU1
L
MPL
I
1 2 s 4 s 6 7 a 9 10 1112
JP2
Z z
1 TBA 1TB8 1TBC 17am
E-:
1 2 3
L L
RMPL MACPL
1TB I
Figure 7-7. CDBA Board Layout

R
7-1
Table 7- 1. DC2000 Line Fuse Values
Fuse Location in Circuit Fuse Designation Fuse Value Type
Ac input power lines, G frame:

230 V ac, 1-55 A output FU1 - FU3 60 A, 500 V Semiconductor
230 V ac, 56-74 A output 100 A, 500 v
230 V ac, 75-107 A output 1 7 5 A, 5OO v
460 V ac, 1-53 A output 60 A, 500 V

460 V ac, 54-69 A output 1OOA, 5OOV
460 V ac, 70-127 A output 175 A, 5OOV
575 v ac, 1-58 A output 60 A, 700 v

575 V ac, 59-1O6 A output 100 A. `7OO v
Ac input power lines, C and CX frames:

230 V ac, 108-260 A output
230 V ac, 261-525 A output
FU1 _ FU3 300 A, 500 V Semiconductor
500 A, 500 v
460 V ac, 128-260 A output 3OOA, 5OOV

460 V ac, 261 -505 A output 500 A, 500 V
575 V ac. 107-183 A output zoo A, 700 V

575 V ac, 184-421 A output 400 A, 700 v
Blower motor lines, CX, J, K and M frames:

230 V ac, 50 Hz B#FU1 - B#FU3 (where 3.2 A, 6oo v FRS-R, dual-element time delay
230 V ac, 60 Hz # is the number of the 4.0 A, 600 V
blower motor)
460 V ac, 50 Hz 1 .8 A, ego V
460 V ac, 60 Hz 2.0 A, eoov
575 V ac, 50 Hz 1.2 5 A, 600 V

575 V ac, 60 Hz 1.8 A, 6OOV
Control power lines, G frames with 0.6 A CPT

230 V ac input CPTFU1, CPTFU2 2.0 A, 600 V FNO.-R, time delay
460 V ac input 1.oA, 600 V
All input voltages CPTFU3 0.75 A, 600 v FNQ-R, time delay
Control power lines, C and CX frames with

3.04 A CPT
230 V ac input .
CPTFU1 CPTFU2 6.0 A, 600 V FNQ-R, time delay
460 V ac input 3.0 A, 600 V
All input voltages CPTFU3 3.2 A, 6OOV FNO.-R, time delay
Control power lines, G, C, CX, J, K, and M

frames with 4. 6 A CPT
230 V ac input CPT(A)FU1 I CPT(A)FU2 8.0 A, 600 V FNQ-R, time delay
460 V ac input 4.0 A, 600 V
575 V ac input 3.2 A, 600 v

All input voltages CPT(A)FU3 5.0 A, $00 V FNQ-R, time delay
7-2
Table 7- 7. DC2000 Line Fuse Values - Continued
Fuse Location in Circuit Fuse Designation Fuse Value Type
Do leg lines, J and K frames:

700 V ac, 251 1 A maximum output FU1 ¢ FU12 2500 A, 1ooov Semiconductor
1000 V ac, 2078 A maximum output 1000 A, 14oov
1300 V ac, 1871 A maximum output 900 A, 1650 v
Do leg lines, M frame, 53mm SCRs:

230/460 v ac. 1455 A maximum output FU1 - FU12 700 A, 700 V Semiconductor
700 V ac, 1455 A maximum output 700 A. 1300 V
1 coo v ac, 1265 A maximum output 630 A, 1300 v
Do leg lines, M frame, 77mm SCRs:

700/1OOO V ac, 1 500 A maximum output FU1 - FU12 1 oonA, 1 coo V Semiconductor
Do line fuse, G frame (regenerative only):

230 V ac input, 1-55 A output FU4 60 A, 500 V Semiconductor
230 V ac input, 56-74 A output 100 A, 500 V
230 V ac input, 75-107 A output 175 A, 500 v
460 V ac input, 1-53 A output 60 A. 700 V

575 V ac input, 1-1O6 A output 160 A, 1300 v
Do line fuse, C and CX frame

/regenerative only):
230 V ac input, 108-260 A output FU4 300 A, 500 V Semiconductor
230 V ac input, 261 -365 A output 400 A, 700 V
230 V ac input, 366-440 A output $00 A, 700 v

460 V ac input, 261 -345 A output 400 A. 700 v
575 V ac input, 107-217 A output 550 A, 1 $00 v

7-3
7-3. DCFB ONBOARD FUSES

WARNING
The DCFB contaiNs fuses FU1 through FU3, defined in
Table 7-2. Neon lamp LTI lights if FUl is blown; LED
CR51 lights if FU2 is blown and control power is ap- Dangerous voltages exist on the DCFB when
plied to the dive; and LED CR55 lights if FU3 is power is on. Turn off drive power and stop
blown and control power is applied. Figure 7-2 shows motor. Allow internal capacitors to discharge
DCFB fuse, neon lamp, and LED locations. before touching or moving the board, or
when attaching or removing meters.
Table 7-2. DCF8 Board Fuses
Fuse Function
FU1 Fuse for the 1 75 V ac power supply brought to 3TB; 7/2 A, 2AG fast acting. FU1 protects the 115 V ac
power supplied for customer use. Check for wiring errors or overload if this fuse blows. When the fuse is
blown and load is connected, neon light LTt on the DCFB board will be lit.
FU2 Fuse for signal-/eve/ power supplies +24, + 15, and + 5 Vdc; 7 A, 2AG fast acting- When FU2 is
blown, the drive is unable to generate fault messages, but LED CR51 will be lit when control power is
applied to the drive. The usual cause of this fuse blowing is an accidental short of + 24 V de, either
while probing or due to a wiring error at the terminal board. If FU2 continues to blow when 1 PL, 2PL,
and 5PL are disconnected from the DCFB board, the board should be replaced.
FU3 Fuse for sigma/-/eve/ power supplies -24 and - 15 V do, 7 A, 2AG fast acting. When FU3 is blown, the
Programmer is unable to display fault messages, but LED CR55 on the DCFB board will be lit when con-
trol power is applied to the drive. The usual cause of this fuse blowing is an accidental short of -24 V
do, either while probing or due to a wiring error at the terminal board. If FU3 continues to blow when
1pL, 2PL, and 5PL are disconnected from the DCFB board, the board should be replaced.
7-4
lAw PL L L L L IA2PL L=_.% lF1PL

vi V2 V3 P1A P2A VM1A VM1B VM2A WBAR w 3E3§ R w§B8: R w IF2PL
II II H II II II II II L II re r1r1r13
I 11 II II I I f1r1 r1r13
I II II II 1 L
w
I I
00002 1
I 1
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R
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E EFQ
SW1 swz sw3 SW4 SW5 -vzo
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E
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IQQDE §mDQD
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ET
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PPL NPL
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f
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CO
-1
F I I 'I I
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9 1
TCPL I I I go
MACPL 1 PL Hz
[::J:J LTD
1
|
FU2 CR51
1 2 3
CNPL
CD
I 7A I
FUN
(Zig 1
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I 7A
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ca
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I
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I
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SPL
N15 P15
OWN
I L--J
0
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DCOM
2
1
I I
1 FPL
g 1
2FPL
|
1D
9
2
1
5PL
I I
2B
25
V'
P5
2PL
01
DS200DCFBC1 B CPTPL FAPL 4PL
Figure 7-2. DCFB Board Layout
7-4. LCS ONBOARD FUSE
'he LCS board operates from 115 V ac input power.

7`he incoming ac line is protected by a 0.25 A, 250 V
fuse, designated FU1. Figure 7-3 shows the layout of
the LCS board, including the location of fuse FU1.
|-
>
z
O
c
m
E P1
m
l"'l
z
--4 JP1l I:]
m
D
:
1 2 3
z
n
r"l
u\
w
-n
x
N
o
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r'
n
m
>
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n
.»
2 5 4 5 5 7 8 9 1 0 1 1 1 2
FU1
|- I I '1
I
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i
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TB1
11 I I I I I I I I I
II
s.-
Figure 7-3. LCS Board Layout Ur
7.5
7-5. SDCI ONBOARD FUSES

WARNING
The SDCI board contains protective fuses FU1 through
FU3, FU5, and FU6, as defined in Table 7-3. Each fuse
has an associated neon light or LED (LT1, CR51, Dangerous voltages exist on the SDCI board
CR55, LT5, and LT6) that mms on if the fuse is blown. when power is on. Stop the motor and turn
Figure 7-4 shows SDCI fuse, neon light, and LED lo- off drive power. Allow internal capacitors to
cations. discharge before touching or moving the
board, or when attaching or removing me
tens.
Table 7-3. SDC/ Board Fuses
Fuse Function
I
FU1 Fuse for the 1 75 V ac power supply brought to the STBA board; 1/2 A, 2AG fast acting. FU1 protects
the 1 15 V ac power supplied for customer use. Check for wiring errors or overload if this fuse blows.
When the fuse is blown and load is connected, neon light LTD on the SDCI will be lit.
FU2 Fuse for +24, + 15, and + 5 V do signal-level power supplies; 7A, 2AG fast acting. When FU2 is
blown, the drive is unable to generate fault messages, but LED CR51 will be illuminated when control
power is applied to the drive. The usual cause of this fuse blowing is an accidental short of +24 V do,
either while probing or due to a wiring error at the terminal board. If the fuse continues to blow when
1PL, 2PL, and 5PL are disconnected from the SDCI, the board should be replaced.
FU3 Fuse for -24 and - 15 V de signal-level power supplies; 7A, 2AG fast acting. When FU3 is blown, the
Programmer is unable to display fault messages, but LED CR55 will be illuminated when control power is
applied to the drive. The usual cause of this fuse blowing is an accidental short of -24 V do, either while
probing or due to a wiring error at the terminal board. If the fuse continues to blow when 1 PL, 2pL, and
5PL are disconnected from the SDCI, the board should be replaced.
FU5 Fuse for internal NRX 10 A field and/or MOV assembly; 15 A, KTK/KLK/ATM fast acting. Depending on
the drive frame size, this fuse is unused or can feed the NRX field and/or the MOV assembly. Neon light
LT5 lights if the fuse is blown. Possible causes include defective SDCI board, defective MOV assembly,
defective field SCR package, and wiring short.
FU6 Fuse for internal NRX 70 A field and/or MOV assembly, 75 A, KTK/KLK/ATM fast acting. Depending on
the drive frame size, this fuse is unused or can feed the NRX field and/or the MOV assembly. Neon light
LT6 lights if the fuse is blown. Possible causes include defective SDCI board, defective MOV assembly,
defective field SCR package, and wiring short.
7-6
VI V2
I I
vs 1A1FL 1FlPL
II II 1 \
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I FPS
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non MOYS 1
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Ni SPL
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I
FAPL
Figure 7-4. SDC/ Board Layout
7-6. TESTPOINTS testpoints are presented here in alphabetical order by

board name (CDBA, CPCA, DCFB, and so on) to assist
The DC2000 drive includes onboard testpoints for use the reader in referencing this material.
in troubleshooting. Testpoints are metal posts located on
specific signal paths. The signal can then be measured
or viewed by connecting an oscilloscope or other meas- 7-6.1 . CDBA Board Testpoints
uring instrument to that testpoint.
Table 7-4 lists and defines the testpoints contained on
Tables 7-4 through 7-13 list the testpoints contained on the CDBA board. Figure 7-1 shows the locations of
boards used 'm the DC2000 drive. Boards containing these testpoints on the board.
Table 7-4. CDBA Board Testpoints
Name Description
I
ACOMA Common reference point for CDBA board. Because the CDBA common is different from
the drive's common level, test measurements on the CDBA must be done with isolated
test equipment that is suitable for measuring floating potentials.
P15A Testpoint for CDBA + 15 V do L 20%) power supply referenced to ACOMA.
REFA Testpoint for driver reference voltage, which sets the amount of current that will drive
the contactor. This voltage is set using pot RV1. RV1 is set at the factory for the contac-
tor to be driven. Consult the factory if the setting is suspected to be incorrect.
7_7
7-6.2. CPCA Card Testpoints

DS20OCPCAG1A
15
Co
Table 7-5 lists and defines the testpoints contained on 'D
the CPCA card. Figure 7-5 shows the locations of these

testpoints on the card. "D
LD
zz
7-6.3. DCFB Board Testpoints

z FE re
Table 7-6 lists and defines the testpoints contained O11 SI
» [1 J:
1 1:
1:
CO
the DCFB board. Figure 7-2 shows the locations of 1:
F'
I
these teslpoints on the board.
70
L 3:
7-6.4. MBHA Board Testpoints 'o
r- z
MPL
r I
Table 7-7 lists and defines the testpoints contained OI1 1 2 3 4 5 6 7 B g 10 11 12 l
the MBHA board, revisions ACA through present. Fig-

ure 7-6 shows the locations of these testpo'mts on the
board.
.*
-4
to
17sA 1TBB
l 1 TBC 1 TBD
7-6. 5. NTB/3TB Board Testpoints |
1 2 4 5 6 7 B 9 11 12
Table 7-8 lists and defines the testpoints contained on

the NTB/3TB board. Figure 7-7 shows the locations of Figure 7-5. CPCA Card Layout
these testpoints on the board.
Table 7-5. CPCA Card Testpoints
Name Description
I
CPH Testpoint for CPCA power positive input. CPH is not referenced to the drive's common
level; therefore all test measurements must be done with isolated test equipment that is
suitable for measuring floating potentials.
CPN Testpoint for CPCA power negative input.
PSP Testpoint for CPCA coil control positive input.
PSN Testpoint for CPCA coil control negative input.
I
Table 7-6. DCF8 Board Testpoints
Name Description
I
P5 Testpoint for regulated + 5 V do (i5%) power supply.

DCOM O V common reference point for test signals.
P15 Testpoint for regulated + 15 V de (i5%) power supply.
N15 Testpoint for regulated -15 V do (i5%} power supply.
ACCT Testpoint for ACCT signal from DCFB to SDCC.
7.8
.. oF.._.,. plllv I-o ..1ll-*ll°\l ";'*"'
Table 7-7. MBHA Board Testpoints
Name Description
I
._,.__Tp1 C1MODE testpoint.

TP2 C2MODE testpoint.
TP3 C3MODE testpoint.
TP4 Oscillator for programmable logic device.
TP5 Received broadcast left fiber-optic signal.
TP6 Transmitted broadcast left fiber-optic signal.
_,___Tp7 Transmitted signal to bridge #1 (primary master).
,,.Tp8 Received signal from bridge #1 (primary master).
, TP9 Transmitted signal to bridge #2 (alternate master).
TP1O Received signal from bridge #2 (alternate master).
TP1 1 Transmitted signal to bridge #3.
TP12 Received signal from bridge #3.
TP13 Transmitted signal to bridge #4.
TP15 Transmitted signal to bridge #5.
TP17 Transmitted signal to broadcast right output.
TP18 Received signal from broadcast right input.
_/f TP19 + 20 v input voltage, nominally +24 V.
_.. TP2O + 5 V do power supply for MBHA (not at same potential as drive).
I
TP21 Common level for MBHA board (not at same potential as drive DCOM).
TP22 Common level for MBHA board (not at same potential as drive DCOM).
Table 7-8. NTB/3TB Board Testpoints
Name Description
DA1 i o v de analog output from 8-bit (SDCCG3) or 12-bit (SDCCG1) D/A converter, same as 3TB pin 53.
DA2 i10 v de analog output from 8-bit (SDCCG3) or 12-bit (SDCCG1) D/A converter, same as 3TB pin 55.
MET1 1:10 v de analog output from 8-bit D/A converter, same as 3TB pin 54.
MET2 i o v do analog output from 8-bit D/A converter, same as 3TB pin 56.
DVM Digital voltmeter (Test 03) input, range i5o V do, same as 3TB pin 49.
COM O v common reference point for test signals, same as 3TB pin 66.
CAUTION
The NTB/3TB board DAC and MET outputs (DA and MET testpoints) are not controlled during powerup
or powerdown of the drive. During these times, which may be as long as 3-4 seconds, the outputs may be as
high as £0 V de. If an output is used to control a process which might respond inappropriately to these
transient outputs, the process should be disabled during these times. One solution is to pass the output
through an NTB/3TB relay driven by SDCC relay outputs, which are always dropped out during powerup
and powerdown. The relay can be wnhgredto pick up after powerup by pointing it at a drive variable
such as TRUEREG (VAR.10).
7_9
u
TOHINOD
CONTROL 5 TBPSA
r
CONTROL 5
z 1ozuno:J
BROADCAST LErI CONTROL 1 GSTAH TBPSB
E ac
L Ll
r
B
G s
U10
W UP bus., JL U22
.I
L
I
I |.-
]
TP20
Sell o1.41 Zldl lzdl

TP1 1 TP\5
TP13 TP14 TP\6 TP17 TP1B
zzal
7ps TP5 1P7 TPB 3 2 1 TPI rp5
UCQM EIIIIJP5
JP1 TP2 TP4 TP19
D'S20OMBHAG1A
Figure 7-6. MBHA Board Layout

'uz e L 5 2 1
5 X305NTB COMPL r _ '
L _ -
_I
.IPO
:D
n.
l I l
Hal
20
In I q
..
ll
19
1 2 Sal z 3 JP21 JP4 JP12 JP1S l"4 5 7
E
L
5___2 1 DPL
u-
o.
__JP19 :ps JPS JP2S ra__2 g__ 2 1 5___2 1 ;_fr,,2
" | \
I I
0
*1 I
L___[ 2*"
: : J : : : L
~0
I 1
5_ _ 2r_-
N
-I
n
L J "
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3 2 I
1.J'°
I " 2 5 elf; s El
N N
E?
__
_1 N JP7
I
ld
J
I
u
I I
PI
1234567 3
11
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a.
.-
UP
JP14 ps
I
LJ*
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on
n
I
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un
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n.
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so
WAfl
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n IL .|I
I
11,,12 3
N
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I
'ldldfi
mar
I
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I
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1
I
I
t
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r
I
e
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I
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N
I
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s
-1
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I
|-
n
y 1
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I
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u. I
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T
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-
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I ZLEIH m
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bf
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ZVO [YU N03
Figure 7-7. NTB/3T8 Board Layout

if I
l 1
DC2000 Digital Adjustable Speed Drive x GEH-6005
7-6.6. SDCC Card Testpoints
Table 7-9 lists and defines the testpoints contained on the SDCC card. Figure 7-8 shows the locations of these testpoints
on the card. Figure 7-8 through 7-15 show typical waveforms of oscilloscope connections at some SDCC testpoints.
Table 7-9. SDCC Card Testpoints
Name Description
DCOM1 0 v common reference point for test signals, same as DCOM2.

DCOM2 0 V common reference point for test signals, same as DCOM1 .
P5 Testpoint for regulated +5 volt (15%) power supply.
TP4 Drive Control Processor (DCP) foreground timing flag (720 Hz).
TP5 DCP blockware timing flag (720 Hz).
TP6 DCP slow background timing flag (90 Hz).
RTS Unused. General-purpose testpoint output from DCP.
TP8 Analog representation of the motor armature current (via the primary shunt lA1 of this bridge only),
with a nominal do offset of about + 2 v. A deviation of 0.5 V represents approximately 1 pu shunt
current (see Figures 7-9, 7-10, and 7-13). In DCFB applications which use dual shunts, TP8 does NOT
represent any of the current in shunt lA2 nor does it represent any current from shunts in other bridges
of a multibridge drive.
FCLK "l'm alive" 8 MHz oscillator output from Motor Control Processor (MCP).
1 NMI Initiates board test (Test 13) when momentarily tied to + 5 v do. For card test only, not recommended
for use in a drive environment.
DACS Diagnostic D/A converter daughterboard select; used with auxiliary diagnostic hardware in conjunction
with EE.600. as
N15 Testpoint for regulated -1 5 volt (t5%1 powergsupply.
P15 Testpoint for regulated + 15 volt (15%) powerfSupply.
CDR TMS32O serial data receive 1.
The testpoints in the upper left corner of the SDCC (CDR, CDX, CLX, CLR, FSX, CLKC, CP5, and
CCM) are reserved for diagnostic purposes for the TMS320C25 processor, via a D/A daughterboard
which allows serial diagnostic D/A converters to be. added for development/test purposes only.
CDX TMS32O serial data transmit.
CLX TMS320 serial transmit clock input.
CLR TMS320 serial receive clock input.
FSX TMS32O serial frame sync pulse for transmit.
FSR TMS32O serial frame sync pulse for receive.
CLKC TMS32O clock oscillator output.
CP5 + 5 V do power supply to TMS320 diagnostic D/A daughterboard.
CCM Common power supply return for TMS320 diagnostic D/A daughterboard 1
TP29 Testpoint for input line frequency (see-Figure 7-15).
TP37 Testpoint for motor armature voltage, scaled 3.4 volts = 1 pu (see Figures 7-1 1`, 7-12, and 7-14).
I
7-11
:SPL
In
2 I 34
U12
7FL
1 I 53 1 | I 19
JP12
to CLKC
U11
r=_'1::l
1 cp5
BIO 1 2 5
Icon
CDX Q
FSR XF 3 N15 p1s TP4 TP5 TP6
CMP U35
;Fsx
A CLX
.CLR
. CDR 2
g
DCOM1
QrM O - - O
P5
DACS
I
EEROM
can
f;
ll'M o--o
ZFM 0 - 0
3
l 1'
-1
U9 g
53 1:1:J JP1
s:z:n
TP12 3
-1
I;
NMI
MTPNT
DCP
IilI]JP14
1 2 3 JP8 3:21
JP22 U1
JP23 JP7
l:l l=1:J r=l:J
9PL "'
MCP _JP16
Wild
1=1_J
U21 RESET
RTS
o
HHHHHHHUHH
I031
FCLK
DCOM2 2 40
TP37
i
\ I
1PL 2
TP29 r I' 1_
DS215SDCCG1A
as TPB 2PL
1
IE
1
SPL 11PL
10
g
Figure 7-8. SDCC Card Layout
w/www
|
1 1
D I * I 0
I I
(2IVlS/DNISIOM (2msnJlvls\on)
Figure 7-9. Current Feedback (SDCC Card TP8) Figure 7-70. Current Feedback (S`DCC Card TP8)
in Discoer tinuous Current in Continuous Current
7-12
'l 'I 'I _ _ 'I
3
\ \
I I I
I
2
I
' I -1
2 l \ l l \ l l |
1
| l \ \ 1
\
\ l.
\
1
1
l .
r \.I Ll
\
L
\ \
\
1 l l l l l l
.I M
I I. \ I
h
1
l. .l
D \ 0 I II I l I lI I '| l l I l l I I I 1
l I I
l l I ..
I I I I I I
\ I4
I I I I I I
I I I
(2MS/DNISION) (ZMS/DIVISION)
Figure 7-11. Voltage Feedback (SDCC Card TP37} Figure 7- 12. Voltage Feedback fsocc Card TP37)
in Discontinuous Current in Continuous Current
- .. - .,
I |
I I I I I
2
1 I
I
\ l
1
o x I (\re/`\/\ 0 o I I
I. I . L
l
ft L
i
I
r I I
l
I I I I I I I
I I I I I I I
I I I I I I
(2MS/DMSION) fans/onvaslonn
Figure 7- 13. Current Feedback rsocc Card TP8l Figure 7- 14. Voltage Feedback (SDCC Card TF37)
Vwth One SCR Open or Disconnected vwth One SCR Open or Disconnected
-l '
6 l l I l l
l H lI
4 | l l I l
0 1 1 I I I II I I _ I
I
l
|
I l l I
I
I _ l
l l
I I I I I
I I I I I I I
(2ms/oMsIon)
Figure 7- 15. Sync Signal (SDCC Card TP29) -

Square Wave Synchronized to Ac Une Frequency
7-13
7-6.7. SDCI Board Testpoints Table 7-70. SDC/ Board Testpoints
Table 7-10 lists and defines the testpoims contained on Name Description
the SDCI board. Figure 7-4 shows the locations of these P5 Testpoint for regulated +5 V do (i5%)
testpoints on the board. power supply.
DCOM O v common reference point for test

7-6.8. SPC Card Testpoints probing.
Table 7-11 lists and defines the testpoints contained on P15 Testpoint for regulated +15 V do (i5%)
the SPC card. Figure 7-16 shows the locations of these power supply.
testpoints on the card.
N15 Testpoint for regulated -15 V do (i5%)
power supply.
I
7-6.9. SPCB Card Testpoints
Table 7-12 lists and defines the testpoints on the SPCB

card. Figure 7-17 shows the locations of these testpoints
on the card.
Table 7-7 7. SPC Card Testpoints
Name Description
I
TP1UP Encoder #1 up counter output.
TP1 DN Encoder #1 down counter output.
TP1Z Encoder #1 marker channel output (if enabled).
TP2DN Encoder #2 down counter output.
TP2Z Encoder #2 marker channel output (if enabled).
RX RS-422 receiver input.
TX RS-422 transmitter output.
SP1TP1 SPA1 differential amplifier output, ahead of pot PI /P2 offset and scaling.
SP1TP2 Final output of SPA1 analog input channel, analog version of VAR.256. An analog volt-
age of i5 V de converts to i511 counts at VAR.256.
SP2TP1 SPA2 differential amplifier output, ahead of pot P4/P5 offset and scaling.
TP2TP2 Final output of SPA2 analog input channel, analog version of VAR.257. An analog volt-
age of i5 V do Converts to i511 counts at VAR.257.
7-14
DC2000 Digital Adjustable Sgeggl Drive GEH-6005
:w 551 X3D9SPC SlGNAL PROCESS TP2UP

: -
E2AB Qn
o : I I - l TP2DN
-5.
QE*
/EZAB 'é'
> EDI
20
EZBH r'1
: N JP1 1 2 s 1 2 3
/EZBB I I JI"
JP5 -.. JP8
ITBB
EZMB JP7 F
I I
13
- re
/E2MB J 1 2' ;_,4

1
H
1 2 3 TP27 1 2 5 TP1UF'
PF1N 5
_. it I
JP4
1:3 I
JP2
123 JP1 O r 1
I I
1
PFD P -1
m TP1DN
o 2' C34
m TP1Z
PF2N l`l
... 'U SF'1TP1
|- q
PFZP 1 1
H8 ,s '"|
..
TXP
¢
-4
m
..
.LD
' n
o 5 .J o
JP9 re
TXN UI
I I
..
. | .
r'
1
Run I zi 11..4 SP2TP2
I
-I
1TBE
1:
- 1 II. * n
to
-5
RXP lo N no no no N
01 be (A bl be bl
F5 P5 PA P5 P2 PI
Tx RX 2RE5P ZSCALE ZZERO 1RE5P 1SCALE 1ZERO
Figure 7- 16. SPC Card Layout
Table 7- 12. SPCB Card Testpoints
Name Description
TP1UP Encoder #1 up counter output. During forward encoder rotation, TPnUP will have a narrow pulse at the
edges of each encoder tooth.
TP1DN Encoder #1 down counter output. During reverse encoder rotation, TPnDN will have a narrow pulse
at
the edges of each encodertooth.
TP1Z Encoder #1 marker channel output (if enabled). If enabled, a narrow pulse will occur coincident with the
leading edge of the marker pulse.
TP2DN Encoder #2 down counter output.
TP2Z Encoder #2 marker channel output (if enabled.
Fiber-optic communications transmitter output, from SDCC. Fiber-optic bridge receiver (COMM IN)
testpoint.
Fiber-optic communications transmitter output, from SDCC. Fiber-optic bridge transmitter (COMM OUT)
testpoint.
SP1TP1 SPA1 differential amplifier output, ahead of pot P1 fP2 offset and scaling.
SP1TP2 Final output of SPA1 analog input channel, analog version of VAR.256. An analog voltage of i5 V do
converts to i511 counts at VAR.256.
SP2TP1 SPA2 differential amplifier output, ahead of pot P4/P5 offset and scaling.
TP2TP2 Final output of SPA2 analog input channel, analog version of VAR.257. An analog voltage of i5 V do
converts to i511 counts at VAR.257.
SPSYO Sync pulse output from SDCC. This testpoint normally contains the sync pulse output of this particular
drive, regardless of whether it is selected as the master sync to all drives of a multi-bridge configuration.
SPSYN Sync pulse listener input to SDCC. In a multi-bridge configuration, this signal is the common ac line sync
passed to all drives if the signal is being derived from the hardware (hardwired) sync or from the fiber-
optic (SYNC IN/SYNC OUT) sync.
SPRS Select local/broadcast mode or used for voting. General purpose signal from the SDCC card. In multi-
bridge master drives, it is used to select local or broadcast mode for the MBHA board. In multi-bridge
follower drives, SPRS may be used for voting on masters for redundant operation.
DCOM Testpoint at signal level common.
7-15
JP1 7PL 5P1TP1 SP1TP2
"Tim
I
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20
19 SPZTP1 iv
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Figure 7-77. SPC8 Card Layout
7-6. 10. STBA Board Testpoints
Table 7-13 lists and defines the testpoints contained on the STBA board. Figure 7-18 shows the locations of these test-
points on the board.
Table 7- 13. STBA Board Testpoints
Name Description
DA1 +_1 OV do analog output from SDCC 8-bit D/A converter, same as STBA pin 34.
DAC1 and DAC2 (8-bit resolution on SDCCG3 cards and 12-bit on SDCCG1 cards), and MET1 and MET2
(8-bit resolution), are outputs from D/A converters. These outputs can source it O V do at no load or 3:8
V do at a 1O mA load (ZOO ohm series impedance). Any drive variable can be steered to these D/A out-
puts and can be scaled to set what value corresponds to a 10-volt output. if the variable attains a magni-
tude greater than this value, the D/A output is clamped to i10 volts rather than rolling over. DAC 1 and
DAC2, intended for diagnostics and system applications, are updated every 1.4 milliseconds. MET1 and
MET2, intended primarily for meter driver functions, are updated every 2.8 milliseconds.
DA2 it O V de analog output from SDCC 8-bit D/A converter, same as STBA pin 35.
MET1 i o v do analog output from SDCC 8-bit D/A converter, same as STBA pin 36.
MET2 i10 V do analog output from SDCC 8-bit D/A converter, same as STBA pin 37.
COM 0 volt common reference point for test signals, same as STBA pin 44.
7-16
asa pa Of
_ #1
g CAUTION
E -J .J
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The STBA board DAC and MET outputs
(DA and MET testpoints) are not controlled
LIE
B.
I
I
I
I I
L;
l; 3
- N
D.
u during powerup or powerdown of the drive.
.I " if: N r- na.. .J
During these times, which may be as long as
.LIE
G.
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3-4 seconds, the outputs may be as high as
g n2u
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pa
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,
u
process which might respond inappropriately
II
1
#
nm- Fl H <
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I I I 1-
(D to these transient outputs, the process should
g_ Z w-
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- on be disabled during these times. One solution

w
E
Il! 8 is to pass the output through an STBA relay
..|
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o
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c-' z F'1 r driven by SDCC relay outputs, which are
Lin 5
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I
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Q
always dropped out during powerup and
v- m y D
N
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powerdown. The relay can be configured to
nZLJ
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;
m pick up after powerup by pointing it at a
na.- _| drive variable such as TRUEREG (VAR.10).
LIE-
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Figure 7- 78. ST8A Board Layout
7-17
Notes:
7-18
CHAPTER 8
SOFTWARE ADJUSTMENTS
8-1. INTRODUCTION 8-2. 1. Equipment Requirements
The DC2000 Adjustable Speed Drive uses microproces~ The ST2000 Toolkit reqmlres an RS-232C link to com-
son-based software that includes adjustable parameters. municate with the drive. It is designed to operate on an
These parameters perform many functions once con- IBM PC AT® or compatible computer (80286 or
trolled through adjustable hardware and software com- higher processor).
binations »
The minimum computer requirements are as follows:

The parameters are modified to customize the drive to
the specific hardware and application. They also enable Hard disk drive, 40 MB minimum (15 MB of this is
field and maintenance personnel to Hue-tune the drive required to load the ST2000 Toolkit)
for optimal performance .
The drive's ST2000 Toolkit or Drive Configurator,
. MS-DOS" 3.0 (or equivalent DOS) or later
LynxOS Version and Programmer are used to make 640K RAM minimum
these software adjustments.
. 5-1/4 inch or 3-1/2 inch disk drive (for software
installation)
8-2. ST2000 TOOLKIT
The DOS-based ST2000 Toolkit is a set of software

. CGA graphics
tools used to configure, maintain, and line-tune the
drive. The toolldt consists of a collection of programs
. Monochrome monitor (multiple shades of gray)
(tools) running under a command shell O11 an IBM PC®
compatible computer (see section 8-2.1 for require- . RS-232C serial port
ments).
• Parallel printer port, Centronics compatible
The toolldt includes an extensive database of DC2000
detinidons, accessed and manipulated using menu- Recommended enhancements include:
driven selections. Additionally, the ST2000 program
can graphically display the drive's program logic on the
computer screen. By viewing the logic flow, the user
. 80286 or higher microprocessor, running at 16
MHz or faster
can better understand and manipulate the drive's adjust-
able values. 2 MBt0 4MB RAM
The ST2000 Toolkit is used at the factory to originally

configure and test the drive system. At the customer
. Disk cache software
site, the toolkit enables GE field engineers and other

trained personnel to reconfigure, fine-tune, and main-
. EGA or VGA color graphics with color monitor
tain the installed drive. Optional modules provide real-
time display of control variables and communications
. 80 MB hard disk drive
data .
8-2.2. Using the ST2000 Toolkit
Publication GEH-5860 provides instructional informa-

don about the ST2000 Toolkit.
8-1
8-3. DRIVE CONFIGURATOR, LYNXOS VERSION 8-3.2. Using the Drive Configurator
The LynxOS-based Drive Configurator is also a set of Publication GEI-I-6203 provides instructional informa-
software tools used to configure, maintain, and fine- tion about the Drive Configurator.
tune the drive. The Drive Configurator is a collection of
programs (tools) designed to run on an IBM PC-
compatible computer equipped with the LynxOS operat- 8-4. PROGRAMMER MODULE
ing system (see section 8-3.1 for requirements).
NOTE
The Drive Conligurator is used to originally configure
and test a drive system, and to time-tune and maintain To avoid drive malfunction, only qualified
that system in the field. It uses a database to generate personnel should use the Programmer.
the configuration for the drive during manufacture, and
to allow GE field engineers and other trained personnel The DC2000 drive includes a Programmer module (see
to adjust the drive configuration for optimal perform- Figure 8-1) with a 16-character digital display and an
ance. Optional modules provide real-time display of alphanumeric keypad. It functions as an operator inter-
control variables and communications data . face for performing software adjustments and diagnostic
testing when the ST2000 Toolkit or Drive Configura-
The database is used to maintain configuration data for tor is not available.
one or more control systems. The product is usually
installed on a central database server. On smaller instal- The Programmer provides a digital display for an al-
lations, the database may reside on the same PC as the phanumeric readout of fault codes, status, RAM values,
Drive Configurator. and EEPROM values. The alphanumeric keypad enables
the user to operate and adjust the drive.
8-3. 1. Equipment Requirements NOTE
The Drive Configurator is designed to operate on an Permanent changes made using the Pro-
IBM PC AT or compatible computer with the follow- grammer module must also be made in the
ing minimum requirements: ST2000 Toolkit or Drive Configurator to
. LynxOS operating system, version 2.1 or later
keep the tools compatible with the drive's
software configuration.
80386 microprocessor The Programmer resides OH the SLCC card, which

. SMBRAM
mounts on the SDCC card. The Programmer is accessed
.
by opening the cabinet door at the front of the drive
150 MB hard disk drive Chapter 6 lists and defines the SLCC's I/O cocnnecdons .
• VGA graphic card and monitor NOTE
• RS-232C serial port The Programmer's parameter address, des-

ignated as EE1.0 (CFGJPR), must contain a
The following enhancements are recommended: 1 (an odd number) to enable it to function. A
. 80486 or higher microprocessor, running at 33

MHz or faster
0 in the address disables the Programmer.
See Parameter Mode (section 8-4.3.2) to
change the value, if needed.
12 to 16 MB RAM
. Color monitor
8-2
-MSPLAY
®
Q
RUN
RUN sLow
sLow JOG
JOG
NA
1fA Us
2/5
2/5 ac
sic
sic Hsxlusc STOP
nes DGR DVD
DVD
R1
R1
un
419
419
R2
SIE
REV
REV
F§ElI
OIF ADDR
rw
4">»
INC
INC:
INC
ARM v ARMI
ARM I HELD]I
FIELD LJ
L_]
l_l
um
Am
All PAUO
PATIO JOG
JOG re
f'1
r'l
1
1 BIo
BeI 9 s+uFT
SHIFT Dec:
DEC
DEC
SPEED TORO HP v
~<,:'
<L;'
v r
REFR DIV# SET RESET
ENTER or
oz- NEXT PREV CLEAR]
HAM onvs
orws TEST MODE
NP 10IX9D5B1003
/e» »®
RED
A
BLACK
WHITE BACKGROUND
sLow
'[ so;
I
t GREEN
BLUE
Figure 8- 1. Programmer Module
8-3
8-4.1. Keypad 8-4. 3. Operating Modes
NOTE The Programmer operates in any of three modes:
This chapter indicates a Programmer key by . Operate Mode, the normal mode which the drive
automatically enters as powerup
enclosing the key name in () symbols. For
example, (STOP) symbolizes the key labeled
STOP. • Parameter (EEPROM or Mirror) Mode, selected by
an operator from Operate Mode
The Programmer keypad enables an operator to control
the drive by: • Diagnostic Mode, selected by an operator from
Parameter Mode
• Examining drive parameters
The Programmer's operating mode determines the
• Entering alphanumeric data function of most keys. This is shown by the color (and
. Running diagnostics
position) of the keys' labels (see Figure 8-1):
• Red labels (top of key) during Operate Mode

Initiating self-tuning programs
. Blue labels (bottom of key) during Diagnostic
Mode
The keypad contains 20 keys. As shown in Figure 8-1,
.
most have more than one label, each a different color
The color indicates the key's function during the asso-
ciated operating mode.
. Black labels (middle of key) during Operate, Diag-
nostic, and Parameter Modes
Green labels (middle, right side of black label),

8-4.2. Display selected by holding down (sHIFt) while presslmg a
key, during Operate, Diagnostic, and Parameter
NOTE Modes; (SHIFt) is also green
This chapter indicates a Programmer display The following paragraphs describe the modes and key
by using a different typestyle. For example, functions.
if the Programmer displays the word
REVERSE, this chapter shows it as
REVERSE. WARNING
The Programmer's display presents an alphanumeric

readout for drive parameters, faults, and keypad inputs. Potential drive activation and inadvertent
The fault code display provides an easier alternative to equipment movement when testing, Through
the SDCC card's indicating LEDs, which must be de- the remainder of this section, do not use
coded. DIAGNOSTIC RUN, SELF-TUNE (I-TUNE
or S-TUNE), or any Programmer RUN
The display uses 6 (of 16) characters for the mnemonic, function on any application (such as crane or
where required. The number of decimal points 'm the elevator) where motion may cause injury.
mnemonic indicates the operating mode:
. One decimal indicates Operate Mode (for example,

8-4.3.1. OPERATE MODE. At powerup, the drive en-
ters Operate Mode. This activates the red and
OPE.RATE MODE) black/green keypad functions .
Two decimals indicate Parameter Mode (for ex- NOTE
ample, P.AR.AMETR_M MODE)
. Three decimals indicate Diagnostic Mode (for ex-

ample, D.l.A.GNOSTIC MODE)
Red key functions are dominant; black/
green key functions only work in Operate
Mode after (SET) has been pressed.
8-4
If a key is not activated, the Programmer briefly dis- (DEC) Press to decrease the speed at which the
plays FL41 L_KEYOFF. drive is running for any of the RUN func-
t tions.
The Operate Mode display is in the form M S.0% I
O%, where M 'indicates Manual mode (alternatively an (REV) Activates a command's reverse function:
A indicates Auto mode), S.0% indicates percentage of
rated speed, and I0% indicates percentage of rated cur- 1. Press (REV) and the Programmer dis-
rent. Note that one decimal point is used to indicate plays REVERSE.
Operate Mode.
2. Press the desired function key: (RUN),
(SLOW), (JOG), (R1), <R2>, OI
WARNING (REFFO.
NOTE
Potential drive activation and inadvertent
equipment movement when testing. Use Op- If (REV)(JOG> is pressed, the drive performs
erate Mode only as a diagnostic tool; motor the REVERSE JOG as long as Me (JOG) key
will rotate, ignoring safety circuits. Do not is pressed. When (JOG) is released, the
attempt to use (RUN), (SLOW), (JOG), (R1), REVERSE JOG function stops. However,
(R2), or (REv), (A/M). the Programmer remains in the Reverse Op-
erate mode, and displays REVERSE to so in-
Red Key Functions. In the Operate Mode, the red key dicate.
functions are used a follows:
(RESET) Resets the drive after fault or error mes-
(STOP) Controlled stop sages appear, produces a Software Reset
(DRV#) Used as part of the access code to Parame- (A/M) Auto/manual operating mode, can toggle
ter Mode between Auto (A) and Manual (M) if the
proper bit is set in EE.690
(SET) Used to enter Parameter Mode (section
8-4.3.2) and to adjust settings of various (RATIO) Not used
keypad functions, activated using the fol-
lowing steps: Black/Green Key Funcnbns. The black/green key
functions are used as follows:
1. Press (SET).
Numerals Black (O) through (9); use (SHIFT) for
2. Press either (RUN), (SLOW), (JoG), green (A) through (F), decimal point, and
(R1 ), (R2), (REFR), or (DRV#). hyphen
3. Enter the desired setting in decimal (PREV) Displays the previous (last) mnemonic en-
numbers (for example, for Drive 77, tered
enter 77 after pressing (DRv#)).
(NEXT) Displays the next mnemonic
4. Press (ENTER).
(ADDR) Displays the last address entered
NOTE
(HEX/DEC) Press to enter hexadecimal format, press
The EEPROM must be Write Enabled to again to remm to decimal format
make these adjustments (see the instructions
on changing parameters in section 8-4.3.2). (ENTER) Press to enter a value
(INC) Press to increase the speed at which the (CLEARI Used to clear a parameter
drive is running for any of the RUN func- MODE)
tions.
8_5
GEH-6005 DC2000 Digimax Adjustable Speed Drive
8-4.3.2. PARAMETER MODE. Parameter Mode allows 3. Press (DRy#).

the user to examine and change any EEPROM (E2) or
EEPROM mirror parameter addresses to customize the 4. Press (7).
drive to an application.
The next step selects either the Parameter Mirror or
There are two types of Parameter Modes: Parameter EEPROM Mode .
Parameter EEPROM Mode. Changes made to To select Parameter EEPROM Mode, press
parameters during this mode can be permanent - (7)-
changes are remembered even if power is removed
from the drive . The display shows P.AR.AMETR_E MODE.
Parameter Mirror Mode. Changes made to pa~ b. To select Parameter Mirror Mode, press (8).
rameters during this mode are overwritten by the
corresponding EEPROM address during powemp The display shows P.AR.AMETR_M MODE.
or a hard reset.
Note that the Programmer uses two decimal points in
Parameter Mode activates the same black/green key the display to indicate Parameter Mode.
functions as the Operate Mode. It also uses red keys
(STOP), (INC), and (DEC). See section 8-4.3.1 (Operate 6. Press (ENTER
Mode) for key definitions .
NOTE
Entering Parameter Mode. Figure 8-2 depicts the Pro-
grammer operating modes and steps to move between Pressing (ENTER) takes the display back one
them. Note that Parameter Mirror Mode can be entered EE address. This key also is used to change
either from the Operate Mode or from the Parameter between Parameter Mirror Mode and Pa-
EEPROM Mode. rameter EEPROM Mode.
To enter Parameter Mode: To enter Parameter Mirror Mode from the Parameter
EEPROM Mode:
1. Check that the Programmer is in the Operate Mode
(display should read M S.O% I O%). 1. Check that the Programmer displays
P.AR.AMETR _E MODE.
2. Press (SET).
PRESS
POWERUP OPERATE (sET><DRv#><7> PARAMETER
> MODE (7) EEPROM
MODE
AI
PRESS
(CLEARIMODE) 1 (8) PRESS
(PREV) r
1
PRESS
(CLEAR/MODE)
>
DIAGNOSTIC PRESS (PREV) PARAMETER
MODE MIRROR
MODE
PRESS (CLE R/MO E)
Figure 8-2. Changing Modes of Operation
8-6
2. Press (CLEARIMODE). 0
To change a parameter, use the steps in the following
1.
example.
The display now displays P.AR.AMETR_M MODE.
Example: Examine and change the minimum delay time
To remrn to the Parameter EEPROM Mode from the from RUN/JOG commanded to reference enabled.
Parameter Mirror Mode, press (PREV). Drive delay time (EE38, STRDLY) is already set at
0.25 seconds. Change it to 0.15 seconds.
Examining Parameters. To examine the present value
of any parameter: 1. Ensure that the SDCC's E2 Enable jumper (JP1) is
in the ENABLE position (2-3), and that EE.2.0,
1. Enter the 3- or 4-digit parameter address. DGNJP contains a 1.
2. Press (ENTER). 2. After examining EE.2.0, enter the following key-

strokes:
The Programmer immediately displays the address
name Zlld present contents. (CLEAR/MODE)(3X8){ENTER)
3. To examine the parameter 'm the next higher or The display shows S.TR.DLY. 25, corresponding to a
lower address, press the (NEXT) or (PREV) key. 0.25 second delay time .
This allows the operator to easily view parameters in a 3. Either press (DEC) until the display value decreases
series of consecutive addresses. to 15, or press (1 ), then (5).
To examine another parameter (not in a next address): In either case, the display shows S.TR.DLY. 15 (note
that the decimal point in this display indicates Parame-
1. Press (CLEAR/MODE) to clear the present address. ter Mode) .
The display then shows P.AR.AMETR_E MODE (the _E 4. Press (ENTER).
characters indicate Parameter EEPROM Mode) or
P.AR.AMETR __M MODE (the _M characters indicate This places the IICW value into EEPROM .
Parameter Mirror Mode).
5. Press (CLEAR/MODE
2. Enter the 3- or 4-digit parameter address.
The display the shows P.AR.AMETR_E MODE.
3. Press (ENTER).
6. To examine other addresses at this point, enter the
The address name and contents appear in the display. desired parameter address, and press (ENTER).
NOTE NOTE
To enter or view in hexadecimal format, The next step is ext:remely'important to pre

press (HEXIDEC). To return to decimal vent accidental reprogramming of the drive.
mode, press (HEXIDEC) again.
7. To seal the new parameter values, remove the I
Changing Parameters. To change parameters, two from EE.2.0, DGNIP, returning to the as shipped
conditions must endstz 0; return SDCC jumper JP1 to the write PROTECT
position (1-2).
The SDCC's EEPROM (E2) jumper IP must be in
position 2-3 for v i t e ENABLE (position 1-2 = E2 Exiting Parameter Mode. To exit Parameter Mode,
write PROTECT), press (CLEAR/MODE) two or three times, as needed (see
Figure 8-2):
l
• Parameter address 2.0, designated as EE.2.0
(DGNJP), must contain a 1 (odd value). If a 0 (even
value) is present, add a 1 and press (ENTER).
. If in Parameter EEPROM Mode, press
(CLEAFVMODE) three times.
8-7
This moves first to Parameter Mirror Mode, then to The displays shows D.l.A.GNOSTIC MODE.
Diagnostic Mode, and Finally to Operate Mode .
. If in Parameter Mirror Mode, press
(CLEAR/MODE) two times.
Exiting Diagnostic Mode. To move from the Diagnostic
Mode to the Operate Mode, press (CLEAR/MODE) once .
To remrn to the Parameter Mirror Mode from the Di-
Tbjs moves first to Diagnostic Mode, then to Operate agnostic Mode, press the (PREV) key.
Mode.
8-4.3.3. DIAGNOSTIC MODE. The Diagnostic Mode is 8-4.4. Drive Diagnostics

used to:
. Provide internal digital displays WARNING
• Run diagnostic checks

Potential drive activation and inadvertent
• Initiate self-tuning procedures equipment movement when testing. Through
the remainder of this section, do not use
This mode activates the blue and black keypad func- DIAGNOSTIC RUN, SELF-TUNE (I-TUNE
tions, with blue functions dominant, (INC) and (DEc). or S-TUNE), or any Programmer RUN
functions on any application (such as crane
Blue keypad functions include (DG S), (DGR), ( DVM ), or elevator) where motion may cause damage
(ARMV), ( ARMI), (FIELDI), (SPEED), (TORO), (Hp), or injury.
( RAM ), ( DRV#), and (TEST).
The Programmer allows an operator to run resident
Black keypad functions are the same as in Operate diagnostic tests on the drive. These tests aid in startup,
Mode (see section 8-4.3.1), except for (HEX/DEC), tuneup, and troubleshooting. To run diagnostic tests, the
which does not function in Diagnostic Mode . drive must be 'm Diagnostic Mode, as described above .
NOTE This section describes the available tests, listed in Table
8-1. Note that some tests are only available with certain
The hexadecimal numeral option (shown on hardware or software configurations.
the keys in green) is not available in Diag-
nostic Mode. 8-4.4.1. RUNNING THE DIAGNOSTIC TESTS. To Illll
diagnostic Tests 3 through 9:
Entering Dzkzgnostic Mode. To enter Diagnostic Mode:
1. Enter Diagnostic Mode as described above.
1. Ensure that the drive is in Parameter Mirror Mode
(the display shows P.AR.AMETR_M MODE) If not, 2. Press the key for the selected test.
see section 8-4.3.2.
To run diagnostic Tests 10 through 15:
2. Press (CLEAR/MODE).
1. Press (TEST). This displays T.E.S.T no.
The display immediately shows D.l.A.GNOSTlC MODE
(note the three decimal points 'm the display used to 2. Press X, where X is the number of the particular
indicate Diagnostic Mode). test to be performed.
If a particular parameter is being displayed in the Pa- 3. Press (ENTER).

rameter Mode, enter the Diagnostic Mode as follows:
To cancel a Diagnostic Test, press (PREV) OHCC .
1. Press (CLEAR/MODE
To exit Diagnostic Mode without displaying any diag-
This displays P.AR.AMETR_M MODE. nostic variables, press (CLEAR/MODE) twice.
2. Press (CLEAR/MODE).
8-8
Table 8- 1. Standard Diagnostic Tests 8-4-.4.2. DIAGNOSTIC TEST DEFINITIONS. This sec-
tion provides descriptions of the available diagnostic
I Name Description tests (listed in Table 8-1).
Test 1 (oGs). keypad selection. Do not
use. Test 3 - DVM Mode. Test 3 uses the Programmer as a
digital voltmeter (DVM) to check analog testpoints on
Test 2 (DGR), keypad selection. Do not
the drive boards.
use.
Test 3 (DVM), keypad selection. Displays The test probe wire, supplied in the miscellaneous parts
digital voltmeter.
packet shipped with the drive, connects from the test-
Test 4 (ARM V), keypad selection. Displays point to be monitored to either the NTB/3TB board's
armature voltage. testpoint DVM or to terminal 3TB-49. The DVM has
Test 5 (ARM I), keypad selection. Displays 'fixed scaling, and can measure de voltage in the i50 V
armature current in amps. range with a i0.5% accuracy.
Test 6 (FIELD l), keypad selection. Displays
field current in amps. -
Tests 4 through 9 ARM V, ARM I, FIELD I,
Test 7 (RPM), keypad selection. Displays SPEED, TORQ, HP. These tests display motor data:
motor speed (revolutions per min- armature voltage, armature current, Held current,
ute). speed, torque, and horsepower. Select the test in Diag-
Test 8 (TORO), keypad selection. Displays
nostic Mode by entering its number. Note that the test
motor torque in 1 Ib-ft. number (black label on key) and test name (blue label)
correspond.
Test 9 (HP), keypad selection. Displays
motor horsepower.
To cancel the previous test and enter a new test, press
Test 10 Displays software revision of SDCC
and SLCC microprocessors.
the appropriate key or (TEST) once .
Tests 11, Display four diagnostic variables Test 10 - Software Revision. Test 10 displays the revi-
31 (selectable): Test 1 1, in hexadecimal sion level of the SDCC and SLCC cards' microproces-
format, Test 31 in decimal format. sors: Drive Control Processor (Dcp), Motor Control
Test 12 Invokes the cell (SCR) test. Processor (MCP), Co-motor Processor (CMP), and
Test 13 Invokes the board test function. LAN Control Processor (LCP) .
Test 14 Current regulator tuneup function.
To run Test 10:
Test 15 Speed regulator tuneup function.
Test 16 Field regulator tuneup function. 1. Press (TEST).
Test 17 Motor B field regulator tuneup
function. 2. Press (1)(0).
Test 24 Same as Test 14, but test results
and calculated parameters are saved 3. Press (ENTER).
in EEPROM, rather than RAM.
Test 25 Same as Test 15, but test results The Programmer displays D. = .0.0.00 M. = oo.oo for
and calculated parameters are saved DCP and MCP, respectively.
in EEPROM, rather than RAM.
Test 26 Same as Test 16, but test results 4. P1'CSS(INC).
and calculated parameters are saved
in EEPROM, rather than RAM. The Programmer displays C. = .0.0.00 L. =O0.00 for
Test 27 Same as Test 17, but test results CMP andLCP, respectively.
and calculated parameters are saved
in EEPROM, rather than RAM. 5. Press (INC).
RAM Test Displays single diagnostic variable
(selectable).
1, -2 igital-to-analog conve or outputs.
MET1, -2 Digital-to-analog converter outputs.
8-9
The Programmer displays D. =.0.0.00 for UCP. Table 8-2. RAM Addresses * for Analog Signals
To enter a new test, press (TEST). RAM Address Signal Description

I
100 Speed feedback

To exit Test 10 press (PREV).
103 Voltage feedback
-
Tests 11, 31 Diagnostic Variable Display. Tests 11 104 CFB
and 31 display four drive variables for diagnostic use. 105 Field current
Test 11 provides hexadecimal values, Test 31 provides 1'l2 CEMF
decimal values. 140 Speed REF output
To run either test: * These addresses contain a variable that represents

an analog signal.
1. Enter the RAM addresses of the variables to be
monitored into E2 locations 110 through 113 for
DIAG1 through DIAG4, respectively. Refer to Pa- NOTE
rameter Mode, section 8-4.3.2 for procedures, and
Table 8-2 for variable addresses. Although tuneup Tests 14, 15, 16, and 17 can
be mn from the Programmer, data retrieved
2. Press (TEST). from these tests is stored in RAM and cannot
easily be saved. Therefore, tuneups should
3. For Test 11, press (1 )(1 ); For Test 31, press be made with the ST2000 Toolkit (see GEH-
<3><1). 5860) or Drive Configurator (see GEH-
6203), or by running Tests 24, 25, 26, and
4. Press (ENTER
27, which store test results in EEPROM.
The test starts and displays 1.2. aaaaH wwH for Test
Tuneups should be run in the following or-
11 OI t .2. AAAAA BBBBB for Test 31. (AAAA is the
der: Test 16, Test 14, Test 15 (or Test 26,
value of the first variable, BBBB is the value of the sec-
Test 24, Test 25).
ond variable.)
5. Press (DEC) or(INC).

Test 14 or 24 - Current Regulaztor Tuneup. To enter
this tuneup function:
The Programmer displays 3.4. CCCCH DDDDH or 3.4.
1. Press (TEST).
CCCCC DDDDD. (CCCC is the value of the third vari-
able, DDDD is the value of the fourth variable.)
2. Press (1 X4) or (2)(4).
NOTE
3. Press (ENTER).
The value displays are in 2's complement.

The Programmer displays E.N.T.R PAR1 as a prompt
Values from 0000 to 7FFF are positive (0 to
to enter a value for the first parameter (the three deci-
+32767); values from FFFF to 8000 are
mals indicate Diagnostic Mode).
negative (FFFF = -1, 8000 = -32768).
-
Test 12 Cell Test. Test 12 checks the SCR (cell).
4. To set a new Parameter 1 value:
a. Enter the selected parameter value (motor

Test 13 - Board Test. Test 13 is the board test function. number)•
Press any key during this test and the Programmer dis-
plays the key's number.
b. Press (ENTER).
To exit this test, press the SDCC card's RESET button.

5. To set Parameter 1 to the default value (0), press
(To run Test 13, the proper bit in address EE.2 must be
(ENTER).
set.)
8-10
The display now shows E.N.T.R PAR 2 as a prompt to To enter this test:
enter a value for Parameter 2.
1. Press (RAm).
6. To set the Parameter 2 value:
The Programmer displays R.A.M. EXAM/MODIFY.
a. Enter the selected parameter value (0 to run
test; 1 to perform calculation only). 2. Enter the desired RAM address _
b. Press (ENTER). 3. Press (ENTER).
7. To set Parameter 2 to the default value (0), press The display now reads D. ..1 .o4H 0
(ENTER). (XXXXXRYYYYY), where XXJIOZX = RAM address
and YYYYY = RAM value at that address. (The 51st
The Current Regulator Tuneup now starts and the Pro- letter can be D, M, or L for DCP, MCP, or LCP.)
grammer displays a tuneup message.
To alter the RAM value:
To abort the tuneup test in progress, press (STOP).
1. After the current RAM value is displayed (see step
To return to the Diagnostic Mode, press (PREV). .
3 above), enter the new value
To return to the Operate Mode, press (CLEARI 2. Press (ENTER).

MODE).
The display now shows the new RAM value, unless the
Test 15 or 25 - Speed Regulator Tuneup. To enter this Modify RAM command is disabled. In that case, the
tuneup function: display shows M.o.D. RAM DISABLED.
1. Press (TEST). To exit the RAM Test (either without changing or after
changing the RAM value):
2. Press (1X5) or (2)(5).
1. Press (PREV) or (CLEAR/MODE).
3. Repeat steps 3 through 7 of Test 14 (or Test 24).
The Programmer then displays D.I.A.GNOSTlC MODE.
-
Test 16 or 26 Field Regulator Tuneup. To enter this
regulator tuneup function: 2. Press (TEST) or (CLEAR/MODE) again.
1. Press (TEST). 8-4.4.3. DAC1, DAC2. MET1, MET2, AND MET3. The
DAC1, DAC2, MET1, MET2, and MET3 analog Olli-
2. Press (1 )(e) OI (2>(6). puts are available for test purposes. The four outputs
function identically, and are programmed similarly to
3. Repeat steps 3 through 7 or Test 14 (or Test 24). Test 11.
RAM Test - Examine/Modify RAM Location Value.

The RAM Test allows users to examine and/or modify CAUTION
the RAM locations values.
If the drive is already using the DAC1 ,
DAC2, MET1, MET2, and MET3 outputs,
WARNING
changing them may cause the drive to misop-
erate. Before entering this test, refer to the
Use caution when altering RAM values. Any drive's elementary diagrams and custom in-
change may also change the drive character- stmctions or PC software to determine this.
istic, causing the system to misoperate.
8-11
Each output has two addresses (see Table 8-3). 2. Enter the signal to be 111om'tored (from Table 8-2)
. The @I address selects the variable to be output

(EE.100 = DAC1, EE.102 = DAC2, EE.104 =
into EE.100. Putting that RAM address in EE.100
produces that signal at the NTB/3TB board's DA1
testpoint and DAC1 terminal (3TB-53) or STBA
MET1, EE.106 = MET2, and EE.210 = MET3). board's DAC1 testpoint and DAC1 terminal
(STBA-34) .
. The MX address is the maximum input value
DAC2, MET1, MET2, and MET3 function like DAC1.
(EE.101 = DAC1, EE.103 = DAC2, EE.105 =
MET1, EE.l07 = MET2, and EE,211 = MET3). When a signal's RAM address is loaded into the DAC
and MET addresses, the signal is output on the
For example, to enter this function: NTB/3TB or STBA board's testpoints and terminals
.
points listed in Table 8-3
1. In Parameter Mode, call up EE. 100-DAC@1 and
EE. 101-DACIMX (select EE.100).
Table 8-3. Diagnostic Mode Analog Output Points
Loaded Into NTBl3T8 or NTBl3TB Terminal STBA Terminal

Address STBA Testpoint Board Point Board Point
EE.100-DAc1@| & DA1 DA1 , 3TB-53 DAC 1 r STBA-34

EE.101-DAC1 MX
EE. 1O2-DAC2@l & DA2 DA2, 3TB-55 DAC2, STBA-35
EE. 1O3-DAC2MX
EE.1 O4-MET1@| & MET1 MET1, 3TB-54 MET1, STBA-36
EE. t O5-MET1 MX
EE.106-MET2@l & MFT2 MET2, 3TB-56 MET2, STBA-37
EE. 107-MET2MX
EE.210-MET3@l & None MET3, 3TB-95 Not available
EE.21 1-MET3MX
8-12
DC2000 Digital AdjuStable Speed Drive GEH-6005
I CHAPTER 9
TROUBLESHOOTING
9-1 • INTRODUCTION These troubleshooting instructions require the standard

tools used when working with electrical equipment.
This chapter provides specific information to help detect Additionally, the following instruments and references
and correct problems with the DC2000 Digital Adjust- shoind be available:
able Speed Drive. This chapter is organized into three
primary sections: . Oscilloscope
General Troubleshooting. This section covers prob-

lems that have no associated fault or error indica-
. Megger
tion, or that cannot be Fixed using the standard fault • Volt-ohm-milliammeter (VOM)
system.
Stability Problem Troubleshooting. This section de-

. Bench vise or heavy-duty C clamp
fines three types of stability problems: cyclical • Renewal Parts Listing
stability problems, mechanical oscillation prob-
lems, and erratic operation problems.
Hardware Summary
Specific Fault Troubleshooting. This section defines
drive faults detected by drive diagnostics and indi- • Elementary diagrams
cated as error codes. Table 9-5 at the end of this
chapter defines these error codes. • IBM PC AT or compatible computer equipped with
ST2000 Toolkit or Drive Con6gurator, LynxOS
SCR Bridge Troubleshooting. This section provides Version (see Chapter 8)
assistance in troubleshooting SCR bridge failures
identified by diagnostic error codes.
WARNING
WARNING
To prevent electric shock, ensure that all
power supplies to this equipment are turned
This equipment contains a potential hazard off. Then ground and discharge the equip-
of electric show or bum. Only adequately ment before performing any adjustment,
trained personnel who are thoroughly famil- servicing, or other act requiring physical
iar with the equipment and the instructions contact with the electrical components or
should maintain this equipment. wiring.
9-2. TOOLS AND INSTRUMENTS 9-3. GENERAL TROUBLESHOOTING
NOTE Table 9-1 outlines the general problems that may occur
with the DC2000 drive. Table 9-2 contains the possible
All tools and instruments used to touch elec- solutions for each problem listed in Table 9-1.
trical components should be insulated and
grounded to meet National Electrical Code
(NFC) standards.
9-1
Table 9- 7. Troubleshooting Ouick Reference Guide
Type of Problem Problem Reference in Table 9-2
Drive faults, LED indication 1. All diagnostic LEDs off

2. All diagnostic LEDs on
3. Fault messages displayed (repetitive)
4. Fault messages displayed (non-repetitive, random)
Programmer problems 5. Programmer display off

6. Error messages displayed
7 . Programmer ineffective, no errors displayed
8. Parameter changes ineffective
9. Diagnostics do not perform
Fuse blowing, MOV failures, and board failures 10. Fuse blowing (ac power fuses)
11. Power supply fuses blowing
12. MOV failures
13. Repetitive board failures
14. Line voltage problems
Operational problems 15. 24 V logic not operating properly

16. Drive/motor does not run
17. Drive runs in the wrong direction
18. Drive does not reverse
19. Drive speed is incorrect
20. Serial link does not function properly
21. Erratic operation
22. Stability problems
23. Signal-level detector chatter
24. Too much coast time on deceleration (regenerative
drives)
Motor problems 25. Motor runs hot

26. Motor audible noise
27. Motor vibration
Improper EEROM/EEPROM rewrites at 28. EEROMIEEPROM rewrites

powerup or reset
Noise, wiring, power supplies, and similar problems 29. Noise or random nuisance faults
30. Wiring procedures
31. Checking power supplies
9-2
Table .9-2. Genera/ Troubleshooting Chart
Problem Correction Procedures

I
1. All diagnostic LEDs off 1. Check Programmer display for drive fault (if used).
2. Check for 3-phase ac input.
3. Check for open ac line fuses (FU1 through FU3) or breaker.
4. Check for open fuses on DCFB or SDCI board.
5. Ribbon cable(s) disconnected, open, loose, or intermittent.
6. Power supplies loaded down or failed - refer to Problem 31 (Checking power sup-
plies)-
7. Use Programmer to attempt to enter the Parameter Mode (see Chapter 8). Refer to
Table 9-5 if any fault codes are detected. A hard reset should clear this lockup con-
dition.
8 . Replace SLCC card firmware.
9. Replace SDCC card firmware.
2. All diagnostic LEDs on 1 . Drive faulted - check fault code list (Table 9-5).
2. NTB/3TB or STBA board's RESET point ¢3TB-58 or STBA-38) connected to + 5 IO
+ 24 v do.
3 . Replace SLCC card firmware.
4 . Replace SDCC card firmware.
3. Fault messages displayed (repetitive) 1 . See Table 9-5, Specific Fault Troubleshooting, for troubleshooting procedures related
to specific drive fault number.
4. Fault messages displayed (non- 1. See Problem 29 (Noise or random faults)-

repetitive, random) 2. See Problem 30 (Wiring procedures).
5. Programmer display off 1. Check that all plugs are connected properly.
2. Check power supplies - see Problem St (Checking power supplies).
3. Replace SLCC card firmware.
6. Error messages displayed 1. See Table 9-5, Specific Fault Troubleshooting, for troubleshooting procedures related
to specific error message.
7. Programmer ineffective, no errors dis- 1. Check that all plugs are connected properly.
played 2. Check jumpers on SLCC card for proper position.
3. Check that the drive is in Auto mode. This mode inhibits certain mode references.
8. Parameter changes ineffective .

1. Check SDCC card's Write Protect jumper, JPl JP1 must be in the 2-3 or ENABLE
position for programming.
2. Check setting in EE.2.0 (DGNJP) - must contain a "1 " to allow reprogramming.
3. If the drive uses multi-motor operation for different gear ranges, spindle orient, and
so on, verify that the proper motor parameters are being adjusted. Check by setting
to 10 the IOC trip setpoint of the motor parameters being adjusted. Starting the drive
causes and IOC fault if the proper motor parameters have been adjusted.
4. Check Problem 7 (Programmer ineffective, no errors displayed).
6. Replace SDCC card firmware.
9. Diagnostics do not perform 1. Check thatthe particular function is available - refer to the Custom Software, soft-
ware jumper descriptions.
2. Check the SDCC card's jumper JP1. JP1 must be in position 2-3 for some diagnostic
tests to work. Refer to Programmer information in Chapter 8.
3. Check the NTB/3TB board's POL point (3TB-38) or the STBA board configurable
discrete input used for polarity select for reverse signal.
4. Refer to Problem 7, (Programmer ineffective, no errors displayed).
9-3
Table 9-2. Genera/ Troubleshooting Chart Continued
. Compare the fuse size with the Renewal Parts List.

I
10. Fuse blowing (ac power fuses) 1

2. Check for out-of-tolerance or sagging ac line voltage on regenerative drives refer to -
Problem 14 (Line voltage problems) and Problem 29 (Noise or random nuisance faults).
3. Using a megger, check for a ground in motor circuit or blower circuit. (Observe applica-
ble WARNINGs and CAUTIONs.)
4. Check to see if drive is being forced into current limit by an overhauling load.
11. Power supply fuses blowing 1 . Check that the fuses are the correct size.
2. Check for any shorted or overloaded power supplies. Refer to Problem 31 .
3. Replace the DCFB or SDCI board.
12. MOV failures 1. Refer to Problem 14 (Line voltage problems).

2. Motor fault causes ac fuses to open during regeneration. Check for grounded armature,
field, or wiring.
13. Repetitive board failures 1. Check all connections at all terminal boards.
2. Check that all ribbon cables and plugs are connected properly (for example, not offset by
one row or pin)-
3. Check stab terminal connections on the DCFB or SDCI and PCCA or PC boards. _
4. Check that all voltages (incoming ac and internal do) are correct.
5. Check for moisture.
6. Check for damage caused by airborne chemical contamination.
14. Line voltage problems 1. Check that the line voltage is within drive specifications, -5 to + 10%.
2. Check that the ac line voltage is balanced line-to-line and line-to-ground.
3. Check for ac line notches or spikes.
4. Check that the ac line frequency is within ii Hz of rated.
5 . When the ac line is supplied by a diesel-driven alternator, check for changes in line fre-
quency during drive acceleration or regeneration.
6. Check for more than 1-1 /2 cycles of ringing following commutation notches in the ac line
caused by the drive. Amplitude should be s 200 V.
7. Check for an ungrounded secondary on the power system transformer directly in front of
the drive, if used. (The transformers are generally a delta/wye type with the neutral of
the Wye grounded through a high resistance or directly to ground.
15. 24 V logic not operating properly 1 . Check the i24 V do power supplies.
2. Check the logic polarity control jumpers per the Custom Software.
3. Check control logic connections at the NTB/3TB or STBA board.
4. Check for proper polarity and common circuit if the i24 V de supply is from a source
other than the drive.
5. Check that the drive is in the proper mode (O, 1, 2, or 3) for the particular motor or
function being operated.
16. Drive/motor does not run 1. Fuses open (or optional circuit breaker open).
2. Fuses open on DCFB or SDCI board.
3. Check all hardware and software jumpers per the Custom Software.
4. Check control logic voltage and state, and power supply voltage levels at theNTB/3TB or
STBA board.
5. Check that the drive is in the proper operate mode (Auto, Manual, etc.).
6. The drive may be stalled in current limit.
17. Drive runs in the wrong direction 1. Check for the logic signal at the NTBl3TB board's POL point (3TB-38) or the STBA con-
figurable discrete input used for polarity select.
2. Armature connections are reversed (correct armature and tech leads)..
3. Check all software and logic polarity control jumpers per the Custom Software.
4. Check the reference polarity.
5. Check the Custom Software to verify that the reverse function is enabled when operating
from the serial link.
9-4
Table 9-2. Genera/ Troubleshooting Chart - i i

Continued
18. Drive does not reverse 1. Check that the drive is regenerative.
2. Switch any two output leads.
3. Check the reference polarity.
4. Check control logic to the NTB/3TB board's POL point (3TB-38) or STBA configur-
able discrete input used for polarity select, if used for reversing.
5. Check the logic polarity control jumpers per the Custom Software.
6. Check the Custom Software to verify that the function is enabled when operating
from the serial link.
19. Drive speed is incorrect 1. Check that the motor design is suitable for the application.
2. Check that the proper reference is enabled per the Custom Software.
3. check for proper reference scaling.
4. Check for noisy tech signal. Refer to Problem 30 (Wiring procedures).
5. Check that the drive is not in current limit.
6. Check that the drive is not in voltage limit.
7. Check that the tech scaling parameters are set correctly.
20. Serial link does not function properly 1. Check that all required jumpers to enable function are set properly.
2. Check the drive's baud rate compared to serial link device (a hard reset is required
following a change in baud rate).
3. Check serial link connections at the NTB/3TB or STBA board.
4. If RS-422 is used, verify that the handshaking lines are properly connected. Check
that the sending device is responding to the drive's DTR signal (low level) when the
device transmits to the drive.
5. Replace the SLCC card.
21. Erratic operation 1. Check power supplies for magnitude and ripple - refer to Problem 31 (Checking
power supplies).
2. Check connections on all ribbon cables.
3. Tighten all connections on terminal boards and all power connections.
4. Confirm correct hardware jumper settings per the Custom Software.
5. Check all parameters per' the software test data sheets in the drive door or Custom
Software.
6. Check for noisy ground connection - refer to Problem 30 (Wiring procedures).
22. Stability problems 1. Check settings of all parameters per the software test data sheets in the drive door
pocket.
2. Check that all contacts on the MA contactor are closing.
3. Refer to section 9-4 (Stability Problem Troubleshooting).
23. Signal-level detector chatter 1. Is signal-level detector looking at a noisy signal (for example, tech feedback?
2. Is enough hysteresis programmed into the appropriate parameter address?
24. Too much coast time on deceleration 1. Check settings in the Custom Software and confirm that regeneration is enabled.
25. Motor runs hot 1. Motor may be overloaded: check for mechanical problems.
2. Check the motor winding temperature. If the motor has Class F insulation and the
winding temperature is less than 130 °C (260 °F), this is normal.
3. Check the rotation of the motor blowers.
4. If the motor runs hot at very low speeds, check the motor application guide for full-
torque speed range.
26. Motor audible noise 1. Unstable regulator - check Problem 22 (Stability problems).
27. Motor vibration 1 . Coast Stop Drive - if the vibration is electrically induced, the vibration disappears. If
it does not disappear, check for mechanical causes.
2. Refer to Problem 22 (Stability problems)-
3. The motor is not mounted level.
4. The motor base is vibrating.
9.5
Table 9-2. General Troubleshooting Chart - Continued

I
28. EEROM/EEPROM rewrites 1. The SDCC card's jumper JP1 must be in the t-2 position during powerup or hard reset.
29. Noise or random nuisance faults 1. Check that the + 5 V de supply is not used externally.
2. Check for suppression on all relays, contactors, and starters.
3. Check all power supplies - refer to Problem 31 (Checking power supplies).
4. Refer to Problem 30 (Wiring procedures).
30. Wiring procedures 1. Check the wire sizes on the ac power connections.
2. Check that the control wires (24 V do, 1 1 5 V ac) do not run in the same conduit or run
parallel closer than 4 inches to the power wires, causing noise pickup.
3. Check that all signal wires (such as tech, encoder, reference, load cell, or RS-232C/RS-
422) are twisted-pair, shielded and that shields are grounded at the drive end only.
4. Check that signal wires are not grounded at more than one end or other than the drive
end only.
5. Check that the signal wires do not run in the same conduit, parallel, or closer than 4
inches to the power wires.
6. Check that there is only one system ground.
7. check that the ground bus is large enough to prevent voltage drops or noise pickup.
31 . Checking power supplies 1. Check the + 1 5 V testpoint for + 15 V de, i5%. Verify with an oscilloscope that there is
less than or equal to 100 mV of ripple.
2. Check the -15 V testpoint for -15 V do, :t5%. Verify with an oscilloscope that there is
3. Check the + 5 V testpoint for + 5 V do, i5%. Verify with an oscilloscope that there is
9-4. STABILITY PROBLEM TROUBLE-SHOOTING 9-4.1. Cyclieal Stability Problems
Because of their similar behavior, this manual classifies This category includes hunting, oscillations in speed or
three broad categories of drive problems as stability current, and similar problems. Generally, these are
problems: characterized by cyclical, well-defined sinusoidal oscil-
lation periods.
Cyclical stability problems
Usually, cyclical stability problems are electrically in-
Mechanical oscillation problems duced. They can be corrected with proportional and
integral gain adjustments .
Erratic operation problems
Most DC2000 drives have at least three regulating
Technically, the last two of these are not true stability loops:
problems. They are included in this section as stability
problems because they share the characteristics of oscil- Current regulator, continuous current
lations or tlucmations 'm the drive.
Current regulator, discontinuous current
This section also discusses troubleshooting of stability
and other problems caused by phase differences be- Speed regulator
tween the ac line power brought to the DCFB or SDCI
board and that brought to the field and/or armature If any of these are mistuned, stability problems can oc-
bridge. Problems caused by such phase differences can cur under the right conditions.
be resolved by setting parameters contained in the
SDCC EEPROM .
9-6
NOTE 0
• DC2000 drives are almost always stable.
I Various forms of position regulators are also

available. Because of their variety, this sec-
. Most stability problems, but not all, are corrected
by adjusting speed loop parameters .
tion cannot address them.
In general, when troubleshooting cascading or se-
ries regulating loops, the correct procedure is to
9-4.2. Mechanical Oscillation Problems stabilize the regulators in the following order:
These are mechanical deficiencies that, under certain 1. Inner regulator

conditions, can be aggravated or excited by electrical
frequencies. For example, such problem include vibra- 2. Current regulator
tion, audible noise, and gear chatter.
3. Speed regulator
9-4.3. Erratic Operation Problems 4. Position regulator (if furnished)
These are intermittent speed or current fluctuations, NOTE

mechanical bumping, or other non-sinusoidal or non-
periodic disturbances. Such problems can be induced If any of these steps stabilize the drive, rec-
by intermittent grounds, noise, or mechanical problems . ord any parameter changes and do not con-
tinue with the remaining steps.
9-4.4. Troubleshooting Procedures

9-4.5. Ac Line Phase Problems
NOTE
For the drive to operate properly, the ac line inputs to
I The parameter checks and adjustments re- the armature bridge must be in phase with the ac line
quired in this section require use of the Pro- sync signal to the DCFB or SDCI board, or phase dif-
grammer. ferences must be compensated for using parameters
stored in the SDCC EEPROM. Problems caused by
9-4.4.1. INITIAL CHECKS. Before troubleshooting the phase differences between these inputs include:
drive for stability problems using Table 9-3, check the
following conditions: • Armature SCR failures
1. All software jumpers match the drive parameter list • SCR test failures (opens or shorts)
(see Chapter 8).
2. A11 hardware jumpers match the jumper selection

. Loss of stability (speed, current, or field regulation
problems)
tables (see Chapter 5).
3. A11 software parameters match the parameter list

. Advance limit too low (cannot achieve rated arma-
mre voltage)
(see Chapter 8) .
4. All wiring is correct and agrees with the drive ele-
. Retard limit too high (cannot regulate zero
speed/volts)
mentary diagrams.
9-4.4.2. PROBLEM DETERMINATION. Use Table 9-3 to

• Fault 22 (PHASELOS) when EE.l87 has a value of
determine the type of problem, keeping the following zero
pointers in mind:
9-7
EEPROM parameter EE.558 (ASYADJ) adds a fixed For example, assume that the Ll, L2, and L3 inputs to
angle offset to the armature tiring circuit to compensate the DCFB or SDCI board for the line sync PLL are
for phase differences between the ac line sync input to connected to phases A, B, and C, respectively. If the
the DCFB or SDCI board and the ac line input to the L1, L2, and L3 inputs to the armature bridge are con-
armature bridge. The default value of ASYADJ is 0. nected to C, A, and B, respectively (lagging the line
The range of possible values is -12000 to 12000, where sync phasing by 120 degrees), set ASYADJ to 10922
16384 corresponds to 180 degrees. A positive value is (120/180 x 16384). If the armature bridge inputs are
used if the armature phasing lags the line sync phasing, connected to B, C, and A, respectively (leading the line
a negative value is used if the armature phasing leads sync phasing by 120 degrees), set ASYADJ to
the line sync phasing. -10922.
Table 9-3. Stability Troubleshooting
Symptoms Procedures
I
1. Unstable when unloaded, but stable 1. Adjust auto-tune parameters then re-run auto-tune.
when loaded; drive is stable but indi-
2. If instability still exists. return adjusted parameters to their
cates gearbox or motor noise, or runs
original settings and skip to Symptom 4.
erratically
2. Speed instability below base speed 1. See Custom Software for gain changes in speed loop.
2. If no improvement, return the adjusted parameters to their
original settings.
3. If there is some improvement, but instability still exists. docu-
ment changes and skip to Symptom 4.
3. Speed instability above base speed 1. See Custom Software for gain changes in stability parameters.
2. If no improvement, return the adjusted parameters to their
original settings.
3. If there is some improvement, but instability still exists. docu-
ment changes and skip to Symptom 4.
4. Drive is unstable: 1. Check that the problem is not tech related. Correct the tech
- over a small part of the speed feedback problem (misaligned or loose coupling, belt slippage,
range, wiring, or excessive ripple).
or when loaded but stable when
2. With an oscilloscope, check that the power supplies are clean
unloaded,
(refer to Problem in Table 9-2).
or such that oscillating frequency
is proportional to speed 3. Run the drive to top speed and push the SDCC's RESET but-
ton. The drive then coast stops. Mechanically induced prob-
lems will still be present as the motor slows down. If the
problem disappears, continue to next step.
4. Determine resonant frequency Fr in Hz with an oscilloscope, if
possible. Convert to radians per second as follows:
Wr = 6.28 x Fr
5. If no improvement, return the parameters to their original set-
tings and skip to Symptom 6.
5. Unidirectional stability problems 1. Inspect the load to ensure that nothing is wrong mechanically.
e. Additional procedures - if these pro- If the above procedures do not stabilize operation, additional steps
cedures are required, contact: may be required, including:
GE Drive Systems & Turbine Controls
1. Checking out the current loop.
Product Service Engineering
Phone (540) 387-7595 2. Running the 'field regulator open loop to verify stability.
9-8
9-5. SPECIFIC FAULT TROUBLESHOOTING . PalMs 400 to 1023

faster blink rate
9-5.1 . Fault Indication binary pattern (left-most LED is 29 [or 512],
second-most LED is 28 [or 256], and so on; see
The DC2000 drive software includes selftest diagnostics Figure 9-2)
to aid in troubleshooting. When the drive detects a
fault, it outputs error (fault) codes to indicate the
problem. Table 9-5 defines these fault codes. Diagnostic LEDs
NOTE
Fault code definitions may change with

product upgrades and revisions. The fault
codes presented in Table 9-5 are current as
0000000000
\ 28 (or 256)
of the issue date of this manual. The ST2000
Toolkit or Drive Configurator, if purchased 29 (Or 5 1 2 )
with the drive, contains current fault code Figure 9-2. Binary-coded LED Display
definitions as of the date the equipment was
manufactured.
The drive displays the fault codes on both the Pro-

. No fault or drive not running
- sequential blinldng, two at a time
grammer and the SDCC card's LEDs. Although the - blinldng from outer positions inward to center,
Programmer's display is easier to read, the LEDs pro- and back
vide a backup, if needed. Additionally, the drive can
broadcast these codes via an optional serial data link. These same LEDs can be set by software jumper to also
coarsely display drive variables when running. (For
9-5.1.1. PROGRAMMER DISPLAY. The Programmer
example, displayed in an absolute or signed bar graph
includes a digital display that shows a fault message mode). However, this setting does not inhibit the LED
(fault number and name). Table 9-5, located at the end fault display.
of this chapter, defines these faults by number.
9-5.1.2. LED DISPLAY. Diagnostic LEDs display codes 9-5.2. Types of Faults
either BCD (binary coded decimal) or binary, depend-
ing on the fault number. They indicate the faults 'm a Table 9-5 lists and describes the DC2000 drive faults.
blinking mode, as follows: There are nine types of faults with the following charac-
. Faults 1 to 399
- slow blink rate
teristics (see Table 9-4):
1. Trip faults. Trip faults are internal protective

- BCD pattern (left-most two LEDs encode the conditions. When detected, they immediately shut
hundreds digit; next four, the tens digit, right- down a running drive. The drive cannot be re-
most, the units digit, see Figure 9-1) started until externally reset, via either a hardware
(hard) reset or a software (soft) reset, as described
in section 9-5.3.
Diagnostic LEDs
2. Filtered faults. Filtered (Pending) Faults are the
DH M00% I
same as Trip Faults with one exception: they must
continue for a time period before the drive shuts
down. These faults are used to minimize nuisance
trips caused by momentary noise glitches when a
I I
shutdown can be slightly delayed without hazard.
hundreds tens units
digit digit digit
3. Non-latched Annunciated Faults. These faults
Figure 9- 7. BCD-coded LED Display report conditions that should be noted, but that do
not need to shut down the drive. However, until
corrected, these faults inhibit a drive from starting.
9-9
If the fault condition disappears, these faults gen- Some faults are configurable, that is, the fault type can
erally clear automatically without requiring a hard be configured by the user. The fault type is selected
or soft reset. using a software jumper stored in EEPROM .
4. Lathed Annunciated Faults. These are the same
as Non-latched Annunciated FaiNts, except that a 9-5.3. Clearing the Fault
hard or soft reset is required to clear them.
There are several ways to reset the drive controller to
5. Brief Faults. To the user, these are the same as clear a fault. A software (soft) reset can be executed
Non-latched Annunciated Faults. The difference is from the Programmer, or by serial command from a
internal to the computer . device connected to the serial link. A hardware (hard)
reset can be executed by pressing the RESET pushbut-
6. Locked Faults. Locked Faults are Trip Faults of a ton on the SDCC card, or by momentarily interrupting
serious nature and cannot be cleared by a soft re- incoming power to the drive .
set. To clear the fault, the condition must be fixed,
then a hard reset performed. Table 9-4 shows the types of resets that clear the
DC2000 drive faults. A soft reset adequately clears
7. Trip States. Trip States are similar to Trip Faults, most latched faults. However, some types of faults
except that they report on conditions external, should be cleared by a hard reset.
rather than internal, to the dive.
NOTE
8. Filtered States. Filtered States are similar to Fil-
tered Faults, except they report on conditions ex- A soft reset displays all faults in the fault
ternal, rather than internal, to the drive . stack, and should be performed instead of a
hard reset, whenever possible. If a soft reset
9. Non-latched States. These are similar to Non- does not seem to restore the drive to normal
latched Annunciated Faults, except that they report operation, use a hard reset.
on conditions external, rather than internal, to the
drive .
NOTE
The type of fault determines how it is

cleared.
Table 9-4. Summary of Fault Types
Drive Shutdown Reset to Clear Fault

Fault Type Internal External No Immediate Delayed Hard Soft Automatic
Trip fault J / J J
Filtered Fault J J J J
Non-latched J _ - J J
Annunciated Fault
and Brief Fault
Latched J ...- J - J J
Annunciated Fault
Locked Fault J - » J J
Trip State J J J J _
Filtered State J J J J
Non-latched State . J _ J - _.- J
9-10
9-6. TROUBLESHOOTING SCR BRIDGE FAILURES

CAUTION
The following sections provide instructions for trouble-
shooting SCR bridge failures identified by diagnostic
error codes. These procedures are intended to assist the If a megger is used to measure SCR cell re
user in identifying the failed SCR cell and the failed sistance, a megger voltage greater than 500
component (SCR or snubber capacitor) in the cell. Fig- V, or failure to remove all connections to the
ures 9-3 through 9-9 show the SCR bridge assemblies SCR cell stack and armature circuit can
for C, CX, G, J, K, and M frame drives. (These draw- damage other drive circuits and/or external
ings were produced from the hardware drawings pro- components•
vided in the door pocket of each drive, and included in
Appendices B through D.)
9-6.1. C, CX. and G Frame Troubleshooting
As described 'm Chapter 8, diagnostic Test 12 tests the
drive's SCR bridge, checldng each SCR cell for short For a C (see Figure 9-3), CX (Figure 9-4), or G (Figure
circuits and opens. The following sections provide pro- 9-5) frame drive, use a VOM to measure the resistance
cedures for using a VOM to measure the resistance of between the following points:
an SCR cell to check for show circuits or opens .
For a reversing drive:
Each output leg of the SCR bridge includes a de resis-
tor/capacitor snubber circuit connected across the SCR Measure the
To check:
cell. The procedures include information to identify resistance between:
whether a short circuit is caused by a shorted SCR or a
shorted capacitor in the do snubber circuit. TM1 T1A and P1(+)
TM2 T2A and PI ( + )
A megger should not be used to perform in-circuit re- TM3 T3A and PI ( + )
sistance checks of the SCR cell. If a megger is used, do TM4 T1B and P2(-)
not exceed 500 V. Remove all connections to the SCR
TM5 T2B and P2(-1
cell stack and armature circuit so that only the resis-
tance of the SCR and de snubber circuit is measured. TM6 T3B and P2(-)
.I
REVERSING SCR'S
I I|
| +
I
:
.I
m
l NDN-REVERSING $CR'Sl
I
n 6
T1A l
II
I TaA
'c
I IT8,*l1
I
l + I
|.
NON-REVER*SING SCR'S
in I A
T3A l
I I I f\o I I
o (D o
P1(+)
0(3) ITTAII IT§AII ITSAII I c1>o P1(+) I 0(3) I
o o o
I I 1 I
o
I= TM1 n r TM2 1 llTM3nl
I (no p1(+) o<3> | | (1>o p a - a i P 0(3) I
I PL
l=T"1»Q1 I TM3
Rv
V ~ 8
FPL 4RpL2FPL 5RpL3FPL 6RPL W/§!§ 1 (l>° p a - > o 0(3> l
®
Tl-ISV
®
THsv
SW of § w _8 RB
THSW THSV
1an TM1 ii ,
TMS
I in TM3 vol 190' 170' 6 FPL FPL
R
3FPL SFPL
® ®
o RW f$ in lw B -§-R be% % rim I I I§-IBI I IT38
6 ~19rJ°. * nu' 1FPL 4+-pEFPL srpL3FPL 6FPL I I
I
T1:B I IT2B IT3nl | o(1> o 0(3) o

l
r o <1>
I
o
I r o<3> o
pa-)
o o
TM4 nu TM5 .TMe
l
o
P2(-)
o o a ' ,we /Q"i lw Jul.
Tm4,¥l
`w pa
TM5 TM6
1RPL 4FpLeNPL 5FpL3RPL srpL qq
Ta(n
JQB
IW a R RW
R R w -( R R
IRPL
4%pBL2RPL 5BFpBLBRPL #EIT I FAN ~ FPL SFPE
I-7gure 9-3. SCR Bridge Assemblies, C Frame Drive Figure 9-4. SCR Bridge Assemblies, CX Frame Drive
9-11
t?)"I'l"l
REVERSING SCR'S NDN-REVERSING SR'S
4FPL 1FPL 5FPL 2FPL SFPL 3FPL
4FPL 1RPL SFPL ERPL 6FPL 3RPL
go;Rllw IQ% RSZv R
4RPL
v a
8
FPL 5RPL EFPL 6RPL 3FPL
)¢Rl;wB9\§R w§lzR
liw
v m REV 2% »=$2w w
3
,or w I `\ 'l I'or or or '1f w '1 `\
o o o o o o I
I o(1> o PE(-) O(3)l
o (1)
pa(->
o (3>o o (1)
P1(+)
o (3>o I I
I I l
o P1(+>
l
l
o(1) 0(3)l
o
T1B
TM4
l o
TEB
TMS
o
T3:B
TM6
o
TIA
TM1
o
T2A
TME
o
T3A
TM3 o
T1A
o
TEA I o
T3A
EJ EJ I: TM1 Tea TM3
(. >
I
l
FAN FERRITE
C RE ASM
( lArI »
Figure 9-5. SCR Bridge Assemblies, G Frame Drive
For a non-reversing drive: For a revelsing drive:
To check- Measure the To check: Measure the

resistance between : resistance between:
TM1 T1A and P1(+I; 1F, 4R K1 and ( + ) heatsink;

T1A and p2(-) 1R, 4F K1 and (-) heatsink
TM2 T2A and PI ( + ) ; 2F, 5R K2 and ( + ) heatsink;
T2A and P2(-) 2R, 5F K2 and (-) heatsink
TM3 T3A and P1(+); SF, 6R K3 and ( + ) heatsink;
T3A and P2(-) 3R, 6F K3 and (-) heatsink
For each measurement, the resistance should be greater For a non-reversing drive:
than 1 MQ. Lower resistance values may indicate ex-
cessive leakage current in the SCR. A resistance of ap- Measure the
To check:
proximately 20 to 40 Q indicates that the corresponding resistance between :
de snubber capacitor may be shorted, a resistance of
less than 5 Q indicates that the SCR cell may be IF K1 and ( + ) heatsink
shorted. 2F K2 and ( + ) heatsink
3F K3 and ( + ) heatsink
NOTE 4F K1 and (-) heatsink
5F K2 and (-) heatsink
To prevent externally connected devices
6F K3 and (-) heatsink
from affecting the resistance measurements,
it may be necessary to remove fuses FU1,
FU2, and/or FU3, and to disconnect loads For each measurement, the resistance should be greater
connected to output lines P1 and P2. than 1 MQ. Lower resistance values may indicate ex-
cessive leakage current in the SCR(s). A resistance of
approximately 20 to 40 Q indicates that the correspond-
9-6.2. J, K, and M Frame Troubleshooting ing do snubber capacitor may be shorted, a resistance of
less than 5 Q indicates that the SCR cell(s) may be
For a J, K (see Figures 9-6 and 9-7), or M (Figures 9-8 shorted.
and 9-9) frame drive, use a VOM to measure the resis-
tance between the following points:
9-12
NOTE To test an unmounted press pack, place it 'm a clamping

fixture to ensure that the encapsulated SCR makes con-
To prevent externally connected devices tact with the external case conducting surfaces. The
from affecting the resistance measurements, compression force can be applied using a bench vise or
it may be necessary to remove the corre- heavy-duty C clamp.
sponding de leg line fuses, and to disconnect
loads connected to output lines P1 and P2.
CAUTION
Note that the SCRs used in J, K, and M frame drives
are press packs. A11 internal interfaces of a press pack
are pressure contacts that require at least 100 pounds of
When compressing a press pack SCR, use
force to make contact. care not to mar the external mating surface.
C RE PANEL (FRDNT IE DD RS IJPEN)

I
• • pa->
_
I
I
I
I 'P REAR BUS
I
I l l Pl(-v-J
?
T 0 FRDNT BUS
I
I
l
a
I
I L11, I I
Fual
I
1 1 l FUEL
I I L15 1 I
FU23 I l
I
|
i I I I
SMALL REACT R
I
I
M c1> 5 L12 I (1> I L14 I (1) I L16
.I
I
I i
I
4 I
l I L .1
I I
I
I
I
l
I
I' l 1
l LARGE REACTUR
!
(2) (2) (a>
I
1
II r -
_
I
I
I
I
I
I
I
I
FU a 41 FU 7 1 8 FU 9 10 11 12 DC LEG FUSE
I
I
I
I
I
I
K1L KEL K3L
I
I
I
I R3l:LR3l,R32
I
I
I
I
(-> (+) (-) (+) c-> <+) I DC SNUBBER
I
I
I
PHASE 1 PHASE 2 PHASE 3 RES=
I
I
I SCR SCR SCR (SERIES C NNECTED)
I
1
I
1
I
I
I
SHVI
SHVI
I
I
I
CARD
CARD
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I K1 lKa K3 LTD
I
fT~
I
I
FR NT BUS
I 1
I
I
I
I
I
I
I
I
<-
I
I
I MIDDLE BUS
CT1
re
|
I
I
I
I
I
I
REAR BUS
I
I
1
I
!
I
<-
I
I
L - - - - - - - Z - $ - - - Q ¢ ¢ q - _ - - s -- $ _ - ¢ - - - # t d - § 9 ¢ - _ - - I - 1 - - - _ : Q u - Q - - : t - ¢ - - _ ¢ ¢ .
Figure 9-6. SCR Stack Connections, J and K Frame Drives
9-13
TYPICAL REVERSING 'SIR BRIDGE (FR NT VIEW)
' - - - - - - - - c E L L - - - - - - - - - " CELL - - - - - - - - - - - c E L L - - - - - - - - ' I

I
RES RES RES I
c ) Q 2 C+) c > 2 C+) (-> S 2 (+>
I
I
I
I
I
m
I
I
V
1R 2R EF
Q Q
IF 3R 3F I
.
I
I
I
f
u H I N I
I
QT; up
I
2TSV 1Tsw 2Tsw 1Tsw
I QUO Q 52
I
I
I
I
I
r 4 > 14 N H
I
I
I
4F E A 4R 5F E é 5R 6F E é ER
I
I
I
I
I
I
K1
PHASE 1 SCR
K2
PHASE 2 SCR
K3
PHASE 3 SCR
:
1
I
L..___...__......______.._____________......__..._______._.____.______I
TYPICAL N N-REVERSING SCR BRIDGE KFRDNT V I E W )

1 '--------
1 C E L L - - - - - - - - - - - - - C E L L - - - - - - - - " - - - c E L L - - - - - - - - - 'I
I I
I RES QED RES l
I I
I (-) (+9 (-> (+) ( ) C+)
I
I d : I
I
I e. :1
I
I
I
I
IF or - :as I
I
I
I I
I I
=
I 1Tsw 1TS'w' 1T'SW I
I
D II E
I
I _ l
m
I
I v
l
I
I
I I
PI v I N I
I
I I
I I
I aTsw 2Tsw aTsw I
I I
I
I
I
D D D I
I
I
I
I
4F E 5F° 6F I
I
I
I
I
I
K1
PHASE 1 SCR
KB
PHASE 2 SCR
K3
PHASE 3 SCR
:
l
1
L__..._.___,...__....._.__.____...__..________.._....._..__,_______.____.._.____1
Figure 9- 7. SCR Stack Assemblies, J and K Frame Drives
9-14
CT1
I CT3
re
IK1 K2 K3
PT < >
• 0
p1(+>
I SMALL
l
[TQ aL 4 I ILe |
.
REACTIJRS
. FLI I
LEG
FUSES
T'
ll<1 l(+> Ke C+) H K: c+>
PHASE 1 PHASE 2 PHASE 3
§HvM~cAF§D
SCR SCR SCR
(SIDE v1Ew> (SIDE VIEW) (SIDE vIEw
-
(-> II-)
FU
3 é r I
q
• I
Q
l
L11
.
L15
i o pE( -)
Figure 9-8. SCR Stack Connections, M Frame Drive
9-15
'-.gm
TYPICAL REVERSINC1 SCR BRIDGE (LEFT SIDE VIEW)

l'
K1 C+) Kg C+) KG (+)
":- R1 "-1F EF -3- R9 I 3F

:»- R2 _4R -]5R :- R10 ']oR
re
p 5/ F
N/
Elfr
lava NAHS
I
170T
19DT >
~
l
`r"
F
F
F F R
4
f I /'
\
:>- R3 . OF :- R7 3. R11 -€>F
_=I- RE ]1R _=J- RB _:s- R12 L
J OR
(-) (-> (->
PHASE 1 SCR PHASE 2 SCR PHASE 3 SCR
L_____________________________,,________________________J
TYPICAL N N-RE ERSING SIR BRIDGE (LEFT SIDE vIEw)

l""""""""°"""l°"""°"°l"l°""l°"""""""'--"""""l""""l
I l
I K1 <+>
I KE (+> K3 c+>
I
I
-:» R1 {]1r R5
]as RE
!-jar
:- R2 - RE R10
E
i
I
I
I
I F F F
I
I H/ H/ D/
I . . .
I . .
uavzm NAHS
. .
I 170T
I 190T I
>
I
I
I I
I F I
Q
I
1 I
1 I
I l
I I
I l
I 1
I I
I I
I :>- RE ::l~ R7 :- R11 I
I
I _3- F34
4F
_Z" RB _='- R12
*SF I
I
I (-> (-> - <-) I
I l
I PHASE 1 SCR PHASE 2 SCR PHASE 3 SCR I
Figure 9-9. SCR Stack Assemblies, M Frame Drive
9-16
_ ~.s
'ii-.
-- ---s.an1n---I-~
Dc2000.Dig-ual Adjustable Speed Drive GEH-6005
Table 9-5. Specific Fault Troubieshooting Using Fault Numbers
No. Name Fault Condition, Causes Type Fault
o CLEAR Clear No Faults present
1 IOC_TRIP Instantaneous over-current Trip fault

The armature current sampled by the do shunt has exceeded the limit set by EE.1507,
IOCTRO. Thearmature curnent.can be monitored by test point TP8 (if present) on the
DCC/SDCC Drive Control Card. Possible causes:
- IOC set too low. Check IOCTRO (EE.1507/1907/2307/27071.
- CFBSFn lEE.1505) set too low, causing saturation of the hardware.
- SCR misfiring. Check wiring for crosstalk, misconnections.
- Current regulator mistuned Run test 14. .
- Armature connections looses brushes not seated properly.
- Mechanical load problems -'-*shaft bind, brake, gear box, etc.
- Current feedback isolator failure; Check 1PL and DRPL on DCI/DCFB.
- Shunt feedback not scaled properly. .
- SCR failure. Run test 12. " :' .. .
- For multibridge, EE.608 or 61 o set improperly in master drives.
2 OVER_SPD Tach overspeed Filtered fault

The magnitude of SFB (VAR.100) has exceeded the overspeed threshold (EE.20). Possible
causes:
- SFB blocks SFBK (BLK.320), SREG (BLK.301) improperly set.
- Speed overshoot due to speed regulator tuning underdamped: SREG (BLK.301 ), SREGA
(BLK.397). SRGA1 (BLK.398), SRGA2 (BLK_399).
Loss of field current.
4 FIELDLOS Field loss Filtered fault

The field current has fallen below the limit set by EE-1562, FLDLSO. Possible causes:
- Blown field fuse. Check for blown MOVs.
- Field connections loose or incorrect.
- FLDLSn set too high. Set at least 25% below FLDMNn, EE-1566.
- FLDECn set too low.
- Field reference blocks set incorrectly lBLK.259 or 300).
- Field gain jumpers set incorrectly on DCI.
Field regulator gain too low. Run field tuneup.
- Incorrect field mode (2/3, NRP, or NRX) selected via EE.573.2.
- For SDCC, U31 date codes z 9420 may require DCP revision; 5.1 O.
This fault can be inhibited by setting EE.1562 to O (for motor #O).
Beginning with revision 6.31, IFLDAFB (VAR.1090) (or FLDFB, VAR.105 if Field #A is en~
abled via EE.5300.0) is normalized by the flux saturation curve defined by EE.1568-EE.1575.
However, FIELDLOS uses UN-normalized field feedback to detect a fault and can be com-
pared to the field loss limit (FLDLSO) by viewing IF FB, VAR.1028. -
5 SFB_POL SFB/Tach -polarity reversed e . . Filtered state

The polarity of SFB does not agree. with the polarity of motor voltage, or frequency. This..fault
is generated when the magnitude of CEMF (VAR.11 2) is greater than 20% and the polarity ..
of SFB is not the same as the polarity of CEMF. Possible causes:
- Reversed tech connections . .
SFB blocks (BLK.320, seeK: BLK.32l7, ENCP1: etc.) improperly set
-
¢
On DC2000, Reversed VFB connections (P1/P2 wired incorrectly)

l - For analog tacks. failure of ribbon cable SPL (pins 39 or 40)
- See also FLT.20. -
7 RESETRUN Run command asserted during reset. P<>*ssible causes: Trip state
Drive powered up or_reset with RUN or JOG closed (dedicated NTB/3TB inputs or STBA or
LTB configurable inputs). `
- Incorrect 3TB or STBA logic polarity (see NTB JP10 or STBA JP1O and JP11, EE.1 .4).
- Auto-start inhibited (EE.5.4).
- Momentary loss of incoming power while running.
8 TOC_.TRIP Timed overcurrent Trip fault

Possible causes:
- Motor mechanically overloaded due to load or wear.
- Field current less than 85% of rated.
- TOC settings too low (EE.1490-1496).
- Armature winding failure.
- DB contactor failure (if used).
- TOC@lN (EE.25) if used, is not pointed at bridge or motor current.
J
9-17
:»~O
:ii
|
Table 9-5, Specil7c Fault Troubleshooting Using Fault Numbers - Continued

9 SERLTRIP Trip generated by serial or LAN command 3Fh Trip state

Possible causes:
"?" command accidentally entered from serial link keyboard.
- Received command 3F from LAN.
I
10 NO_CTS Serial link lost transmit capability due to CTS handshake Trip fault
The serial link has data to transmit (such as a fault code), but is unable to send it due to the
Clear-To-Send RS232 handshake line. Possible causes:
- Improper configuration of COMPL.4 and COMPL.5.
- Improper configuration of NTB.JP.6 and JP.7
- Failure of connector 6PL or SDCC or STBA board.
1'
13 EECKSMO Bad page o EE checksum, EE.O - EE.255 - _ Latched

The actual EEROM checksum in the given range does not agree with the stored checksum . annunciated
Possible causes: fault
- Block load of EEROM attempted with DCC/SDCC JP1 open or in 1 .2 position.
- Drive reset or lost power while EEROM was being updated.
- DCC/SDCC JP1 was changed during update or touched with static charge.
- STZOOO or LAN download aborted or failed while in progress, or communication failure
(Rev 1.70 and earlier). r
In the first case, the actual EEROM is not affected, and it is safe to reset the fault, enable
the jumper, and perform the block load again. In all other cases, an effort should be made to
find the faulty settings and correct them. Set EE.2.1 and perform two hard resets to force a
correction to the checksums.
14 REG_SAT CFB too low at fully advanced firing Filtered fault

The current loop has fired 60 fully advanced (as controlled by EE.1544, ADVLMn- or
EE.1592, HADLMn) firings in a row and armature current remained less than 10%. Detec-
tion of this condition can be inhibited by setting EE-571.1, MFLTJP.
Possible causes:
EE.565-EE.568 not set, causing current loop autotune to incorrectly compute
settings for EE.1544 and EE.1 592.
- EE.1544, EE.1 592, or EE.1581 (ILIMCO) set too low.
- Main contactor not picking up, or picking up too slowly. Increasing EE.39 (MAPDLY) will" Jr
correct for slow magnetics.

- Open connections or contactors in the motor armature circuit.
- Do fuse open. J
- Inspect 5 PL, DRPL, and SCR gate lead connectors. Run test 12.
Note in applications using the enhanced current regulator (EE.5l/0.1). EE.1581 may be set
so low that the current regulator does not have enough authority to advance to CEMF limit
(EE.1592). In this case, FLT.14»logic is net able to detect an open loop/firing circuit. Raising
EE.1581 (typically by 25%) allows this protection to function with little impact on perform-
ance. Beginning with revision 5.00 (DRVTYP=85). FLT.222 gives enhanced detection of
this fault detection.
15 VFB_LOSS VFB too low for given firing angle Filtered fault
The drive has failed to measure at least 1 % armature voltage when the firing angle is within
75 degrees of full advance and current is at least 5%. The analog VFB signal can"be moni-
tored for a circuit failure at control card test point "TP37. Detection of this condition can be
inhibited by setting EE.571 .6, MFLTJP. Possible causes:
- Voltage select jumpers and power connections on the PCCA card are incorrect.
- 5PL failure. Check 5PL-25 and -26 (right-mdst pair of wires in cable).
- Failure of VFB circuitry on the SDCI/DCFB. Check VFB at TP37.
- Possible blown do fuse.
- For DCFB, VM1A/B voltage feedback not connected (see EE.5'/0.1 1).
16 NORMOPEN Normally open interlock is closed Filtered state

Possible causes:
- Improperly selected source of NORMOPEN (EE.292, EE.4.14)
- External interlock closed or improperly connected
9-18
DC2000 Digital Adjustable Speed Drive GEH,6005
Table 9-5. Specific Fault Troubleshooting Using Fault Numbers - Continued
I No., Name 9 Fault Condition, Causes Type Fault
17 XSTOP xsTopcMD, VAR.679, hardware XSTP input is open Trip state

Possible causes:
- Improperly selected source of XSTOP input (EE.253)
- External input open or intermittent
- Failure of ribbon cable SPL
- Improper choice of XSTOP mode (EE.6.4)
Note that prior to revision 2.31 , this was a filtered fault, and XSTOPCMD could be TRUE
briefly, causing a stop but not a fault.
18 STALL_OC Timed overcurrent at stalled rotor Trip fault

Possible causes:
- Mechanical failure (failed brake, frozen bearing. etc.)
Field current less than 85% of rated
SOC settings too low (EE.1490-1496)
- Armature winding failure
- DB contactor failure (if used
- If motor was rotating, speed threshold too high (EE.1492 or EE.21) or problem in
speed feedback measurement (BLK.320).
- SOC@lN (EE.30) if used, is not pointed at bridge or motor current
19 OVERVOLT Instantaneous overvoltage Filtered fault

The armature voltage has exceeded the limit set by EE.579, IOVTHR. The analog VFB signal
can be monitored for a circuit failure at DCC/SDCC testpoint TP37.
Possible causes: v
Advance limit set too high (EE.1544 or EE.1592).
Crossover set too high (EE.1567).
Drive unstable. Run tests 14 and 16 to check arm/field regulators.
VFB circuit failure. Check DCC/SDCC TP37. 1
's
For DCFB, VM1A/B voltage feedback not connected (see EE.5l/0.1 1).
20 SFB_LOSS SFB/Tach feedback loss ,. Filtered fault

The magnitude of SFB does not agree with the magnitude of motor voltage or frequency.
This fault is generated when the magnitude of CEMF (VAR.112) is greater than 20% (4000 ;
counts) and the magnitude. of SFB (VAR.1 OO) is less than 2%. Possible causes: f
- Tach leads broken . :
- Tach hardware scaled-improperly (Analog: NTB.SW.1) 2
- For analog tacks. failUre.of ribbon cable 6PL (pins 39 or 40)
I
I
- Encoder connected improperly (STBA/SDCC jumpers, EE.7, BLK.326, etc.)
- Encoder jumpers set for 15 volt encoder when 5 volt encoder used
- Encoder "Z" channel polarity holding counters in reset.
- SFB blocks (BLK.320, SFBK; BLK.301, SREG; etc.) improperly set
- Loss of field current
\i0J
.
- Open de fuse or armature loop
Bug during reset in revision 1.10-1.50 when using CEMF as SFB
For debug purposes only, this fault may be inhibited by FLTJPR.7.
21 NORMCLSD Normally closed interlock is open Filtered state

Possible causes'
Improperly selected source of NORMCLSD (EE.291 , EE.4.14)
- External interlock open or improperly connected
22 PHASELOS As line dip or imbalance Trip fault

Possible causes:
- EE.582 or 583 setting is too sensitive.
- Low ac line or phase imbalance.
- Blown fuse in ac line or on SDCI/DCFB card.
-
LoOse ac power connections.
-
Failure in i 15 volt power supplies.
For EX2000 see EE.5'/6.
Beginning with revision 5.36, for DC2000 only, this fault requires a hard reset to clear. For
revision 6.31 and later (DC2000 only.), if EE.6283.6 is set, this fault can be cleared by in-
voking a soft reset (a firm reset is performed). See EE.6283.6 for details.
Beginningwith revision 5.41, field and armature SCR firings are inhibited when this fault
occurs.
9-19
Table 9-5. Specific Fault Troubleshooting Using Fault Numbers - Con tinned
23 FIELDTOC Field timed overcurrent Trip fault

The field current has exceeded the reference by an amp-seconds rating defined by EE.1563,
Fl'OCGO. Possible causes:
- Field SCR shorted.
- Field regulator unstable or running in voltage-regulated mode.
- Fl'OCGn set too sensitive.
- Excessive field forcing through BLK.259 or 300 (VAR.165).
- Incorrect field mode (2/3, NRP, or NRX) selected via EE.'573.2.
For SDCC, U31 date codes 2 9420 may require DCP revision 2 5.1 O.
Field SCR firings are inhibited when this fault occurs.
Beginning with revision 6.31, IFLDAFB (VAR.1090l (or FLDFB, VAR.105 if Field #A is en-
abled via EE.5300.0) is normalized by the flux saturation curve defined by EE.1568-EE.1575.
However, FIELDTOC uses UN-normalized field feedback to detect a fault which is typically
equivalent to lF FB, VAR.1 O28 .
25 COM _FAlL Commutation failure Trip fault

The drive has shut down because it detected an imminent SCR commutation failure.
Possible causes:
- Open or intermittent connection on pins 1 or 2 of ribbon cable 1PL.
- Shorted or open SCRs.
- Insufficient commutation voltage margin due to ac line dips or CEMF limit or crossover
set too high.
- improper CT burden selection settings on SDCI/DCFB. Set for higher horsepower rating.
- Commutation failure threshold set too low (EE.581 , CFLTHR).
- Dc current in ac line saturating CTs due to high loads and multiple bridge reversals at a
rapid rate (faster than 60 Hzl.
- Nuisance trips due to hardware/software sensitivities prior to 302DClANG1/AJG2,
301 DCCAMG1, and 1.60 (AG) revisions. Increase EE.581.
- Leads swapped in CT connector, ICPL, on SDCI/DCFB card. Compare VAR.104 and
VAR.1019 for same polarity and magnitude. Use burden switches for coarse
adjustment, EE.1 520 for fine.
- -
Bug in MPG3 revisions 2.15 2.20 when SDCC and DCFB are used. FLT.25 must be
inhibited in these revisions.
Inhibit this fault by setting EE.581 to 32767. When this fault is detected, armature SCR fir-
ings are immediately inhibited (no phase-back occurs).
26 AC_IOCUR Ac instantaneous overcurrent Trip fault

Current as instrumented by the as line current transformers has exceeded the limit set by
EE.580, ACIOCT. Possible causes:
- improper CT burden selection on the SDCI/DCFB. Verify settings and that the scaling of
CTCFB (VAR.101 9) roughly matches CFB (VAR.104) using test 31 .
- ACIOCT set too low. Set to 32767 to inhibit this fault.
- Current regulator overshoot. Run current loop tune-up.
- Open or intermittent connection on pin 1 or 2 of ribbon cable 1PL.
- Commutation failure or ac shoot-through. Run cell test.
- Refer to additional items under FLT.25 (COM_FAlL).
- For early revisions, see note under EE.587 and increase EE.580.
- During cell test, a shorted cell exists and firing angle used during test is too advanced.
Temporarily defeat FLT.26 using EE.580 or reduce the firing angle using EE.1580.
As of revision 2.1 1 , armature SCR firings are immediately inhibited when this fault is de-
tected.
27 NO__LSYNC Indeterminate line sync input Locked fault

The drive is not receiving a suitable ac line synchronization signal from the SDC!/DCFB. Test
point TP29 on the DCC/SDCC (not on early DCC revisions) should show a 5-volt square wave
of the line frequency. Possible causes:
- Fuses blown or missing on the DCI/DCFBISDCI interface card. (Note: if fuses are
blown, check for MOV failures).
- Excessive ac line phase imbalance or notching.
- Failure of 1PL cable (pin 29) or DCI/DCFB/SDCI card.
- For multibridge, failure of LAN power supply or SPCB card, misconfiguration of master
or follower drive (EE.572).
Field and armature SCR firings are inhibited when this fault occurs.
For revision 6.31 and later (DCZOOO only), if EE.62.83.6 is set, this fault can be cleared by
invoking a soft reset (a firm reset is performed). See EE.6283.6 for details.
9-20
28 ILL__MODE Illegal Run mode commanded Trip state

Not used in the AC/DC2000 (replaced by more descriptive faults such as FLT.360).
29 CNTRL_ON Control-on loop open Trip state

Possible causes:
- Open circuit or noise between 3TB.42 and 3TB.44 on NTB.
- Intermittent connection in 6PL pins 'I or 2.
- Open circuit on STBA K28 + and K28- (STB.64 and STB.66)- See also STBA JP29
and JP30.
- STBA RLY 3 dropped out or RLY 3 contact not bypassed from control-on circuit.
See STBA Jp31, JP32. and JP39.
The control-on loop should not be used as the normal stopping mode for the drive. It is
intended for real emergency use only or as a safety lockout when the drive is already
stopped.
31 NO_PHSEQ indeterminate phase sequence input Locked fault

The drive is not receiving a suitable ac line signal for determining the phase sequence or line
sync. Test point TP29 on the 301 DCC/SDCC card (not on early revisions) should show a 5
volt TTL level square wave of line frequency. Possible causes:
- Line or power supply card fuses blown.
- Excessive ac line phase imbalance, noise. or notching.
- Failure of 1PL cable (pin 29 or 6) or DCI/DCFB/SDCI card.
- 115 volt power supplies outside 10% limit.
- (Multibridge) Failure of LAN power supply or SPCB card, misconfiguration of master or
follower drive (EE.572).
For revision 6.31 and later (DCZOOO only), if EE.6283.6 is set, this fault can be cleared by
invoking a soft reset (a firm reset is performed). See EE.6283.6 for details.
32 TOC_ANUN Timed overcurrent alarm Non-latched

annunciated
fault
33 NEGPHSEQ Negative phase sequence not allowed Trip state
This fault can only occur if a negative sequence ac line source has been detected and
EE.5'/0.1 is set to inhibit negative sequence operation. If the SDCC and DCFB cards are
being used and the bi-phase PLL is enabled (see EE.570.3 for MP group 3). only positive
sequence operation is allowed, independent of EE.570.1.
- Reverse any 2 ac input lines and recheck.
- Check items listed for FLT.31 .
Field and armature SCR firings are inhibited when this fault is detected. Note some applica-
tions using the DCFB board do not allow drive operation with reverse phase sequence.
34 PLLTRACK Ac line synchronization PLL error too high Non-latched

Either noise or a frequency change on the ac line instrumentation has caused the PLL error annunciated
to exceed the acceptable limit. The response of the PLL circuit may be changed by EE.575, fault
PLL_GN. Possible causes:
- Excessively noisy, notched, or unbalanced ac line.
-
.p
Fuses blown or missing on DCI/SDCI/DCFB.

- PLL_GN set too low (especially variable frequency ac lines).
- Failure of 1 15 V do power supplies.
- Bi-phase PLL enabled (EE.570.4) but 3-phase L1IL2/L3 not connected to DCFB.
- Bi-phase PLL enabled lEE.570.4) but gains not set lEE.576, 577).
- (K-frame followers) EE.5l/5 (EE.570.4=o) or EE.576/577 (EE.570.4=1) should be set
high to avoid nuisance faults from PLLs which are not being used. (K~frames run from
master's PLL).
35 O_SPEED Run while rota.ting, flying restart inhibited Non-latched

Motor rotating when RUN or JOG commanded. Possible causes: state
- RUN commanded while motor coasting or externally driven.
- ZSPEED (EE.21) set too low.
- Too much noise or offset (Analog: check EE.49) in tech feedback.
- Need to enable flying restart mode (EE.5.3).
36 SERL._ERR Annunciates bad serial message. Possible causes' Non-latched

- Incorrect Baud rate (EE.120). annunciated
- Noise on serial link wiring. fault
- Bad message checksum in protocol mode.
- Invalid message (too many characters).
r
P
9-21
No. Name Fault Condition, Causes Type Faugh
38 EELOCKED EE writes disabled Non-latched

EEROM cannot be modified via the serial link, LAN, or Programmer unless EE.2.0 is set. state
39 EEWRFAIL EE write verify fail. Possible causes: Non-latched

- SDCC JPt in disabled position. annunciated
-Exceeded maximum changes to EEROM (10,000 changes per 256 word page). fault
- EEROM (U9l has failed.
40 SPEEDLIM Speed reference outside limits. Possible causes: Non-latched

- BLK.255, RUNRF output exceeds EE.356 state
- BLK.256, JOGRF output exceeds EE.376
- BLK.301, SREG command exceeds EE.1418
- EE.290, RFLM@I pointing to a TRUE value
The speed regulator can impose both maximum and minimum limits. The other sources
impose only an absolute maximum limit.
41 KEY_OFF The key pushed is presently disabled (see EE.690). Non-latched

KPDJP1 (EE690) has been programmed to disable this function. annunciated
- Check the loading of KPD JP1 (EE_690)_ fault
42 XSTPOPEN XSTOP input open when RUN or JOG requested. On STBA board, these signals are con- Non-latched
nected to configurable inputs. Possible causes: state
- EE.253, xsTp@l not pointed to correct source of the XSTOP input.
- XSTOP input open or intermittent.
- Failure in NTB/3TB, STBA, or SDCC board, or connector SPL.
45 SPDTRACK Speed tracking fault. Possible causes: Trip fault

- Speed tracking improperly set up (EE.26-28).
- Drive unstable or unable to hold speed.
- Speed regulator blocks improperly set up-
This fault can be inhibited by setting EE.27 to O.
46 CFB_OFST CFB VCO zero offset too high Non-latched

While the drive is stopped ( no current flowing in the shunt), it has measured more than 3% annunciated
current, indicating an excessive zero offset in the current feedback isolator on the fault
DCI/SDCI/DCFB card. Detection of this condition can be overridden by EE.571 .4.
Possible causes:
- DRPL connected incorrectly at shunt or plug on DCI/SDCI/DCFB.
- Twisted-pair wires from shunt picking up noise. Route away from power leads and
twist pair tighter.
- Failure in the current feedback isolator on the DCI/SDCI/DCFB.
52 NCLSDANN Normally closed interlock is open Non-latched

annunciated
fault
57 NOPENANN Normally open interlock is closed Non-latched

_annunciated
fault
65 A1 F__OPEN Cell test open circuit detected in A1 F Trip fault

Inadequate current was detected in the SCR during the open circuit SCR test. Possible
causes:
- SCR or leg fuse failure.
- The open circuit firing angle may need to be tailored for the motor under test using
EE.1577, cTsTvo.
- 5PL or SCR gate lead cable/connection failure.
66 A2F_OPEN Cell test open circuit detected in A2F (see FLT.65) Trip fault
67 A3F_OPEN Cell test open circuit detected in A3F (see FLT.65) Trip fault
68 A4F _OPEN Cell test open circuit detected in A4F (see FLT.65) Trip fault
9-22

69 A5F__OPEN Cell test open circuit detected in A5F Trip fault
70 A6F._OPEN Cell test open circuit detected in ASF (see FLT.65) Trip fault
71 FWD_OPEN Cell test detected no forward current Trip fault
Inadequate current was detected in the SCRs during the open circuit SCR test in multiple cells.
The fault code indicates whether the problem affects all SCRs, only forward or reverse, or
some other combination. Listen for current in the motor during the test to isolate firing versus
feedback problems. Possible causes:
- SCR or fuse failures.
- The open circuit test firing angle may need to be tailored for the motor under test using
EE.1577, CTSTVO.
- 5PL or SCR gate lead cable/connection failure.
- Shunt feedback wiring damaged or not connected.
- Current feedback isolator failure on SDCI or FB.
- Armature loop open or motor not connected.
- Inadequate time allowed for contactor to close (EE.39 MAPDLY).
- Regeneration enabled on non-regenerative drive (EE.1500.1, 1900.1)
- Simulator mode enabled (EE.570.0).
- Firing power failure. Check for + 24 volts on gate pulse primary during drive test 12.
72 ARM__OPEN Open circuit test detected no armature loop Trip fault

More than 5% voltage was detected at the beginning of the second pass of cell test, but VFB
was OK at the beginning of the first pass. This would normally happen if the short circuit test
fired into an open circuit, so the VFB senses snubber voltage due to lack of a discharge path.
Possible causes:
- Blown do fuse.
- Open circuit in armature, do contactor, or wiring.
- Insufficient time allowed for do contactor to close --
increase EE.39.
- Failure in VFB sensor (DCFB) or connections l5PL).
- PI or P2 connection to armature (for snubbers and VFB) is open.
This fault can be overridden by setting EE.571 .1 1 .
73 A1 R_OPEN Cell test open circuit detected in A I R (see FLT.65) Trip fault
74 A2R_OPEN Cell test open circuit detected in A2R (see FLT.65) Trip fault
77 A5R_OPEN Cell test open circuit detected in ASR (see FLT.65) Trip fault
78 A6R_OPEN Cell test open circuit detected in A6R see FLT.65) Trip fault
79 REV_.OPEN Cell test revealed no reverse current (see FLT.71) Trip fault
80 SHRTFAIL Short circuit cell test failed Trip fault

When cell test detects a short on the first pass, cell test runs the test again, testing cells in
the same order. If the second pass detects a different shorted cell than on the first pass,
FLT.8O is reported. Possible causes:
-The short circuit test thresholds for voltage and current need to be increased for the
motor under test. See EE.1578 and 1579.
-SCR misfiring due to dv/dt.
-
SCR mitigating due to noise coupling or misconnection of gate leads.
- Noise in the CFB and VFB sensor hardware.
9-23
81 A1_SHORT Cell test short circuit detected in A1 Trip fault

Motor current or voltage was detected in the SCR during the short circuit SCR test. Possible
causes:
- SCR shorted.
- SCR misfiring due to dv/dt.
- SCR mitigating due to noise coupling or misconnection of gate leads.
- The short circuit test thresholds for voltage may need to be tailored for the motor
under test. See EE.1578 and 1579.
- Prior to revision 1.84, open armature or VFB not O when cell test invoked, especially if
fault reported is A6_SHORT. Check de fuse, motor not at standstill, or bad VFB sensor
circuitry.
Note that for K frame (multibridge) drives, if a cell is shorted, the master drive will report
which leg (Al - A6). If the short is in a follower bridge, that follower drive will report a
FLT.232, MBRGSHRT, to pinpoint the location of the shorted cell.
82 A 2 _SHORT Cell test short circuit detected in A2 (see FLT.81) Trip fault
83 A3__SHORT Cell test short circuit detected in A3 (see FLT.81) Trip fault
84 A4_SHORT Cell test short circuit detected in A4 (see FLT.81) Trip fault
85 A5 _SHORT Cell test short circuit detected in A 5 (see FLT.81) Trip fault
86 A 6 _SHORT Cell test short circuit detected in A 6 (see FLT.81) Trip fault
97 OPENFAIL Open circuit cell test failed Trip fault

When cell test detects a failure on the first pass, cell test runs the test again. If the second
pass detects a different set of cells open than on the first pass, FLT.97 is reported (revision
1.84 to present). Possible causes:
- The open circuit test firing angle needs to be increased (EE.1577).
- Intermittent connection in 5PL ribbon cable or power wiring.
-See also FLT.71 .
98 MULTOPEN Cell test detected multiple opens (see FLT.71) Trip fault
99 ALL_OPEN Cell test detected no forward or reverse current (see FLT.71} Trip fault
129 DRIVETYP Programmed drive type doesn't match hardware configuration Trip fault
Possible causes:
- Software installed at U22/U23 does not match EE.550, DRVTYP
- Hardw are installed at 1 PL does not match EE.556, HDWTYP
DRIVE TYPE EE.550 EE.556 INTERFACE CARD VOLTS AT 1 PL-38
DCZOOO
DC2000
5
85
5 or o
5
DCI (531x3020c11
DCI or SDCI
2.3 2.7
2.3 - 2.7
_
Note: EE.556 is invalid for EE.580=85.
DCZOOO 5 or 85 4 DCFB (DS2OODCFBl 1.8 - 2.2
- Failure of ribbon cable 1PL pin 38
- Failure of DCC/SDCC card.
The actual voltage being read by the DCC/SDCC card at 1 PL-38 is displayed under the head-
ing "DTYP" of drive test 13 (113) using an RS232 terminal connected to COMPL.
130 MCPBDREV Invalid MCP software revision (SDCC sockets U22/U23) Trip fault
The revision of the MCP software, in SDCC sockets U22 and U23, is not recent enough to
support features selected by the EEROM configuration, or the MCP software is not compatible
with the other EPROMs on the SDCC card. Possible causes:
-EEROM not configured per application requirements
- Software revision (per PROM labels and per drive test 10) older than specified in
MCPREV (EE.66)
- SDCC only: MCP revision less than 4.34 when DCP is greater than 4.33. This is a
locked fault which can be corrected only by installing a compatible EPROM set for
U12/U11 and U22/U23.
9-24
131 MCP_FAlL SDCC motor control processor U21 (MCP), selftest failed Trip fault
MCP has failed its powerup selftest. Pass/fail status of MCP is also displayed on an RS232
terminal running test 13 (]13). Possible causes:
- Socketed ICS on the SDCC control card not properly seated
- Failure of U21 on SDCC card. Replace card.
tsz MCPROMCK MCP EPROM (SDCC U22/U23) checksum error Trip fault
The MCP EPROMs have been improperly programmed or have failed. Possible causes:
- U22 or U23 on SDCC card not properly seated.
- Failure of U21 , U22, U23 or SDCC card.
- U21 is an 80c1 96KC chip instead of an 80c196KB. Prior to revision 1.90 (AK). U21 must
be an 80c1 96KB microcontroller.
133 DPRMFAIL DCP/MCP Dual port RAM (acc/socc U8) selftest failed Trip fault
MCP has detected a failure in the U8 dual-port RAM during its powerup selftest. Pass/fail
status is also displayed on an RS232 terminal running test 13 (113). Possible causes'
Socketed IC on the DCC/SDCC control card not properly seated.
134 DCPB__DOG Timeout, MCP watchdog of DCP background Trip fault

The MCP has detected an execution rate failure of the background software in the DCP. DCP
background monitors a byte (DPRM__.DCPB_MCPB__WDOG) 11 times a second, and if it is
negative, DCP resets it to O. MCP background decrements the byte 22 times a second, and
generates fault 134 if it ever gets down to -100 counts. (See related fault 377).
Possible causes:
- Socketed ICS on the SDCC control card not properly seated or bent pins
- Failure of SDCC card
- Noise disturbing SDCC control card due to improper wiring practices
- EEPROM configuration has overloaded processor
- Card connected to 1PL or 3PL installed or operating incorrectly.
- Intermittent, noisy, or out-of-spec low-level power supply.
135 DCPF_DOG Timeout. MCP watchdog of DCP foreground Trip fault

The MCP has detected an execution rate failure of the foreground software in the DCP. MCP
background increments a byte (DPRM_DCPF_WDOG) approximately 22 times a second. DCP
background also increments this byte, about 1 1 times a second. DCP foreground resets this
byte to zero about 90 times a second. If MCP ever sees this byte larger than 100, then it
generates fault 135. See related fault 375. Refer to FLT.134 for possible causes.
136 MCPF__DOG Timeout, MCP watchdog of MCP foreground Trip fault

The MCP has detected an execution rate failure of its foreground software. MCP background
increments a byte (DPRM_MCPF_WDOG) about 22 times a second. DCP background also
increments this byte, about 1 1 times a second. MCP foreground resets this byte to zero
about 360 times a second. If MCP background ever sees this byte larger than 100, then it
generates fault 136. See related fault 378. Refer to FLT.134 for possible causes.
For the DC2000, this fault can be caused by the loss of the line sync input (1PL~29). Begirt
ring with revision 5.31, field and armature SCR firings are inhibited when this fault occurs.
For revision 6.31 and later (DCZOOO only), if EE.6283.6 is set, invoking a soft reset will re-
initialize MCP with out requiring a hard reset (a firm reset is performed). See EE.6283.6 for
details.
NOTE - Multiple soft resets may be required.
137 MCPEXRAM 80c196 processor external RAM U97 powerup test fail Trip fault
External RAM device U97 (SK bytes) on the SDCC control card failed the powerup test for
one or more memory locations. Possible causes:
- Defective SDCC card .
- Socketed device on SDCC not inserted fully or pin bent under.
9-25
1 38 CMPSHRAM 80C196/TMS320c25 shared RAM U36/37 powerup test fail Trip fault
Shared RAM devices U36 and U37 (32K words) on the SDCC control card failed the powerup
test for one or more memory locations. During powerup, this RAM, which is accessible by
both the MCP (U21) and CMP (U35), is tested by MCP, once with CMP halted, and once
with CMP running. If the RAM test fails with the CMP halted, FLT.138 is reported. If the
RAM test fails with the CMP running, FLT.145, DPRCFAIL, is reported. Possible causes:
- Defective SDCC card. .
- Socketed device on SDCC card not inserted fully, or pin bent under.
1 39 CMPBDTYP Co-motor processor (CMP) drive type mismatch Trip fault

The CMP software, in SDCC sockets U36 and U37, is not appropriate for the selected drive
type (see EE.550 and EE.551 , DRVTYP and ALGTYP) and the available card hardware.
.
There is a relevant mod to the DCC card at revision ANM1 This was built from an AMG1
tab, which became an ANG 1 base assembly. When populated with AJ (1 .80) firmware, it
became an ANM1 Card, date 5/10/91 .
Prior to the ANM1 card revision:
Supported types
EE.DRVTYP = 5, EE.ALGTYP = o
EE.DRVTYP = 5, EE.ALGTYP = 0, 1 oo, 300
Verify EE settings, and that jumpers JP17, WJ7, and WJ8 are set properly.
For the ANM1 and later card revisions:
Supported Types:
EE.DRVTYP = 5, EE.ALGTYP = o
EE.DRVTYP = 7
EE.DRVTYP = 9, EE.ALGTYP = o, TOO, 300
Verify EE settings, and revision and insertion of CMP PROMs U36 and U37.
140 CMPBDREV Invalid CMP (U36,U37) software revision Trip fault

The revision of the CMP software, in DCC sockets U36 and U37, is not recent enough to
support features selected by the EEROM configuration, or the CMP software is not compati-
ble with other EPROMs on the SDCC card. Verify the EEROM is configured properly and
software revision (per PROM labels and per drive test 10) is at least as high as specified
revision in MCPREV (EE.661.
141 CMP_FAlL CMP (SDCC U35) selftest failed Trip fault

CMP has failed its powerup selftest. Pass/fail status of CMP is also displayed on an RS232
terminal running test 13 (113). Carefully check that all socketed ICS on the SDCC card are
properly seated. The SDCC card should be replaced if this does not correct the fault.
142 CMPROMCK CMP EPROM (SDCC U36,U37) checksum error Trip fault
The CMP EPROMs are improperly programmed or have failed, and must be replaced. Ensure
they are properly seated in their sockets.
143 CMPBDACK CMP bad acknowledge Trip fault

The CMP (U35) is not properly responding to the MCP (U21 ). Possible causes:
- Check seating of socketed components on the control card
- Check that the software revisions in U22lU23 and U36/U37 (DCC) are compatible
- Excessive CPU load on the MCP or CMP processor. Check EE configuration to ensure
unneeded functions are not enabled.
- Failure of DCC or SDCC control card.
144 CMPNOACK CMP no acknowledge Trip fault
CMP (U35) is not responding to MCP (U21). Check items listed for FLT.141, or replace the
SDCC.
145 DPRCFAIL MCP/CMP Dual port RAM or shared RAM selftest failed Trip fault
MCP has detected a failure in the U33 dual-port RAM (DCC) or U36/U37 shared RAM (SDCC)
during its powerup test. Pass/fail status is also displayed on an RS232 terminal running test
13 (]13). Possible causes'
- Seating of socketed ICS on SDCC card.
- Wrong revision of PAL in socket U91 on SDCC card--must be AB or later.
- Defective DCC or SDCC card.
146 CMP_WDOG MCP/CMP watchdog fault Trip fault
The MCP has detected an execution rate failure of the CMP software. Possible causes:
- Seating of socketed ICS on SDCC card.
- Noise disturbing SDCC card due to improper wiring practices.
- JP33 not in 1-2 position.
9-26
147 CIRCLATC MCP Diagnostic Circular List latch annunciation Non-latched

Indicates that the MCP Diagnostic Circular List has latched to the frozen state. The infor- annunciated
mation preserved in the buffer may be interrogated via the drive serial link (see EE.600). fault
148 SENCWDOG Serial absolute encoder communications watchdog Trip fault
The absolute encoder function via the serial interface on the SPC card is enabled by
MCNFlG.12 (EE.570), but no serial communications have been received for 150 msec.
Possible causes:
- Hardware not setup properly: DCP JP31 2-3; spc.sw.1.7 off
Encoder connected to + 15 volts, common, 1TB.13 and 1TB.14
- Encoder failure, not sending serial information
- Failure in SPC card or ribbon cable 7PL pins 19 or 20
For the BEI serial encoder with the D17 interface, hook-up is as follows:
BEI terminal Drive terminal
A TXD 1TB-14 RXP (DCC card) 1TB-13 RXN (SDCC card)
B /TXD 1TB-1 3 RXN (DCC card 1TB~14 RXP (SDCC card)
I CKT GRND 3TB-66 COM
P +15 V d c 3TB-62 +15
J CHASSIS
Note that connections to 1TB depend on which drive control card is installed. either DCC
or SDCC. Connect u to v to set the baud rate to 2400. Connect L to I to get increasing
counts for CCW rotation, or connect L to P to get increasing counts for CW rotation. Other
baud rates (not currently supported by the drive) are: Q-R, 19200, S-R, 9600, and T-U,
4800. See also FLT.149.
149 ENC_UART Serial absolute encoder communications error Nor:-latched

The absolute encoder function via the serial interface on the SPC card is communicating annunciated
with the drive, but the character or message error rate is excessive (more than 1 bad mes- fault
sage for every 10). Possible causes:
- Baud rate set incorrectly on encoder--should be 2400
- Wrong polarity on RXP/RXN (1TB.14I13)--for DCC card, need RXP mostly plus write
RXN; for SDCC card, RXN should be mostly plus (see FLT.148)
- Excessive noise pickup due to routing of RXP/RXN twisted pair or power.
See also FLT.148.
165 FLDB_LOS Field #B current feedback loss Trip fault
The field current has fallen below the limit set by EE.1 564, FLBLSO.
Possible causes:
- Field #B enabled (EE.570.9). but not installed
- Blown field fuse.
- Field connections loose or incorrect.
- FLBLSn set too high. Set at least 25% below FLDMNn, EE.1566.
- FLBECn set too low.
- Field reference blocks set incorrectly lBLK.259 or 300).
- Field feedback gain set incorrectly.
- Field #B regulator gains too low.
This fault can be inhibited by setting EE.1564~to o, or inhibiting field #B via EE.570.9.
Beginning with revision 6.31 r IFLDBFB (VAR.1091) (or FLDFB, VAR.105 if Field #A is dis-
abled and Field #B is enabled via EE.5300.0) is normalized by the flux saturation curve
defined by EE.1568-EE.1575. However, FLDB__LOS uses UN-normalized field feedback to
detect a fault and can compared to the field loss limit (FLBLSO) by viewing IF2FB,
VAR.1029.
166 FLDB_TOC Field #B timed overcurrent Trip fault

The field current has exceeded the reference by an amp-seconds rating defined by
EE.1ses, FBTOCO.
Possible causes:
- Field SCR(s) shorted.
- Field regulator unstable or running in voltage regulated mode.
- FTOCGn set too sensitive.
- Excessive field forcing through BLK.259 or 300 iVAR.165).
Field SCR firings are inhibited when this fault occurs.
Beginning with revision 6.31 I IFLDAFB (VAR.1090) (or FLDFB. VAR.105 if Field #A is dis-
abled and Field #B is enabled via EE.5300.0) is normalized by the flux saturation curve
defined by EE.1568-EE.1575. However, FLDB_TOC uses UN-normalized field feedback to
detect a fault which is typically equivalent to lF2FB, VAR.1029.
9-27
Table 9-5. Speci17c Fault Troubleshooting Using Fault Numbers - Continued
167 FLDB_TRK Field #B undercurrent tracking Filtered fault

The field current has remained below the field command by at least 15% of rated for more
than 5 seconds.
Possible causes:
- Field #B enabled (EE.570.9). but not installed
- Hot field. Unable to achieve commanded current.
- Field regulator unstable. Check tuneup.
- See also FLT.165, FLDB_LOS.
Set EE.571 .o to inhibit field tracking for both field #A and #B.
Beginning with revision 6.31 IFLDBFB (VARJO91) (or FLDFB, VAR.105 if Field #A is dis-
|
abled and Field #B is enabled via EE.5300.0) is normalized by the flux saturation curve de-
fined by EE.1568-EE.1575. FLDB_TRK uses this normalized field feedback to detect a fault.
1 68 IA2 _OFST DCFB card IA2 shunt VCO zero offset too high Non-latched
While the drive is stopped (no current flowing in the shunt). it has measured more than 5 % annunciated
current, indicating an excessive zero offset in the current feedback isolator lA2 on the fault
DCFB. Detection of this condition can be overridden by EE.571 .4-, MFLTJP.
Possible causes:
- lA2 connected incorrectly at shunt or plug on DCFB.
- Second shunt enabled via EE.1501 .2, but not connected.
Twisted pair from shunt picking up noise. Route away from power leads and twist pair
tighter.
- Failure in the current feedback isolator on the DCFB.
1 69 VM1 _OFST DCFB armature voltage (VM1l feedback VCO zero offset too high Non-latched
During powerup, or while the drive has stopped if EE.570.5, MCNFIG, is set, a zero offset annunciated
greater than 5% has been detected in the VM1A/VM1B armature voltage sensor circuitry on fault
the DCFB. Possible causes:
- EE.569 is set beyond its range (SDCC/DCFB combination only).
- EE.569 is set to improper value. Run test 14 to set automatically.
- EE.570.5 is set and drive can be externally rotated while stopped.
Failure of DCFB.
- Wiring error in connection of armature signals (VM1A/B) to feedback interface card.
Detection of this condition can be overridden by EE.571 .5, MFLTJP.
187 CFB_POL_ Do (armature) shunt polarity reversed Filtered state

The drive has measured a 20% reverse current while firing the forward bridge or a 20%
forward current while firing the reverse bridge. Possible causes and solutions:
- Run cell test (12) to confirm fault (revision 1.50 AF or later). Note in DCFB dual shunt
applications, cell test reports this fault regardless of whether shunt IA or lA2 is
backwards, so both shunts should be checked.
- DPRL wired backward at shunt or plugged in backward on SDCI/DCFB.
- Gate lead plugs connected to wrong SCRs.
- Twisted pair from shunt picking up noise. Route away from power leads and twist
pair tighter.
- Failure in the current feedback isolator on the SDC!/DCFB.
- During cell test on multibridge drives, if a cell is shorted, it is possible for reverse current
to flow in a shunt. Inhibit this fault and run cell test again to locate the shorted SCR.
Detection of this condition can be overridden by EE.571 .3, MFLTJP.
188 FLD_OFST Field current feedback VCO zero offset too high Non-latched
During powerup, a zero offset greater than 5% has been detected in the field current sensor annunciated
circuitry on the SDCI/DCFB. Field firing is inhibited and the drive makes additional offset fault
measurements. If the excessive offset was actually due to a decaying field current, when
the current decays, the fault will automatically clear if the offset returns to normal. Report-
ing of an excessive offset and the concurrent field firing shutdown can be inhibited by
EE.571 .4, MFLTJP. The maximum erroneous offset due to a decaying field under these
conditions is 5% of rated. Possible causes:
-
Drive came out of a hard reset before field decayed. Hold reset button closed for ten
seconds before releasing and see if fault clears.
- JP1 , JP2, or P3 on DCI not set correctly.
- Failure of SDCI/DCFB.
- For SDCC, U31 date codes 2 9420 may require DCP revision 2 5.10.
9-28
189 VFB_OFST Bridge or armature voltage feedback VCO zero offset too high Non-latched
During power-up, or while the drive is stopped if EE.570.5, MCNFIG, is set, a zero offset annunciated
greater than 5% has been detected in the bridge (P1IP2) voltage sensor circuitry on the fault
DCI/DCFB/SDCI. Possible causes:
- EE.574 is set beyond its range.
- EE.574 is set to improper value. Run test 14 to set automatically.
- EE.570.5 is set and the drive can be externally rotated while stopped.
- Failure of the DCI/DCFBISDCL
- Open or intermittent connection on pins 25 or 26 of ribbon cable 5PL.
- Wiring error in connection of armature signals (P1/P2) to feedback interface card.
Detection of this condition can be overridden by EE.571 1.5, MFLTJP.
1 SO IDlSC_FL Discontinuous current sensor failure, stuck discontinuous Filtered fault

The discontinuous current sensor is not detecting any armature current when CFB is actu-
ally greater than 1 pu. On the DCI card, this sensor is a hardware circuit which looks at
CFB, and is only used with the DCC control card standard current regulator and only prior
to revision 2.20. On the DCFB, or when a Dcl is used with the SDCC, or when the en-
haneed current regulator is used (EE.570.2), or after revision 2.17, discontinuous current is
determined using the VFB signal. Possible causes of this fault:
- Circuit failure on DCI/DCFB.
- .
Routing, twisting, or installation of shunt to DRPL wiring
- Failure or low scaling of VFB circuit (revision 2.20 or later).
Detection of this fault can be inhibited by setting EE.571 .2. lt is recommended that
EE.571.1 be set if the enhanced current regulator is enabled and the MP firmware revision
is less than 2.20.
191 ICONT_FL Discontinuous current sensor failure, stuck continuous Filtered fault
When the drive is stopped, the discontinuous current sensor is reporting armature current.
Possible causes:
- Dc shunt installed incorrectly or connections loose.
- Routing of twisted pair from the shunt to DRPL on the DCI. Twist the pair tighter and
route away from noisy wiring.
- DRPL plugged in incorrectly or loose.
- Current feedback isolator failure on the DCI.
- Failure or high scaling of VFB circuit (revision2.20 or later).
Detection of this fault can be inhibited by setting EE.571 .2. Please refer to additional help
at FLT.190.
192 DIMETRIC Dimetric (do bus shoot-through) fault Trip fault

The drive has shutdown because it detected an SCR bridge dimetric fault. During the first
45 degrees after each firing, the average do voltage is sampled over three intervals of ap-
proximately 15 degrees each. If the sum of these voltage magnitudes is less than
EE.DlMTRC, and the average de current (VAR.CFB) is greater than 15 percent, then fault
192, DIMETRIC, is reported. Possible causes:
- Shorted SCR. Run cell test (test 12).
- EE.588. DIMTRC, setting is too high.
- A commutation failure occurred but was not detected. Check EE.581 .
When this fault is detected, armature and field SCR firings are immediately inhibited (no
phase-back occurs first).
9-29
GEH-6005 DC2000 Digital Adjustable Speed drive
193 VARMTRCK Mismatch of bridge and armature voltage feedback signals from DCFB Trip fault
Voltage feedback variables VARM and VBRIDGE from the DCFB have differed by more than
20% for 360 firings while the MD contactor is supposed to be closed.
Possible causes:
- VM1A/B on DCFB not connected to motor armature.
- P1A/B on DCFB not connected to SCR bridge output.
- DIP switches scaling for P1 A/P2A (SW4) and VM1A/B (SW5) on the DCFB ' not set to
same voltage range.
-MD contactor not closing when it should.
- Impedance added between the bridge and the armature is dropping more than 20%
voltage. If this is OK, inhibit FLT.193 via EE.571 .14.
- Failure of VCOs on the DCFB or VCO counters on the SDCC.
-VCO counters not loaded in LCA logic due to invalid value in EE.1.5.
-Revision of DCP is less than 2.32.
Detection of this condition can be overridden by EE.571 .14, MFLTJP. Also see EE.570.1 1 .
194 HDWRTYPE Mismatch of firmware settings and drive hardware detected Trip fault
The drive has detected a discrepancy between firmware configuration jumpers and actual
hardware installed. Possible causes:
- DCFB detected at 1 PL, but SDCI selected via EE.573.0.
- Field #B enabled (EE.570.9) without DCFB or with field #A in the 2/3 wave mode
(EE.573.2)-
- Multibridge enabled (EE.607.0) without DCFB or while not in simulator mode.
195 DCFBFAIL DCFB logic cell array failure Trip fault

The feedback signal from the DCFB to the SDCC indicates that the programmable logic
device on the DCFB has failed to configure itself on powerup. Possible causes:
- Configuration PROM or LCA on DCFB missing, failed, or not fully seated.
- Failure of 1PL ribbon cable (pin 28 should go low after initialization).
- Failure of the DCFB.
Inhibit this fault by setting EE.571 .12 (weight 4096).
196 LEG_LOSS A c leg current low or unbalanced Trip fault

Possible causes:
- EE.584 or 585 set too sensitive.
- Blown leg fuse or open SCR or gate lead. Run cell test.
- Ac line phase imbalance.
- Erroneously reported by software revisions prior to 1.51 .
- Logic current limit (EE.1508) set near or below current limit.
A setting of o in EE.585, LEGSEN, inhibits FLT.196.
197 OVERV_MB 'Instantaneous overvoltage for motor #B Filtered fault

The armature voltage connected to DCFB (only) analog voltage input VM2A has exceeded
the limit set by EE.606, MBOVLT. This voltage could be either the GF2000 motor voltage,
r'
or- motor #B in a dual-motor (parallel) application. Possible causes:
- VM2A not connected to a valid voltage feedback.
- VM2A not scaled properly via EE.1524, VM2SFO.
- Fault input connected to VNIA1 instead of VMA2, per EE.573.5 .
- See help for FLT.19 for additional causes.
9-30
.p
I
I
vii- ii
I No. Name Fault Condition, Causes Type Fault
198 FIELDTRK Field undercurrent tracking Filtered fault

The field current has remained below the field command by at least 15% of rated for more
than 5 seconds. Possible causes:
- Hot field. Unable to achieve commanded current.
- Field regulator unstable. Check tuneup.
- See FLT.4, FIELDLOS.
- Wrong field mode (2/3, NRP, or NRX) selected via EE.573.2.
- For SDCC, U31 date codes 2 9420 may require DCP revision .2 5.1 O.
Set EE.571 .O to inhibit field tracking.
Beginning with revision 6.31, IFLDAFB (VAR.1090) (or FLDFB, VAR.105 if Field #A is en-
abled via EE.5300.0) is normalized by the flux saturation curve defined by EE.1568-
EE.1575. FIELDTRK uses this normalized field feedback to detect a fault.
199 IOC_RVRS Reverse bridge instantaneous overcurrent Trip fault

The bridge current in the reverse direction as sampled by the do shunt has exceeded the
limit set by EE.1527, IOCRVO. Possible causes:
- IOC set too low. Check IOCRVO (EE.1527)-
- See other causes listed for FLT.1 .
200 IOC_MTRB Armature instantaneous overcurrent for motor #B (DCFB only) Trip fault
The armature current as sampled by the de shunt IA2 (DCFB only) has exceeded the limit set
by EE.1529, IOCMBO. Possible causes:
- IOC set too low. Check IOCMBO (EE.1529).
- Shunt lA2 not connected to a valid current feedback signal.
- Shunt IA2 not scaled properly (EE.1521, CF2SFn).
- CF2SFn (EE.1521) set too low, causing saturation of the hardware.
201 IOC_ARM Armature instantaneous overcurrent Trip fault

The armature current as sampled by the do shunt has exceeded the limit set by EE.1525,
IOCARO. Possible causes:
- ROC set too low. Check IOCARO (EE.1525).
202 SYINLOSS Loss of ac line sync input Trip fault
The SYNC signal on the DCI/SDCI/DCFB is not tracking an appropriate ac line frequency.
Possible causes: -
- Bridge power which connects to power supply card not turned on. Check L1/L2/L3 inputs
to card; for DCFB also DIP switch settings.
- Line or power supply card fuses are blown or missing. (Check MOVs).
- Failure of SDCI/DCI or 1PL (pin 29). Verify line frequency TrL signal at TP29 on
DCC/SDCC.
- Misconfiguration of PLL configuration. Check EE.570.3 and EE.572.4, 6, & .10
all normally O. Verify EE.570.4.
- Excessively noisy. notched, or unbalanced ac line.
- Failure of 115 volt power supplies.
- (Early DRVTYP=5 K-frames only) Failure of LAN power supply or SPCB. misconfiguration
of multibridge master orfollower drive (EE.572). .
-On revision 1 .40 and earlier, this fault is erroneously reported and should be inhibited via
EE.571 .7.
Presence of ac line sync is essential for proper field and armature operation, even in the
simulator mode, as the PLL and field regulator do not operate in the absence of this input.
Beginning with revision 5.31, field and armature SCR firings are inhibited when this fault
occurs.
Beginning with revision 5.36, for DC2000 only, this fault requires a hard reset to clear. For
revision 6.31 and later (DCZOOO only). if EE.6283.6 is set, this fault can be cleared by invok-
ing a soft reset (a firm reset is performed). See EE.6283.6 for details.
203 NO_BURST SYOSC (synchronized firing burst generator) failed Trip fault
The pulse train from the oscillator used to form the SCR firing bursts is missing. This signal
should appear on 1 PL-14 as a 20% duty cycle, 25 kHz, TTL waveform. Possible causes:
- Failure of U61 or U27 on the SDCC. Replace SDCC.
- Failure of ribbon cable 1PL.
-
Misoperation of control card due to noise or intermittent connection on control card.
Cheek installation of socketed components.
9-31
204 LO_ACFRQ Low ac line frequency, less than 45 Hz (or phase loss) Filtered fault
The drive is not receiving a suitable ac line sync signal from the DCI/DCFB or its frequency is
outside acceptable range. Possible causes:
- Alternator power supply (if used) not maintaining line frequency.
- Fuses blown on the interface card. Check MOVs.
- Excessive ac line phase imbalance or notching.
- Nuisance fault due to software error prior to revision 1.20.
- See additional items under FLT.202.1 .
This fault can be overridden by EE.571 .1 O. Beginning with revision 5.31, field and armature
SCR firings are inhibited when this fault occurs.
205 Hl _ACFRQ High ac line frequency, greater than 70 Hz (or phase loss) Filtered fault
206 AC_GT__DC Ac current exceeds do current trip Trip fault

The magnitude of ac current transformer current, VAR.1 O19, CTCFB, has exceeded the
magnitude of do shunt current, VAR.104, CFB, by the trip threshold, EE.1519, ACGDCn.
Possible causes:
- Improper CT burden selection on the DCI/DCFB.
- Improper scaling of CTCFB via EE.1520, CTTRMn.
- ACGDCn, EE.1519, set too low.
- Too much circulating ac current or bridge fault.
This fault may be inhibited by setting EE.1519 to O.
207 CT_OFSET High ac.current transformer offset read when current should be O Trip fault
A reading of over 250% current has been read on one of the current transformers when the
drive is not firing SCRs. Possible causes:
- Open or intermittent connection on pins 1 or 2 of ribbon cable 1 PL.
- Failure of CT interface circuitry on the DCI/DCFB.
- Failure of DCC/SDCC.
This fault may be inhibited by setting EE.581 to 32767.
208 1L1 _LOSS Ac current transformer IL1 too loquat given CFB level Trip fault
Possible causes:
- ICPL on DCI/DCFB not connected.
- CTs not burdened correctly.
- (Non-regenerative only) Fault must be inhibited via EE.587.
- EE.587 set too low.
VAR.1019 for same polarity and magnitude. Use burden switches for coarse adjustment,
EE.1520 for fine.
- For early revisions, see note under EE.587 and increase EE.587.
209 IL3 _LOSS Ac current transformer IL3 too low at given CFB level Trip fault
210 CT_POLAR Ac current transformer IL1 or IL3 polarity reversed Trip fault
Possible causes:
- Leads swapped in CT connector, ICPL, on SDCI/DCFB card. Compare VAR.1 O4 and
EE.1520 for fine.
- CTs improperly burdened on DCI/DCFB.
- Gate leads connected to wrong SCRs.
- Hardware too sensitive prior to 531XDCIANG1/AJG2 revision.
- For early revisions, see note under EE.587 and set EE.571 .8.
Once CTs are known to be wired correctly, this fault may be inhibited by setting EE.571 .8.
21 1 CFB_LOSS CFB too low at given ac current transformer level Trip fault
Possible causes:
- CTs not burdened correctly. Set burdening to a higher horsepower.
- EE.586 set too low.
.
EE.1520 for fine.
Nuisance trips due to hardware/software sensitivities prior to 302DCIANG1/AJG2,
302DCCAMG1 , and 1.60 (AG) revisions. Increase EE.586 by up to 2:1 to
desensitize (see note under EE.587).
9-32
212 HSO_OVFL Internal armature firing circuit failed Locked fault

Fault 212 indicates an internal software overflow in the high speed output buffer.
Possible causes:
- Software malfunction due to noise or intermittent connection on 301DCC. Check
external signal wiring practices, installation of socketed components, ribbon
cables, and low voltage power supplies.
- Armature current regulator bandwidth set higher than software is able to achieve.
Try reducing bandwidth.
- For K/L frame (muitibridge) follower drives, the master drive was hard reset, causing
.
the follower to lose synchronization.
- Inappropriate PLL selection (EE.570.4) or gain (EE.575-577).
- Loss of sync signal, see FLT.202 (SYINLOSS) possible causes.
This fault may be inhibited via EE.571 .9. Field and armature SCR firings are inhibited when
this fault occurs.
For revision 6.31 and later (DCZOOO only), if EE.6283.6 is set, this fault can be cleared by
invoking a soft reset (a firm reset is performed. See EE.6283;6~for details.
213 CTSTFAIL Cell test failed to determine the state of the SCRs due to setup Trip fault
Cell test detected a short during one pass and an open circuit during the other pass, and
thus was not able to reliably determine the bridge health. Possible causes:
- The cell test configuration parameters (EE.1577 - EE.1579) are all set too low for
adequate signal-to-noise margins, and must be raised.
- Failure of the CFB and/or VFB sensing circuitry (DCl/DCFB).
- Excessive noise in CFB and VFB due to poor wiring or loose connections
214 CTST_VFB Cell test detected too much armature voltage at startup Trip fault
At the .beginning of the shoricircuit test, VFB was greater than 5% and the SCRs cannot
be reliably tested. Possible causes: .
- The motor was rotating when cell test was invoked.
- Dc contactor not closing, or longer MAPDLY time needed (EE.39).
- Excessive offset in the VFB circuitry (See EE.574).
- Failure in the VFB sensor or connections (DCIIDCFB).
- Excessive leakage in the bridge snubbers or SCRs, coupled with an open armature
loop (especially if do contactor is used).
This fault may be overridden by setting EE.571 .1 1.
215 VFB_FAIL Ce!! test detected a low or reverse armature voltage Trip fault
During the open circuit test, VFB magnitude or polarity was incorrect. Possible causes:
- Reversed or open connections of armature to power connect card.
- Open connections in ribbon cable 5PL pins 25 or.26.
- Open circuit test firing angle too low -- increase EE.1577.
- Failure in VFB circuitry on control card or power supply card.
- Revision 1.90 only: Erroneously reported during cell test in simulator.
This fault can be overridden by setting EE.571.1 1 .
221 VAC_OFST V12 or V13 feedback VCO zero offset too high Non-latched
The DC offset in DCFB signals V12 and V13 are continuously computed. FLT.221 is gen- annunciated
erated if a zero-offset greater than 3% has been detected in one or both of these signals. fault
Possible causes:
- Failure of DCFB card or ribbon cable 1 PLY
- Wiring error in connection of signals (V1N2/V3) on DCFB card
- Excessive coupling of common mode noise into floating commons of DCFB card via
feedback connections due to poor cable routing.
Detection of this condition can be overridden by EE.1500.15, MJPROO. Effective revision
4.35.
9-33

222 lINT _SAT Enhanced current integrator saturated (DRVTYP=85) Non-latched

The enhanced current regulator integrator has remained saturated (reached the limit, annunciated
ILIMc0 EE.1581) for 60 firings in a row. Detection of this condition is enabled by setting fault
EE.6283.2 (MCFGJP). Possible causes: .
- Voltage feedback is scaled incorrectly. Check EE.1503 (VFBSFO) and hardware jump-
ers on the DCI/DCFB card for correct scaling.
Ac voltage input is NOT actually within the nominal range indicated by the data used
to calculate the integrator limit (ILIMcO, EE.1581 ).
EE.1581 (ILlMcO) is still set too low even though the above two conditions are OK.
Voltage feedforward gain tuned too low, check EE.1585 (WVFBcO), EE.1 586
lGVFFcO). and EE.1594 (HlRCPO)-
(Simulator only) EE.ARMRES, ARM_TC, or EE.lOCTRn set too low.
223 ILP_OPEN Enhanced current integrator saturated at CFB less than 5 % (DRVTYP=85) Non-latched
The enhanced current regulator integrator has remained saturated (reached the limit, annunciated
lLIMcO EE.1581) for 60 firings in a row and armature current has remained less than 5%. fault
Detection of this condition is enabled by setting EE.6283.0 (MCFGJP). By setting
EE.6283.1, this fault can be changed from an brief annunciated fault (does not stop the
drive) to a trip fault. Possible causes: [4.41]
Voltage feedback is scaled incorrectly. Check EE.1503 (VFBSFO) and hardware
jumpers on the DCI/DCFB card for correct scaling.
EE.1 581 (ILIMcO) is set too low.
Voltage feedforward gain tuned too low, check EE.1585 lWVFBcO). EE.1586
(GVFFcO). and EE.1594 (HIRCPO>.
Open connections or contactors in the motor armature circuit.
Open connections in 5PL, DRPL, or SCR gate leads.
DC fuse open.
(Simulator only) EE.ARMRES, ARM_TC, or EE.lOCTRn set too low.
225 IOC_MTRA Armature instantaneous over-current for motor #A Trip fault

The armature current as sampled by the do shunt lA1 has exceeded the limit set by
EE.6302, IOCMAO. Possible causes'
- IOC set too low. Check IOCMAO (EE.6302).
- Shunt IAA not scaled properly (EE.1505, CFBSFn).
- CFBSFn (EE.1505) set too low, causing saturation of the hardware.
226 CFBB_POL Motor B lA2 shunt polarity reversed (DCFB only) Filtered state
Used primarily in 2-motor applications with separate motor loops. The drive has measured
a 20% reverse IA2 shunt (DCFB only) current while firing the forward bridge or a 20%
forward IA2 shunt current while firing the reverse bridge. Possible causes and solutions'
- Run Cell test (1 Zi to confirm fault.
- IA2 wired backwards at shunt or plugged in backwards on DCFB.
- Gate lead plugs connected to wrong SCRs.
- Twisted pair from shunt picking up noise. Route away from power leads and twist
pair tighter.
Failure in the current feedback isolator on the DCFB card.
During cell test on rnultibridge drives, if a cell is shorted it is possible for reverse cur-
rent to flow in a shunt. Inhibit this fault and run cell test again to locate the shorted
SCR.
Detection of this condition can be overridden by EE.571.3, MFLTJP.
9-34

230 MBLCONFG Multibridge EE configuration error Non-iatched

An invalid EE configuration for multibridge exists. Probable causes: annunciated
- MBLTTL (EE.61 O) set to less than 2 drops fault
- MBLCFG (EE.608) A + B total drops doesn't equal MBLTTL total drops
- Cell test or torque proving activated on revisions which do not contain these features.
The configuration must be corrected and all bridges hard reset.
231 CTACSHRT indeterminate shorted cell detected during SCR test Trip fault
During the short circuit cell test, current was detected in either the shunt or CT, but the
voltage produced across the armature was insufficient to determined which cell was
shorted, perhaps because the EE.1578 voltage detection threshold was set too high, the
EE.1579 current detection threshold was set too low, or the EE.1580 firing angle was set
too low. Review these adjustments and repeat the cell test.
232 MBRGSHRT A multibridge follower detected a short in its bridge Trip fault
During a cell test of the multibridge, a follower detected CT or shunt current during a
period when none of that follower's cells were being gated, indicating a shorted cell.
Normally. under such a condition, the master bridge will detect which leg (A1 - A6) is
shorted and report a FLT.81 - 86, and the follower bridge containing the short will report
a FLT.232 to pinpoint the shorted cell.
233 MBBALANC K/L frame multibridge master/follower current out of balance Non-latched
A drive's current has stayed in error from the master current reference by over 50% for annunciated
over 2 seconds and the master current reference is greater than 50%. As of revision fault
4.35, if this fault condition persists for over 5 seconds, the fault changes from brief an-
nunciated to trip. Possible causes:
- The drive has been stopped by a local stop command.
- The drive is not generating any current due to blown fuse, open contactor or
connection, or failure in the firing circuit hardware.
- Failure in the drive current feedback circuitry.
- For follower bridges, balance regulator gain (EE.61 Zi set too low.
- EE.MBLTTL or MBLCFG set incorrectly in master drive(s).'
Detection of this fault may be inhibited by setting EE.607.5.
234 MBLSCHEX KIL frame multibridge follower feedback checksum error on fiber-optics Non-latched
The master drive received an invalid message from a follower drive over the fiber-optic annunciated
link. Possible causes: fault
- Two followers have the same drop number (EE.609, MBLDRP).
- Loose or bad coupling in the fiber-optics, or cable crimped.
- Stray light entering fiber-optics through unused MBHA connector.
9-35
GEI-I-6005 DC2000 Dagirm Adjustable Speed Drive

235 MBLSLVRN K/L frame multibridge follower running when master bridge is stopped Non-latched
Follower drives cannot run unless the master drive is running. Possible cause: annunciated
Follower commanded to run from Programmer or other local source when master fault
drive is not running.
236 MBLMNOEC K/L frame master bridge did not hear its own message on the fiber-optic Non-latched
The master drive listens to the commands it sends to the followers on the fiber-optic ca- annunciated
ble. This fault is reported if the master drive did not hear these messages. (If it hears fault
these messages, but they are garbled, FLT.237 is reported.) Possible causes:
- EE.572.3 not set.
- Failure of the MBHA board or its power supply.
- Failure of the SPCB daughter card.
237 MBLMBDEC K/L frame master bridge received a garbled echo of its own message Non-latched
The master bridge cannot hear its own fiber-optic transmissions correctly. annunciated
- Multiple bridges programmed to be the master (EE.609, MBLDRP).
- Crimp or sharp bend in fiber-optic cable.
238 MBLMCHEX K/L frame follower drive received a garbled message from the master Non-latched
The follower bridge cannot hear fiber-optic transmissions from the master correctly. Pos- annunciated
sible causes: fault
- Multiple bridges programmed to be the master (EE.609, MBLDRPI.
- Crimp or sharp bend in fiber-optic cable.
239 MBLMLATE K/L frame follower drive failed to receive command from master when expected Non-Iatched
The follower drive did not hear the command from the master bridge in time. or not at all. annunciated
- Follower drive not using master line sync signal lEE.572.4).
- EE.572.3 not set.
- Failure of the MBHA board or its power supply.
- Failure of the SPCB daughter card.
- Master drive not powered or in reset.
Since revision 3.36, MBLMLATE will automatically clear when the master is restored if
the follower was not running when the fault occurred. provided the follower is using its
own line sync rather than the master's.
330 DCP_FAIL DCP selftest failed Trip fault

U1 on SDCC card failed.
331 DCPROMCK DCP EPROM checksum error Trip fault

U1 1 or U12 failure.
9-36
332 DLCAPROG Logic cell array U32 powerup test fail Trip fault
The programmable logic cell array (LCA) device U32 has failed to program correctly. Pin
55 of this device indicates programming status. After a powerup or reset, this pin should
be low. After U32 is programmed by U1, the pin should be high. FLT.332 is reported if U1
detects this pin in the wrong state either before of after programming. Possible causes:
- Defective SDCC.
- Socketed device on SDCC not inserted fully, or pin bent under.
333 MLCAPROG Logic cell array U31 power-up test fail Trip fault
The programmable logic cell array (LCA) device U31 has failed to program correctly. Pin
55 of this device indicates programming status. After a powerup or reset, this pin should
be low. Programming of this LCA is done daisy-chained with LCA U32. U32 is pro-
.
grammed first, then it passes programming data from U1 through it to U31 After U31 is
thus programmer by U1. the pin should be high. FLT.333 is reported if U1 detects this pin
in the wrong state either before of after programming. Possible causes:
- Defective SDCC.
- Socketed device on SDCC not inserted fully, or pin bent under.
335 DPRLFAIL Dual port RAM between DCP and LCP on the SLCC card failed initialization test Trip fault
Possible causes:
- Improper SLCC installation, including 3PL and 9PL (if used)
- Failure of SLCC card or 3PL.
- (S)LCC enabled via CFGJPR (EE.1 .O), but card not installed .
336 DPRMFAIL Dual port RAM between DCP and MCP on the SDCC card failed initialization test Trip fault
Possible causes:
D
Improper seating of U8, or bent IC pins
Q
Failure of SDCC card.
337 DPRUFAIL Dual port RAM between DCP and UCP on the.Ucc card failed initialization test Trip fault
The EX2000 uses a TCCB microapplication card connected via 3PL. This fault indicates a
failure in the SDCC card test of TCCB memory. Possible causesz'
- Improper TCCB installation.
- Failure of TCCB card or 3PL ribbon cable.
- TCCB UCC card enabled via CFGJPR (EE.1 .8), but card not installed.
338 TRC_ANUN Timed overcurrent alarm Non-Iatehed

annunciated
fault
339 TRC_TRIP Timed overcurrent Trip fault
Possible causes'
Motor mechanically overloaded due to load or wear.
Field current less than 85% of rated.
TRC settings too low (EE.1489, 1493, 1497).
CFGJPO.8 (EE.1498.8) is set.
Armature winding failure.
DB contactor failure (if used).
TRC@lN (EE.25) if used, is not pointed at bridge or motor current.
340 NOLCPDPR LCC or SLCC DPRAM not detected Trip fault

LAN card not detected or not responding, or LCC detected when SLCC is required. Pos-
sible causes:
- LAN card (LCC) enabled by EE.1 .O, but not installed.
- LAN card (SLCC) enabled by EE.1 .1, but LCC installed instead. (Valid only if SDCC is
present).
- LCC/SLCC installed incorrectly. Check all LCC/SLCC connectors and socketed ICS.
- Failure of 3PL, LCC/SLCC card. or DCC/SDCC card.
341 NOUCPDPR UCC DPRAM not detected .A

Trip fault
Microappl cation card not detected or not responding. Possible causes:
- Microapplication card enabled by EE.1 .8 but not installed.
9-37
No. Name Fault Condition, Causes Type Fault \
342 MOTOR_OT Motor Thermal Switch Fault

The input pointer MOTA@I (EE.3604) is typically pointed at the local drive I/O which is
monitoring the Motor Thermal Switch. For FLTJP1 .3 = O, the sense of fault is 1 =
Faulted, O = No Fault. For FLTJP1.3 = 1, the sense of fault is o = Faulted, 1 = No Fault.
The enumerations at FLTJP1 .O select the behavior of the fault. If the fault input pointer is
not used (pointed at zero) the fault is disabled.
Possible Causes:
- MOTA@l lEE.36o4l Pointed incorrectly
- Improper sense selected by FLTJP1.3 (EE.361 2.3)
- Motor is overheating
343 XFMR_OT Transformer Thermal Switch Fault

The input pointer.XOT@lN (EE.3605) is typically pointed at the local drive I/O which is
monitoring the Transformer Thermal Switch. For FLTJP1.7 = o, he sense of fault is 1 =
Faulted, O = No Fault. For FLTJP1.7 = 1 , the sense of fault is O = Faulted, 1' = No Fault.
The enumerations at FLTJP1.4 select the behavior of the fault. If the fault input pointer is
not used (pointed at zero) the fault is disabled .
Possible Causes:
- XOT@lN (EE_3605) Pointed Incorrectly
-Improper sense selected by FLTJP1.7 (EE.3612.7)
Transformer is overheating
344 BRK_SPLY Brake Power Supply Fault `

The drive sequencing sets RLSEBRAK (VAR.814), which is sent to the brake supply, to
release the brake. The brake supply provides a feedback Boolean that is wired into the
local drive l/o and is set when the brake supply is trying to release the brake. There is
typically a delayed comparison between RLSEBRAK and the brake supply feedback in order
to determine if the brake is responding. The input pointer BPSA@l (EE.3606) is typically
pointed at the result of this comparison for the purpose pf determining a fault condition.
For FLTJP1.1 1 = O, the sense of fault is 1 = Faulted, O = No Fault. For FLTJP1 .1 1 = 1.
the sense of fault is O = Faulted, 1 = No Fault. The enumerations at FLTJP1 .8 select the
behavior of the fault. If the fault input pointer is not used (pointed at zero) the fault is dis-
abled.
Possible Causes:
BPSA@l (EE.3606) Pointed Incorrectly
- Improper sense selected by FLTJP1.11 (EE.3612.11)
as
- Brake Supply is operating improperly
345 UNKNOWNL LCC/SLCC fault outside its valid range. Possible causes: Latched
Communication failure between DCC/SDCC and LCC/SLCC (noise?). annunciated
Failure of LCP processor on LCC/SLCC card, or 3PL/9PL. fault
346 UNKNOWNM MCP fault outside its valid range. Possible causes: Latched
Communication failure between DCP and MCP on DCC/SDCC card (noise?). annunciated
Failure of MCP processor on DCC/SDCC card. Check seating of U21 . fault
Failure of U8 on DCC/SDCC card. Check seating of socketed parts.
347 UNKNOWNU UCC fault outside its valid range Latched

Not used yet. anhunciated
fault
348 LPROTMON Line Protection Monitor Fault

The input pointer LPMA@l (EE.3607) is typically pointed at the local drive I/O which is
monitoring the Fuse Blown indication from the LPPA/B module lLPPA E4 & E5). For more
information, see LPPA. For FLTJP1.15 =. O, the sense of fault is 1 = Faulted, O = No
Fault. For FLTJP1 .15 = 1. the sense of fault is O = Faulted, 1 = No'Fault. The enumera-
tions at FLTJP1 .12 select the behavior of the fault. If the fault input pointer is not used
(pointed at zero) the fault is disabled. Possible Causes:
- LPMA@l (EE.3607) Pointed incorrectly
Improper sense selected by FLTJP1.15 (EE.3612.15)
- LPPA/B giving fuse blown indication
9-38
~*
Dc2000 Digital Adjustable Speed Drive GEH-6005
349 OVTMP_AN Bridge Thermal Switch Fault

The input pointer OTMW@l (EE.3610)is typically pointed at the local drive l/o which is
monitoring the Bridge Warning Thermal Switch. For FLTJP2.5 = O. the sense of fault is 1
= Faulted. O = No Fault. For FLTJP2.5 = 1, the sense of fault is O = Faulted, 1 = No
Fault. The enumerations at FLTJP2.3 select the behavior of the fault. If the fault input
pointer is not used (pointed at zero) the fault is disabled. Possible Causes:
- OTMW@l (EE.36tO) Pointed Incorrectly
*I - Bridge Warning Thermal Switch failure or wrong sense
- Bridge is becoming overheated .
350 BLOCKERR Block Compiler Error Trip fault
An error in the block source list, EE.800-1022, was detected during compilation. A brief
explanatory message appears on the serial link when the compile command ("Z") is is-
suede
352 MINREVNO Software revision too low for EEROM configuration Trip fault
The required revisions indicated by EE.6'5-66 are newer than the actual revisions reported
by test 10. Possible causes: .
-DCP or MCP software revision too old for level requested in EEROM
-LCP software revision too old for level requested in EEROM (DP O-1.87 only)
-EE.65-66 calling for wrong so.ftware revisions
EE.67 calling for' wrong software revision (DP revs O-1.87 only)
-EE.67 must be set to O when DCP 1.60 is used with LCP 5.00 or higher
-Prior to revision 1.70, may indicate bad MCP (try setting EE.66 = O)
-Hardware failure: DCC/SDCC or LCC/SLCC control cards or 3PL. Check seating of
socketed components and ribbon cables.
353 LCPREVNO LCP software revision too lbw for EEROM configuration . Trip fault la |
The required LCP revision indicated by EE.67 is newer than the actual revision reported by
test 10. Possible causes:
- LCP software revision too oldlfor level requested in EEROM.
- EE.67 calling for wrong software revision.
- Hardware failure: DCC/SDCC or LCC/SLCC control cards or 3PL. Check seating of
socketed components and ribbon cables.
354 UCPREVNO UCP software revision toolow for EEROM configuration (trip) Trip fault
This fault code is not presently used in the drive firmware.
355 THA_ANUN Motor A Thermal Model Alarm (Annunciation) Non-latched

This fault occurs when the temperature state of BLK.THRMA reaches or exceeds the annunciated
square of the value set in THAALM [3568]. Possible Causes: fault
- Motor is too hot. Reduce motor loading before trip occurs.
- THAALM 135681 set too low. .
- THATau [3567] (motor time constant] set incorrectly.
- THA@lN [3566] pointed at inc'orrect address.
- THA@SP [3570] pointed at incorrect address.
- THA@GS [3571] pointed at incorrect address.
356 THA TRIP Motor A Thermal Model Trip Trip fault

This fault occurs when the temperature state of BLK.THRMA reaches or exceeds the
square of the value set in THATRP [3569]. Possible Causes:
- Motor is too hot. Reduce motor loading.
1
¢ THATRP [3569] set too low.
- THATau [3567] (motor time constant) set incorrectly.
- THA@IN [3566] pointed at incorrect address.
- THA@SP [3570] pointed at incorrect.~address.
- THA@GS [3571] pointed at incorrect address.
.*
9-39
Table 9-5. Specific Fault Troubleshooting Using Fault Numbers - Continued _,A
357 THB _ANUN Motor B Thermal Model Alarm Non-latched

This fault occurs when the temperature state of BLK.THRMB reaches or exceeds the annunciated
square of the value set in THBALM [3579]. Possible Causes: fault
- Motor is too hot. Reduce motor loading before trip occurs.
- THBALM [3579] set too low.
- THBTau [3578] (motor time constant) set incorrectly.
- THB@IN [3577] pointed at incorrect address.
- THB@SP [3581] pointed at incorrect address.
- THB@GS [3582] pointed at incorrect address.
358 THB_TRIP Motor B Thermal Model Trip Trip fault
This fault occurs when the temperature state of BLK.THRMB reaches or exceeds the
square of the value set in THBTRP [3580}. Possible Causes:
- Motor is too hot. Reduce motor loading.
- THBTRP [3580] set too low.
- THBTau [3578] (motor time constant) set incorrectly.
- THB@lN [3577] pointed at incorrect address.
- THB@SP [3581] pointed at incorrect address.
- THB@GS [3582] pointed at incorrect address.
359 LlNK_LOS Link Presence Fault

Some drives are implemented such that an IOS is the master of the drives functions. The
drive may want to take corrective action through the fault mechanism if the Master IOS
drops off line. Auxcmd's can provide a Link Present bit from the Master IOS and LINK@l
(EE.3611) would typically be pointed at the appropriate Auxcmd. For more information,
see EE.AUXCMA,B,C,D.
For FLTJP2.9 = O. the sense of fault is 1 = Faulted', O = No Fault.
For FLTJP2.9 = 1, the sense of fault is O = Faulted, 1 = No Fault.
The enumerations at FLTJP2.6 select the behavior of the fault.
If the fault input pointer is not used (Pointed at zero) the fault is disabled .
Possible Causes:
- LlNK@I (EE.361 1) Pointed Incorrectly
- improper sense selected by FLTJP2.9 lEE.3613.9)
- Link Presence detection indicates fault
- Data link communication to IOS lost
360 TESTWRUN Tests 12-19 commanded while drive is already running Non-latched
Drive must be stopped before a tuneup, cell test, or board test can be initiated from any state
source.
361 CTST_NH Cell test inhibited (See EE.2.4) Trip state

The cell test or torque proving operations have been invoked although cell rest has been
disabled by EE.2.4. Some applications, such as elevators, may require special external
control sequences before cell test should be allowed.
362 CTST_TIM Cell test response timeout Trip fault

The start/stop sequencer timed out waiting for the motor control processor to complete a
cell test/torque proving cycle. Possible causes:
- Failure of DCC/SDCC MCP processor due to noise or intermittent card or IC socket
connection--check U22/U23, etc.
- (DC2000) Line sync power removed then reapplied without a hard reset
363 PROC_RSP No process response to enable request Trip fault

Blockware or motor control processor has not responded to a request by the start/stop
sequencer. possible causes: '
- CORE block not programmed correctly.
Other MCP faults exist but are inhibited by EE.4.1 O.
9-40

364 PROC_TRC1 No process response to a regulate torque request (see FLT.363) Trip fault
365 S$ _LOGIC Illegal start/stop sequencer logic state. Trip state

This fault indicates the drive's sequencing logic has reached an undefined state, due to a
failure in the DCC/SDCC card firmware.
366 MCONOPEN M contactor reporting open/closed when it should be open/closed Trip state
For DCC, the drive has been commanded to start, and has requested that the main con-
tactor close, but ten seconds have elapsed and the feedback variable, MACLOSFB
(VAR.823), which indicates the status of the contactor, indicates it has not closed. Note:
From revision 1.82 to 1.91 l this fault did not trip the drive.
For SDCC, revision 2.22 to present, the commanded main contactor states (MDACLOSD,
VAR.823 and BCL SD, VAR.766) do not agree with the actual states (MACLOSFB,
VAR.823 and MDBCLSFB, VAR.765) or simulated ~contactor states. See EE.1498.4 and
VAR.761.
Possible causes:
- MACLOSFB not pointed to contactor input via EE.295, MCLS@l.
Failure in contactor, wiring, or pilot relay.
- For SDCC, MDBCLSFB not pointed to contactor input via EE.244, MBCL@l.
- For SDCC, MAPDLY, EE.39 set too short.
This fault can be inhibited by FLTJPR.4 (EE.4) beginning with revision 2.31 .
357 FAN_LOSS Normally closed "loss of fan" interlock is open Filtered state
Possible causes:
- Failure of cooling fan(s), blower fuses, etc.
- Improperly selected source of FAN_LOSS (EE.296).
- External interlock from fan open or improperly connected.
This fault can be changed from an alarm to a trip via FLTJPR.2 (EE.4).
Beginning on revision 4.35, this fault is affected by the fault power-up timer. See EE.36
FUPDLY and vAR.819 FTPUPTIM.
368 OVERTEMP Normally closed "overtemperature" interlock is open Filtered state
Possible causes:
- Overheating due to loss of blower, clogged air filters, etc.
- improperly selected source of OVERTEMP (EE.297).
- External interlock from thermal sensor open or improperly connected.
This fault can be changed from an alarm to a trip via FLTJPR.3 (EE.4).
Beginning on revision 4.35, this fault is affected by the fault power-up timer. See EE.36
FUPDLY and VAR.8t9 FTPUPTlM.
369 MCONALRM Main contactor feedback alarm Non-latched
This fault occurs when the contactor feedback status while running does not agree with annunciated
the commanded contactor state. Possible causes: fault
EE.295, MCLS@l, or EE.244 not pointed at valid contactor status.
- ..EE.39, MAPDLY, set too short for actual contactor timing.
- EE.45, AUXDLY. set too `short for contactor debouncing.
- Failure in contactor coil driver wiring or circuitry.
- Failure in contactor auxiliary contact feedback wiring.
After revision 2.30, this fault can be inhibited by FLTJPR.4 (EE.4).
370 REVSPEED Speed feedback reports reverse speed Trip fault

This fault is generated when the value of the Boolean pointed to by REVS@I (EE.298) is
TRUE. Possible causes:
- Improper address in EE.298.
- SFB shows rotation opposite to that of the speed command .
371 MOPENRUN RUN request received before main contactor has been closed Non-latched
This fault occurs when EE.MCRQ@lis not pointed at zero (indicating that the contactor is state
being controlled externally). EE.SEQJPR.4 is set (indicating that RUN requests should not
be accepted if the contactor has not been closed), VAR.MACLOSED is false (indicating
the contactor is not closed), and a RUN request is received.
Possible causes:
- External start logic sequencing is incorrect.
- EE.SEO.JPR.4 is set incorrectly.
9-41

372 DCP_EXEC DCP general execution fault Trip fault

Indicates that execution of the foreground module is overflowing the basic execution period
and is doing so to such an extent as to severely limit execution of the background module.
Detection of this condition trips the drive and resets the block interpreter, so that re-
compilation (or hard reset) is required in order to re-activate the functional block structure.
This fault indicates that the scheduled functions severely stress the execution capabilities
of the DCP CPU, so that adjustment of the source list is almost certainly required.
373 DCP_FRGD DCP foreground execution fault Non-latched

Indicates that execution of the foreground module is overflowing the basic execution period annunciated
at a moderate rate. This fault indicates that the scheduled functions somewhat stress the fault
execution capabilities of the DCP CPU, so that adjustment of the source list may be re-
quired. This fault can be inhibited by FLTJPR.5 (EE_4).
374 DCP__BKGD DCP background execution fault Non-latched

Indicates that average execution rates of the background modules are falling below accept- annunciated
able levels. See VAR.514-516 for algorithm details. Possible causes: fault
- Too much foreground loading (block sourcelist loading)
- Too much background loading (winder, serial link, etc.)
This fault can be inhibited by FLTJPR.5 (EE.4).
375 DCP_WDOG Internal DCP watchdog time-out (annunciated). The DCP processor has detected an execu- Latched
tion rate failure of the foreground software in the DCP. DCP background increments a byte annunciated
(DPRM_DCPF_WDOG) approximately 1 1 times per second. MCP background also incre- fault
ments this byte, about 22 times per second. DCP foreground resets this byte to zero about
90 times per second. If DCP background ever sees this byte larger than 50, it generates
fault 375. See related FLT.135. Refer to FLT.134 for possible causes.
376 LCP_WDOG DCP/LCC watchdog time out Trip fault

Failure of watchdog between the drive control processor (DCP) and the LAN control proc-
essor (LCP). If LCP is enabled (CFGJPR.O), DCP monitors a byte from LCP every 89 mini-
seconds. If it is equal to 165, P resets a counter, otherwise DCP increments the coun-
ter. Fault 376 is generated by DCP if the counter ever reaches 10. DCP sets the byte to 85
to allow LCP to verify that DCP is functioning. Possible causes:
- Failure in 3PL or 9PL cable.
- Failure of LCC/SLCC card.
This fault can be inhibited by FLTJPR.9 (EE.4).
377 MCP_WDOG DCP/MCP watchdog time out Trip fault

The DCP has detected an execution rate failure of the background software in the MCP.
MCP background monitors a byte (DPRM_DCPB_MCPB_WDOG) 22 times per second, and if
it is positive, MCP resets it to O. DCP background increments the byte 1 1 times per sec-
ond, and generates fault 377 if it ever gets up to 100 counts. See related fault 134.
Possible causes:
- U22/U23 installed incorrectly (interchanged, backwards, bent pins).
- JP22 on DCC/SDCC card (near crystal X1) not installed.
_ U21 failed.
- Failure of DCC/SDCC card
- U22/U23 defective.
- U21 r U22, U23, U8 or other socketed parts not fully seated.
- Excessive noise on DCOM bus interfering with DCC/SDCC card.
This fault can be inhibited by FLTJPR.1 1 (EE.4).
9-42
No. Name Fault Condition. Causes Type Fault
378 MCPFWDOG MCP foreground watchdog time out Trip fault

The DCP has detected an execution rate failure of the MCP foreground software. DCP
background increments a byte (DPRM_MCPF_WDOG) about 1 1 times per second. MCP
background also increments this byte, about 22 times per second. MCP foreground resets
this byte to zero about 360 times per second. If DCP background ever sees this byte larger
than 100, it generates fault 378. See related fault 136. Refer to FLT.134 for possible
causes. This fault can be inhibited by FLTJPR.1 1 (EE.4).
379 UCP_WDOG DCP/UCC watchdog time out Trip fault
380 BAD_HEXF Bad records in hex download file from LAN or serial link Latched
During a hex ASCII download to EEROM, a record with a bad length, address, record type, annunciated
or checksum was received, possibly due to noise corruption. Only record types O data fault
record) and 1 (end of file record) are allowed. Possible causes:
- Bad hex file
- More than 5 seconds elapsed between successive download records
- Time-out waiting for end of file record (revision 1.71 to present)
- Noise. Try again with drive stopped, or use isolated serial hook-up.
381 EECKSM1 Bad page 1 EE checksum (EE.256 - EE.51 1) Latched

See FLT.13. annunciated
fault
382 EECKSM2 Bad page 2 EE checksum (EE.512 - EE.767) Latched
annunciated
fault

annunciated
fault
384 EECKSM4 Bad page 4 EE checksum (EE.1O24 - EE.1279) Latched

annunciated
fault

annunciated
fault
386 EECKSM6 Bad page 6 EE checksum (EE.1536 - EE_1791) Latched

annunciated
fault
387 EECKSM7 Bad page 7 EE checksum {EE.1792 - EE.2047) Latched

annunciated
fault
388 EECKSNI8 Bad page 8 EE checksum (EE.2048 - EE_2303) Latched

annunciated
fault

annunciated
fault
390 EECKSM1O Bad page 10 EE checksum (EE.2560 - EE_2815) Latched

annunciated
fault

annunciated
fault
9-43

annunciated
fault

annunciated
fault
394 EECKSM14 Bad page 14 EE checksum (EE.3584- - EE.3839) Latched

annunciated
fault
annunciated
fault
396 EEBADSIZ EEROM U9 is the wrong size part for SDCC Locked fault
The SDCC requires a larger EEROM (28c256) than was used on the DCC (28c64). The
drive has detected the wrong part in socket U9 of the SDCC. Possible causes:
- The wrong part is installed in U9.
- The first and second EEROM pages of a valid U9 contains identical data. Change any
EEROM location, then hard reset to see if this corrects the fault.
To replace a DCC with an SDCC and keep the DCC configuration, either use sT2ooo to
load your configuration into the new SDCC EEROM or use the following commands using a
PC with a program which can communicate serially with the drive via COMPL, and which
can upload and download files.
.
1 With the desired configuration EEROM installed, upload its configuration to a file in
the PC by sending the following command to the drive'
"x0-4095 < Enter >
Note: You can use either the DCC or SDCC to do this, provided EE.3.4 is set.
2. With the new EEROM installed in the SDCC, download the file to the drive.
Note: If the EEROM is totally blank (no programming label attached). the
Programmer must first be used to set EE.2 and EE.3 to 21 before completing step 2.
397 IOSEECHK IOS portion of the drive EEROM has a bad checksum Latched
The drive has detected an incorrect checksum in the IOS portion of the drive EEROM. annunciated
Possible causes and solutions: fault
- IOS EEROM not being used, but does not contain all zeroes. Prior to revision 2.41,
this EEROM was not checked by the firmware. To zero the IOS EEROM, send the
three-character string ":FF" to the drive using RS232 terminal mode.
- If IOS (including command language blocks) is not being used, inhibit the IOS and
this fault by setting EE.5500.0.
- Invalid download of IOS EEROM. Repeat the download. *.a
- Bad EEROM U9 on SDCC.
The IOS checksum may be recalculated without erasing the IOS pattern by setting EE.2.1
temporarily and doing a hard reset. Alternately, the serial hex command ":OOFFFF0101 "
will force a calculation of the IOS checksum.
398 IOS_OVFL Drive IOS code stack or timing overflow Trip fault
The IOS portion of the drive firmware has run too long or has corrupted the stack. The
drive trips under this condition. Possible causes:
- The IOS blocks are timed incorrectly. Try using a different pattern of blocks 41 O-41 3.
399 lOS_FLT IOS portion of drive is faulted Trip fault

The drive has detected a fault in the IOS portion of the drive firmware.
Possible causes:
- IOS block enabled, but SLCC not installed.
- IOS blocks enabled, but IOS inhibited via EE.5500.0 (IOSJPR)_
- SLCC not enabled via EE.1.1 (CFGJPR).
- The IOS has tried to log an out-of-range fault to the fault stack. Fault numbers from
IOS must be BOO or greater.
IOS blocks include BLK.410-BLK.418 (lOSn, CLNGn, etc.).
9-44
Table .9-5. Specific -Fault Troubleshooting Using Fault Numbers - Continued

400 L__STKOVR The internal stack has filled the second-to~last byte in the stack area Trip fault
Possible causes:
- LCC/SLCC is defective. Replace the LCC/SLCC.
- LCP programming error. Replace the LCP software with a previous release.
401 L_ECKSUM During initialization, a program code checksum error was found Trip fault
Possible causes:
LCC/SLCC EPROMs are defective. Replace the EPROMs.
LCC/SLCC is defective. Replace the LCC/SLCC.
402 L_If TRAM During initialization, the internal 8OC196 RAM failed Trip fault
Possible causes:
LCP is defective. Replace the LCP (80Ct96)_
403 L_EXTRAM During initialization, the external 80C196 RAM failed Trip fault
Possible causes:
- The external RAM is defective.
- LCCISLCC is defective. Replace the LCCISLCC.
404 L_INTMRS During initialization, the internal BOC196 timers failed Trip fault
Possible causes:
LCP is defective. Replace the LCP (80C196).
405 L_DPRAM During initialization, the dual port RAM failed Trip fault
Possible causes:
- The dual-port RAM is defective.
- LCC/SLCC is defective. Replace the LCCISLCC.
406 L_KPDSHT During initialization, the keypad was shorted Trip fault
Possible causes:
- The keypad has a row shorted to a column. Replace the keypad.
- A key was pushed during initialization. Remove any pressure that might be on the
face of the keypad during initialization.
407 L_STKRAM During initialization, the stack RAM (a portion of the external RAM) failed Trip fault
Possible causes:
- The external RAM is defective.
- LCC/SLCC is defective. Replace the LCC/SLCC.
410 L_LANFLT The BlU is unable to properly receive the data it is transmitting Latched
The BIU has not heard the last 128 bytes sent out on its serial port. annunciated fault
Possible causes:
- Jumpers J1 3, 14, 15, 16, 17. and 18 not set correctly. Check for proper settings.
- The serial lines are shorted. Check for proper wiring connections.
- The SLCC is configured for an isolated DLAN but there is no DLAN power supply
connected to the SLCC. Check for proper wiring connections and power supply if.
needed.
- There are too many termination resistors in the DLAN circuit. Check the DLAN
termination resistors (no more than five sets should be on the LAN).
- There is another drop on the DLAN with the same drop number as this drop. Ensure
that all drops have a unique drop number.
- All drops are not programmed with the same link size. Ensure that all drops have
the same number programmed for the total number of drops on the LAN.
-Hardware driver or receiver, or serial port is defective. Replace the LCC/SLCC.
41 1 L_FRZMSK The Freeze Mask contains more than six variables to be transmitted Latched
Possible causes: annunciated fault
- The Freeze Mask (EE622) contains more than six variables to be transmitted. Adjust
the FREEZE___MASK (EE622) to send no more than six variables.
9.45
41 2 L_BIUMSG The received message does not contain the correct number of bytes Latched
Possible causes: annunciated
- The receiving hardware is defective. fault
- The serial port of this device is defective. Replace the LCC/SLCC on this drop.
- There are too many termination resistors in the circuit. Check the DLAN termination
resistors (no more than five sets should be on the LAN).
- The serial link lines were temporarily shorted. Check the DLAN for possible shorts.
- Defective driver hardware on the transmitting drop. Replace the sender's DLAN card.
- An invalid message was sent on the LAN. If the sender is a user's program, then
check the messages being for proper length.
41 3 L__LANMlS The DLAN contains drops with EXPECTED_ACK enabled and disabled Trip fault
This drop has EXPECTED_ACK disabled while another drop (or drops) on the DLAN has
EXPECTED_ACK enabled, or there is more than one drop with the same drop number.
Possible causes:
- Some other drop has EXPECTED_ACK and WElGHTED_ZERO active while this drop
does not. Ensure that the EXPECTED_ACK and WElGHTED_ZERO are consistent
between all drops on the LAN.
- Duplicate drop numbers being used on the LAN. Ensure that all drops have a unique
drop number. Ensure that all drops have the same number programmed for the total
number of drops on the LAN.
414 L._DCPWAT DCP did not update the DCP watchdog in 240 milliseconds Trip fault
Possible causes:
DCP failure. Replace DCC/SDCC.
Dual Port RAM failure. Replace LCC/SLCC.
Bad 9PL cable. Replace 9PL cable.
416 LARCMSGF This ARCNET node did not receive an ACK after a transmitted message Latched
This node did not receive an ACK for a message that was transmitted five times. annunciated
- The destination node is not present on the ARCNET LAN. Ensure that the destination
node is present.
- The ARCNET cable is open or shorted. Ensure that the ARCNET cable is not open or
shorted between nodes.
417 LARCTAFL The destination node does not have any free receive buffers Latched
This node is unable to send a message because the destination node does not have any annunciated
receive buffers available, or because the ARCNET LAN is constantly being reconfigured. fault
Possible causes:
- Too many messages are being sent to the destination node. Limit the messages
being sent to a drive (100/sec).
- The ARCNET cable is open or shorted. Ensure that the ARCNET cable is not open or
- The ARCNET module is malfunctioning causing constant reconfigurations. Replace
the malfunctioning ARCNET module, if possible.
- The destination node is malfunctioning. Replace the destination node LCC/SLCC.
418 LARCRECO This node is experiencing ARCNET LAN reconfigurations Latched

This node has experienced at least one reconfiguration every 1.28 seconds for a period of annunciated
80 seconds. A soft reset will clear the fault only if a 1.28 second time period has elapsed fault
without a reconfiguration occurring. Possible causes:
- No other ARCNET nodes visible from this node. Ensure that there are other ARCNET
nodes active on the LAN.
- The ARCNET cable is open or shorted- Ensure that the ARCNET cable is not open or
- The ARCNET module for this node has defective drivers or receivers. Replace
ARCNET module.
- An ARCNET module is malfunctioning, causing constant reconfigurations. Replace
defective ARCNET module, if possible.
- There is a 'T' connector in the circuit with an open cable connected to one end.
Remove or terminate the end of the open cable with a 100-ohm resistor.
9-46
419 LARCRSET This node's ARCNET module unexpectedly experienced a RESET Latched
- Loose or poor connections to the LCC/SLCC connectors (power, digital, LAN). fault
Secure or replace all cables connected to the LCC/SLCC.
- Circulating currents due to separated grounds between boards or ARCNET nodes.
- Defective ARCNET module. Replace, if possible.
- Defective LCC/SLCC. Replace.
420 LARCSMCG There is an error in th format of a received ARCNET message Latched
.I
Possible cause: annunciated
- The sender produced an invalid message. Correct the message at the source. fault
421 LARCXRAM During initialization, the ARCNET external RAM failed Latched
- The ARCNET module or external RAM is defective. Replace ARCNET module, if fault
possible.
- LCC/SLCC is defective. Replace.
422 LARCFBIN The format of a received STATUS_S_FEEDBACK message is incorrect Latched

- An ARCNET cable is open or shorted. Check ARCNET cables for opens and shorts. fault
- An ARCNET repeater or node is working incorrectly. Check the ARCNET nodes and
repeaters for passing messages.
- The source of the STATUS _S_FEEDBACK message formed the message incorrectly.
Check the source code for proper STATUS_S_FEEDBACK format.
423 LARCRBFL This ARCNET node's receive buffer has overflowed and a message is lost Latched
- Some other ARCNET node or nodesare sending messages to this node faster than fault
this node can accept the messages. Limit communications to this node. Do not
I exceed 100 messages per second to this node.
1-
425 LDLANMSG DCP has passed an erroneous message to LCP to transmit on DLAN Latched
- DCP has misioaded the outgoing message. Replace evaluation PROMs with released fault
PROMs (DCP PROMS).
- Hardware fault. Check the 3PL ribbon cable and connectors.
426 LARCOUTM DCP has passed an erroneous message to LCP to transmit on DLAN PLUS Latched
DCP has misloaded the outgoing message. Replace evaluation PROMs with released fault
PROMs (DCP PROMs).
- Hardware fault. Check the 3PL ribbon cable and connectors.
427 LCLKSYNC This ARCNET node's clock has been resynchronized with the master clock because there Latched
was more than 64 msec of error between the two clocks. FLT.427 is not a fault; it is a annunciated
momentary condition. Possible cause' fault I
- Turning the master clock on and off. Ensure that the master clock is not turned off.
428 LARCRBFF This ARCNET node's receive buffer has overflowed and a message has been lost. Latched
- Some other ARCNET node or nodes are sending messages to this node faster than fault
this node can accept the messages. Limit communications to this node. Do not
exceed 1 message per 22 msec to this node.

429 LACCAPFL The ac drive's de bus programmed capacitance is too large Latched
This fault may show up in a PARENT (the do bus regulator) or a CHILD (an ac drive tied to annunciated
the do bus). For the CHILD, this fault means the programmed bus capacitance (EE.587, fault
CAPVDC) is larger than 32767, and the value will not be sent to the PARENT. For the
PARENT, this fault declares that:
1) A CHILD has sent a capacitance value greater than 32766 and the value has been
discarded.
2) Drop O has sent a capacitance value. (there should not be a drop O on ARCNET).
3) A capacitor message (PROT 1 1 h) has been received with an invalid length of message
(there should be two bytes to define the cap value).
4) The TOTAL DC BUS CAPACITANCE has exceeded 65535, and has been clamped to
65535. The TOTAL value is passed to DCP through DPRAM DCP VAR.1440.
Possible causes and solutions:
- CHILD EE.587 is larger than 32766. Limit EE.587 to
0 o - 32766.
- PARENT - A CHILD has sent a capacitor value larger than 32766. The drive firmware
doesn't allow the drives to send a value larger than 32766. Check the senders of the
common do bus capacitor message (ARCNET protocol 1 1 h) and limit the value to O -
32766.
-
PARENT Drop O sent a common do bus capacitor value. Find which ARCNET drop
has been programmed to be drop O and program the correct drop number. There
should not be a drop O.
PARENT - A drop has sent more/less than 2 bytes for the cap value. Find which
ARCNET drop is sending the invalid message and correct the message. (If a drop
sends an invalid message, then that drop's value will not get loaded into the
CAP_TABLE.)
- PARENT The TOTAL DC BUS CAPACITANCE has exceeded 65535. Modify the
¢
CHILDREN capacitance so that the TOTAL does not exceed 65535.

To help debug the Common Bus Capacitor TOTAL, you can (through ST2000 Toolkit,
Drive Configurator, or some other RS232 terminal) examine the capacitor table and TOTAL
value by typing in "LB8DOH < cr or 'L47312 <er> .
The first two words are the TOTAL calculated capacitance (LSWORD first).
The next word is a mirror of the TOTAL CAP in DPRAM (DCP VAR.1440)- This word will
be clamped to 65535 if the accumulated capacitance exceeds 65535. The double word of
TOTAL calc cap does not get clamped.
The next 255 words contain each ARCNET drop's (1-255) capacitor value, or 65535 if no
capacitor value has been received, or the capacitor value received plus 32768 if the
"CHILD" is not in Link Presence. Only the entries with their msbit cleared are added up to
make the TOTAL cap. (See EE.706.4, EE.706.5(ARCJP1). EE.719(CBREGU). EE.587
(CAPVDC))-
550 EECKSM16 Bad page 1 6 EE checksum (EE.4-096 - EE.4351) Latched

annunciated
fault
9-48
L - . --


annunciated
fault
552 EECKSM18 Bad page 18 EE checksum (EE,4608 - EE.4863) Latched

annunciated
fault

annunciated
fault
554 EECKSM2O Bad page 20 EE checksum (EE.5120 - EE.5375) Latched

annunciated
fault

annunciated
fault

annunciated
fault
annunciated
fault

annunciated
fault
l _ 559 EECKSM25 Bad page 25 EE checksum (EE.6400 - EE.6655) Latched

annunciated
fault
560 EECKSM26 Bad page 26 EE checksum (EE.6656 - EE.691 1) .Latched

annunciated
fault

annunciated
fault

annunciated
fault

annunciated
fault
564 EECKSM3O Bad page 30 EE checksum (EE.7680 - EE.7935) Latched

annunciated
fault
565 EECKSM31 Bad page 31 EE checksum (EE_7936 - EE.8175) Latched

annunciated
fault
9-49
/
567 GND_ANUN Excess Ground Current Fault Annunciated Non-latched

A ground current signal is brought into local drive analog I/O, conditioned in blockware, annunciated
and sent to a SLD which produces an excess-ground-current Boolean. The input pointer fault
GNDA@l (EE.3608) is typically pointed at this Boolean to provide an Excess Ground Cur-
rent fault. For FLTJP2.2 = O, the sense of fault is 1 = Faulted, O = No Fault.
For FLTJP2.2 = 1, the sense of fault is o = Faulted, t = No Fault. The enumerations at
FLTJP2.0 select the behavior of the fault. If the fault input pointer is not used (pointed at
zero) the fault is disabled .
Possible Causes:
-GNDA@l (EE.3608) Pointed Incorrectly
-Improper sense selected by FLTJP2.2 (EE.3613.2)
SLD compare level set incorrectly
-Excess Ground Current exceeds annunciated level
568 GND_TRIP Excess Ground Current Fault Trip Trip fault

A ground current signal is brought into local drive analog I/O. conditioned in block ware,
and sent to a SLD which produces an excess-ground-current Boolean. The input pointer
GNDT@l (EE.3609) is typically pointed at this Boolean to provide an Excess Ground Cur-
rent Trip fault. The enumerations at FLTJP2.15 select the sense of the fault. For
FLTJP2.15 = O, the sense of fault is 1 = Faulted, O = No Fault. For FLTJP2.15 = 1, the
sense of fault is O = Faulted, 1 = No Fault. If the fault input pointer is not used (pointed
f at zero) the fault is disabled.
Possible Causes:
- GNDT@l (EE_36Qg) Pointed incorrectly
- SLD compare level set incorrectly
- Excess Ground Current exceeds trip level
570 MBDO1TRP Multibridge follower LAN drop #1 is tripped Trip fault

This fault is displayed at the master drive of a multibridge when a follower drive is
tripped. Check the follower drive fault code to determine the cause.
571 MBDOZTRP Multibridge follower LAN drop #2 is tripped Trip fault
572 MBDOBTRP Multibridge follower LAN drop #3 is tripped Trip fault
573 MBDO4TRP Multibridge follower LAN drop #4 is tripped Trip fault
577 MBDOBTRP Multibridge B group master LAN drop #8 is tripped Trip fault
578 MBDOSTRP Multibridge B group master LAN drop #9 is tripped Trip fault
579 MBD1OTRP Multibridge B group master LAN drop #10 is tripped Trip fault
580 MBD1 1 TRP Multibridge B group master LAN drop #11 is tripped Trip fault
581 MBD12TRP Multibridge B group master LAN drop #12 is tripped Trip fault
601 MBDO1ALM Multibridge follower LAN drop #1 has a fault Non-latched

This fault is displayed at the master drive of a multibridge when a follower drive has an annunciated
annunciated (not a trip) fault. Check the follower drive fault code to determine the cause. fault
Note it is possible that the follower fault code was a "brief" annunciated fault, such as
FLT.34 (PLLTRACK), which may no longer be present, giving the appearance that the
master is reporting a follower fault when none exists on the follower's Programmer dis-
play- If ST2000 is connected to the master drive in terminal mode when the fault occurs,
the follower fault code and its alphanumeric will be displayed on the screen.
This fault can also be generated by the master when the master is running and has com-
manded the follower drives to run, but a follower drive reports back that it is not running
(perhaps because the follower was locally commanded to stop). This latter condition may
or may not trip the master drive, depending on EE.607.3.

annunciated
fault
I
9-50
r.
I I
No. Name Faun Cbndiuon, qua; Type Fault

annunciated
fault

annunciated
fault
608 MBDOBALM Multibridge B group master LAN drop #8 has a fault Non-latched
annunciated
fault
609 MBDO9ALM~ Multibridge B group follower LAN drop #9 has a fault Non-latched
annunciated
fault
610 MBD1OALM Multibridge B group follower LAN drop #1 O has a fault Non-latched
annunciated
4.
fault
611 MBD1 1 ALM Multibridge B group follower LAN drop #1 1 has a fault Non-latched
annunciated
fault
612 MBD12ALM Multibridge B group follower LAN drop #1 2 has a fault Non-latched
annunciated
fault
632 MBDO1NAK Multibridge follower LANdrop #1 is not responding Non-latched

This fault is displayed at the master of a multibridge drive when a follower drive is not annunciated
communicating with the master drive. For additional diagnosis, check for fault codes at fault
follower drives to see if follower is able to hear master. Possible causes:
- Follower drive not powered-up or not enabled via EE.607.0.
- Defective, loose, or dirty fiber-optic connection.
- EE.610, MBLTTL, not set correctly to total' number of drops.
- Follower drop numbers. EE.609, not assigned sequentially or uniquely.
- MCPs of all bridges not at same firmware revision.
- MBHA card failure or not powered up check followers for faults).
- SPCB card failure (check SPRS, RX, and TX testpointsl.
- For 12-pulse systems, failure of simplex cable from MBHA C1MODE to respective
master SPCB MODE.
633 MBDO2NAK Multibridge follower LAN drop #2 is not responding Non-latched

annunciated
fault
634 MBDO3NAK Multibridge follower LAN drop #3-is not responding Non-latched
annunciated
I
fault
635 MBDO4NAK Multibridge follower LAN drop #4 is not responding Non-latched

annunciated
fault
639 MBDO8NAK Multibridge B group master LAN drop #8 is not responding Non-latched
annunciated
fault
640 MBDOSNAK Multibridge B group follower LAN drop #9 is not responding Non-latched
annunciated
fault
641 MBD1ONAK Multibridge B group follower LAN drop #10 is not responding Non-latched
annunciated
fault
l
9-51
642 MBD11NAK Multibridge B group follower LAN drop #1 1 is not responding Non-latched
annunciated
fault
643 MBD12NAK Multibridge B group follower LAN drop #12 is not responding Non-latched
annunciated
fault
662 HI_VOLTS -
LNMON Block High Line Voltage Detected Configurable
The LNMON block takes line voltage (VAR.108) and scales it by 20000/LMVSCL. If the
result is greater than LMHIVT for LMCTIM milliseconds then VAR.1 O88 is set and a fault
occurs.
Possible Causes:
- LMHIVT [3590] set too low
- LMVSCL [3588] set incorrectly
- LMCTIM [3589] set too low
- Line voltage is too high
- See also LNMON BLK.344 and VAR.1 O8 ACLINMAG.
663 LO_VOLTS LNMON Block - Low Line Voltage Detected Configurable

The LNMON block takes line voltage (VAR.1D8) and scales it by 20000/LMVSCL. If the
result is less than LMLOVT for LMCTlM milliseconds then VAR.1089 is set and a fault
occurs.
Possible Causes:
- LMLOVT [3591] set too high
- LMVSCL [3588] set incorrectly
- Line voltage is too low
- See also LNMON BLK.344 and VAR.1 O8 ACLINMAG.
664 HI_FREC1 -
LNMON Block High Line Frequency Detected Configurable
The LNMON block takes line frequency (VAR.109) and compares it against LMHIFQ
EE.3592. If the result is greater than LMHIFQ for LMCTIM milliseconds then VAR.1 148 is
set and a fault occurs.
Possible Causes:
0 LMHIFQ [3592] set too low
- Line frequency is too high
- See also LNMON BLK.344 and VAR.109 ACLINFRO..
665 LO_FREQ -
LNMON Block Low Line Frequency Detected Configurable
The LNMON block takes line frequency (VAR.109) and compares it against LMLOFQ
EE.3593. If the result is less than LMHIFO for LMCTIM milliseconds then VAR.1 149 is set
and a fault occurs.
Possible Causes:
- LMLOFO. [3593] set too high
- Line frequency is too low
- See also LNMON BLK.344 and VAR.109 ACLINFRQ.
9-52

666 AUX _FLT1 Aux Fault 1 - Generic Paintable Fault Configurable

Aux faults are generic paintable faults whose behavior is configurable with a jumper enumera-
tion of AXFJP1. The input pointer AXF#@l, when used, points to the Boolean value that sig-
nals the fault condition. The sense of the input Boolean may be either high-enable or Iow-
enable, and is configured with a jumper bit of AXFJP1 . If the fault input pointer is not used
- Improperly selected source pointer AXF1 @|
- Wrong sense of input determined by AXFJP1.3
- Faulted condition at AXF1 @l
667 AUX _FLT2 Aux Fault 2 - Generic Pointable Fault Configurable

Aux faults are. generic paintable faults whose behavior is configurable with a jumper enumera-
.
tion of AXFJP1 The input pointer AXF#@l, when used, points to the Boolean value that sig-
nals the fault condition. The sense of the input Boolean may be either high-enable or low-
enable, and is configured with a jumper bit of AXFJP1. If the fault input pointer is not used
- improperly selected source pointer AXF2@I
- Faulted condition at AXF2@I
668 AUX.__FLT3 Aux Fault 3 - Generic Pointable Fault Configurable

tion of AXFJP1. The input pointer AXF#@l, when used. points to the Boolean value that sig-
.
enable, and is configured with a jumper bit of AXFJP1 If the fault input pointer is not used
- improperly selected source pointer AXF3@I
- Wrong sense of input determined by AXFJP1 .1 'l
- Faulted condition at AXF3@l
I
669 AUX _.FLT4 Aux Fault 4 - Generic Pointable Fault Configurable
1 Aux faults are generic paintable faults whose behavior is configurable with a jumper enumera-
.
tion of AXFJP1 The input pointer AXF#@l, when used. points to the Boolean value that sig-
enable, and is configured with a jumper bit of AXFJP1 . If the fault input pointer is not used
(pointed at zero) the fault is disabled. Possible Causes'
- Improperly selected source pointer AXF4@l
tion of AXFJP2. The input pointer AXF#@l, when used, points to the Boolean value that sig-
nals the fault condition. The sense of the input Boolean may be either high-enable or Iow-
- Improperly selected source pointer AXF5@I
671 AUX_FLT6 Aux Fault 6 - Generic Pointable Fault Configurable

tion of AXFJP2. The input pointer AXF#@l, when used. points to the Boolean value that sig-
- improperly selected source pointer AXF6@l
9-53
672 AUX __FLT7 Aux Fault 7 - Generic Pointable Fault Configurable

Aux faults are generic paintable faults whose behavior is configurable with a jumper
enumeration of AXFJP2. The input pointer AXF#@l, when used, points to the Boolean
value that signals the fault condition. The sense of the input Boolean may be either high-
enable or low-enable, and is configured with a jumper bit of AXFJP2. If the fault input
pointer is not used (pointed at zero) the fault is disabled. Possible Causes'
- Improperly selected source pointer AxF7@l
- Wrong sense of input determined by AXFJP2.1 1
- Faulted condition at AXF'7@l

Aux faults are generic paintable faults whose behavior is configurable with a jumper
enumeration of AXFJP2. The input pointer AXF#@l, when used, points to the Boolean
value that signals the fault condition. The sense of the input Boolean may be either high-
enable or low-enable, and is configured with a jumper bit of AXFJP2. If the fault input
pointer is not used (pointed at zero) the fault is disabled. Possible Causes:
- improperly selected source pointer AXF8@l
808 DPROMCKS Main CPU EPROM checksum failure at U1 1 or U12 (IOS page) Latched
Main processor PROM checksum failure detected in IOS code section. annunciated
fault
so DEVERIFY Value to EEROM, main CPU not verified Latched

The last value loaded to EEROM on the main processor did not verify. annunciated
fault
81 1 SERLCKSM Checksum of transmitted message does not agree with data received Latched
annunciated
fault
812 MLDCKSUM Checksum of transmitted message does not agree with the data in memory Latched
annunciated
fault
815 EE_CKSUM Main CPU EEROM checksum error detected in IOS section Latched
annunciated
fault
815 EElD._.FLT Main CPU EEROM identification failure in IOS section Latched
Main processor IOS EEROM identification failure detected. annunciated
fault
826 ENGSTALL IOS LAN message buffer full. Permissive engines temporary stop Latched
A LAN message buffer is full and permissive engine processing has been temporarily sus- annunciated
pended. fault
827 LUP_WDOG IOS watchdog timer between LAN CPU and main CPU timeout Latched
The watchdog timer between the LAN processor and the main processor has timed out. annunciated
fault
831 L _RWTOUT LAN memory read/write sent but drop did not answer Latched
A LAN memory read or write request was sent to a network drop but the drop did not annunciated
answer. fault
832 WVAR_M$G LAN message buffer full. Math engines temporary stop. Latched
A LAN message buffer is full and math engine processing has been temporarily sus- annunciated
pended. fault
9-54
835 E2_CKSUM Main CPU EEROM checksum error in IOS section Latched
Main processor IOS EEROM checksum error detected. annunciated
fault
836 E2ID_FLT Main CPU identification failure detected in IOS section Latched
Main processor IOS EEROM identification failure detected. annunciated
fault
837 EEMCKSUM Main CPU IOS EEROM RAM mirror checksum error Latched
Main processor IOS EEROM RAM mirror checksum error detected. annunciated
fault
838 E2MCKSUM Main CPU IOS EEROM RAM mirror checksum error Latched
Main processor IOS EEROM RAM mirror checksum error detected. annunciated
fault
839 STAKOVFL IOS scheduler had a task stack overflow Latched

Main processor RTOS operating system task stack overflow. annunciated
fault
841 SENGSTAL LAN message buffer full. Sequence engines temporary stop Latched
A LAN message buffer is full and sequence engine processing has been temporarily sus- annunciated
pended. fault
842 DIAGCOLL Diagnostic data collection fault Latched
An error has been detected in collecting the data for a diagnostic message. annunciated
fault
844 NO_IOS IOS-in-a-Drive is not available Latched

The IOS-in-a-Drive functionality is not available either because it has been disabled or an annunciated
EEPROM image has not been downloaded from the lOS configurator. Other causes of this fault
fault include:
- An invalid or NO EEPROM image was detected by the IOS-in~a-Drive firmware and the
IOS EEPROM configuration was required. Either download the correct lOS configuration
or inhibit the fault by clearing IOSJPR (EE.5500.1 ),
- A configuration was downloaded into an IOS with features that are not supported by
the firmware. Either update the firmware or use the correct version of the lOS
compiler (upward compatibility error).
845 BRIDGFLT Primary network bridge fault Latched

The primary network bridge for a network (FO) message was not in link presence. The annunciated
message was rerouted through the backup bridge drop. fault
846 IOS_INIT IOS portion of IOS-in-a-Drive did not initialize correctly Latched
This error is caused by an invalid EEPROM image or by an EEPROM image that exceeds annunciated
the size constraints of RAM or EEPROM. fault
847 LCP_SYNC The LCP/IOS initialization had an error Latched

The initialization protocol between the LCP and IOS ended either because the LCP did not annunciated
respond within 1 second, or the LCP returned an unexpected initialization state to the fault
IOS's initialization request.
848 REFRESH The IOS is sending out too many refresh bits Latched
There are certain control bits on the drive and IOS that must be refreshed every 1.28 annunciated
seconds after they have been set. The IOS is limited to four such signals active at any fault
given time. The refresh fault is issued when this limit has been exceeded.
849 ACTR_CFG IOS actor/tracker configuration error Latched

The actor/tracker subsystem did not initialize correctly. The tracking system has not been annunciated
enabled. fault
9.55
850 lOS_BUSY The IOS-in-a-Drive background tasks are not executing Latched
The IOS portion of the IOS-in-a-Drive is not being given enough time in the drive block annunciated
scheduling to complete its background scans. This is caused when the scan time of the fault
IOS exceeds ten seconds. More time must be allocated to the IOS in the drive patterns
by using the IOSEP , losz, IOSEP, and IOSB drive blocks if this error occurs.
851 GENI_ERR Error detected on Genius Controller Latched
Genius controller board fault. An error was detected on the I.IGENI controller board. This annunciated
fault should never occur on an IOS-in-a-Drive, because there is no Genius I/O support fault
available.
852 BAD_MSG A message was received on ARCNET that had an invalid format Latched
A message was received that could not be successfully decoded by the IOS. The mes- annunciated
sage was ignored and flushed from the message queue. fault
853 TRKR_MSG An actor/tracker message could not be processed correctly Latched

An actor/tracker message was received that could not be successfully decoded or proc- annunciated
essed by the tracking subsystem. This includes problems with internal actor event fault
queues overflowing. The message was ignored and flushed from the message queue.
854- MSG_OVFL The message object could not transmit a message Latched
The LAN message buffer is full so the message block cannot transmit any more mes- annunciated
sages until buffer space becomes available. fault
855 OOE_FLT Order of execution recursion fault Latched

A call has been made to an order of execution (OOE) sequence that is currently active. anraunciated
Check the OOE logic to ensure that there is not a recursive call to an OOE. fault
856 OBJ_FLT Order of execution calls an unknown object Latched
A request has been made within an OOE to execute an object type that is not yet sup- annunciated
ported by the firmware. Verify that you have the current versions of IOS firmware and fault
compiler.
857 IOS_U857 Undefined IOS error Latched

A new IOS fault has been generated that is not yet supported by the ST2000 data base annunciated
files. Please alert PD of the problem. This fault corresponds to fault 157 on a stand alone fault
los.
858 IOS_U858 Undefined IOS error Latched
A new IOS fault has been generated that is not yet supported by the STZOOO data base annunciated
files. Please alert PD of the problem. This fault corresponds to fault 158 on a stand alone fault
IOS.
859 CLMSGBAD CLMSG used while IOS enabled Latched
The CLMSG block was called when the IOSep blocks were also allowed to generate mes- annunciated
sages. The CLMSG block can only be used when IOSJPR (EE 5500) bits O, 1, and 2 are fault
reset, which will disable the IOS-in-a-Drive functionality. Either set IOSJPR to the appro-
priate value or replace the CLMSG block with an IOSEP block to get rid of the fault.
860 lOS__REV IOS Prom Revision Mismatch

The IOSB firmware revision level is less that the level requested by the IOSB EEPROM
configuration. Either update the PROM set to the appropriate level, or recompile the con-
figuration file using the revision level of the lOSB firmware.
1023 RESET DCC/SDCC is in a hard reset condition Trip fault

If all ten LEDs on the DCC/SDCC are lit continuously, and no fault code is being dis-
played via the RS232 link, Programmer, or LAN connection, the control card is probably
being held in reset. Possible causes:
- External reset input, 3TB-58 or STBA-38, is closed, holding reset high.
- Failure in + 5 V do or £ 1 5 V do control power supplies to the control card.
- EPROMs U22/U23 on the control card not inserted correctly.
- Failure of DCC/SDCC control card.
9-56
CHAPTER 10
DIAGNOSTIC LISTS
10-1. INTRODUCTION A set of four pointers determine the MCP variable for
display in the first four columns. These pointers are
The DC2000 drive software includes the following three EE.600 (MDAIIN), EE.603 (MDAZIN), EE.552
diagnostic features that send selected data to memory: (MPNTR1), and EE.553 (MPNTR2) for the four col-
. Motor Control Processor (MCP) Diagnostic Circu-

lar List
umns, respectively, left to right.
The user selects an MCP variable to display in the first

four columns of the list by entering the variable's ad-
• Drive Control Processor (DCP) Circular List dress (see the description of EE.6282 bit 0 in Table 10-
Blocks 1) into the associated pointer.
• LAN Control Processor (LCP) History Buffer The remaining columns display the bridge current, the
tiring angle, the cell pair select counter, and asynchro-
These features enable variable data to be captured while nous current regulator firing data.
the drive is in operation, and to be read by the user as
an aid in troubleshooting.
10-2.2. MCP Diagnostic Circular List Operation
The MCP and DCP lists are accessed via a serially con-
nected computer using either the ST2000 Toolkit (see Software jumper MDGNIP (addresses EE.6282.0
GEH-5860) or Drive Configurator, LynxOS Version through EE.6282.4) controls the operation of the MCP
(see GEH-6203). The LCP History Buffer is intended to Diagnostic Circular List (see Table 10-1).
be accessed by a Man-Machine Interface 2000
(MM2000) via the drive's DLAN+ connection. Publi-
cation GEH-6212 describes the MM2000; GEH-6213 10-2.3. Circular List Display
provides coniguradon information .
The MCP Diagnostic Circular List can be viewed using
Tables 10-1 through 10-3, located at the end of this the ST2000 Toolkit (see GEH-5860) or Drive Configu-
chapter, define the EEPROM addresses for each of the rator, LynxOS Version (see GEH-6203). To dLisplay the
drive's diagnostic functions. circular list:
1. Using the Programmer, ST2000 Toolkit, or Drive

10-2. MCP DIAGNOSTIC CIRCULAR LIST Conigurator, select the circular list freeze options
by setting software jun1per.MDGNJP .
While the DC2000 drive is mining, selected MCP data
is continuously sent to memory, providing a circular list 2. Select an MCP variable to display by entering its
of MCP variable data. When a stop command, trip, address into one of the four pointers. To do this:
fault, or trigger from the DCP disables the drive, the
data is latched (frozen) 'm memory. This data prowldes a a. Refer to Table 10-1 to find the available vari-
picture of motor control events that occurred just before ables and their addresses (or use the ST2000
the drive stopped. Toolkit or Drive Configurator to read them at
address EE.6282.0). Select up to four variables
for any one Circular List display.
10-2.1. Circular List Content .1
I
b. Use the Programmer keypad, ST2000 Toolldt

The MCP Diagnostic Circular List resides as a page in (EDIT2000 menu item), or Drive Configurator
RAM, 8 columns wide by 128 rows deep. Each column to enter this address into a pointer.
is 1 word wide.
10-1
3. Using the terminal emulation mode of the ST2000 used. For example, a circular list consisting of four 16-
Toolldt or Drive Configurator, enter either of two bit (two-byte) channels, will be 2048 samples long. If
RAM dump commands: more channels are used, the length of the list is reduced
accordingly.
*m60000 Displays the most recent 22 lines in un-
signed format
10-3.1. CLST Blocks
*m60o0o-- Displays the most recent 22 lines in
signed (+/-) format Three CLST blocks are available, each corresponding
to a different functional level: CLST1 (basic level),
"m58288-60336-- Displays all 128 lines 'm signed CLST2 (intermediate level), and CLST3 (advanced
(+/-) format level). Each succeeding functional level builds upon the
functionality of the proceeding level. These levels are
The output is a nine-column page of data arranged as defined in the following sections.
follows:
EEPROM addresses EE.5868 through EE.588l control
Column 1 RAM location (address) the operation of the CLST block. Variable VAR.l453
Columns 2 - S Circular list data, selected MCP vari- contains status information for the block. Table 10-2
ables defines these EEPROM and variable addresses, 'mc1ud-
Colunm 6 Bridge current, VAR. 1092 ing the CLST block(s) to which each address applies.
(IBRIDGE), 5000 = l pu
Column 7 Firing angle, 0 = full advance, 16383 10-3.1.1. CLST1 (BASIC) BLOCK. CLST1 requires the
= 180-degree retard least amount of processor execution time. This list con-
Column 8 Cell pair select counter, range 250- sists of four 16-bit (two-byte) channels that are recorded
255 or 0-12 (1000 added if firing re- at the block's scheduled rate (deNned in the block
verse bridge, 10000 added if armature source list described in Chapter 4). Data is recorded
tiring is enabled) while the variable selected by pointer EE.5868
Column 9 Asynchronous current regulator Ering (CL@RUN) is high. Recording stops when the up*
data CL@RUN variable goes low.

Lines 1 - 21 Circular list data
Line 22 First seven columns: 00000 value = Data recording can also be toggled 011 and off by an *
frozen, valid data, 00001 or 65535 = (asterisk) command via the drive serial link.
not frozen, therefore invalid data. Last
column: address of the line corre- 10-3.1.2. CLST2 (INTERMEDIATE) BLOCK. In addition
sponding to when the trigger occurred to the functions in the CLST1 block, CLST2 includes
(if displayed in signed format, add the following features:
Data flow
65536 to obtain the trigger address)
oldest data = top line, newest data =
bottom line
. Selectable data recording rate
Post-trigger data capture delay

NOTE
• List overwrite lock
Typically at least four lines are displayed after
the trigger. . RUN command inverter
The data recording rate is selected using EE.5879

10-3. DCP CIRCULAR LIST BLOCKS (CL_RAT), as defined in Table 10-2. This enables the
user to collect data at a rate different from (slower than)
The DCP Diagnostic Circular List (CLST) blocs cap- the block execution rate. The data recording rate, en-
ture up to eight user-selected DCP variables, with each tered as milliseconds, is converted to an integer number
variable assigned to a channel. The total memory space of scheduled block executions. The actual collection
used by the circular list is 16 kB, the length of the list is rate is reported in the status line (header) when the cir-
determined by the number and size of the channels cular list is read.
10-2
The post-trigger data capture delay enables the circular LD Returns the status of the circular list when the
list to capture a number of samples, defined by EE.5880 list is collecting. When the list is stopped, this
(CL__DLY), after the CL@RUN variable goes low. This command dumps the contents of the circular
feature allows the user to sample data surrounding a list in ASCII form.
trigger event.
NOTE
The list overwrite lock prevents data surrounding a
trigger event from being overwritten by subsequent re- The LD command can be used with the ter-
starting of the block. When the variable selected by minal emulation mode capture or log func-
pointer EE.5878 (CL@LCK) goes high, the circtNar list tion to save the circular list contents to a tile.
is allowed to start and stop only once . The file can then be used for off-line analysis
of the data.
The logical sense of the CL@RUN command can be
inverted using EE.5881.0 (CL_.TPR). The first line of a data dump contains the fol-
lowing header information, based upon which
10-3.1.3. CLST3 (ADVANCED) BLOCK. In addition to circular list block (CLST1, CLST2, or CLST3)
the functions in the CLST1 and CLST2 blocks, CLST3 is enabled.
includes the following fear res:
For a CLST1 block, the first line of the data
Eight data collection channels (rather than four) dump contains the following information:
• Data averaging on channels 3 through 6 0 0 BIockRate 1 00000 OO000

00000 00000
• Collection of data in bytes (8 bits), words (16 bits),
or double words (32 bits) where BlockRate, the scheduled rate of the cir-
cular list block, is equal to 1 (720/sec), 2
The eight data collection channels are con.tigured using (360/sec), 4 (180/sec), or 8 (90/sec).
EE.5877 (CL_TYP). Channels l and 2 may collect data
as bytes, words, or double words; Channels 3 through 6 For a CLST2 or CLST3 block, the first line of
may collect data as bytes or words, and may be conlig- the data dump contains the following informa-
med to average data over their collection intervals, and tion:
Channels 7 and 8 collect data only as bytes.
StopDelay TimeRate BlockRate CoIlectRate
As in CLST2, the data recording rate is selected using StpReqTmO StpSamplTm2,1 ,0
EE.5879 (CL_RAT). When averaging is selected for a
channel, data samples are accumulated at the block exe- where:
cution rate. The samples are then averaged and stored
as a data point at the rate defined by CL_RAT . StopDelay is equal to EE.5880 (CL_DLY), the
number of data samples collected after the
stop request.
10-3.2. Circular List Display
TimeRate is equal [O EE.5869 (CL_RAT), the
The contents and/or status of the DCP Circular List can requested data collection rate in millisec-
onds.
be viewed using the ST2000 Toolkit (see GEH-5860) or
Drive Configurator, LynxOS Version (see GEH-6203) . BlockRate, the scheduled rate of the circular
Using the terminal emulation mode of the ST2000
Toolkit or Drive Configurator, enter any of the follow- list block, is equal to 1 (720/sec), 2
ing serial commands: (360/sec), 4 (180/sec), or 8 (90/sec).
L Returns the status of the circular list. CollectRate is the data collection frequency in
number of scans.
10-3
StpReqTmO is the stop request LAN time (least Bit# Source Bit# Source
O NOFAULT, 801 8 REFENAB, 81 5
significant word). 1 9
FATALFLT, 803 RUNNING, 81 1
(or TRIPFLT) 10 ZEROSPD, 812
StpSamplTm2,1,O is the stop sample full LAN 2 ORWINSPD, 832 11 UPTOSPD, 820
time using three words (48 bits), 3 RUNACT, 804 12 UPTOPOS, 821
4 JOGACT, 805 13 REG1 LIM, 895
5 MACLOSED, 810 14 CURLIM, 827
The second line of the data dump contains the 6 MPWRENAB, 882 15 CEMFLIM, 828
RUN pointer and all data pointers. 7 PRECOND, 813
LDn Returns the status of the circular list when the EE.647 (HISTP1) - The DCP variable selected using
list is collecting. When the list is Stopped, this Mis pointer, History Pointer #1.
command dumps at least one 11111 screen of the
circular list data in ASCII form. The display EE.648 (HISTP2) - The DCP variable selected using
begins with data point n, where n is a number this pointer, History Pointer #2.
of samples from Sample 0, the stop sample.
Negative values for n refer to samples taken If the history buffer is configured for two variables,
before the stop command, positive values refer only the HISTP1 and I-IISTP2 variables are included.
to samples taken after the stop command. For
n values that are too small, the data dump starts As selected using EE.615.5 (LCPJP1), the trigger to
with the oldest collected sample. For values lock the history buffer can be a LAN command, a trip
larger than 20, the data dump starts 20 samples fault, ardor the history lock bit. The history lock bit is
before the end of the list data. selected by pointer EE.649 (HISLOC).
The 'first line of the data dump contains the The delay time between frames is selected using bits 0
RUN pointer and all data pointers. through 6 of EE.646 (HISTD). The delay in 20 msec
intervals is given by the following fornnNa:
LR Resets the list to the beginning (clears the list).
This command also enables a locked list to be Delay (HISTD + 1) x 20 msec
II
restarted.
The minimum time delay between frames is 20 msec
(I-IISTD = 0), the maximum delay is 1280 msec, or
10-4. LCP HISTORY BUFFER 1.28 sec (HISTD = 63).
TI-IE LCP History Buffer is a circular list of periodi- NOTE

cally sampled variables that are stored in the DC2000
drive as frames. As selected using EE.615.7 (LCPJP1), Only bits 0 through 5 of EE.646 are used to
the history buffer may contain 51 frames of Eve vari- set the delay time. Bits outside of this range
ables, or 102 frames of two variables. are ignored.
If the history buffer is configured for Eve variables per Table 10-3 Lists and defines the EEPROM addresses that
frame, the variables are: control the operation of the LCP History Buffer .
VAR.S59 GCPCFB) - Current feedback to LCP, Unlike the MCP and DCP circular lists, the LCP His-
scaled and filtered. tory Buffer is intended to be accessed by an MM2000
via the drive's DLAN+ connection. The Drive History
VAR.103 (VFB) - Voltage feedback, a representation Monitor (DS207DI-IIS) monitors the drive's LCP His-
of the motor's applied voltage, as received from the tory Buffer and, when the buffer is locked (data collec-
MCP. . tion stopped), uploads the buffer contents to disk. The
tile containing the history data can be viewed using the
VAR.590 (RUP_OUTO) - Low word of Stams_S output Trending Display Console (TDC) typically implemented
bits RUP OUT (DPRL_STATUS_S_OUT). on the third virtual console of the MM2000. Refer to
RUP_OUTO contains the first 16 of 32 Status__S publications GEI-I-6212 and GEH-6213 for information
outputs from the DCP. The DCP source of each bit on the MM2000 Drive History Monitor and TDC.
is as follows:
10-4
DC2000 Digits] Adjustable Speed Drive GEH-6005
Table 70- 7. MCP Circular List Software Jumpers EE.6282 (MDGNJP/
I Bit Definition
EE.6282.0 Enable fast update rate for MCP circular list

The MCP diagnostic circular list is an 8 word wide by 128 deep history of selected motor control processor vari-
ables sampled surrounding a configurable trigger point such as a stop, trip, fault, or trigger from DCP. The list may
be viewed using the serial fink RAM dump command.
Examples*
"rn60000 Display most recent 22 lines in unsigned format
*m6oooo-- Display most recent 22 lines in +I- signed format
"m58288~60336-- Display all 128 lines in +/- signed format
The data in this display is interpreted as follows:

Oth column Address of this line
1st column EE.600, MDA1lN. selected MCP variable see list below)
2nd column EE.603, MDA2lN, selected MCP variable
3rd column EE.552, MPNTR1, selected MCP variable
4th column EE.553, MPNTR2, selected MCP variable
5th column Bridge current, +/-5000 = 1pu (IBRIDGE, VAR.1092)
6th column Firing angle, O=full advance, 16383 =18O degree retard
7th column Cell pair select counter, range 250-255 or O-12
1000 added if firing reverse bridge
10000 added if armature firing is enabled
8th column Asynchronous current regulator firing data
The last line in the example displays, at address 60336, contains special data. Columns 1-7 will be O if the list is
frozen, and 65535 or -1 if the list is active and hence the data not valid. Column 8 gives the address of the line
corresponding to when the trigger occurred (if displayed in signed format, add 65536 to get the trigger address).
Normally at least 4 lines are displayed after the trigger.
EE.6282, MDGNJP, contains jumpers to control operation of the circular list. Bit O controls the execution rate of
the circular list. Clear= = >once per firing; set= = >every 15 degrees. Bit 1 must be set to enable trigger/hold
from DCP via VAR.714 (MCLISTFR). Bit 2 is a manual trigger/hold. Bit 3 is a "hold next" trigger. Bits 4-6 config-
ure the MCP trigger source.
(See help memo for EE.6282.1 for details on these jumper bits.)
Addresses of MCP variables are:

10 RTCLK 154 lL1 32940 FLOPERR 49572 VARMFB
90 PLLXO 158 lL3 32942 FLOPOUT 49574 VBRGFB
92 TICSDDEG 260 MBBALANC 32954 IRDROP 49620 ACLINMAG
98 ALPHA 32818 SFB 32956 PLLERR 49644 IA FB
100 FIRETIME 32868 M _VAFlLT 32972 CTCFB 49646 IA2FB
112 lF_OFST 32870 M _IAFILT 49504 DROPIFB 49648 IF FB
120 lA_OFST 32884 LINEFREQ 49558 IARMFB 49650 lF2FB
138 ILOPOUT 32934 FIRCMD 49560 IBRIDGE
14-4 ILOPREF 32936 ILOPERR 49562 CEMF
WARNING--These M CP addresses are for debug use only, not for application level use. These addresses are sub-
ject to change in tuture revisions.
Note, during cell test. the circular list pointers are automatically overridden and cell test diagnostic information is
captured on the c ircular list. To capture cell test diagnostics regardless of whether the cell test passes or faults,
set the trigger source to be "MCP preconditioned." Circular list data during cell test is:
1st column Cell test state machine; 1-12 = short, 13-24 = open ckt test
2nd column CT current (VAR.1 O19)
3rd column Bridge current
4th column Bridge voltage
5th column Cell pair counter
6th column Fault code detected on first trial
7th column ILOPOUT
8th column During open ckt test, bit pattern of passed cells
Value Description
o ( O) Update circular list once per firing (~6O degrees)
1 ( 1) Update MCP circular list every 15 degrees
10-5
Table 10- 1. MCP Circular List Software Jumpers EE.6282 {/WDGNJP) - Continued
Bit Definition
I
EE.6282.1 Enable trigger/hold from DCP VAR.714, MCLISTFR

EE.6282, MDGNJP, contains jumpers to control operation of the MCP circular list.
Bit O controls the execution rate of the circular list. Normally left clear to capture data once per firing. Set to cap-
ture data every 15 degrees to diagnose asynchronous current regulator/firing circuit operation. This bit also con-
trols the update rate of VARs 290 and 291 .
Bit 1 must be set to enable trigger/hold from DCP via VAR.714, MCLISTFR. When set, if this VAR is true, the cir-
cular list will remain frozen. On the active edge of this VAR, if not already triggered, the list will trigger and fault
CIRCLATC will be annunciated briefly.
Bit 2 is a manual trigger/hold. If set, the circular list will trigger and remain frozen until the bit is cleared.
Bit 3 is a "hold next" trigger. If set, the next time the circular list is triggered, it will remain frozen until the bit is
cleared.
Bits 4-6 configure the MCP trigger source:

o Any fault (if EE_570_10=O); MCP precondition (if EE.570.10= 1 )
1 Any trip fault
2 MCP preconditioned
3 MCP armature firing disabled
4-7 Reserved
These sources are in addition to the DCP trigger source, if enabled.
See the help memo for EE.6282.0 for additional information.

Value Description
O ( O) Ignore DCP trigger source
1 ( 2) Enable trigger/hold from VAR.714
EE.6282.2 Manually trigger and hold MCP circular list
Value Description
o ( O) Enable automatic triggering of MCP circular list
1 (4) Manually trigger and hold MCP circular list
EE.6282.3 Permanently hold data from next circular list trigger
Value Desc!/brian
o ( O) Release circular list data on falling edge of trigger
1 ( 8) Lock circular list data on next trigger
EE.6282.4 MCP circular list trigger/hold event source
Value Descnbtion
o ( O) Trigger on any fault (unless EE.570.10 is set)
1 (16) Trigger on any trip fault
2 (32) Trigger when drive is stopped (MCP preconditioned)
3 (48) Trigger when MCP inhibits armature firing
10-6
Table 10-2. DCP Circular List Software Jumpers

I
Address Mnemonic Definition CLST Blocks

I
EE.5868 CL@RUN Circular List Run Command Pointer All

This EE contains the address of a Boolean which is the circular list run command.
When the run command is High, the block collects data. When it is Low, it stops
collecting data and the data may be read. The RUN Command input can be in-
verted via the use of the CL_JPR.O jumper (CLST2, CLST3 only).
The restarting of the circular list will cause it to continue collecting data. By the
nature of a circular list, data will eventually be overwritten leaving the last 16
Kbytes of collected data intact. If the Overwrite Lock lEE.5878) is ser, the block
will not be allowed to restart, thus preserving previously captured data (CLST2,
CLST3 only).
Additionally, if CL@RUN is ser to O, the keyboard character * (asterisk) will
toggle the starting and stopping of data collection. This status is shown as
an asterisk on the status line when toggled on (collect). The interpretation
of the * command does not depend on the state of CL_JPR.O jumper bit.
EE.5869 CL@CH1 Circular List Channel 1 Data Pointer All
EE.5873 CL@CH5 Circular List Channel 5 Data Pointer CLST3
EE.5877.0 CL_TYP Circular List Channel 1 Data Type CLST3

Value Description
O ( O) Channel Not Active
1 ( 1) Collect Byte
l
2 ( 2) Collect Word I
4 ( 4) Collect Double-Word
EE.5877.3 CL__TYP Circular List Channel 2 Data Type CLST3

Value Description
1 ( 8) Collect Byte
2 (16) Collect Word
4 (32) Collect Double-Word

Value Description
1 ( 64) Collect Byte
2 (128) Collect Word
3 (192) Collect Word and Average

Value Description
1 (256) Collect Byte
10-7
Table 70-2. DCP Circular List Software Jumpers - Continued
Address Mnemonic Definition CLST Blocks
EE.5877.10 CL_TYP Circular List C flannel 5 Data Type CLST3

Value Description
o ( O) Channel Not Active

Value Description

Value Description

Value Descrlbrion
EE.5878 CL@LCK Circular List Overwrite Lock Pointer CLST2,

This EE contains the address of a logical Boolean which acts as the Overwrite CLST3
Lock for the Circular List block. If the Overwrite Lock is set, the block will be al-
lowed to start once and stop once but will not be allowed to restart, thus preserv-
ing previously captured data (CLST2, CLST3 only). This feature is intended to
allow unsupervised collection of data surrounding a single event where there is the
.possibility of accidentally restarting the circular list and thus overwriting the col-
lected data.
EE.5879 CL_RAT Circular List Data Collection Rate CLST2.

Specifying the data collection rate allows for data collection at a rate different CLST3
from (slower than) the block execution rate. The actual collection rate may be
slightly faster than the rate specified by CL_RAT as the time is rounded to fit an
integer number of block executions. The actual collection rate is reported in the
circular list status when the circular list is read (dumped).
EE.5880 CL_DLY Circular List Capture Stop Delay CLST2,

CL_DLY contains an integer number of data points to be captured after the Circu- CLST3
lar List block loses its run enable. This allows the Circular List to capture data
surrounding an event rather than just up to an event. Note that for a value in
CL_DLY that is larger than the list length the delay will be limited to the length of
the list.
EE.5881.0 CL_JPR Circular List RUN command invert CLST2,

The RUN command input can be inverted via the use of the CL__JPR.O jumper CLST3
(CLST2, CLST3 only). Note that this jumper bit does not change the interpretation
of the Serial Link "*" command.
Value Description
O ( O) Do not invert logical sense of Circular List RUN Command
1 ( 1) Invert logical sense of Circular List RUN Command
VAR.1453 CL_STATE Circular List State All

CL_STATE contains information on the state of operation of the circular list. It may
be deciphered as follows:
O Waiting for run command (stopped)
2 Waiting for stop command (collecting)
4 Stop requested in Non-write scan (may occur when CL_RAT <> O)
e Exhausting Stop Delay
8 Circular List is Locked (no restart without reset)
10-8
Table 70-3. LCP History Buffer Software Jumpers
l Address Mnemonic Definition
EE.615.5 LCPJP1 History Circular List Trigger selection

These bits select the trigger to lock the History Circular List. Note that the History Buffer can be
locked by a LAN command, regardless of the LCPJP1 setting.
Value Description
o ( O) Trip fault or HISTORY_LOCK_BlT (HISLOC EE,649)
1 Caz) Only the HISTORY__LOCK_BlT (HISLOC EE.649)
2 (64) Any fault or HISTORY__LOCK_BIT (HIS LOc EE.649)
3 (96) Neither a fault or HlSTORY_LOCK_BlT (HISLOC EE.649)
EE.615.7 LCPJP1 Capture 2 or 5 variables per History Snapshot

Defines whether 2 or 5 variables are to be captured per History Snapshot. (A HARD RESFT is re-
quired after changing this parameter.)
Value Description
O ( O) 5 variables per snapshot
1 (128) 2 variables per snapshot
EE.622.8 FRZMSK History variable #1 (HISTORY1) - Freeze Mask is the mask used for selecting up to six freeze parame-
ters which will be sent on the LAN.
Value Description
o ( O) HISTORY VARIABLE #1 (HISTORY1 VAR.5 86) is not included
1 (256) Hl5T0RY VARIABLE #1 (HISTORY1 VAR.586) is included
EE.622.9 FRZMSK History variable #2 (HISTORYZ) - Freeze Mask is the mask used for selecting up to six freeze parame-
ters which will be sent on the LAN.
Value Description
o ( O) HISTORY VARIABLE #2 (HISTORY1 VAR.587) is not included
1 (512) HISTORY VARIABLE #2 (HISTORY1 VAR.587) is included
EE.646.0 HISTD History delay time between History snapshots

History delay time (HlSTD.O-.5) defines the delay time between History snapshots in 20 msec inter-
vals. The minimum delay time is 20 msec.
Example: If HlSTD.O-.5 = 1, then the delay time is 40 msec.
If HlSTD.0-.5 = 5, then the delay time is 120 msec.
The History buffer contains 51 frames of 5 variables or 102 frames of 2 variables. Inter frame time
is [20msec + (HISTD.O-.5 * 20msec)l. Frame O reports the drive time at lock, 5 or 2 variable
frames, the time delay between frames, and the DCP RAM locations pointed to by HISTP1 and
HISTP2.
If 5 variables per frame are selected, then the variables are
1) Current Feedback (LCPCFB VAR.559)
2) Voltage Feedback (VFB VAR.103)
3) Status_S OUT (STSSOUTO VAR.590)
4) @ HISTP1 (EE.647)
5) @ HlSTP2 (EE.648)
If 2 variables per frame are selected. then the variables are
1) @ HISTP1 (EE647)
2) @ HlSTP2 (EE648)
EE.647 HISTP1 History pointer #1 to DCP RAM

History pointer #1 selects the DCP variable to be loaded into HISTORY1 ¢VAR.586). The SLCC will
store HISTORY1 contents into the History buffer. HISTORY1 is updated every 2.7 msec.
EE.648 HISTP2 History pointer #2 to DCP RAM

History pointer #2 selects the DCP variable to be loaded into Hl$TORY2 (VAR.587). The SLCC will
store HISTORY2 contents into the History buffer. HISTORY2 is updated every 2.7 msec.
EE.649 HISLOC History lock pointer used for History lock bit
The history lock pointer determines which DCP Boolean variable (when set) will lock the history circu-
lar list (known as the History lock bit).
I
10-9
Notes:
10-10
DC2000 Digimax Aqiustable Speed Drive GEH-6005
CHAPTER 11
PARTS REPLACEMENT
11-1. INTRODUCTION
CAUTION
This chapter provides instructions for replacing printed
wiring boards and SCR modules in the DC2000 Digital
Adjustable Speed Drive . While power is applied to the drive, do not
remove or reinsert printed wiring boards or
GE carefully tests all equipment before shipping, and connections. This can damage the equip-
does not expect equipment to fail under normal condi- ment.
tions. Most components never require repair or re-
placement. To replace a board in the drive:
1. Ensure that power to the drive is off.

WARNING
2. Carefully disconnect all cables, as follows:
Disconnect all power supplies before per- For a ribbon cable, place one hand on each
forming any maintenance, adjustments, side of the cable connector that mates with the
servicing, parts replacements, or any other board connector. Gently pull the cable connec-
act requiring physical contact with electrical tor with both hands.
working components or wiring of this
equipment. For a cable with a pull tab, pull the tab.
Circuit breakers, if supplied as part of the For a screw terminal connector, loosen the
total system, may not disconnect all power to screw at the top of each terminal and gently
the equipment (see system elementary dia- pull each wire free.
grams). Whether the ac voltage is grounded
or not, high voltage to ground may be pres- 3. Carefully remove the board, as follows:
ent at many points.
Some boards are held in place by plastic snaps
(holders). Push these holders back to release
11-2. REPLACING BOARDS the board.
Some boards are mounted on standoffs with

CAUTION screws. Remove the screws to release the
board.
To prevent component damage caused by 4. On the replacement (new) board, set all jumpers,
static electricity, treat an boards with static pots, and switches in the exact position as those on
sensitive handling techniques. Use a the board being replaced.
grounding strap when changing boards.
Store boards in anti-static bags or boxes. To fine-tune pots, refer to Chapter 5. If a board
revision has added or eliminated a configurable
Printed wiring boards may contain static-sensitive com- component, or readjustment is needed, refer to the
ponents, which must be considered when handling and tables in Chapter 5, or the instructions provided
replacing a board. GE ships replacement boards in anti- with the replacement board
static bags or boxes. It is important that they be stored
and transported in these bags or boxes when not in-
stalled in the system.
11-1
NOTE 1. Lower the card carriers to expose the rear of the

unit, where the SCR modules are located.
Because of upgrades, boards of different re
vision levels may not contain identical hard- 2. Identify the defective SCR module and its location.
ware. However, GE Drive Systems ensures Refer to section 9-6 and the fault codes listed in
compatibility of replacement boards. Table 9-5 .
5. If the SDCC or SLCC card is replaced, onboard 3. Disconnect the wires from the defective SCR mod-
software from the old card must be transferred to ule. If needed, mark the wires so that they can be
the new (replacement) card. Refer to section connected correctly to the new module .
5-4.11.3 for the SDCC or section 5-4.15.2 for the
SLCC for instructions O11 transferring the onboard 4. Remove the bus bar, mounting screws, and SCR
software to the replacement card. module.
6. Install the new board, ensuring that all holders snap 5. Clean old lubricant and din from the mounting sur-
into position or that the board is mounted securely face.
on the standoffs.
6. Apply a thin film of VERSILUBE Plus lubricant to
7. Reconnect all cables, ensuring that they are prop- both contacting surfaces.
erly seated at both ends.
7. Install the new module, reconnecting the wires, bus
bars, and mounting screws. Tighten the screws to
11-3. REPLACING BRIDGE COMPONENTS the torque specifications listed in Table 11-1.
11-3.1. SCR Module Repair/Replacement - For mounting screws:

G, C, and CX Frame Drives
a. Tighten screws one as a time, progressing
The following procedure is used to replace an SCR counterclockwise on 4-screw mounting, until
module in a G, C, or CX frame drive . all screws are snug.
NOTE b. Tighten to required torque in opposite order,

progressing clockwise on 4-screw mounting,
In addition to standard repair tools, this pro- beginning with the last screw snugged.
cedure requires GL322 VERSlLUBE® Plus
lubricant (part no. 104X214AB059). 8. Remove all excess VERSILUBE Plus from edges of
SCR module.
Table 71- 1. SCR Module Mounting and Connecting Torque Requirements
Torque Requirements
Frame Size SCR Module Part Number Heatsink Bus Bar*
Mounting Screws Mounting Screws
G 104X125DC O56 28 in lb 25 in lb
C 104x125Dc O57 55 in lb 60 in lb
CX 104-X125DC 058, 059 55 in lb 60 in lb
* To avoid excess torque on connected modules, support the bus bar while tighten-
ing screws.
11-2
*.
11-3.2. SCR Module Repair/Replacement -

J, K. and M Frame Drives WARNING
NOTE
To prevent possible injury or damage to the
In addition to standard maintenance tools, SCR stack assembly to be removed, ensure
this procedure requires GL322 VERSILUBE that the red GLASTIC shelf is under the
Plus lubricant (part number 104X214AB059) stack assembly to be replaced, and that the
and #600 emery paper; bottom center bus is in the slot in the shelf.
The shelf should rest on the sheet metal sup-
.
11-3.2.1 REMOVING DEFECTIVE SCR. To remove the port for the NTB/3TB or STBA board and
defective SCR module: on the on the red GLASTIC angle on the
back panel of the drive core. A screw or bolt
1. Ensure that an power to the drive is disconnect- should be inserted through the hole in the
ed. shelf as described above to prevent the shelf
from sliding out when the stack assembly is
2. Remove the six 1/4-20 kepnuts to remove the removed.
Lexan" baffle located across the bottom of all three
stack assemblies. 5. Remove the Lexan baffle on the bottom and face of
the stack assembly.
3. Identify the defective SCR and its location. Refer to
.
section 9-6 and the fault codes listed in Table 9-5 6. Disconnect the brown control wires to the capaci-
tors at the bottom of the stack assembly.
NOTE
7. Ensure that the GLASTIC shelf is pushed all the
For J and K frame drives, the SHVI board way in. At the bottom of the stack assembly, re-
must be removed if the defective SCR is on move the three 1/2-inch kepnuts and carriage bolts
the phase 3 stack assembly. For M frame .
located on the center bus
drives, the SHVM board must be removed if
the defective SCR is on Me phase 2 stack as- 8. At the top of the stack assembly, remove the two
sembly. 1/2-inch kepnuts and carriage bolts on the bottom
of the fuses,
4. Place the red GLASTICQ shelf (part number
104X2301AB001) under the stack to be removed, 9. Remove the four 3/8-inch bolts to the red barrels
with the bottom center bus tab in the slot. Push the holding the stack assembly to thelcore back panel.
GLASTIC shelf in all the way (staying above the Then carefully slide the stack assembly out onto the
metal air deflectors and red GLASTIC angle on the GLASTIC shelf.
core back panel). Insert a screw or bolt through the
hole in the shelf. The screw should be located be-
hind the sheet metal support for the NTB/3TB or WARNING
STBA board, to prevent the shelf from sliding out
when the SCR stack assembly is removed.
The stack assembly weighs approximately
125 lb. Hands with care to prevent personal
injury or damage to the stack assembly.
11-3
10. Remove the stack assembly from the core drive and c. Lubricate the heatsink with GL322
place it on a clean work table for further disassem- VERSILUBE P1uS lubricant.
bly.
2. Clean and lubricate the new SCR as described for
11. To disassemble the section containing the defective the heatsink in step 1.
SCR, place the stack assembly on its side with the
clamp nuts up. 3. Replace the SCR cell, ensuring that its orientation
and polarity are correct (the same as the defective
12. Alternately loosen each clamp nut then remove SCR removed in section 11-3.2.1).
them and their washers. Place each nut and washer
on a clean surface in the same orientation and order 4. Place the heatsink onto the SCR clamp, ensuring
that they were removed. that the dowel pin is inserted into the hole of the
SCR. Be careful not to scratch or dent the SCR.
13. Remove the spring bar gauge and place it on the Rotate the SCR back and forth several times to en-
work table. sure proper seating. Plug the SCR terminal into the
terminal housing.
14. Remove the heatsink. Ensure that the SCR does
not stick to the heatsink. 5. Check the spring bar gauge and adjust to zero if
required. Place the spring bar gauge onto clamp.
15. After noting the polarity of the SCR terminal , dis- Tighten the clamp nuts Engel tight. Ensure that the
connect the terminal from the terminal housing and same number of threads is exposed on each stud.
remove the defective SCR. Using a torque wrench, tighten each nut to 20 in-lb.
11-3.2.2. INSTALLING NEW SCR. To install the RCW 6. Alternately tighten each nut 1/4 turn at a time until
SCR module: each nut has been tightened an additional 2 ams.
1. Prepare the heatsink as follows: 7. Replace the repaired stack assembly by following
the removal procedure in section 11-3.2.1 in re-
a. Clean the heatsink, removing all old verse order.
VERSILUBE Plus lubricant and foreign mat-
ter .
b. Dress the surface of the heatsink with #600 grit
emery paper, using random motions.
CAUTION
Be careful not to break through the plating

when dressing the heatsink with the emery
paper. A break in the plating may cause im-
proper conductivity.
11-4
DC2000 Digital Acliustable Speed Drive GEH-6005
CHAPTER 12
SPARE AND RENEWAL PARTS
12-1 . INTRODUCTION 12-4. PART NUMBER STRUCTURE
This chapter contains information needed when ordering A GE part number is structured so that different por-
spare and renewal (replacement) parts for the DC2000 tions of the number identify the type of equipment and
Digital Adjustable Speed Drive. This information con- location of manufacture. For ordering, a customer does
sists of a parts listing with the catalog (part) numbers. not need to understand this makeup - the equipment's
Both the part name and the complete part number nameplate provides the complete number. However,
must be included when ordering. since the information is used for some software appli-
.
cations, this section defines the part number structure
GE recommends that the customer keep a set of spare
parts on hand to minimize system downtime if repair is A part falls into one of four categories:
needed.
-
Order-specific assemblies major assemblies or items
that make up a specific drive, made up of common
12-2. CUSTOM RENEWAL PARTS LISTING assemblies
In addition to the parts list in this manual, GE provides -

Common assemblies subassemblies used in many GE
a separate Renewal Parts List with the drive's custom Drive Systems products, not just a particular drive
instructions or PC software. As indicated, this custom
list applies specifically to the equipment furnished O11 a -
Components individual pans that make up assemblies
customer's particular application at the time of ship-
ment. Printed wiring boards
If this Renewal Parts List is missing, contact the nearest These categories and the makeup of their part numbers
GE Sales Office or GE Sales Representative to obtain a are defined below.
copy. Include the drive model number, serial number,
and GE requisition number.
12-4.1. Order-specific Assembly Part Numbers
12-3. ORDERING RENEWAL PARTS Order-speciic assemblies make up the particular drive
provided. Other items obtained specidcally for the or-
Renewal parts should be ordered by contacting the der may use a similar part number structure .
nearest Sales Office or an authorized GE Sales Repre-
sentative. Include: For example, if 3VXYZ999CD001 is the part number
for an order-specific assembly:
• Drive model number, located on its nameplate
. Part name
3V = assembly provided by GE Drive Systems,
Salem, Virginia
Complete part number, located on its nameplate XYZ999 = original order identification number
Parts still under warranty may be obtained directly from CD = assembly type: CD for core drive, LU for
the factory (designated on the system elementary dia- lineup, CA for case, PN for panel
gram), as described in Appendix O.
001 = unit idemtificadon number
12-1
12-4.2. Common Assembly Part Numbers 12-4.4. Board Part Numbers
Common assemblies are subassemblies used as compo- A pr'mted wiring board is designated by an alphanu-
nents of order-speciic assemblies. Common assemblies meric part (catalog) number. The parts numbering
are not designed for a particular drive, but provide a series used for boards are described in Chapter 5 .
function used in other GE products .
NOTE
A common assembly part number consists of the num-
ber 36 followed by up to 14 alphanumeric characters . The factory may substitute later versions of
boards based on availability and design en-
For example, 36C774524AAG35 is the part number for hancements. However, GE Drive Systems
the DC2000 drive's IPL cable . ensures compatibility of replacement boards.
12-4.3. Component Part Numbers 12-5. DC2000 DIGITAL ADJUSTABLE SPEED

DRIVE PARTS LISTS
Components are the basic parts that make up assem-
blies. They represent the lowest discrete level of a sys- The tables included in this section list part numbers for
tem. Component part numbers consist of a combination the boards, subassemblies, and components used in
of alphanumeric characters that define the class and DC2000 C and CX frame (Table 12-1), G frame (Table
specific item. 12-2), I and K frame (Table 12-3), and M frame (Table
12-4) drives. For a listing of parts specific to a particu-
For example, if 104X109AD038 is the part number, lar drive, refer to the Renewal Parts List (described
then: above) provided with the equipment.
104X = component
109 = component type (fuse)
AD038 = item or rating (500 V, 3.2 A, FNQ)
12-2
Table 72- 7. DC2000 C and CX Frame Drive Parts List

I
Description Catalog (Part) Number of.

I
Bal un assembly, ARCNET, requires SLCCG 1 36B605594AEG01 1

Bal un assembly, DLAN, requires SLCCG2 36B605594AEG02
Basic Drive Terminal Board (STBA) DS2OOSTBAG1 A 1
Blower motor, for CX frames with 230/460 V ac input 104-X215BA O08 1

Blower motor, for CX frames with 575 V ac input 104X21 5BA O30
Cable, 10 A NRX field shunt to 2TB-1, -2 (CX frames) 336A3485AP G02 1
Cable, 10 A NRX field shunt wires (C frames) 336A3485AP G06 1
Cable, 11PL, SDCC to 1 1 PLX 336A3485AF GO1 1
Cable, 170 °C thermal switch to 2TB-1 1, -12 336A3485AA G02 1
Cable, 190 °C thermal switch to 2TB-3, -4 336A3485AA G01 1
Cable, 1 FPLX to FSAA (with DCFB) 336A3485AD G05 1

Cable, 1FPLX to FSAA (with SDCI) 336A3485AP G03
Cable, 1PL, SDCC to DCFB or SDCI 36C774524-AAG35 1
Cable, 24 A MFC to 2TB 336A3485AQ G03 1
Cable, 24A exciter FN, FP to 2TB~2, -1 (CX frames) 336A3485AN G01 1
Cable, 2PL, with SLCC 36B605787ACG01 t

Cable, 2PL, without SLCC 36B605787AAG01
Cable, 3PL, SDCC to SLCC 36C774524AAG36 1
Cable, 4-PL, DCFB or SDCI to NTB/3TB or STBA 36C774524AAG37 1
Cable, 5 pL, DCFB or SDC] to PCCA, PCN, or PCR 36C774524AAG38 1
Cable, 6PL, SDCC to NTB/3TB or STBA 36C774524AAG39 1
Cable, '/pL, SDCC to SPC 36C774524AAG51 1
Cable, 8PL, SDCC to NTB/3TB and LTB (with LTB board) 36C774524AAG200 1
Cable, SPL, SDCC to NTBl3TB or STBA (without LTB board) 36C774524AAG41
Cable, ac fuses to MA contactor (C frames) 36A358218BRG02 1
Cable, ac fuses to MA contactor (CX frames) 36B605619ACG01 3
Cable, ACFU K2, K3 to 2TB-5, -e 336A3485AM G02 1
Cable, ACFU to CPTFU1-1, CPTFU2-1 (top) 336A3485AB G04 1
Cable, ACFU to SCRs, for CX frames without an MA contactor (quantity 3 in 36B605619ADG01 3/6
non-regenerative drives, 6 in regenerative drives)
12-3
Table 72- 1. DC2000 C and CX Frame Drive Parts List - Continued
Description Catalog (Part) Number Qty.

I
Cable, ARCPL, with SLCCG1 and ARCNET 36B605796AAG01 1

Cable, ARCPL, with SLCCG2 and DLAN 36B605796AAG09
Cable, blower centrifugal switch to 2TB-17, -18 (CX frames) 336A3485AR G01 1
Cable, blower motor fuses to ACFU (CX frames) 36A358260CRG01 1
Cable, blower motor to blower motor fuses (CX frames) 36A358260CRG02 1
Cable, CPTFU3-2 to 2TB-14 (bottom) 336A3485AB G01 1
Cable, CPTX to CPTFU and 2TB-13 336A3485AC G01 1
Cable, de fuse/bus to P2 bus (CX frames) 36B605619ABG07 2
Cable, do PI jumper (CX frames) 36A358260CFG01 1
Cable, do P1A to SCR bus P1 (C frames) 36A3582t 8BEG04 1
Cable, do P2 jumper (CX frames) 36A358260CFG02 1
Cable, de P2 to SCR P2 bus, non-regenerative drives (C frames) 36A358218BEG05 1

Cable, do P2 to SCR P2 bus, regenerative drives (C frames) 36A358218BEG01
Cable, do shuntlbus to P1 bus (CX frames) 36B605619ABG06 2
Cable, DCFB 2FPL to 2FPLX 336A3485AD G02 1
Cable, DCFB IA2PL to 2TB-25, -26 336A3485AG G02 1
Cable, DCFB IF2PL to 2TB-29, -30 336A3485AJ G02 1
Cable, DCFB IFPL to 1 FPLX 336A3485AD G01 1
Cable, DCFB MACPL to 2TB-19, -20, -27, -28 336A3485AK G01 1
Cable, DCFB or SDCI IA1PL tO 2TB-15, -16 336A3485AG G01 1
Cable, DCFB or SDCI IF1PL tO 2TB-21, -22 336A3485AJ G01 1
Cable, DCFB to ACFU & PI, P2 buses 336A3485AH G01 1
Cable, DCFB VM1A, B to 2TB-9, -10 336A3485AE G01 1
Cable, drive shunt to 2TB-15, -16 336A3485AL G01 1
Cable, FAPL , 2 fans (CX frames) 36A358260CBG01 1
Cable, FAPL with snubber resistor (C frames) 36A358218CDG03 1
Cable, FAPL without snubber resistor (C frames) 36A358218CDG01 1
12-4
Table 72-1. DC2000 c and CX Frame Drive Parts List - Continued

I

I
Cable, field shunt to 2TB-21, -22 (CX frames with internal 10 A field exciter) 336A3485AO G01 1
Cable, FSAA SP, SN to 2TB-21, -22 (cx frames) 336A3485AO G02 1
Cable, FSAA to 2TB-5, -6 (CX frames) 336A3485AM G01 1
Cable, IOPL, SLCC to LTB 36C774524AAG43 1
Cable, left scrubbers, with PCCA 336A3485AT G01 1
Cable, left snubbers, with PCN or PCR 36A358160FFG02 1
Cable, MA contactor coil wires (C frames) 36A358160FYG02 1

Cable, MA contactor coil wires (CX frames) 36A358160FYG06
Cable, MA contactor to SCR, long, for CX frames (quantity 1 in non- 36B605619ACG06 1-3
regenerative drives with less than 3OO hp, 2 [doubled] in 300 hp non-
regenerative drives; 3 in regenerative drives)
Cable, MA contactor to SCR, non-regenerative drives (C frames) 36A358218BXG06 3
Cable, MA contactor to SCR, regenerative drives (C frames) 36A35821 8BXG04 3
Cable, MA contactor to SCR, regenerative drives (C frames) 36A35821 SBXGO5 3
Cable, MA contactor to SCR. short, for CX frames (quantity 2 in non- 36B605619ACG03 2-4
regenerative drives with less than 300 hp; 4 [doubled] in 300 hp non-
regenerative drives; 3 in regenerative drives)
Cable, MATB wires, with size 5 MA contactor (CX frames) 36A358260ECG03 1
Cable, MATB wires, with size 6 MA contactor (CX frames) 36A358260ECG02 1
Cable, MET1 to 1 1PLX-1 , -4 336A3485AS G01 1

Cable, MET2 to 1 1 PLX-2, -5 336A3485AS G02 1
Cable, MET3 to 1 1 pLx-3, -6 336A3485AS G03 1
Cable, MET4 to 1 1 pLx-8, -7 336A3485AS G04 1
Cable, NTB/STB to LTBIRTBA 115 v ac feed 36A3591 OOCYG14 1
Cable, OPTPL (RTBA jumper) 36A3591 OOCYG13 1
Cable, PI and P2 buses to 2TB-9, -10 336A3485AH G09 1
Cable, PCCA pi, P2 to 2TB-9, -10 336A3485AH G08 1
Cable, right snubbers, non-regenerative drives with PCCA 36A3581 GOFRGO8 1
Cable, right scrubbers, regenerative drives with PCCA 36A3581 GOFRGO7 1
Cable, right snubbers, regenerative drives with PCR board 36A358160FRG02 1
I
Cable, RPL, RTBA to LTB 36A3591 OOCRG01 1
Cable, SDCI Ac2, AC3 to 2TB-5, -6 336A3485AM G03 1
12-5

I

I
Cable, SDCI MACPL to 2TB-19, -20 336A3485AK G02 1
Cable, SDCI NPL and PPL to 1 FPLX 336A3485AP G05 1
Cable, SDCI vi, V2, and V3 to Fu1, FU2, and FU3 336A3485AH G07 1
Cable, SDCIG1 to 10 A NRX exciter 336A3485AP GO1 1
Cable, STBA CP1PL to 2TB-13 and -14 336A3485BB G01 1
Contactor, MA, size 4 104X105CB O13 1

Contactor, MA, size 5, 1 OO kVA/250 hp (CX frame) 104-X105CB O17
Contactor, MA, size 6,1 50 kVA/300 hp (CX frame) 104X105CB 016
Control power transformer (CPT) assembly, 4.6 A, 230/460 V ac 36B605573BEG01 1

Control power transformer (CPT) assembly, 4.6 A, 575 V ac 36B605573BEG02
Control power transformer (CPT) assembly, 3.04 A, 230/460 V ac 36B605573BFG01
Current transformer (CT) assembly, 2000:1, regenerative C frames 246B8237AD G01 1

Current transformer (CT) assembly, 5000:1 round, regenerative CX frames 246B8237AE G01
Do Power Supply and Instrumentation Board (S cl), w/ 10 NRX field exciter DS2OOSDCIG1A 1
Do Power Supply and Instrumentation Board (SDCI), w/o field exciter DS20OSDClG2A
Diode module, DM10, 10 A NRX field exciter 104»X125DC 065 1
Drive Control Card {SDCC) with firmware D521 5SDCCG1A 1

DS2t5SDCCG3A
Drive Terminal Board (NTB/3TB) 531 X305NTBA_GO 1
Fan, Muffin, rack cooling (quantity 1 for C frame, 2 for CX frame) 104X215CA O03 1/2
Fan, Tarzan®, SCR bridge (C frames) 104X215CA O04 1
Ferrite cores (quantity 3 in non-regenerative drives, 6 in regenerative drives) 151A7823P37 3/6
Field exciter, 24 A NRP with 1 A shunt DS202OFECNRP001A 1

Field exciter, 24 A NRP with 2 A shunt DS202OFECNRP002A
Field exciter, 24 A NRP with 5 A shunt DS2020FECNRPO05A
Field exciter, 24 A NRP with 1O A shunt DS202OFECNRP010A
Field exciter, 24 A NRP with 15 A shunt DS2020FECNRPOt 5A
Field exciter, 24 A NRP with 20 A shunt DS202OFECNRPO20A
Field exciter, 24 A NRP with 25 A shunt DS202OFECNRP025A
Field exciter, 24 A NRX with 1 A shunt DS202OFECNRXOO1A 1

Field exciter, 24 A NRX with 2 A shunt DS2020FECNRX002A
Field exciter, 24 A NRX with 5 A shunt DS2020FECNRX005A
Field exciter, 24 A NRX with 10 A shunt DS202OFECNRX01OA
Field exciter, 24 A NRX with 15 A shunt DS2020FECNRXO15A
Field exciter, 24 A NRX with 20 A shunt DS202OFECNRX02OA
Field exciter, 24 A NRX with 25 A shunt DS202OFECNRX025A
Fuse, 1.25 A, 600 v, dual~element time delay (BFU1 BFU3 for CX frames 218A4531P1 1 3
with 575 V ac, 50 Hz blower motor)
12-6
Table 12-1. DC2000 C and CX Frame Drive Parts List - Continued

I

I
Fuse, 1.8 A, 600 V, dual-element time delay, FRS-R (BFU1 - BFU3 for CX 218A4531P14 3
frames with 460 v, 50 Hz or 575 V ac, 60 Hz blower motor)
Fuse, 2.0 A, 600 v, dual-element time delay, FRS-R (BFU 1 BFU3 for CX 21 8A4531 P15 3
frames with 460 v, 60 Hz blower motor)
-
Fuse, 200 A, 700 V, semiconductor (FU1 FU3 for C frames with 575 V ac input, 323A2432P72 an
107 - 183 A output; FU4 for regenerative C frames with 460 V ac input, 128 -
175 A output)
Fuse, 3.0 A, 600 V, FNO-R, time delay (CPTFU 1, CPTFU2 for 3.04 A CPT, 460 V 104X109BE 020 2
ac input)
Fuse, 3.2 A, 600 V, dual-element time delay, FRS-R (BFU1 - BFU3 for CX frames 218A4531P19 3
with 230 v, 50 Hz blower motor)
Fuse. 3.2 A, 600 V, FNQ-R, time delay (CPTFU1, CPTFU2 for 4.6 A CPT, 575 V 104X109BE 021 2/1
ac input; CPTFU3 for 3.04 A CPT, all input voltages)
Fuse, 300 A, 500 v, semiconductor (FU1 - FU3 for C frames with 230 V ac input, 323A2432P53 3/4
-
108 - 260 A output or 460 V ac input, 128 260 A output; FU4 for regenerative
-
C frame drives with 230 V ac input, 108 260 A output)
Fuse, 4.0 A, 600 v, dual-element time delay, FRS-R (BFU1 BFU3 for CX frames 218A4531P21 3
with 230 V, 60 Hz blower motor)
Fuse, 4.0 A, 600 V, FNO-R, time delay (CPTFU 1 I CPTFU2 for 4.6 A CPT, 460 V 104X109BE 023 2
ac input)
-
Fuse, 400 A, 700 v, semiconductor (FU1 FU3 for C frames with 575 V ac input, 323A2432P74 3
184 - 217 A output and CX frames with 575 V ac input, 218 - 421 A output)
Fuse, 400 A, 700 v, semiconductor (FU4 for regenerative C frames with 460 V ac 323A2432P74 1
input, 176 - 260 A output and CX frames with 230 V ac input, 261. - 365 A out-
-
put or 460 V ac input, 261 345 A output)
Fuse, 5.0 A, 600 V, FNO-R, time delay (CPTFU3 for 4.6 A CPT, all input voltages) 104X109BE 024 1
-
Fuse, 500 A, 500 v, semiconductor (FU1 FU3 for CX frames with 230 V ac in- 323A2432P55 3
put, 261 - 525 A output or 460 V ac input, 261 - 505 A output)
Fuse, 550 A, 1300 V, semiconductor (FU4 for regenerative C frames with 575 V 323A2433P1 8 1
-
ac input, 107 217 A output)
Fuse, 6.0 A, 600 v, FNO-R, time delay (CPTFU1, CPTFU2 for 3.04 A CPT, 230 v 104-X1O9BE 026 2
ac input)
Fuse, 600 A, 700 v, semiconductor (FU4 for regenerative CX frames with 230 V 323A2432P76 1
-
ac input, 366 440 A output or 460 V ac input, 346 -
425 A output)
Fuse, 700 A, 1300 v, semiconductor (FU4 for regenerative C frames with 575 V 323A2433P20 1
-
ac input, 218 421 A output)
Fuse, 700 A, 700 V, semiconductor (FU4 for regenerative CX frames with 230 V 323A2432P77 1
ac input, 441 - 525 A output or 460 V ac input, 426 - 505 A output)
12-7

I
Description Catalog (Pan) Number Oty.

I
Fuse, 8.0 A, 600 v, FNO-R, time delay (CPTFU1, CPTFU2 for 4.6 A CPT, 104Xt09BE O29 2
230 V ac input)
Gate leads, left, non-regenerative drives 36A358218CEGO'! 1
Gate leads, left, regenerative drives 36A358218BCG01 1
Gate leads, right, non-regenerative drives 36A358218CEG02 1
Gate leads, right, regenerative drives 36A358218BCG02 1
Jumpers, auxiliary interlock (C frames) 36A358218ERG01 2
Jumpers, voltage select 36A358160XRG02 2
Keypad, with SLCC card 104X152AE 002 1
LAN Communications Card (SLCC) with firmware: G1 can be used with DS215SLCCG1A t
DLAN or ARCNET; G2 with DLAN only; and G3 with neither DLAN nor DS21 5SLCCG2A
ARCNET. os215sLccG4A
LAN I/O Terminal Board (LTB) 531 X307LTBA __G1 1
Maintenance kit 36A358941AAG02 1
MET1, O 125%, SMET, non-regenerative drives 68A7614-C22BUAAAB00 1

MET2, o 125%, IMET, non-regenerative drives 68A7514C22BUAAAB00 1
MET3, o 125%, VMET, non-regenerative drives 68A7614C22BUAAABOO 1
MET4, O 125%, FMET, non-regenerative drives 68A7614-C22BUAAAB00 1
MET1, 125 o 125%, SMET, regenerative drives 68A7614C22YTAAAB00 1

MET2, 125 O 125%, IMET, regenerative drives 68A7614C22YTAAAB00 1
MET3, 125 O 125%, VMET, regenerative drives 68A7614C22YTAAABOO 1
MET2, 0 150%, IMET, non-regenerative drives 68A7614-C22BCCCCB00 1

MET2, O 175%, IMET, non~reger1erative drives 68A7614C22CAEEEB00
MET2, o 200%, IMET, non-regenerative drives 68A761 4C22BDFFFB00
MET2, 0 250%, IMET, non-regenerative drives 68A7614C22BEAAAB00
MET2, O 275%, IMET, non-regenerative drives 68A7614C22CCBBBB00
MET2, 0 300%, IMET, non-regenerative drives 68A761 4C22BFCCCB00
MET2, 0 325%, IMET, non-regenerative drives 68A'7614C22CDDDDBOO
MET2, o 375%, IMET, non-regenerative drives 68A7614C22CFAAABOO
MET2, O 500%, IMET, non-regenerative drives 68A7614C22BHAAABOO
MET2, 1 50 0 150%. IMET, regenerative drives 68A7614C22YCCCCBOO 1

MET2, 175 O 175%, IMET, regenerative drives 68A7614C22SAEEEBOO
MET2, 200 0 200%, IMET, regenerative drives 68A7614C22YDFFFB00
MET2, 250 0 250%, IMET, regenerative drives 68A7614C22YEAAABOO
MET2, 275 o 275%, IMET, regenerative drives 68A7614C22$CBBBBOO
MET2, 300 O 300%, IMET, regenerative drives 68A7614C22YFCCCB00
MET2, 325 0 325%, IMET, regenerative drives 68A7614C22SDDDDB00
MET2, 375 O 375%, IMET, regenerative drives 68A7614C22SFAAAB00
MET2, 500 O 500%, IMET, regenerative drives 68A7614C22YHAAABOO
12-8
.¢._.*.-- __
Table 72-7. DC2000 C and CX Frame Drive Parts List - Continued

I
l
f Description Catalog (Part) Number of.

MET4, o - 140%, FMET 68A7614C22BVBBBBOO 1
MET4, 0 - 150%, FMET 68A7'614C22BCCCCB00 1
MET4, o - 175%, FMET 68A7614C22CAEEEBOO 1
Plug (1 1PLX), used with any meters 21 8A4609P1 1
Potted ferrite box 246B2333AA G02 1
Power Connect Board (PCN), non-regenerative drives with s 460 V ac input, 531X122PCNA G1 1
without DCFB, and without common isolation transformer
Power Connect Board (PCR), regenerative drives with 5 460 V ac input, 531X12tPCRA G1
Power Connect~Card (PCCA), regenerative drives with DCFB DS20OPCCAG 1 A 1

Power Connect Card (PCCA), non-regenerative drives with DCFB DS20OPCCAG2A
Power Connect Card (PCCA), regenerative drives with SDCI DS2OOPCCAG7A
Power Connect Card (PCCA), non-regenerative drives with SDCI DS2OOPCCAG8A
Power Supply Board (DCFB, drive will contain either a DCFB or an SDCI DSZOODCFBG1 B 1
board)
RC network (MA contactor) 36A358207AAG04 1
Relay Terminal Board (RTBA), 110 V do relay coils DS2OORTBAG1A 1

Relay Terminal Board (RTBA), 24 v do relay coils DS200RTBAG2A
Relay Terminal Board (RTBA), 115 V ac relay coils DS200RTBAG3A
RTBA board requires SLCCG1 or G2 card.
Resistor, ACS snubber, with PCCA 104X123DE 014 6
Resistor, DCS snubber, with PCCA 104X123DE O15 1
SCR module, 160 A, 1200 v, for C frames with 230 V ac input, 108 - 260 104X125DC O20 3/6
-
A output or 460 V ac input, 128 260 A output (quantity 3 in non-
regenerative drives, 6 in regenerative drives)
SCR module, 160 A, 1400 v, for C frames with common isolation trans- 104X125DC O44 3/6
former, 230 V ac input, 108 - 260 A output or 460 V ac input, 128 260 -
A output (quantity 3 in non-regenerative drives, 6 in regenerative drives)
SCR module, 160 A, 1600 v, for C frames with 600 V ac input, 107 217 - 104X125DC O57 3/6
SCR module, 250 A 'Special', 1200 v, for CX frames with 230 v ac input, 104X125DC O48 3/6
366 - 525 A output or 460 V ac input, 426 - 505 A output (quantity 3 in
non-regenerative drives, 6 in regenerative drives)
SCR module. 250 A 'Special', 1400 V, for CX frames with common isolation 104X125DC O53 3/6
-
transformer, 230 V ac input, 366 525 A output or 460 v ac input, 426 -
505 A output (quantity 3 in non-regenerative drives. 6 in regenerative drives)
SCR module, 250 A, 1200 v, for CX frames with 230 v ac input, 261 - 104-X125DC O21 3/6
-
365 A output or 460 V ac input, 261 425 A output (quantity 3 in non-
12-9

Description Catalog (Part) Number Qty .
SCR module, 250 A, 1400 V, for CX frames with common isolation trans- 104-X125DC O45 3/6
former, 230 V ac input, 261 -
365 A output or 460 V ac input, 261 - 425
SCR module, 250 A, 1600 v, for CX frames with 600 V ac input, 281 - 104X125DC O58 3/6
354 A output (quantity 3 in non-regenerative drives, 6 in regenerative drives)
SCR module, 90 A, 1600 v, TM10, 10 A NRX field exciter 104X125DC 056 1
SCR, 250 A 'Special', 1600 v, for CX frames with 600 V ac input, 355 an
104X125DC O59 3/6
421 A output (quantity 3 for non-regenerative drives, 6 for regenerative
drives)
Shunt, 1 A (field) 104X149CC 030 1

Shunt, 2 A (field) 104X149CC 031
Shurlt, 5 A (field) 104X149CC 032
Shunt, 10 A (field) 104x149CC O33
Shunt, 15 A (field) 104x149cc 056
Shunt, 50 A (drive) 50-140034NTAA 1

Shunt, 60 A (drive) 50-140034NWAA
Shunt, 80 A (drive) 104x149CA 006
Shunt, 100 A (drive) 50-140034PKAA
Shunt, 150 A (drive) 50-14-0034PZAA
Shunt, ZOO A (drive) 50-140034RLAA
Shunt, 250 A (drive) 50-140034RSAA
Shunt, 300 A (drive) 50-140034-RXAA
Shunt, 400 A (drive) 50-14-0034SCAA
Shunt, 500 A (drive) 50-140034SFAA
Signal Processor Card (SPC) 531 X309SPCA _G1 1
Splice, CPT primary, 460 V ac AMP#1-321 235-1 1
Terminal board, 32 point (2TB) 246B8210AB G32 1
Terminal board, 6 point, MATB (CX frames) 104X1 54AA O57 1
Thermal switch assembly with terminals, 170 °C 336A3390AF GO1 1
Thermal switch assembly with terminals, 190 °C 36A358106ARG01 1

J
12-10
DC2000 Digital Acliustable Speed Drive GEH-6005
Table 72-2. DC2000 G Frame Drive Parts List

I
Description Catalog (Part) Number

I
Oty .
Bal un assembly, ARCNET, requires SLCCG1 36B605594AEG01 1
Basic Drive Terminal Board (STBA) DS200STBAG 1 A 1
Cable, 1 15 V ac to 2 fans 36A358160REG05 1
Cable, 115 V ac to card fan 36A358160REG04 1
Cable, 11PL, SDCC to 11PLX 336A3485AF G01 1
Cable, 170 °C thermal switch to 2TB~1 1, -12 336A3390AD O01 1
Cable, 170 °C thermal Switch to 2TB-11 , -12 336A3485AA G02 1
Cable, 190 °C thermal switch to 2TB-3, -4 104-X152AC O80 1
Cable, 190 °C thermal switch to 2TB-3, -4 336A3485AA G01 1
Cable, 1PL, SDCC to DCFB or SDCI 36C774524AAG35 1
Cable, 2pL, with sLcc card 36B605787ACG01 1

Cable. 3PL, SDCC to SLCC 36C774524AAG36 1

{
Cable, 4PL, DCFB or SDC! to NTB/3TB or STBA 36C774524-AAG37 1
Cable, 5PL, SDCC to DCFB or SDCI 36C774524»AG38 1
Cable, 6PL, SDCC to NTB/3TB or STBA 36C774524-AAG39 1
Cable, 7 PL, SLCC to SPC 36C774524-AAG51 1
Cable, 8PL, SDCC to NTB/3TB and LTB (with LTB board) 36C774524AAG200 1
Cable, 8PL, SDCC to NTB/3TB or STBA (without LTB board) 36C774424.AG41
Cable, ACFU to CPTFU1~1, CPTFU2-1 (top) 336A3485AB G05 1
Cable, ACFU to MA contactor, #10 wire, with 40 A contactor s6Aa58166FDG03 3

Cable, ACFU to MA contactor, #8 wire, with > 40 A contactor 36A358160FDG04
Cable, ACFU to MA phase 2, regenerative drives with 250°1 CT 36A358160FDG03 1
Cable, ACFU to SCRs, non-regenerative drives without MA contactor 36A358160FDG06 1
Cable, ACFU to SCRs, regenerative drives without MA contactor 36A358160FDG05 1
Cable, ARCPL, with SLCCGt and ARCNET 36B605796AAG01 1

Cable, CPTFU3-2 to 2TB-14 (bottom) 336A3485AB G01 1
Cabie, CPTX to CPTFU and 2TB-13 336A3485AC G01 1
12-11
Table 72-2. DC2000 G Frame Drive Parts List - Continued

I
Cable, DB contactor coil wires 36A35821 8AEG07 1
Cable, DB contactor to DCFU 36A35821 8AFG04 1
Cable, DCFB 1 FPL to 1 FPLX 336A3485AD GO1 1
Cable, DCFB 2FPL to 2FPLX 336A3485AD G02 1
Cable, DCFB IA2PL to 2TB-25, -26 336A3485AG G02 1
Cable, DCFB IF2PL to 2TB-25, -26 336A3485AJ G02 1
Cable, DCFB MACPL to 2TB-19. -20, -27, -ze 336A3485AK G01 1
Cable, DCFB or SDCI IA PL to 2TB-1 5, -16 336A3485AG G01 1
Cable, DCFB or SDCI IF PL to 2TB-21 I -22 336A3485AJ GO1 1
Cable, DCFB to ACFU & P1 , P2 buses 336A3485AH G17 1
Cable, disconnect switch to ACFU 36A358218AYG03 3
Cable, drive shunt to 2TB-1 5, -16 336A3485AL G01 1
Cable, FU2, FU3 to 2TB-5, -6 336A3485AM G04 1
Cable, FU4-P2 to SCR bus P2, shunt P1A to SCR bus PI 36A358160FAG10 2
Cable, fuse to overload relay 36A358218ARG01 1
Cable, left snubbers, with PCCA 336A3485AT GO2 1
Cable, left scrubbers, with PCN or PCR board 36A358160FFG01 1
Cable, MA contactor coil wires 36A358160FYG04 1
Cable, MA contactor to SCR, #10 wire, norm-regenerative drives s 25 hp 36A358160FCG05 1
Cable, MA contactor to SCR, #10 wire, regenerative drives S 25 hp 36A358160FBG05 1
Cable, MA contactor to SCR, #8 wire, non-regenerative drives > 25 hp 36A3581 60FCG06 1
Cable, MA contactor to SCR, #8 wire, regenerative drives > 25 hp 36A358160FBG06 1
Cable, MET1 to 11pLx-1, -4 336A3485AS GO1 1

Cable, MET2 to 1 1PLX-2, -5 336A3485AS G02 1
Cable, MET3 to 1 1PLX-3, -6 336A3485AS G03 1
Cable, MET4 to 1 1 PLX-8, -7 336A3485AS GO4 1
12-12

I

I
Cable, NTB/3TB to LTB/RTBA 115 V ac feed 36A359100CYG14 1
Cable, OPTPL (RTBA jumper) 36A359100CYG13 1
Cable, overload relay to MA contactor, line side 36A358218AXG08 1
Cable, overload relay to MA contactor, load side 36A358218AXG07 1
Cable, PI and P2 buses to 2TB-9 and -10, with PCN or PCR 336A3485AH G16 1
Cable, PCCA pi, P2 to 2TB-9, -10 336A3485AH G08 1
Cable, right snubbers, non-regenerative drives with PCCA 36A358160FRG06 1
Cable, right snubbers, regenerative drives with PCCA 36A358160FRG05 1
Cable, right scrubbers, regenerative drives with PCR board 36A358160FRG01 1
Cable, RLC network wires 36A3591 1 1BRG01 1
Cable, RLC network wires, regenerative drives with special CT assembly 36A3591 1 1 BRGO2 1
Cable, RPL, RTBA to LTB 36A359100CRG01 'I
Cable, SDCI Acz and AC2. to 2TB-15, -16 336A3485AM G03 1
Cable, SDCI MACPL to 2TB-19, -20 336A3485AK G02 1
Cable. SDCI NPL and PPL to 1FPLX 336A3485AP G05 1
Cable, SDCI V1, V2, and V3 to FU1, FU2, and FU3 336A3485AH G15 1
Cable, SDCIG1 to 10 A NRX field exciter 336A3485AP G01 1
Cable, STBA CP1PL to 2TB-13 and -14 336A3485BB G01 1
Capacitor, 1.o oF, i 10%, 1500 v, RLC network 104x122AA 432 3
Contactor, MA, 40 A (10 kVA/25 hp) 104X105CD out 1

Contactor, MA, 55 A ( 1 5 kVA/30 hp) 104X105CD O02
Contactor, MA, 80 A (30 kVA/75 hp) 104X105CD OO6
Contactor, normally open, DB 104X105CA O64 1

Contactor, normally closed, DB t04X105CA O71 1
Auxiliary contacts, DB 104X105CA O25 1
Control power transformer (CPT) assembly, 4.6 A, 230/460 v ac 36B605573BEG01 1

Control power transformer (CPT) assembly, 4.6 A, 575 V ac 36B605573BEG02
Control power transformer (CPT) assembly, 0.6 A, 230/460 v ac 36B605573BRG01
Current transformer (CT) assembly, 4T/#14, 25011 , regenerative drives 246B8237AA G01 1
Current transformer (CT) assembly, 4T/#14, with RLC network 246B8237AB G01
Current transformer (CT) assembly, 1000:1, regenerative drives 246B8237AC G01
12-13
Table 72-2. DC2006 G Frame Drive Parts List -- Continued

Description Catalog (Part) Number oTy
Dc Power Supply and Instrumentation Board (SDCI), w/ 10 A NRX field exciter DS2OOSDClG1A 1
Do Power Supply and Instrumentation Board (SDCI), w/o field exciter DS2OOSDCIG2A
Diode module, DM1 O, 10 A NRX field exciter 104X125DC O65 1
Drive Control Card (SDCC) with firmware DS215SDCCGtA 1

DS21 5SDCCG3A
Drive Terminal Board (NTB/3TB) 531X305NTBA _G1 1
Fan, Muffin, rack cooling (all input voltages), heatsink (575 V ac input, 104X215CA O03 1 /2
2 100 A do output)
Ferrite cores (quantity 3 in non-regenerative drives, 6 in regenerative drives) 151A7823P37 3/6
Fuse, 0.75 A, BOO v, FNQ-R, time delay (CPTFU3 for 0.6 A CPT) 104X109BE O06 1
Fuse, 1.0 A, 600 V, FNO-R, time delay (CPTFU1 , CPTFU2 for 0.6 A CPT, 460 104X109BE O08 2
V ac input)
Fuse, 10 A, 600 v, KTK-R10, special cartridge, for motor blower motor protec- 104X109BC 020 3
tion option
-
Fuse, 1OO A, 500 v, semiconductor (FU1 FU3 for 230 v ac input, 56 - 74 A 323A2432P51 3/4
output or 460 V ac input, 54 - 69 A output, FU4 for regenerative drives with
230 v ac input, 56 - 74 A output)
-
Fuse, 100 A, 700 v, semiconductor (FU 1 FU3 for 575 V ac input, 59 106 - 323A2432P71 3/1
A output; FU4 for regenerative drives with 460 V ac input, 5 4 - 86 A output)
Fuse, 160 A, 1300 V, semiconductor (FU4 for regenerative drives with 575 V 323A2433P1 6 1
ac input, 1 - 106 A output)
-
Fuse, 175 A, 500 v, semiconductor (FU1 FU3 for 230 V ac input, 75 - 107 323A2432P52 3/4
A output or 460 V ac input, 70 - 127 A output; FU4 for regenerative drives
with 230 V ac input, 75 - 107 A output)
Fuse, 2.0 A, 600 v, FNO-R, time .

delay (CPTFU1 CPTFU2 for 0.6 A CPT, 230 104X109BE 016 2
V ac input)
Fuse, 2OO A, 700 v, semiconductor (FU4 for regenerative drives with 460 V ac 323A2432P72 1
input, 87 -
127 A output)
Fuse, 3 A, 600 v, KTK-R3, special cartridge, for motor blower motor protection 104X109BC 018 3
option
Fuse, 3.2 A, 600 v, FNO-R, time delay (CPTFU1, CPTFU2 for 4.6 A CPT, 575 104x109BE 021 2
V ac input)
Fuse, 4.0 A, 600 v, FNO-R, time .

delay (CPTFU1 CPTFU2 for 4.6 A CPT, 460 104X109BE O23 2
V ac input)
Fuse, 5 A, 600 V, KTK-R5, special cartridge, for motor blower motor protection 104X109BC O19 3
option
12-14

I

I
Fuse, 5.0 A, 600 v, FNO-R, time delay (CPTFU3 for 4.6 A CPT, all input 104X109BE O24 1
voltages)
Fuse, 60 A, 500 v, semiconductor (FU1 - FU3 for 230 V ac input, 1 55 A- 323A2432P50 3/4
-
output or 460 V ac input, 1 53 A output; FU4 for regenerative drives with
-
230 V ac input, 1 55 A output)
Fuse, 60 A, 700 v, semiconductor (FU1 - FU3 for 575 V ac input, 1 58 A- 323A2432P70 3/1
output, FU4 for regenerative drives with 460 V ac input, 1 - 53 A output)
Fuse, 8.0 A, 600 v, FNQ-R, time delay (CPTFU1, CPTFU2 for 4.6 A CPT, 104X109BE O29 2
230 V ac input)
Gate leads, left, non-regenerative drives 36A358218CEG01 1
Gate leads, left, regenerative drives 36A358218BCG01 1
Gate leads. right, non-regenerative drives 36A358218CEG02 1
Gate leads, right, regenerative drives 36A358218BCG02 1
Heater, for motor blower motor protection option:

1/12 hp @ 40 °C, 460 V ac CR123C036A 3
1/12 hp @ 40 °C, 230 V ac CR123C071A
1/3 hp @ 40 °C, 575 V ac CR123C097A
1/2 hp @ 40 °C, 575 V ac CR123C109A
113 hp @ 40 °c, 460 v ac CR123C1 18A
1i2 hp @ 40 °c, 460 v ac CR123C148A
3/4 hp @ 40 °C, 460 v ac CR123C184A
1 hp @ 40 °C, 460 V ac CR123C196A
1i3 hp @ 40 °c, 230 v ac CR123C239A
1i2 hp @ 40 °c, 230 v ac CR1 23C326A
3/4 hp @ 40 °c, 230 v ac CR123C356A
1 hp @ 40 °C, 230 . V ac CR123C379A
Interlock, auxiliary, 2 NO & NC 104X105CD 011 1
Jumpers, auxiliary interlock 36A358218ERG01 2
Jumpers, voltage select 36A358160XRG02 2
Keypad, with SLCC card 104X152AE 002 1
LAN Communications Card (SLCC) with firmware: G1 can be used with DS215SLCCG1A 1
DLAN or ARCNET; G2 with DLAN only; and G4 with neither DLAN nor DS21 5SLCCG2A
ARCNET. DS215SLCCG4A
LAN IIO Terminal Board (LTB) 531 X307LTBA_G1 1
Maintenance kit 36A358941AAG02 1
MET1, O 125%, SMET, non-regenerative drives 68A7614~C22BUAAAB00 1

MET3, o 125%, VMET, non-regenerative drives 68A7614C22BUAAAB00 1
MET4, O 125%, FMET 68A7614C22BUAAAB00 1
12-15

I

MET1, 125 O 125%, SMET, regenerative drives 68A7614C22YTAAABOO
MET2, 125 0 125%, IMET, regenerative drives 68A7614C22YTAAABOO
MET3, 125 0 125%, VMET, regenerative drives 68A7614C22YTAAAB00
-
ME'T2, O 150%, IMET, non-regenerative drives 68A7614C22BCCCCB00 1
-
MET2, O 175%, IMET, non-regenerative drives 68A7614C22CAEEEBOO
MET2, o - 200%, IMET, non-regenerative drives 68A7614C22BDFFFBOO
MET2, O - 250%, IMET, non-regenerative drives 68A7614C22BEAAABOO
MET2, 0 - 275%, IMET, non-regenerative drives 68A7614C22CCBBBBOO
MET2, O - 300%, IMET, non-regenerative drives 68A7614C22BFCCCBOO
MET2, O - 325%, IMET, non-regenerative drives 68A7614C22CDDDDBOO
MET2, O - 375%, IMET, non-regenerative drives 68A7614C22CFAAAB00
MET2, O - 500%, IMET, non-regenerative drives 68A7614C22BHAAAB00
MET2, 150 O 150%, IMET, regenerative drives 68A7614C22YCCCCBOO 1

MET2, 175 o 175%, IMET, regenerative drives 68A7614C22SAEEEBOO
MET2, 200 O 200%, IMET, regenerative drives 68A7614C22YDFFFBOO
MET2, 250 o 250%, IMET, regenerative drives 68A7614C22YEAAABOO
MET2, 275 o 275%, IMET, regenerative drives 68A76t4C22SCBBBBOO
MET2, 300 o 300%, IMET, regenerative drives 68A7614C22YFCCCBOO
MET2, 325 o 325%, IMET, regenerative drives 68A7614C22SDDDDBOO
MET2, 375 o 375%, IMET, regenerative drives 68A7614C22SFAAAB00
MET2, 500 O 500%, IMET, regenerative drives 68A7614C22YHAAABOO
MET4, O .. 1-40%, FMET 68A7614C22BVBBBBOO 1
MET4, O - 150%, FMET 68A7614C22BCCCCB00 1
MET4, O - 175%, FMET 68A7614C22CAEEEBOO 1
Overload relay, for motor blower motor protection option CR324C310A 1
potted ferrite box 246B2333AA G02 1
Power Connect Board (PCN), non-regenerative drives with S 460 V ac input, 531X122PCNA G1 1
Power Connect Board (PCR), regenerative drives with s 460 V ac input, 531X121PCRA G1
Power Connect Card (PCCA), regenerative drive with DCFB DS2OOPCCAG1A 1

Power Connect Card (PCCA), non-regenerative drive with DCFB DS20OPCCAG2A
Power Connect Card (PCCA), regenerative drive with SDCI DS20OPCCAG7A
Power Connect Card (PCCA), non-regenerative drive with SDC! DS2OOPCCAG8A
Power Supply Board (DCFB, drive will contain either a DCFB or an SDC! DS2OODCFBG1 B 1
board)
RC network (MA contactor) 36A358207AAG03 1
RC network (non-regenerative drives with DB contactor) 36A358207AAG01 1
Reactor, RLC network 104X220FB O25 1
12-16
DC2000 Diguax Adjustable Speed Drive GEH-6005

6 Description Catalog (Part) Number Qty.
Relay Terminal Board (RTBA), 110 V de relay coils DS2OORTBAG1A 1

Relay Terminal Board (RTBA), 24 v do relay coils DS2OORTBAG2A
Relay Terminal Board (RTBA), 115 V ac relay coils DS200RTBAG3A
Resistor, 50 Q, 40 W, RLC network 104X123DE O16 12
Resistor, ACS snubber, for 575 V ac input with PCCA 104X123DE 014 6
Resistor, DCS snubber, for 575 V ac input with PCCA 104X123DE 015 1
-
SCR module, 40 A, 1200 V for drives with 230 V ac input, 1 74 A output 104X125DC O60 3/6
or 460 V ac input, 1 - 69 A output (quantity 3 in non-regenerative drives,
6 in regenerative drives)
SCR module, 40 A, 1400 v, for drives with common isolation transformer, 104X123DC O55 3/6
230 V ac input, 1 - 13 A output or 460 V ac input, 1 - 14 A output
(quantity 3 in non-regenerative drives, 6 in regenerative drives)
SCR module, 90 A, 1200 V for drives with 230 V ac input, 75 - 107 A out- 104X125DC O61 3/6
put or 460 V ac input, 70 - 127 A output (quantity 3 in non-regenerative
drives, 6 in regenerative drives)
SCR module, 90 A, 1400 V, for drives with common isolation transformer, 104X123DC 054 3/6
- -
230 V ac input, 14 107 A output or 460 V ac input, 15 127 A output
(quantity 3 in non-regenerative drives, 6 in regenerative drives)
SCR module, 90 A, 1600 v, TM10, 10 A NRX field exciter 104X125DC O56 1
SCR, 90 A, 1600 V for drives with 600 V ac input (quantity 3 in non- 104X125DC O56 3/6
1
Shunt, 1 A (field) 104X149CC O30 1
Shunt, 2 A (field) 104X149CC O31
Shunt, 2 A (drive) 104X149CC O31 1
Shunt, 5 A (drive) 104X149CC O32
Shunt, 10 A (drive) 104X149CC 033
Shunt, 150 A (drive) 104x149cc 040
Signal Processor Card (SPC) 531 X309SPCA;G1 1
Splice, CPT primary, 460 V ac AMP#1-321235-1 1
Switch, disconnect (100 A) 104X203DB O03 1
Switch, disconnect (150 A) TEC36150 1
Terminal board, 32 point (2TB) 246B8210AB G32 1
Thermal switch assembly with terminals, 170 °C 336A3390AF G01 1
Thermal switch assembly with terminals, 190 °C 36A358106ARG01 1
J
12-17
Table 12-3. DC2000 J and K Frame Drive Parts List

I
Description Catalog (Part) Number Frame Qty.

Size
I
Bal un assembly, ARCNET, requires SLCCG1 36B605594-AEG01 J, K 1

Basic Drive Terminal Board (STBA) DS2OOSTBAG1 A J, K 1
Blower motor, 230/460 V ac input 104-X21 5BA O08 J, K 3

Blower motor, 575 V ac input 104-X215BA O30
Cable, 11PL, SDCC to 11PLX 336A3485AF GO2 1
Cable, 190 °C thermal switch to 2TB 336A3438AE G1 9 1

Cable, 170 °C thermal switch to 2TB 336A3483AE G20 1
Cable, 1CPL, DCFB or SDCI to SHVM 336A3438AJ G05 J, K 1
Cable, 1PL, SDCC to DCFB or SDCI 36C774524AAG62 J, K 1

Cable, 2pL, with SLCC 36B605787ACG06 J, K 1
Cable, 2pL, without SLCC 36B605787AAG05
Cable, 2TB-13, -14 to CDBA or CPCA 1TB-11, -12 (1 10 V ac) 336A3485AH G12 J 1
for MDA
Cable, 2TB-st, -32 to CDBA or CPCA 1TB-1 1, -12 (1 10 v ac) 336A3485AH G14 1
for MDB
Cable, 2TB-19, -20 to CDBA or CPCA MACPL (24 V) for MDA 336A3438AH GO 1 J 1
Cable, 2TB-27, -28 to CDBA or CPCA MACPL (24 V) for MDB 336A3438AH G1 3 1
Cable, 3PL, SDCC to SLCC 36CI774524AAG36 J, K 1
Cable, 4PL, DCFB or SDCI to NTB/STB or STBA 36C774524-AAG61 J, K 1

Cable, 5PL, DCFB or SDCI to PCCA 36C774524AAG38 J, K 1
Cable, 6PL, SDCC to NTB/3TB or STBA 36C774524AAG46 J, K 1

Cable, 6TB-23, -24 to 6TB-61, -62 336A3438AQ GO3 J 1
Cable, 7PL, SDCC to SPC or SPCB 36c774524AAG51 J, K 1
Cable, 8PL, SDCC to NTB/3TB and LTB (with LTB board) 36C774524AAG201 J, K 1
Cable, SPL, SDCC to NTB/3TB or STBA (without LTB board) 36C774524AAG44
Cable, ac line filter wires 336A3438AB G1 7 K 1
Cable, ARCPL, with SLCCG1 and ARCNET 36B605796AAG02 J, K 1
Cable, blower fuse to CPTB-1, -2, -3 336A3483AT G13 K 1
Cable, blower motor centrifugal switch to 2TB-17, -18 336A3438AA G12 J 1
Cable, blower motor fuses to 2TB 336A3438AA GO8 J, K 1
Cable, blower motor power, 2TB to line 336A3438AA G09 J t

Cable, blower motor to STB 336A3438AA G03 J 1
12-18
Table 72-3. DC2000 J and K Frame Drive Parts List - Continued

I
Frame
Size
Q w
I
Cable. blower motor to BTB 336A3438AA G11 J 1

Cable, blower motor to fuse wires 336A3438AA GO1 J, K 3
Cable, blower wires, blower power = line voltage, s 600 V ac 336A3438AC G03 J 1
Cable, board enclosure door ground strap 36A358218EcG01 J, K 2
Cable, CNPL, DRPL 336A3438AH G09 J 1
Cable, CP1PL, STBA to 2TB (with STBA) 336A3485BB G11 J 1
Cable, CPT to CPTB 336A3483AT G14 K 1

Cable, CPT, CPTA wires, control power = line voltage 336A3438AC G20 J 1
Cable, CPTA wires 336A3438AC G01 J 1
Cable, CPTA wires 336A3438AC G21 J, K 1
Cable, CPTA wires, 230 V ac 336A3438AC G04 J 1
Cable, CPTA wires, 460 V ac 336A3438AC G05
Cable, CPTA wires, 575 V ac 336A3438AC G06
Cable, CPTAFU3 to 2TB 336A3485AB G03 J, K 1
Cable, CPTAX to CPTAFU 336A3485AC G03 J, K 1
Cable, CPTFU wires, control power = line voltage, S 600 V ac 336A3438AC GO2 J 1
Cable, CPTFU wires, control power == line voltage 336A3438AC G07
Cable, CPTFU3 to 2TB 336A3485AB G02 J, K 1
Cable, CPTX to CPTFU and CPTPL 336A3485AC G02 J, K 1
Cable, do snubber fuse wires, > 600 v ac 336A3438AF G05 J 1
Cable, DC1PL, DC2PL, SHVlG1B to 2TBH 336A3438AG G12 J, K 1
Cable, DCFB 1FPL to 1FPLX (with DCFB) 336A3485AD G03 J, K 1
Cable, DCFB 2FPL to 2FPLX (with DCFB) 336A3485AD G04 J, K 1
Cable, DCFB IA1 PL to SHVI 336A3483AH G21 J, K 1
Cable, DCFB lA2PL to SHVI 336A3483AH G22 J, K 1
Cable, DCFB v i , v2, vs, p1A, P2A to sHvl 336A3438AR G11 J, K 1
Cable, DCFB VM1A, VM1 B tO SHVI 336A3438AR G12 J, K 1
Cable, DCFB VM2A, VM2B to SHVI 336A3438AR G13 J, K 1
Cable, FAPL, DCFB or SDCI to board enclosure fans (with 2 fans) 336A3438AK G01 J 1
Cable, FAPL, DCFB to board enclosure fans (with 3 fans) 336A3438AK G02
Cable, FS, FCPL to 6TB 336A3438AN G01 J 1
12-19

I
Description Catalog (Part) Number Frame Qt y

Size
J
Cable, IF1PL, DCFB or SDCI to 2TB-21, -22 336A3485AJ G03 J, K 1

Cable, lF2PL, DCFB to 2TB-29, -30 (with DCFB) 336A3485AJ G04 J, K 1
Cable, IOPL, SLCC to LTB 36C774524AAG47 J, K 1
Cable, M1 B, P2 buses to 2TBH 336A3438AR G18 J 1
Cable, MACPL, DCFB to 2 TB-19, -20, -27, -28 (with DCFB) 336A3485AH G02 J, K 1
Cable, MET1 to 11PLX-1, -4 336A3438AL G17 J, K 1

Cable, MET2 to 1 1PLX-2, -5 336A3438AL G18 1
Cable, MET3 to 11PLX-3, -6 336A3438AL G19 1
Cable, MET4 to 1 1PLX-8, -7 336A3438AL G20 1
Cable, motor A FMFI' to 6TB 336A3438AL G02 J 1
Cable, motor A IMET to 6TB 336A3438AL G01 1
Cable, motor A SMET to 6TB 336A3438AL G04 1
Cable, motor A VMET to STB, > 460 V ac 336A3438AL G03 1
Cable, motor A VMET to GTB, s 460 V ac 336A3438AL G08
Cable, motor B FMET to STB 336A3438AL G06 1
Cable, motor B IMET to 6TB 336A3438AL G05 1
Cable, motor B SMET to 6TB 336A3438AL G10 1
Cable, motor B VMET to GTB, > 460 V ac 336A3438AL G07 1
Cable, motor B VMET to 6TB, s 460 V ac 336A3438AL G09
Cable, motor A shunt to 6TB, S 600 V ac 336A3438AG Got J 1
Cable, motor A voltage P1, P2, s 600 V ac 336A3438AD G01 J 1
Cable, motor B shunt to STB, s 600 V ac 336A34-38AG G02 J 1

Cable, MPL, CDBA or CPCA to MDA 336A3438AH G03 J 1
Cable, MPL, CDBA or CPCA to MDB 336A3438AH GO4 1
Cable, OPTPL [RTBA jumper) 36A3591OOCYG13 J, K 1
Cable, OPTPL, LTB to RTBA, 1 15 V ac feed 36A359100CYG15 J, K 1
Cable, P1, P2 buses to 2TBH-9, -10 (with SDCI) 336A3438AR GO9 J 1

Cable, P1, P2 buses to SHVI 336A3438AD GO7 J, K 1
Cable, P1A, P2 buses to 2TBH 336A3438AR G16 J 1
Cable, PI A, P2A buses to 2TBH 336A3438AR G15 J 1
Cable, PCCA p A , P2A to SHVI p A , P2A (with SDCI) 336A3438AR G17 J 1
Cable, RBL resistor wires, < 700 V ac 336A3438AM G01 J 1

Cable, RBL resistor wires, > 700 V ac 336A3438AM G02
Cable, RPL, LTB to RTBA 36A359100CRG02 J, K 1
Cable, SDCI IA1PL to 2TBH-15, -16 (with soci) 336A3438AH G40 J 1
Cable, SDCI MACPL to 2TB-19, -20 (with SDCI) 336A3485AH G10 J 1

Table 12-3. DC2OOO J and K Frame Drive Parts List - Continued

I

Size
I
Cable, socl PPL, NPL to 1 FPLX (with sDc11, nix field supply 336A3438AN G06 J 1
Cable, SDCI to SHVI, voltage feedback (with SDCI) 336A3438AR G10 J 1
Cable, shunt A to 2TBH-15, -16 336A3438AG G10 J 1
Cable, shunt A to 2TBH-15, -16 and shunt B to 2TBH-26, -25 336A3438AG GO7 K 1
Cable, shunt B to 2TBH-25, -26 336A3438AG G11 J 1
Cable, SHVI attenuation jumpers, < 700 V ac 336A3438AJ G03 J 7
Cable, SHVI L1, L2, L3 336A3438AB G01 J, K 1
Cable, SHVI L1, L2, L3 to 2TB 336A3438AB G15 J 1
Cable, SHVI M1, B1 to 6TB (MDA coil) 336A3438AH G08 J 1
Cable, SHVI M1A, M1B, M2A, M2B to 2TBH-9. -10, -23, -24 336A3438AR G14 J, K 1
Cable, SHVI M2, B2 to STB (MDB coil) 336A3438AH GO7 J 1
Cable, SHVI MPL to RMPL 336A3438AJ G01 J 1
Cable, SHVI pi, P2 to 2TBH-9, -10 (with SDCI} 336A3438AR G08 J 1
Cable, SHVI PI I P2 to 6TB, S 600 V ac 336A3438AD G02 J 1
Cable, SHVIG1A CPL, regenerative drives 336A3438AJ G02 J 1
Cable, SHVIG1A VPL wires 336A3438AD GO3 J 1
Cable, SQPL, DCFB to sHvl (with DCFB) 336A3483AH G15 J, K t
Cable, Tarzan fans to 2TB 336A3438AA G10 J, K 1
Cable, Tarzan fans to 6TB 336A3438AA G05 J 1
Cable, thermal switch to 6TB 336A3438AE G01 J 1
Capacitor, 0.25 oF, 1000 V, SCR snubber (C1 C6) 104X1 22AA 450 J, K 6
for 0.7 < kVA s 1
Contactor Driver Board (CDBA) DS2OOCDBAG1B J, K 1
Contactor Pilot Card (CPCA} DS20OCPCAG1A J 1
Control power transformer (CPT) assembly, 4.6 A, 230/460 V ac 36B605573BEG01 J K 1

Control power transformer (CPT) assembly, 4.6 A, 575 V ac 36B605573BEG02 J K
Control power transformer (CPT) assembly, 450 VA, 230/460 V ac 336A3401AC G01 J
Control power transformer (CPT) assembly, 450 VA, 575 V ac 336A3401AC G02 J
Control power transformer (CPTA) assembly, 500 VA 9T58B70 J
12-21

I

Size
I
Current transformer (CT) assembly, CT1 and CT3, 5000:1, 246B2304AA GO1 J 1
regenerative drives with SHVIG1A
Current transformer (CT) assembly, CT1 , 500021 , 24-6B2304AA G02 J, K 1
regenerative drives with SHVIG1 B
Current transformer (CT) assembly, CT3, 5000:1, 246B2304AA G03 J, K 1
regenerative drives with SHVIG1B
Dc Power Supply and Instrumentation Board (SDCI), < 600 v ac DSZOOSDCIGZA J, K 1

input
Drive Control Card (SDCC) with firmware DS215SDCCG1 A J, K 1

l
DS21 5SDCCG3A
Drive Terminal Board (NTB/3TB) 531 X305NTBA _G1 J, K 1
Fan, Tarzan 104X21 5CA O04 J, K 3
Fan, tubeaxial, 115 V ac, board enclosure 323A2375P1 J 2/3
Fiber-optic cable, bridge #2 to bridge #1 336A3473AL 170 K 1
Fiber-optic cable, MBHA to SPCB 336A3473AL 1 10 K 1
Fuse, 1.25 A, 600 V, dual-element time delay (B#FU1 B#FU3 for 218A4531 PI 1 J, K 6
575 V ac, 50 Hz blower motors)
Fuse, 1.8 A, 600 v, dual-element time delay, FRS-R (B#FU1 - 218A4531 P14 J, K 6
B#FU3 for 460 V ac, 50 Hz or 575 V ac, 60 Hz blower motors)
Fuse, 900 A, 1650 v, semiconductor, do leg lines for 1300 V ac 323A2433P21 J, K 12

input, 1871 A maximum output 12 fuses per leg)
Fuse, 2.0 A, 600 V, dual-element time delay, FRS-R (B#FU1 218A4531P15 J, K 6

B#FU3 for 460 V ac, 60 Hz blower motors)
Fuse, 1000 A, 14OO V, semiconductor, do leg lines for 1000 V ac 323A2434P1 J, K 12

input, 2078 A maximum output (2 fuses per leg)
Fuse, 2500 A, 1000 V, semiconductor, do leg lines for 700 V ac 323A2433P23 J, K 12

input, 2511 A maximum output (2 fuses per leg)
Fuse. 3.2 A, 600 V, dual-element time delay, FRS-R (B#FU1 d -

218A4531P19 J, K 6
Fuse, 3.2 A, 600 v, FNO-R, time delay (CPTFU1, CPTFU2, 104X109BE O21 J, K 4-
CPTAFU1, CPTAFU2 for 575 V ac input)
Fuse, 4.0 A, 600 V, dual-element time delay, FRS-R (B#FU1 218A4531P21 J, K 6

12-22

I
( Description Catalog (Part) Number Frame Qty.

Size
I
Fuse. 4.0 A, 600 v, FNO-R, time delay (CPTFU1, CPTFU2, 104X109BE 023 J, K 4
CPTAFU1, CPTAFU2 for 460 v ac input)
Fuse, 5.0 A, 600 v, FNO.-R, time delay (CPTFU3, CPTAFU3 for all 104X109BE O24 J, K 2
input voltages)
Fuse. 8.0 A, 600 V, FNO-R, time delay (CPTFU1, CPTFU2, 104x109BE O29 J, K 4
CPTAFU1 , CPTAFU2 for 230 v ac input)
Fuse, ac line filter PDFP1O01 A25v15P J, K 3
Fuse, do snubber, > 600 V ac PDFP1OOOASV1GDC J 2
Gate leads, non-regenerative drives, all voltages 336A3401AB G03 J, K 1
Gate leads, regenerative drives, all voltages 336A3401AB G04
Jumper, metal, 6TB, CPT, 230 V ac 104x154AA 110 J 2
Jumper, metal, 6TB, MDA/MDB 7
Jumpers, 6TB MB CNPL voltage 336A3438AH G03 J 1
Jumpers, 6TB MDA auxiliary voltage 336A3438AH G10 J 1
Jumpers, 6TB MDB auxiliary voltage 336A3438AH G02 J 1
Jumpers, PCCA voltage select 36A358160XRG02 J, K 2
Keypad, with SLCC card 104X152AE O02 J, K 1
LAN Communications Card (SLCC) with firmware: G1 can be used DS215SLCCG1A J, K 1
with DLAN or ARCNET; G2 with DLAN only; and G3 with neither DS215SLCCG2A
DLAN nor ARCNET_ DS215SLCCG4A
LAN I/O Terminal Board (LTB) 531 X307LTBA _G1 J, K 1
Maintenance kit 36A358941AAG02 J, K 1
MET1, O 125%, SMET, non-regenerative drives 68A7614C22BUAAABOO J, K 1
MET3, O 125%, VMET, non-regenerative drives 68A7614C22BUAAABOO 1
MET4, o 125%, FMET, non-regenerative drives 68A7614C22BUAAABOO 1
MET1 , 125 0 125%, SMET, regenerative drives 68A7614.22YTAAAB00 J, K 1

MET2, 125 0 125%, IMET, regenerative drives 68A7614C22YTAAABOO 1
MET3, 125 O 125%, VMET, regenerative drives 68A7614C22YTAAAB00 1
-
MET1, SMET, o 100%, non-regenerative drives 104X1 17CC 012 J 1
-
MET1, SMET, 100 - 0 100%, regenerative drives 104X1 17CC 013
MET2, o - 150%, IMET, non-regenerative drives 68A7614C22BCCCCBOO J, K 1
MET2, o - 175%, MET, non-regenerative drives 68A7614C22CAEEEB00
MET2, O - 200%, IMET, non-regenerative drives 68A7614C22BDFFFB00
MET2, O - 250%, IMET, non-regenerative drives 68A7614C22BEAAABOO
MET2, O - 2`75%, IMET, non-regenerative drives 68A7614C22CCBBBB00
MET2, o - 300%, IMET, non-regenerative drives 68A7614C22BFCCCB00
MET2, O - 325%, IMET, non-regenerative drives 68A7614C22CDDDDBOO
MET2, O - 375%, IMET, non-regenerative drives 68A7614C22CFAAABOO
MET2, O - 500%, IMET, non-regenerative drives 68A7614C22BHAAABOO
12-23

I
Description Catalog (Part} Number Frame Qty.

She
MET2, 150 - O 150%, IMET, regenerative drives 68A7614C22YCCCCBOO J, K 1
MET2, 175 - o 175%, IMET, regenerative drives 68A7614C22SAEEEBOO
MET2, -
200 o 200%, IMET, regenerative drives 68A7614C22YDFFFB00
MET2, 250 - 0 250%, IMET, regenerative drives 68A7614C22YEAAAB00
MET2, 275 - 0 275%, IMET, regenerative drives 68A7614C22SCBBBBOO
MET2, 300 - o 300%, IMET, regenerative drives 68A7614C22YFCCCB00
MET2, 325 - o 325%, IMET, regenerative drives 68A7614c22sD00DB00
375 - 0 375%, IMET, regenerative drives
J
MET2, 68A7614C22SFAAAB00
MET2, 500 - O 500%, IMET, regenerative drives 68A7614C22YHAAAB00
MET2, IMET, O - 1200 A, 200 mV, non-regenerative drives 104X1 15A0 O50 J 1
MET2, IMEI', O - 1600 A, 200 my, non-regenerative drives 104X1 15AD O51
MET2, IMET, O - 2000 A, 2OO mV, non-regenerative drives 104x115Ao O52
MET2, IMET, 0 - 2400 A, 200 mV, non-regenerative drives 104X1 15A0 053
MFT2, IMET, O - 3000 A, 200 mV, non-regenerative drives 104X1 15AD O54
-
MET2, IMET, 0 4000 A, 200 my, non-regenerative drives 104X1 15AD 055
MET2, IMET, O - 5000 A, 200 my, non-regenerative drives 104X1 15AD 056
MET2, IMEI', O - 6000 A, 200 my, non-regenerative drives 104X1 15AD 091
-
MET2, IMET, O 10000 A, 200 mV, non-regenerative drives 104X1 15AD 093
MET2, IMET, 1200 - O - 1200 A, 200 mV, regenerative drives 104X1 15AD O74
- -
MET2, IMET, 1600 0 1600 A, ZOO my, regenerative drives 104X1 15AD 075
-
MET2, IMET, 2000 - 0 2000 A, 200 mV, regenerative drives 104X1 15AD 076
MET2, IMET, 2400 - 0 - 2400 A, 200 mV, regenerative drives 104X1 15AD O77
-
MET2, IMET, 3000 0 3000 A, 200 my, regenerative drives 104x1 15AD 078
-
MET2, IMET, 4000 0 4000 A, 200 mV, regenerative drives 104X115AD O79
-
MET2, IMET, 5000 0 5000 A, 2OO mV, regenerative drives
-_ 104X1 15AD 080
MET2, IMET, 6000 - 0 - 6000 A, 200 mV, regenerative drives 104X1 15AD O92
-
MET2, IMET, 10000 0 10000 A, 200 mV, regenerative drives 104X1 15AD O94
MET2, IMET, O - 150%, non-regenerative drives 104x1 17CC O23 J 1

MET2, IMET, O - 200%, non-regenerative drives 104X1 t7CC O41
MET2, IMET, 150 - O - 150%, regenerative drives 104X1 t7CC O24
MET2, IMET, 200 - O - 200%, regenerative drives 104X117CC O40
MET3, VMET, O - 300 V, non-regenerative drives 104X1 17AA 011 J 1

-
MET3, VMET, 300 0 - 300 V, regenerative drives 104X1 17AA 013
MET3, VMET, 0 - 120%, non-regenerative drives 104X1 17CC O16
MET3, VMET, 120 - 0 - 120%, regenerative drives 104X1 17CC 017
MET3, VMET, O - 300 v, non-regenerative drives 36A362717DB001 J 1

MET3, -
VMET, O 600 V, non-regenerative drives 296C868DY G01
MET3, VMET, 0 - 6OO V, non-regenerative drives 36A362717DB003
MET3, VMET, 0 - 750 v, non-regenerative drives 296C868DY G03
MET3, VMET, 300 - 0 - 300 V, regenerative drives 36A362717DB002
MET3, -
VMET, 600 O - 600 v, regenerative drives 296C868DY G02
MET3, VMET, 600 - 0 - 600 V, regenerative drives 36A362717DB004
MET3, VMET, 750 - 0 - 750 V, regenerative drives 296C868DY G04
MET4, o
140%, FMET 68A7614C22BVBBBBOO J, K 1
MET4, o
150%, FMET 68A7614C22BCCCCB00
MET4, O 175%, FMET 68A7614C22CAEEEB00
12-24

I

Size
I
MET4, FMET, O - 5 A, internal shunt 104X1 15AD O29 J 1

MET4, FMET, o - 10 A, internal shunt 104X1 15AD O30
MET4, FMET, o - 20 A, internal shunt 104X1 15AD O31
MET4, FMET, O - 30 A, internal shunt 104x115AD O32
MET4, FMET, o 30 A, external shunt, 200 my 104X115AD O36
MET4, FMET, 0 - 50 A, external shunt, 200 mV 104X115AD O38
MET4, FMET, 0 - 100 A, external shunt, 200 mV 104X115AD O39
MET4, FMET, 0 - 150 A, external shunt, 200 mV 104X115AD 041
Multi-bridge Hub Communications Board (MBHA) DS2OOMBHAG1A K 1
Multi-bridge Signal Processing Card (SPCB) DS2OOSPCBG1A J, K 1
Plug ( 1 1 PLX), used with any meters 218A4609P1 J, K 1
Power Connect Card (PCCA), regenerative drives with DCFB DS200PCCAG5A J, K 1
Power Connect Card (PCCA}, non~regenerative drives with DCFB DS200PCCAG6A
Power Connect Card (PCCA), non-regenerative drives with SDCI DS2OOPCCAG1OA
Power Supply Board (DCFB), 2 600 V ac input DSZOODCFBG1B J, K 1
Reactor (L12 - L1 6) 206B2603G1 J, K 6
Relay Terminal Board (RTBA), 110 V do relay coils DS2OORTBAG1A J, K 1
Relay Terminal Board (RTBA), 24 V do relay coils DS2OORTBAG2A
Relay Terminal Board lRTBA), 115 v ac relay coils DS200RTBAG3A
Resistor, bleeder (quantity 2 for < 700 V ac, quantity 3 A200J2500EA-TH J 213
for 2 700 V ac)
SCR High Voltage Interface Board (SHVI). s 600 v ac input DS2OOSHVlG1A J 1

DS2OOSHVIG1B J, K
SCR module, 77 mm, 2100 v, for 700 V ac input, 2511 A maxi- 323A3371 J, K 6/12
mum output with 2 fuses per leg (quantity 6 for non-regenerative
drives, 1 2 for regenerative drives)
SCR module, 77 mm, 3000 v, for 1000 V ac input, 2078 A 323A3772 J, K 6/12
maximum output with 2 buses per leg (quantity 6 for non-
regenerative drives, 12 for regenerative drives)
SCR module, 77 mm, 4400 v, for 1300 V ac input, 1871 A 323A3375 J, K 6/12
maximum output with 2 fuses per leg (quantity 6 for non-
regenerative drives, 12 for regenerative drives)
Signal Processor Card (SPC) 531 X309SPCA _G1 J 1
Splice, CPT primary, 460 or 575 v ac AMP#1 -321235-1 J, K 1
Terminal board, 22 point, 30 A, 600 V 104X154AA O29 J 4
Terminal board, 36 point (2TB) 246B8210AB G36 J, K 1
Terminal board, 4 point with cover, (2TBH) 246B2398AC G02 J, K 2
12-25
Table 12-3. DC2000 J~and K Frame Drive Parts List - Continued
Description Catalog (Part) Number Frame Qty .

Size
Terminal board, 4 point, 30 A, 600 V (BTB) 104X154AA O05 J 1
Thermal switch assembly, 190 °C, non-regenerative drives, 336A3390BD G01 J, K 1

1500 V ac
Thermal switch assembly, 190 °C, regenerative drives, 336A3390BD G03
1500 V ac
Thermal switch assembly, 190/170 °C, non-regenerative drives, 336A3390BD G02
1500 V ac
Thermal switch assembly, 190/1 70 °C, regenerative drives, 336A3390BD GO4
1500 V ac
12-26
Table 72-4. DC2000 M Frame Drive Parts List

I
4 Description Catalog (Part) Number Qty.

I
Bal un assembly, ARCNET, requires SLCCG1 36B605594»AEG01 1

Bal un assembly, DLAN, requires SLCCG2 36B605594-AEG02
Basic Drive Terminal Board (STBA} DS20OSTBAG1 A 1
Blower motor, 230/460 V ac input 104X215BA 008 2

Blower motor, 230/460 V ac input CEMT 104X215BA 019
Blower motor, 575 V ac input 104x215BA O30
Cable, 11pL, SDCC to 'l 1PLX 336A3499AK G01 1
Cable, 170 °C thermal switch to 2TB, optional 336A3499AC G06 1
Cable, 190 °C thermal switch to 2TB 336A3499AC G05 1
Cable, 1 CPL, DCFB or SDCI to SHVM 336A3438AJ G05 1
Cable, 1FPL, DCFB to 1 FPLX (with DCFB) 336A34»99AF G02 1

Cable, 1FPL, SDCI to 1FPLX (with SDCI) 336A3499AF G04
Cable, 1FPLX to MFCA (with SDCI and field supply) 336A3499BC G03 1
Cable, 1 PL, SDCC to DCFB or SDCI 36C774524-AAG62 1
Cable, 2FPL, DCFB to 2FPLX (with DCFB) 336A3499AF G03 1
Cable, 2PL, with SLCC 36B605787ACG06 1

Cable, 2TB to MFCA FP, FN, and AC IN (with DCFB or SDCI and field supply) 336A3499BC G02 1
Cable, 2TB to MFCA SP and SN (with DCFB or SDCI and field supply) 336A3499BD G01 1
Cable, 3PL, SDCC to SLCC 35C774524AAG36 1
Cable, 4PL, DCFB or SDCI to .NTB/3TB or STBA 36C774524AAG61 1
Cable, 5 PL, DCFB or SDCI to PCCA 36C774524AAG38 1
Cable, 6PL, SDCC to NTB/3TB or STBA 36C774-524AAG46 1
Cable, 7PL, SDCC to SPC or SPCB 36C774524-AAG51 1
Cable, 8PL, SDCC to NTB/3TB and LTB (with LTB board) 36C774-524AAG201 1
Cable, 8PL, SDCC tO NTB/3T8 or STBA (without LTB board) 36C774524AAG44
Cable, ARCPL, with SLCCG1 and ARCNET 36B605796AAG02 1

Cable, blower centrifugal switch to 2TB 336A3499AA G03 1
Cable, blower motor to fuse wires 336A3438AA G01 2
Cable, blower motor-fuse jumper 336A3499AA G01 1
Cable, board enclosure door ground strap 36A358218ECG01 1
12-27
DC2000 Digital Adiustable Speed Drive
Table 12-4. DC2000 M Frame Drive Pans List - Continued

I

I
Cable, CDBA or CPCA to 2TB (MDA), 1 10 V 336A3499AQ GO2 1

Cable, CDBA or CPCA to 2TB (MDA), 24 V 336A3499AO G01
Cable, CPI PL, STBA to 2TB (with STBA) 336A3485BB G01 1
Cable, CPTAFU and 2TB to CPTAX 336A3499AE GO2 1
Cable, CPTAFU to CPTAX, 575 V ac 336A3499AE G04 1
Cable, CPTAFU3 to 2TB-32 336A3499AD G03 1
Cable, CPTFU to CPTX, 575 V ac 336A3499AE G03 1
Cable, CPTFU, CPTPL to CPTX, 230/460 v ac 336A3499AE G01 1
Cable, CPTFU1, CPTFU2 to CPTAFU1. CPTAFU2 336A3499AP G02 1
Cable, CPTFU3 to 2TB-14 336A3499AD G02 1
Cable, do bus PI, P2 to SHVM P1, P2 336A3499AF G01 1
Cable, do snubber wires, 600 V ac 336A3499AB G02 1
Cable, DCFB VI, V2, V3 tO SHVM (with DCFB) 336A3499AH G01 1

Cable, DCFB VM1A, VM1B to SHVM (with DCFB) 336A3499AH GO2 1
Cable, DCFB VM2A, VM2B to SHVM (with DCFB) 336A3499AH G03 1
Cable, FPL, 1FPLX to MFCA (with DCFB and field supply) 336A3499BC G01 1
Cable, IA PL, DCFB to SHVM (with DCFB) 336A3499AG GO2 1

Cable, lAtPL, SDCI to 2TB (with SDCI) 336A3499AVV G01
Cable, lA2PL, DCFB to SHVM (with DCFB) 336A3499AG G03 1
Cable, IF1PL, DCFB or SDCI to 2TB-21, -22 336A3499AL G01 1
Cable, lF2PL, DCFB to 2TB-29, -30 (with DCFB) 336A3499AL G02 1
Cable, K1, K2 buses to CPTFU1, CPTFU2 336A3499AP G03 1
Cable, K2, K3 buses to 2TB-5, -6 336A3499AP G01 1
Cable, MACPL, DCFB to 2TB-19, -20, -27, -28 (with DCFB) 336A3499AM G01 1
Cable, MACPL, SDCI tO 2TB-19, -20 (with SDCI) 336A3499AM G02
Cable, MDA feedback bus to 2TBH (with DCFB if internal contactor and with 336A3499AV GO2 1
SDCI if internal contactor and remote voltage feedback)
Cable, MDA feedback bus to 2TBH (with SDCI if no remote voltage feedback, 336A3499AV G03
with or without internal contactor)
Cable, MET1 to 11PLX-1, -4 336A3499BB G01 1

Cable, MET2 to 1'\PLX-2, -5 336A3499BB G02 1
Cable, MET3 to 11PLX~3, -6 336A3499BB G03 1
Cable, MET4 to 11PLX-8, -7 336A3499BB G04 1
Table 12-4. DC2000 M Frame Drive Parts List - Continued

I

I
Cable, MPL, CDBA or CPCA to MDA contactor (with CDBA or CPCA) 336A3499BA G01 1
Cable, OPTPL (RTBA jumper) 36A359100CYG13 1
Cable, OPTPL, LTB to NTB/3TB 36A359100CYG15 1

Cable, OPTPL, NTB/3TB to RTBA (without LTB) 336A3499BE G01
Cable, RPL, LTB to RTBA 336A3499AY G01 1
Cable, SCR firing, non-regenerative, all input voltages 336A3499AZ G03 1
Cable, SCR firing, regenerative, all input voltages 336A3499AZ G04
Cable. SCR snubber wires, 1000 V (used with 1000 v if required) 336A3499BF G01 1
Cable. SDCI VI, V2, V3 to SHVM (with SDCI) 336A3499AH G04 1

Cable, shunt (motor A) to 2TBH-15, -16 336A3499AR G01 1
Cable, SHVM DC1PL, DC2PL to 2TBH-15, -16, -25, -26 336A3499AS G01 1
Cable, SHVM L1, L2, L3 to KG, K2, K3 buses 336A3499AD G01 1
Cable, SHVM M1A, M1B to 2TBH-9, -10 (with DCFBl 336A3499AV G01 1
Cable, SHVM M2A, M2B to 2TBH-23, -24 (with DCFB) 336A3499AU G01 1
Cable, SHVM pi, P2 to 2TBH-9, -10 (with SDCI) 336A3499AF G05 1
Cable, sHvm pi A, P2A to PCCA pi, P2 (with soon) 336A3499AH G05 t
Cable, sopL, DCFB to SHVM (with DCFB) 336A3499AG G01 1
Cable, Tarzan fans to 2TB 336A3499AN G01 1
-
Capacitor, 0.25 oF, 1000 V, SCR snubber (C1 C6) for > 600 V ac 104x122AA 450 6
-
Capacitor, 0.25 oF, 600 v, SCR snubber (C1 C6) for s 600 V ac 104x122AA 429
Capacitor, 0.5 oF, 2000 v, do snubber (C30) for s 600 v ac 104X1 22AA 431 1
Contactor Driver Board (CDBA) DS20OCDBAG1B 1
Contactor Pilot Card (CPCA) DS200CPCAG1 A 1
Contactor, 1300 A, low speed (MDA), available for class G only 104X106MA G01 1
Contactor, 2500 A, high speed (MDA) 246B2323AA G01
Contactor, 2500 A, low speed (MDA), available for class G only 246B2323AA G02
Contactor, 900 A, low speed (MDA), available for class G only DS303A7A01 LXAOO3XT
Control power transformer (CPT, CPTA) assembly, 4.6 A, 230/460 V ac 36B605573BEG01 2
Control power transformer (CPT, CPTA) assembly, 4.6 A, 575 V ac 36B605573BEG02
Current transformer (CT) assembly, CT1, 500011, regenerative drives 24-6B2304AA G04 1
Current transformer (CT) assembly, CT3, 5000°1, regenerative drives 246B2304AA G05 1
Do Power Supply and Instrumentation Board (SDCI), w/o field exciter DS20OSDCIG2A 1
Drive Control Card (SDCC) with firmware DS21 SSDCCG1 A 1

DS215SDCCG3A
12-29

I

I
Drive Terminal Board (NTB/3TB) 531X305NTBA _G1 1
Fan, Tarzan 104X21 5CA O04 2

Field exciter, 24 A NRP with 1 A shunt DS202OFECNRPO01 A 1
Field exciter, 24 A NRP with 2 A shunt DS2020FECNRPOO2A
Field exciter, 24 A NRP with 5 A shunt DS2020FECNRP005A
Field exciter, 24 A NRP with 10 A shunt DSZOZOFECNRPO1OA
Field exciter, 24 A NRP with 15 A shunt DS2020FECNRPO1 5A
Field exciter, 24 A NRX with 1 A shunt DS202OFECNRXOO1A 1

Field exciter, 24 A NRX with 2 A shunt DS202OFECNRXOO2A
Field exciter, 24 A NRX with 5 A shunt DS2020FECNRXOO5A
Field exciter, 24 A NRX with 10 A shunt DS202OFECNRXO1 OA
Field exciter, 24 A NRX with 20 A shunt DS2020FECNRXO2OA
Fuse, 1.25 A, 600 v, dual-element time delay (B#FU1 B#FU3 for 575 V 218A4531P1 1 6
ac, 50 Hz blower motors)
Fuse, 1.8 A, 600 V, dual-eiement time delay, FRS-R (B#FU1 B#FU3 for 21 8A4531 P14 6
460 V ac, 50 Hz or 575 V ac, 60 Hz blower motors)
Fuse, 1000 A, 1000 v, semiconductor, do leg lines for 700/1000 V ac input, 323A2432P14 12
77 mm SCR, 1500 A maximum output (2 fuses per keg)
Fuse, 2.0 A, 600 v, dual-element time delay, FRS-R (B#FU1 B#FU3 for 218A4531P1 5 6
Fuse, 3.2 A, 600 V, dual-element time delay, FRS-R (B#FU1 B#FU3 for 218A4531P19 6
Fuse, 3.2 A, 600 V, FNQ-R, time delay (CPTFU1, CPTFU2, CPTAFU1, 104X109BE O21 4
CPTAFU2 for 575 V ac input)
Fuse, 4.0 A, 600 V, dual-element time delay, FRS-R (B#FU1 B#FU3 for 218A4531 P21 6
Fuse, 4.0 A, 600 V, FNO-R, time delay (CPTFU1, CPTFU2, CPTAFU1, 104x109BE O23 4
CPTAFU2 for 460 v ac input)
Fuse, 5.0 A, 600 V, FNQ-R, time delay (CPTFU3, CPTAFU3 for all input volt- 104x109BE O24 2
ages)
Fuse, 630 A, 1300 v, semiconductor, do leg lines for 1000 V ac input, 53 323A2432P1 9 6/12
mm SCR, 655 A maximum output (1 fuse per leg) or 1265 A maximum out-
put (2 fuses per leg)
Fuse, 700 A, 1300 V, semiconductor, do leg lines for 700 V ac input, 53 323A2432P20 6/12
Fuse, 700 A, 700 v, semiconductor, do leg lines for 230/460 V ac input, 53 323A2433P6 6/12
12-30

I
Description Catalog (Part) Number of.

I
Fuse, 8.0 A, 600 v, FNO-R, time delay (CPTFU1, CPTFU2, CPTAFU1 r 104X109BE O29 4
CPTAFU2 for 230 V ac input)
Jumper, MDA link (drives without MDA contactor) 336A3434-DV 001 1
Jumpers, PCCA voltage select 36A358160XRG02 2
Keypad, with SLCC card 104X1 52AE O02 1
LAN Communications Card (SLCC) with firmware: G1 can be used with DS215SLCCG1A 1
DLAN or ARCNET; G2 with DLAN only; and G3 with neither DLAN nor DS215SLCCG2A
ARCNET. DS215SLCCG4A
LAN I/O Terminal Board (LTB) 531 X307LTBA _G1 1
Maintenance kit 36A35894tAAG02 1
MET1, O - 125%, SMET, non-regenerative drives 68A7614C22BUAAAB00 1

MET2, o - 125%, IMET, non-regenerative drives 68A7614C22BUAAAB00 1
MET3, o . - 125%, VMET, non-regenerative drives 68A7614C22BUAAABOO 1
MET4, o - 125%, FMET, non-regenerative drives 68A7614C22BUAAABOO 1
MET1, 125 0 125%, SMET, regenerative drives 68A7614C22YTAAAB00 1

MET2, 125 0 125%, IMET, regenerative drives 68A7614C22YTAAABOO 1
MET3, 125 O 125%, VMET, regenerative drives 68A7614C22YTAAAB00 1
MET2, 0 150%, IMET, non-regenerative drives 68A7614C22BCCCCB00 1

MET2, 0 175%, IMET, non~regenerative drives 68A7614C22CAEEEB00
MET2, 0 200%, IMET, non-regenerative drives 68A7614C22BDFFFBOO
MET2, 0 250%, IMET, non-regenerative drives 68A7614C22BEAAABOO
MET2, 0 275%, IMET, non-regenerative drives 68A76'I 4C22CCBBBB00
MET2, 0 300%. IMET, non-regenerative drives 68A7614C22BFCCCB00
MET2, 0 325%, IMET, non-regenerative drives 68A7614C22CDDDDBOO
MET2, o 375%, IMET, non-regenerative drives 68A7614C22CFAAABOO
MET2, 0 500%, IMET, non-regenerative drives 68A7614C22BHAAABOO
MET2, 150- 0 - 150%, IMET, regenerative drives 68A7614C22YCCCCBOO 1

MET2, 175 - 0 - 175%, IMET, regenerative drives 68A7614-C22SAEEEB00
MET2, 200 - 0 - 200%, IMET, regenerative drives 68A7614C22YDFFFBOO
MET2,
MET2,
250
275
_ 0 - 250%, IMET, regenerative drives
- 0 - 275%, IMET, regenerative drives
68A7614C22YEAAABOO
68A7614C22SCBBBB00
MET2, 300 0 - 300%, IMET, regenerative drives 68A7614C22YFCCCBOO
- 0 - 325%, IMET, regenerative drives
Q
MET2, 325 68A7614C22SDDDDBOO

MET2, 375 _ 0 - 375%, IMET, regenerative drives 68A7614C22SFAAAB00
MET2, 500 - 0 - 500%, IMET, regenerative drives 68A7614C22YHAAABOO
.
MET4, O 140%, FMET 68A7614C22BVBBBBOO 1
-
MET4, O 150%, FMET 68A7614C22BCCCCBOO
-
MET4, o 175%, FMET 68A7614C22CAEEEB00
Power Connect Card (PCCA), regenerative drives with DCFB DS2OOPCCAG5A 1

Power Connect Card (PCCA), non~regenerative drives with DCFB DS2OOPCCAG6A
Power Connect Card (PCCA), non-regenerative drives with SDCI DS200PCCAG1 OA
12-31
GEH-»600S DC2000 Digital Adjustable Speed Drive
Table 72-4. DC2000 M Frame Drive Parts List -- Continued
Description Catalog (Part) Number Qty .

I
Power Supply Board (DCFB, drive will contain either a DCFB or an SDCI) DSZOODCFBG 1 B 1
Reactor, large, for > 600 v ac 246B231 9BA G03 3
Reactor, small (L12 - L16) 206B2603G1 6
Relay Terminal Board (RTBA), 1 10 V do relay coils DS20ORTBAG1A 1

Relay Terminal Board (RTBA), 24 V do relay coils DS20ORTBAG2A
Relay Terminal Board (RTBA), 1 15 V ac relay coils DS2OORTBAG3A
Resistor, 5.0 Q, 40 W, 1000 V runs, SCR snubber for 1000 V ac 323A2354P8 12
Resistor, 50 Q, 40 W, de snubber (R3O R32), with PCCA, input voltage 104X123DE O18 3
s 600 V ac
SCR High Voltage M Frame Interface Board (SHVM) DS2OOSHVMG1A 1
SCR module, 53 mm, 1400 V for 230/460 v ac input, 728 A maximum out- 323A3350 6/12
put with 2 fans, 1 fuse per leg; 1428 A maximum output with 2 fans, 2
fuses per leg, or 1455 A maximum output with 2 blowers, 2 fuses per leg
(quantity 6 for non-regenerative drives, 12 for regenerative drives)
SCR module, 53 mm, 2100 V for 700 V ac input, 728 A maximum output 323A3351 6/12
with 2 fans, 1 fuse per leg or 1455 A maximum output with 2 blowers, 2
fuses per leg (quantity 6 for non-regenerative drives, 12 for regenerative
drives)
SCR module, 53 mm, 3000 V for 1000 V ac input, 655 A maximum output 323A3352 6/12
with 2 fans, 1 fuse per leg or 1265 A maximum output with 2 fans, 2 fuses
per leg (quantity 6 for non-regenerative drives, 1 2 for regenerative drives)
SCR module, 77 mm, 21 OO V for 700 V ac input, 1462 A maximum output 323A3371 6/12
with 2 fans, 2 fuses per leg or 1500 A maximum output with 2 blowers, 2
drives)
SCR module, 77 mm, 3000 V for 1000 v ac input, 1242 A maximum output 323A3372 6/12
with 2 fans, 2 fuses per leg or 1500 A maximum output with 2 blowers, 2
drives)
Shunt, 100 A, 100 mV 50-140034-PKAA 1

Shunt, 150 A. 100 mV 50-14-003-4-PZAA
Shunt, 200 A. 100 mV 50- 140034RLAA
Shunt, 250 A, 100 mV 50-140034RSAA
Shunt, 300 A, 100 mV 50-140034RXAA
Shunt, 400 A, 100 mV 50-140034SCAA
Shunt, 500 A, 100 mV 50-140034SFAA
Shunt, 600 A, 100 mV 50-140014SJAA
Shunt, 800 A, 100 mV 50-140014SNAA
Shunt, 1.0 kA, 100 mV 50-140014SSAA
Shunt, 1.2 kA, 100 mV 50-140014SUAA
Shunt, 1.5 kA, 100 mV 50-140014TCAA
12-32

Signal Processor Card (SPC) 531X309SPCA _G1 1
Splice, CPT and CPTA primary, 460 V ac Amp#1-321235-1 2
Switch, disconnect, 1200 A, 600 V (DSW) 104X205FA G05 1

Switch, disconnect, 1600 A, 600 V (DSW) TPYY561 6TSPL
Terminal board, 36 point (2TBl 246B8210AB G36 1
Terminal board, 4 point with cover, (2TBH) 246B2398AC G02 2
Thermal switch assembly with terminals, 190 °C, s. 600 V ac, standard 336A3390BF G03 1
Thermal switch assembly with terminals, 190 °C, > 600 V ac, standard 336A3390BF G01
Thermal switch assembly with terminals, 190/170 °C, s 600 V ac, optional 336A3390BF G04 1
Thermal switch assembly with terminals, 190/170 °C, > 600 V ac, optional 336A3390BF G02
12-33
GEH-6005 DC2000 Digital Acliustahle Speed Drive
Notes:
12-34
I APPENDIX A
GLOSSARY OF TERMS
CPL - I/O connector. See Chapter 6. card - Alternate term for printed wiring board .
1FPL through FPL - I/O connectors. See Chapter 6. CMP - Co-motor Processor. The TMS320C25 digital
signal processor (U35) mounted on the SDCC. The
-
1PL through 8PL, 11PL, 16 PL I/O connectors. See CMP performs math-intensive functions to support
Chapter 6. the motor control algorithms beyond the Motor
Control Processor's (MCP's) ability.
1RPL through 6RPL - I/O connectors. See Chapter 6.
COMPL - I/O connector. See Chapter 6.
1TB through STB - I/O connectors. See Chapter 6.
CNPL - IIO connector. See Chapter 6.
ACNA - ARCNET Connect Board, DS200ACNA. This
board provides the connection for an ARCNET data configure - To select specific options, either by setting
link between the drive and other devices . the location of hardware jumpers or loading soft-
ware parameters into memory.
actor/tracker - Actors and trackers are software ob-
jects used in the IOS2000 Intelligent Operator Sta- -
CP1PL through CPSPL I/O connectors. See Chapter
tion to track events in a process line. Publication 6.
GEH-6205 describes the actor/tracker objects.
CPCA - Contactor Pilot Card, DS200CPCA. This card
A/D - Analog-to-digital conversion. provides power to open and close contacts of a do
contactor with a coil voltage of 115 V do. Applies
application software - Job-speciiic software resident 'm full voltage to close contacts and keep them closed.
the drive, designed specifically for the customer's
application. CPT, CPTA - Control power transformer.
ARCNET - See DLAN + . -

CPTPL I/O connector. See Chapter 6.
ARCPL - I/O connector. See Chapter 6. CT - Line current transformer.
BCD - Binary coded decimal. CT1PL, CTSPL - UO connectors. See Chapter 6.
board - Printed wiring board. CX frame - Size of DC2000 drive, also referred to as
C Extension frame. See Table 4-1.
building blocks (software) - Standard modules (blocks)
of microprocessor code that perform specific soft- D/A - Digital-to-analog conversion.
ware functions (for example, a speed regulator).
Blocks are configured into the application program. DCIPL, DCZPL - I/O connectors. See Chapter 6.
C frame - Size of DC2000 drive. See Table 4-1. DC2000 drive - A microprocessor-based power con-
verter that produces a controlled de output for cus-
C Extension frame - Size of DC2000 drive, also re- tomer applications.
ferred to as CX frame. See Table 4-1.
DCFB - Power Supply Board; DS200DCFB. This
CDBA - Contactor Driver Board, DS200CDBA. This board furnishes de power to drive control boards
board provides power to open and close contacts of and provides instrumentation for field circuits .
a do contactor with coil voltages of 30-40 V de.
Forces contacts closed by initially applying 105 V
do to coil for 250 msec .
A-1
DCP - Drive Control Processor. An 80C186 processor FEAN DS2020FEAN 50 - 100 A NRX/NRP Field
mounted on the SDCC. Its software consists of user Exciter Module. This module provides excitation
interfaces, outer regulating loops, and system-level for a 50 to 100 A motor field. It operates with ei-
functions . ther of two types of non-reversing 'field supplies:
non-plugging (NRX) or plugging (NRP).
diagnostics - Software that checks drive hardware or
software, providing error indications that identify -
FEBN DS2020FEBN 75 A NRX/NRP Field Exciter
the type or location of malfunction. Module. This module provides excitation for up to
a 75 A motor field. It operates with either of two
DIP switch - Switch used on some boards to configure types of non-reversing field supplies: non-plugging
I/O options. (NRX) or plugging (NRP) .
DLAN - Drive local area network. A communications FECN - DS2020FECN 24 A NRXINRP Field Exciter
link between drives and controllers, featuring a Module. This module provides excitation for up to
maximum of 32 drops with transmissions at 57.6 a 24 A motor field. It operates with either of two
kbaud. types of non-reversing field supplies: non-plugging
(NRX) or plugging (NRP) .
DLAN+ (or DLAN PLUS) - GE Drive System's ver-
sion of ARCNET, using an ARCNET controller frame size - Size of drive cabinet, or cabinets. Deter-
chip with modified ARCNET drivers. A communi- mined by hardware components required for power
cations link between drives and controllers, featur- application.
ing a maximum of 255 drops with transmissions at
25 Mbaud. G frame - Size of DC2000 drive. See Table 4-1.
-
DPR Dual-ported RAM. Used for communications GLASTIC - A fiberglass-reinforced, mineral-filled
between two processors, such as the DCP and polyester electrical instation material .
CMP »
hardware (hard) reset - Reset generated by a hard-

Drive Configurator, LynxOS Version - A Lynxos- ware device, rather than by a software reset. Used
based software package used to coni'ure and per- to reset the drive boards, clear some faults, and al-
form diagnostics on the DC2000 drive. GEH-6203 low certain parameter changes. Activated by
describes the Drive Coniigurator, LynxOS Version. pressing the SDCC's RESET button or by connect-
See also ST2000 Toolldt. ing NTB/BTB terminal board point 3TB-58 or
STBA terminal board point STBA-38 to +5 or +24
drop - In network communications, any electonic de- V do.
vice connected to the network that transmits and/or
receives and is assigned a valid drop number. IA1PL, IA2PL, IFIPL, IFZPL - I/O connectors. See
Chapter 6.
DVM - Digital voltmeter.
ln1Mough 1N8 - I/O connectors. See Chapter 6.
EE or E2 - See EEPROM definition.
I/O - Input/output. Interfaces that allow the flow of
EE enable device - Device used to enable or protect data into and out of a device.
EEPROM programming. A hardware jumper (JP1)
011 the SDCC card. IOPL - I/O connector. See Chapter 6.
EEPROM - Electrically erasable programmable read- J frame - Size of DC2000 drive. See Table 4-1.
only memory, also called EE or E2 (E squared) .
Contains the drive parameters . K frame - Size of DC2000 drive. Consists of multiple J
frame dives, one of which is configured as the
EPROM Erasable programmable read-only memory. master drive, the rest of which are configured as
follower drives.
FAPL - I/O connector, See Chapter 6.
KPPL - I/O connector. See Chapter 6.
A-2
DC2000 Digital Aqiusrable Speed Drive GEH-6005
LAN - Local area network. A communications link that MPL - I/O connector. See Chapter 6.
enables attached devices to communicate with each
l other over a limited geographical area. node - In network communications, a junction or con-
nection point (terminal or computer) .
LCP - LAN Control Processor. An 80C196KC proces-
sor (U1) mounted on the SLCC . -
NPL I/O connector. See Chapter 6.
LCS - LAN Current Source Board, 531X207LCS. This NRP - Non-reversing, plugging.
board provides a 5/15 V de power supply and a
voltage-limited 0.3 A current source, -
NRX Non-reversing, non-plugging.
LED Light-emitting diode. Used as a visual indicator NTB/3TB Drive Terminal Board, 531X305NTB. This
for a board or drive function. board contains the drive's customer connection
terminals (3TB) for most signal-level I/O. It also
LTB LAN I/O Terminal Board, 531X307LTB. Op- contains most of the hardware customizing jumpers
tional board that provides an interface between the and potentiometers, plus passive interface circuitry.
drive and external devices, such as COIIIHCIOIS,
lights, pushbuttons, and interlocks. OT1 through OT8 - I/O connectors. See Chapter 6.
LynxOS - A personal computer operating system pro- PAL - Programmable array logic. An array of user-
duced by Lynx Real-Time Systems, Incorporated. programmable logic gates contained on a single
chip which is used to replace a number of separate
M frame - Size of DC2000 drive. See Table 4-1. packages.
MA - Main ac contactor. parameters - Adjustable software settings used to pro-

gram and tune the DC2000 drive .
MACPL - UO ccmnector. See Chapter 6.
PCCA - Power Connect Card, PCCA. This board pro-
MBHA - Multi-bridge Hub Communications Board, vides an 'interface between the DC2000 control cir-
DS200MBHA. This board provides a fiber-optic cuits and the SCR power bridge.
interface between the member drives in a multi-
bridge lineup, and between the 6-pulse lineups that -
PCN, PCR Power Connect Board, 531X122PCN or
make up a 12-pulse system. 531X121PCR. This board provides an interface
between the control circuits and the SCR power
MCP - Motor Control Processor. An 80C196 micro- bridge. The PCN board is used in a non-
controller (U21) located on the SDCC. Its software regenerative drive, the PCR board is used in a re-
consists of current regulators, and motorltechnol- generative drive .
ogy-speciNc functions .
PL - Plug (may be plug or receptacle).
MD - Main de contactor.
plug-in connector - A type of I/O connector, typically
MFC - Motor held consol. containing more than one pin, and made so that a
connecting cable (with wires matching the connec-
l.LGENI Controller Board - IC660ELB9l2G. An op- tor pin-out) plugs onto it as one unit.
tional board for the Unit Controller 2000 (UC2000)
.
that provides an interface to the Genius I/O bus PPL - I/O connector. See Chapter 6.
module - An electrom'c assembly of boards, compo- -

Programmer (module) An operator °mterface module
nents, or a combination of these, that together per- that includes a digital display and keypad, used for
form a specific function. software adjustment, diagnostic testing, and digital
fault code readouts. Included on the SLCC card.
MOV - Metal-oxide varistor .
A-3
PROM - Programmable read-only memory. A read- SHV1 - SCR High Voltage Interface Board,
only memory (ROM) chip that is programmed at DS200SI-M. This board provides an interface for
the factory for use in a given device. signals from a J or K frame drive's SCR power
bridge to the DCFB or SDCI board, and to the
RAM - Random access memory. Memory that can be PCCA card.
both read from and written to .
SHVM - SCR High Voltage M Frame Interface Board,
regenerative - Ability of a drive to return power from DS200SHVM. This board provides an interface
the motor armamre to the ac line. Creates a braking from an M frame drive's SCR power bridge to the
effect O11 the motor » DCFB or SDCI board, and to the PCCA card.
RMPL, RPL - IIO connectors. See Chapter 6. SLCC - LAN Communications Card, DS215SLCC.
This card provides isolated and non-isolated input
RS-232C - A serial link communications interface stan- circuits for communications to the drive. The
dard for interconnecting data terminal equipment, SLCC contains the Programmer module .
such as printers, CRTs, or computers, to data
communications equipment, such as modems, for software (soft) reset - Reset initiated by software in-
transmissions over a telephone line or network. put, rather than by a hardware device. Activated by
RS-232C uses an unbalanced or singlehanded volt- a serial input, or by pressing the Programmer's
age interface. This connection is provided on the RESET key.
DC2000 drive only for interfacing with the ST2000
Toolkit or Drive Configurator . SPC - Signal Processor Card, 531X'309SPC. This card
processes inputs before sending them to the SDCC .
RS-422 A serial link communications interface stan- It provides encoder feedback, converts current ref-
dard that defines electrical interface characteristics. CICIICC signals to voltage reference signals, and re-
This standard permits greater distances between ceives RS-422 inputs .
equipment and faster data transfer than RS-232C.
RS-422 is characterized by a balanced or differen- SPCB - Multi-bridge Signal Processing Card,
tial voltage interface . DSZOOSPCB. This board provides an 'interface be-
tween the SDCC and MBHA boards. The SPCB
RTBA - Relay Terminal Board, DS200RTBA. This consists of two encoder follower circuits, two proc-
board provides ten relays that can operate from ess control analog signal interface circuits, and H-
voltages supplied by the LTB or external voltages ber-optic interface circuits.
supplied by the customer. Seven of the relays have
two form C contacts, the other three have four SQPL - I/O connector. See Chapter 6.
form C contacts. The relays are available with
three coil voltages: 110 V de (GI); 24 V de (G2); stab - A wide, raised metal post on a printed wiring
or 115 v ac, 50/60 Hz (G3). board IIO path used a type of jumper connection to
configure various board options. Connection is
SCR Silicon-controlled rectifier (thyristor). made using a wire terminal that plugs onto the stab.
SDCC - Drive Control Card, DS215SDCC. The card Sta111s_S - GE proprietary communications protocol
contains the drive's primary control circuits includ- that provides a way a commanding and presenting
ing three 16-bit microprocessors: the Co-motor the necessary control, configuration, and feedback
Processor (cmp), Drive Control Processor (DCP), data for a device.
and Motor Control Processor (MCP).
ST2000 Toolkit - A DOS-based software package used
SDCI - Do Power Supply and Instrumentation Board, to configure and perform diagnostics on the
DS200SDCI. This board furnishes do power to DC2000 drive. GEH-5860 describes the ST2000
drive control boards and provides instrumentation Toolldt. See also Drive Coniigurator, LynxOS
for Held circuits. Version.
A-4
STBA - Basic Drive Terminal Board, DS200STBA. testpoint - A hardware point, usually a metal ring or
This board contains the drive's customer connection post, located on a printed wiring path, used for
terminals for most signal-level I/O. It provides a testing a signal or voltage on a board.
basic set. of features derived from the NTB/3TB,
LTB, and RTBA boards. TP - Testpo'mt. See definition above.
SYTB - I/O connector. See Chapter 6. UART - Universal asynchronous receiver/transmitter .

TB, TB1, TBPSA, TBPSB - I/O connectors. See VCO - Voltage controlled oscillator. An oscillator cir-
Chapter 6. cuit whose output frequency is proportional to the
voltage applied to it.
terminal board connector - A type of I/O connector in
which individual wires are inserted into a connector Y9PL through Y3SPL - I/O connectors. See Chapter
point and are fastened by turning a screw on the 6.
terminal.
A-5
Notes:
A-6
c APPENDIX B
HARDWARE DRAWINGS, c, CX, AND G FRAME DRIVES
B-1. INTRODUCTION drives, and sheet DA applies only to C frame drives.

Note that these drawings also apply to other GE Drive
The DC2000 Digital Adjustable Speed Drive's conigu- Systems products, such as GF2000 Do Generator Field
ration varies according to the customer application re- Exciters and ME2000 Do Motor Field Exciters; there-
quirements. Therefore, GE provides hardware drawings fore, the drawings may show equipment not present in
to show the locations of the drive's terminal board 211 DC2000 drive•
points, printed wiring boards, connector plugs, and
power fuses. These drawings are located in the drive NOTE
door pocket.
Drive hardware drawings may change with
Figure B-1 includes the hardware drawings (336A3511 product upgrades and revisions. The draw-
series) for C, CX, and G frame drives. Sheet AA ap- ings presented in this manual are current as
plies to all three frame sizes, sheet BA applies only to G of the issue date.
frame drives, sheet CA applies only to CX frame
B-1
'f;','CI'
RIGHT SIDE VIEW
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DR
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REVJ REVA RENL7 PRINTS TO ENGINEER I [35 / I FQ: /

11-04-93 03-03-95 GENERAL ELECTRIC J
Rave REV5 ISSUED COMPANY CGRE

9-6-94 09-22-93
D R I V E SYSTEMS DEP1
REVS
1-E7-95
R E V BY
MADE
w.l3. BAKER
SALEM VA. USA. 336A35HAA
c0n7nn so SH, nm 1 -I
Figure B-1. C, CX, and G Frame Hardware Drawing 336A351 7 (Sheet AA)
B-2
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REV.1 REV.4 REV,7 PRINTS TD ENGINEER

10 - 08 - 93 GENERAL ELECTRIC 'G' FRAME
REV.2 REV.5 ISSUED CBMPANY EERE
03-03-95 09-22-93
DRIVE SYSTEMS DEPT.
REV.3 'REV.6 MADE BY
w.G. BAKER
SALEM, VA. U.S.A. 336A3511BA
C:1NT.NN sH, FL SH. nu 1
Figure B- 1. C, CX, and G Frame Hardware Drawing 336A357 7 (Sheet BA)
B-3
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REV.1 REV.4 REV.7 PRINTS TO ENGINEER

10-08-93 GENERAL ELECTRIC 'C' FRAME
REV.2 REV.5 `lssu:n
I
CDMPANY EXTENSIDN CORE
09-22-93
DRIVE SYSTEMS DEPT.
REVS REV.6 MADE BY
w.r5 BAKER
SALEM, VA. u.s.A. 336A3511CA
CDNTDN SH. SH. nm. 1 J
Figure B-1. C, CX, and G Frame Hardware Drawing 336A357 7 (Sheet CA)
B-4
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n I
co 6Al:s(£>
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( FAN 1J ( FAN )
( FAN ~1
q
REV.1 REV.4 REV.7 PRINTS TO ENGINEER
D3-03-95 GENERAL ELECTRIC 'C' FRAME
REv.a REV.5 ISSUED CEIMPANY CURE
06-14-95 09-22-9 3
DRIVE SYSTEMS DEPT.
REV.3 REV.6 MADE BY
w.G. BAKER
SALEM. VA, U.S.A. 336A3511DA
|
I |
cunT.nn SH. SH. ND. 1
Figure B- 1. C, CX, and G Frame Hardware Drawing 336A351 1 Sheet DA)
B-5
Notes:
B-6
APPENDIX c
HARDWARE DRAWINGS, J AND K FRAME DRIVES
C-1. INTRODUCTION available. Table C-1 shows the applicability of each

drawing to the drive configuration.
The DC2000 Digital Adjustable Speed Drive's configu-
ration varies according to the customer application re- NOTE
quirements. Therefore, GE provides hardware drawings
to show the locations of the drive's terminal board Drive hardware drawings may change with
points, printed wiring boards, connector plugs, and product upgrades and revisions. The draw-
power fuses. These drawings are located in the drive ings presented in this manual are current as
door pocket. of the issue date.
Figure C-1 includes the hardware drawings (336A3508

series) for the J and K frame configuration currently
Table C- 7. Hardware Drawing 336A3508_, J and K Frame Drive Applications
Drive Drawing Number Suffix

-
Deseription AA AB AE AF BA BB BC CA DA EA FA GA
J Frame with 2TB, J J J J J
Input s 600 V ac

-
Input 600 1000 V ac
J Frame with 2TB, J J J J ./

Input > 1000 v ac

Input 5 600 V ac
K Frame with 2TB, J J J J J

Input S 1000 V ac
K Frame with 2TB, J J J J .f

Input > 1000 V ac

Input s 1000 V ac

Input > 1000 V ac
J
C-1
m <r
m <r an m
m TDP VIEW
Cr D LORD
m ru re m
m m
2TBH -
@@
i
.» MET3 META*
I
FRDNT VIEW 1.
2TBH o
an o
ez) METERS .
o°§b
OOOO
CPTFU MPLX CDCl
(CARD BDXD
(CARD
(1>
(1> c1>
(1> (1>
(1> (MDA-CD)
1 E 3
<a)
<a) (e> (E)
(E) 1FPLX
PTCT
CPTAFU w CDC2
ca
@
@
Cl) <1> (1)
c1> (1) (1> 2lrPLX
1 2 3
(2)
(2) ca) CE)
J
DCFU
c1> (1)
(1)
T
L> 1 2
"
L
(3e> can CE>

(LEFT DEER) (RIGHT DEER)
, ' ARPANET/DLAN BALUN

so
ED
r' min 0,0 O AC INCUMING BUS
RTB LTB 3TB UR STBA I I K1 - REAR
KG - MIDDLE
CARD CARD CARD (\|(\
o'o 0 K3 - FRBNT
BLDWER
\ o- a- @
B1FU1
B1FU2
B1FU3
O
O
I B2FU1
B2FUE
8EFu3
\
B3FU1
B3FU
B3FU3
U!
TYPICAL
N l . i J a
1M
BLOWER
FUSES
FRDNT END
T Ia
"Wla
FANS r
J
FAN1 FANS FAN3
L I
REV.1 JAF REV.4 REV.7 PRINTS TO ENGINEER

11-4-93 GENERAL ELECTRIC J FRAME
REV.2 REV.5 ISSUED CDMPANY W/ETB
09-22-93 DRIVE SYSTEMS DEPT.
REVB Revs MADE BY
¢A.F1NCH
SALEM, VA. USA. 336A3508AA
CDNTDN SH SH.N0. 1 J
Figure C-1. J and K Frame Hardware Drawing 336A3508 (Sheet AA)

C-2
F FIELD
V VDLTS
GD o
ET l§5&553i
F
§:<
<l§3
FRDNT VIEW
I
METEESS
A AMPS
@6(
STB
(CARD
(CARD Bax)
Bax)
u> <23) (45) I(67>
"'1
I
CPTAI
I
l
o
Cr
___J
I
"'1 can (44> (66) (ser
I
I CPTF
CPT,
I CD (D (D -FU3
I
___J 1 2 3
ca>(2>
~cTAF3-2
(LEFT DDDR) (RIGHT DDDR)
ED
E) r."" ARPANET/DLAN BALUN
t o r-*\ > o AC INCDMING BUS
RTB
CARD Il LTB
CARD rI 3TB DR STBA
CARD
I
(\l£) f\Ic
I
O KG
K1 - REAR
MIDDLE
K3 - FRONT
I
BLOWER
lI I I I.
B1FU1
BIFUE
.
'Of
BaFu1
BaFua
B3FU1
B3FU
111
f 111
1M
TYPICAL
BLDWER
FUSES
I Ia
la
I la
B1FU3 B2FU3 BSFU3 FRDNT END
RIGHT SIDE
BEHIND 6TB PANEL
FAN 5 r
J \ \ r
FANl FANS FAN3
6TB CPTA
CPT
no
\
REVJ JAF REVA -| REV.7 PRINTS To ENGINEER

11-4-93 GENERAL ELECTRIC J FRAME
Rave REVS ISSUED CDMPANY W/6TB
09-22-93 DRIVE SYSTEMS nzpl
REVS REVS MADE BY
JA.FINCH
SALEM, VA. U.S.A. 336A3508AB
CDNTDN SH. SH. N0- 1 J
Figure C- 1. J and K Frame Hardware Drawing 336A3508 (Sheet A8)
C-3
I I
FRDNT VIEW
w
I
I
o » \C)@
U*
I
--I
Ln
-'
Q
2TBH
Ln '~.D
1-1 1-1
'
--I
m <r If)
("l
OJ §
ru
LO oD
CLI m
(U ru CLI .
I
MBHA
UID
TB @@@ i
e
GD e
GD
o"§58So
CPTFU 11PLX
(CARD BOX)
<1> (1)
(1) (1)
(1)
®
ED
I 1 2 3
ca) (E)
I CPTAFU
(E) CE)
IFPLX
in
(1) (1> (1)
(1) (1) 2FP_X
in
l::::J
1Ag; 1 E 3
(a> (2)
(2) (2)
(2)
(1)
(35)
(LEFT DEER) (RIGHT DDERD
DOOR)
0 of'ARPANET/DLAN BALUN
of
QD
o O AC INCEIMINE BUS
RTB LTB 3TB DR STBA K1 - REAR
CARD CARD CARD o K2 - MIDDLE
K3 - FRDNT
e- a
_
1-
1L 0
TYPICAL
..
BLDWER Q' 111 11 2
|!
(> lil II 2
111 II 2
B1FUl
B1FU2
Bu-Q
BEFU
B3FU1
B3FU
BLOWER
FUSES
FRDNT END
B1FU3 8EFu B3FU
FAN r
J' 5
FAN1 FAN2 FAN3
REV.1 REV.4 REV.7 PRINTS TI] ENGINEER

GENERAL ELECTRIC K FRAME
REVS REV.5 ISSUED CDMPANY W/2TB`
H-16-93 DRIVE SYSTEMS DEPT.
REV.3 REV.6 MADE BY
J.A FINCH
SALEM, VA. U.S.A. 336A3508AE
CDNTDN SH. SH. NO. 1 J
Figure C- 1. J and K Frame Hardware Drawing 336A3508 (Sheet AE)

C-4
I l
r
FRDNT VIEW
LAN
as. [II]
MBHA TB
GD QUO METERS
(>(:)[]'_/mTB
(:)(:)(:)'}_/mTB
(CARD BOX)
(CARD BOX)
6TB
(1> . <45)
o
II
I I
c3a> (76
(LEFT DEER) (RIGHT DEER)
as 'f' ARPANET/DLAN BALUN

rI
I
O O AC INCDMING BUS
I RTB
CARD
l LTB
CARD
3TB UR STBA
CARD C) C) I K1 - REAR
KG - MIDDLE
K3 - FRENT
»1l lI l I %I I»
TYPICAL
BLDWER HI II
C)
iii! 111 Ila
b C) 11% lla
BIFU1 B2FU1 BagFUl BLDWER
BIFUE BEFU B3Fua FUSES
B1FU3 B2FU3 B3FU3 FRDNT END
FAN 5 rJ
FAN1
FANI I FANS FAN3
'i
REV.1 REV.4 RE\M7 PRINTS TU ENGINEER

Rave REVS ISSUED CDMPANY W/6TB
M-16-93 DRIVE SYSTEMS DEP1
RE\L3 'Revs MADE BY
~iA.FINCH
SALEVL VA. U.S.A. 336A3508AF
cnnLun SH. $H.ND. 1 _|
Figure c- 1. J and K Frame Hardware Drawing 33 6A3508 (Sheet AH
C-5
FRDNT VIEW
INSIDE CARD BEX
BACK VIEW
LEFT DEER HINGE r
PCCA
SIDE
H Dcl
DCFB
DR
SDCI
CPTA I
CPTAX *o TCCB
I FANS
CPT
SPCA
y E
SLCC
DR
SPC8
CPTX
SDCC
II
FANI
FAN1 FAN2
nav; REVA REv.`7 PRINTS TO ENGINEER

JAR
H-4-93 GENERAL ELECTRIC K FRAME
REVS REVS ISSUED COMPANY
09-22-93 DRIVE SYSTEMS DEPL
never REVS MADE BY
A.FINCH
SALEM V A use 336A35088A
cnnlmn SH. SH. ND. 1 J
Figure C- 1. J and K Frame Hardware Drawing 336A3508 (Sheet BA)
C-6
I I
FRDNT VIEW
INSIDE CARD BDX
PCCA
DCIA,
DCFB
DR
I mm
FAN3
TCCB
/
g SDCC
SPCA
be
SPC8
FAN1 FAN2
REV.1 RE , REV.7 PRINTS TO ENGINEER

JAF v4
I L FRAME
H-4-93 GENERAL ELECTRIC
REV.2 REV.5 ISSUED CDMPANY
REV.3 REV.6 MADE BY
JA.FINCH
SALEM, VA. u.s.A. 336A3508BB
cnnlun SH. SH. ND. 1 J
Figure C-1. J and K Frame Hardware Drawing 336A3508 (Sheet is;
C-7
FRDNT vlEw
INSIDE CARD BOX
BACK VIEW
LEFT DEER HINGE PQCA
SIDE
H
CPTAFU DCFB
CPTFU
CPTA
BTB FAN3
(D
CPT
SPCA
DR
l(22w SPCB
¢
SDCC
II
FAN1 FAN2
'1
RE\L1 RENL4 Rzwn7 PRINTS TD ENGINEER

RE\L2 RE\L5 ISSUED QUMPANY W/STB
11-16-93 DRIVE SYSTEMS DEPT
RE\L3 RENL6 MADE BY
A.FINCH
SALEN VA. USA. 336A35088C
cnnlnn SH SH. NU 1
Figure C- 7. J and K Frame Hardware Drawing 336A3508 (Sheet BC)
C-8
TYPICAL REVERSING SIR BRIDGE (FRDNT VIEW)

I f"""-"'°'""-"---""-"'---""---°----'--'-----'---'---"l°""°"'"-"ll
I
I
CELL
RES
CELL
RES
CELL
RES :
I
I
(-> 2 (+) (~> 2 C+) (-) 2 (+) :
Q
c J
:| c 2
:I
IIg
c : c J
wI
I
I
1R IF ER 2F 3R 3F |
I
I
I 1
14 u H .
H - '
H N I
I
Q; go up
go 63Q go;
I I
I
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BTSW
§7§
aTsw
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2TSW
QUO
1Tsw I
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I I
I N #4 H H 1.4 H I
I I
A E A
I I
I |
I I
I 4F 4R 5F 5R SF SR I
1
I 1S |
I |
I
g K1 I Kg K3 g
I
I PHASE 1 SCR PHASE 8 SCR PHASE 3 SCR I

-_._------.._____-___----_--..__.._._....___._____._..___.....__....____|
TYPICAL NON-REVERSING SCR BRIDGE (FRONT v1Ew>
II - - - - - - - -
I
I 5"A
CELL - n - - - - - - -
5" CELL " " " " ' - " ' * " ° " " CELL
' " " " ' ° ' ° - ' ° 1
RES
I
I
I
I
I (-> (+) (-> (+) (-> $ 2/2 C+) I
I
8.3
I
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I 2
J
E
:
D
:
3
D
I
I
I
I
I I
I 1F
IF EF 3F l
I I
I I
I I
I 1Tsw 1Tsw 1Tsw I
I
I
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I
E D D
I
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l > v I >~
Pa 4 I Pl
Pl l N
I
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2Tsw aTsw g aTsw
r
I
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l
I
D D D I
I
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I dP 5F OF I
I I
I I
I
I K1 I KG K3 I
l
I PHASE 1 SCR PHASE E SCR PHASE 3 SCR I
_ . _ . _ _ . _ . _ _ _ . . . . _ . _ _ _ . . _ _ _ _ - _ . _ _ _ _ _ _ . . _ _ . . _ _ _ . . . _ _ _ _ _ _ _ _ _ _ _ . . _ _ _ _ _ _ _ _ _ _ 1
'
REV.1 REV 4 REV 7 PRINTS TO ENGINEER

GENERAL ELECTRIC J, K, L FRAME
REV.2 REV.5 ISSUED CDMPANY
09-22-93
DRIVE SYSTEMS DEP1
REV.3 REV.6 MADE BY
.LA.FINCH
SALEN VA u;A 336A3508CA
CDNT.Dn SH. SH. ND. 1 J
Figure C-1. J and K Frame Hardware Drawing 336A3508 (Sheet CA)
C-9
I I
CURE PANEL (FRDNT VIEW DDDRS DPEN)

r...............................................--..------..--............
I
..........................----....... --------
I
I
|
|
I
|» 0 • pa(-)
PA) REAR BUS
I
I
I
A
1 O'
O' 9 FRENT BUS
I
I
I
LM I FUN
FÙ21 | L13
I 1 FUN l I L,152
! 1 Furs I I
l '
I
l l .
SMALL REACT DR
I
I
I I I I
I
I
I
I H)
(1> l L12 I | u>
(1> I L14 I U) ! L16
l ! J
I
I I
J LARGE REACTER
I I I
.
41
I I
.
ce>
|
I
. (8)
(8) QQ
v*-
I
I
I
I
I
I
I
1 .I
_
"T
I
I
I
I
FU 1 3 4 FU 5 6 7 8 FU 9 ID 11 112
11 DC LEG FUSE
f
\
I
LJ LJ LJ
I
I
I K1L
L,J K3L
F
I
I
I
I
I
45- R3&R3LR3a
I
I
I
(-) (+> (-D (+) -3 (+> DC SNUBBER
|
I
I
I PHASE 1 PHASE 2 PHASE 3 RES
I
I
I SCR SCR SCR (SERIES CONNECTED)
I
I
I
I
I
I
I
SHVI
I
I
I
CARD
I
I
1
1
|
I
I
I
I
I
I
I
I
I
I
I K1 Kg K3 CTR
I
| I-V*\
|
I
I
FRONT BUS
I
I
I
I
I
I
|
I
l 4'
MIDDLE BUS
1
I
I
I
CT1
I Y\
I
I
I
REAR BUS
I
I
1I <-
I
I
I
L -....--....-..-...... -..- _
-..-..-..- _____--
REV 1 REwarm REv.7 PRINTS TO ENGINEER

10-11-93 GENERAL ELECTRIC L FRAME
REVS Rswns ISSUED CBMPANY
Rcvza REV.6 MADE BY
JA.F1NCH
SALE% VA, USA. 336A3508DA
CDNTEN SH. SH. ND. 1
Figure C- 7. J and K Frame Hardware Drawing 33 6A3508 (Sheet DA)
C-10
I I
CORE PANEL (FRDNT VIEW DDDRS DPEN)

V--"'--*-*'**"'-"*'""*°"'*-"'""'*-'"l"*"""--*--1
I I
I PE BUS (-) REAR I
I I
I PI BUS (+) FRDNT I
I I
I I
I
I
I
I
"1
R21
2 - L t
Rae
Eu
| R23
2u
| I
I
I
I
I C21 CEE C23 C30 I
I
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(1 a\
<> min <> I
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®
I I
I C1 ca C3 C4 C5 CO I •
I
©©
I
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2
I
I
I
I
I
I I
I K1L K2L K3L I
I
l y
I
I
I
I
(-> (+) (-) (+) (-) I (+>
I
I
I
I PHASE 1 PHASE E PHASE 3 I
I SCR SCR SCR I
I I
I I
I I
I I
I I
I
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-- /
1,
/'
I
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I I
I I
I I
I I
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h--------_-_--_-_-___-__-____________-_-_--________J
szE~/.1 new REIv.7 PRINTS TO ENGINEER

GENERAL ELECTRIC J FRAME
R E V 5 R E \ / . 2 ISSUED COMPANY
F2E§'v.:3 sas;\a'.E5 MADE BY
JA.FINCH
SALEM VA u;A 336A3508EA
CDNTDN SH. SH ND. 1
J
Figure C- 1. J and K Frame Hardware Drawing 336A3508 (Sheet EA)
C-11
EERE PANEL CFRDNT VIEW DEDRS DPEN)

v-'---"---'-"--"°---**'**"*'""-""-*'--'""-""1
I I
l P2 BUS (-) REAR I
i I
I PI BUS K+) FRONT I
l I
I I
I I
I I
I I
I I
I
" I
I
I
I
I
© C1
© C3 I
I
I
I
I
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1
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I
I
I I
I K1L K2L K3L I
I I
I I
I
I
I I
(->
PHASE 1
C+) (->
PHASE
PHASE 2
(+> K + ) ( ~ >
PHASE 3
I
I
I
I SCR SCR SCR I
I I
I I
I I
I I
I /
I
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_
f I
I
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II I
I
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I I
L__________________________________________________J
-I 'I
RE:\fJ REVA REv.7 PRINTS TD ENGINEER

R E : \ / . 5 R E V 2 dssuzn CBMPANY
09-22-93 DRIVE SYSTEMS DEPT
REv.3 I?Ev_6 MADE BY
JA. FINCH
SALEM, VA. U.S.A. 336A3508FA
cnnlnn SH. SH ND. 1 J
Figure C- 7. J and K Frame Hardware Drawing 336A 3508 (Sheet FA)
C-12
I I
CURE PANEL (FRONT VIEW DEDRS DPEN)

V"'°----"-'*--"'-*'"'-'*-""**"-""'-"-"*-"------1
I I
I pa BUS (-> REAR I
I I
I PI BUS (+) FRDNT I
I I
I I
I I
I I
I I
I I
I I
I I
I I
I I
I 4,1=FRDNT I
I 1 2 Lu 2 / a=REAR 1"a 1 2 1"a 1"z I
I C1 C2 C3 C4 C5 C6 I
I I
I I
I I
I I
I I
I I
I K1L K2L K3L I
I I
I
I
I
(-) (+)
(+) (-> (+ (->
I (+)
I
I
I
I PHASE 1 PHASE 2 PHASE 3 I
I SCR SCR SCR I
I I
I I
I I
I I
I I
I
I I
I / I
I I
I I
I I
I I
I I
I I
I I
I I
L_____________________________-___-________________J
REV.1 REV.4 REv.7 PRINTS TO ENGINEER

GENERAL ELECTRIC K, L FRAME
RE\L2 Rains ISSUED CDMPANY
I2IE'V/.:3 lZl'UIE; MADE BY
JA.FINCH
SALEM VA. use 336A3508GA
CUNLDN SH. SH ND. 1 J
Figure C- 1. J and K Frame Hardware Drawing 336A 3508 (Sheet GA)
C-13
Notes:
C-14
APPENDIX D
HARDWARE DRAWINGS, M FRAME DRIVES
D-1. INTRODUCTION AH apply to all M frame drives, sheet AE applies only

to M frame drives with input voltages of 600 V ac or
The DC2000 Digital Adjustable Speed Drive's contigu- less, and sheet AF applies only to M frame drives with
ration varies according to the customer application re- input voltages between 600 and 1000 V ac.
quirements. Therefore, GE provides hardware drawings
to show the locations of the dive's terminal board NOTE
points, printed wiring boards, connector plugs, and
power fuses. These drawings are located in the drive Drive hardware drawings may change with
door pocket. product upgrades and revisions. The draw-
ings presented in this manual are wrrent as
Figure D-1 includes the hardware drawings (336A3509 of the issue date.
series) for M frame drives. Sheets AA, AB, AD, and
D-1
FRONT VIEW
<2 <>
CDC1 (meA-CD)
EE- 9
10
l
15 aTBH
MBA SHP1 16
L1 L2 L3
E L 23
24
MFCA DSW 25
0
ES
I
l
FL
K1 K3 U
D P1A
I 0
I
(7 METERS 2TB
.QUO.
|
QD •
CXDC) @a 1
ca
CARD BDX
1FPLX E E
E E
36
2FPLX
2 2
TYPICAL CPT
E
2
11PLX E FUSE HDLDER

CPTFU
PTCT"
QARDV-
g CPTAFU /DR >
<3
l
RTB
CARD
| QUO.
l LTB CARD
1 3TB/STBA CARD
C)
BM1
@z» o
C)
O
C)
w; \ ARPANET/DLAN
BALUN
B1FU1 B2FU1
\'"'
nm
TYPICAL
rd§-
@
VT§
-" 1
I
B1FU2 8aFua
IW
_1
|
B1FU3 B2FU3 -Ni;
FRDNT END DF TYPICAL
BLEWER FUSE HDLDER
T FAN1 FAN2
T
'l 'l
Rzvn7 PRINTS TD ENGINEER

M FRAME
R E \ L 4 R E \ ! l
GENERAL ELECTRIC
RE\L2 REVS ISSUED CDMPANY
H-08-93 DRIVE SYSTEMS DEP1
Rzwna RE\L6 MADE BY
w. DINKEL
SALEM. VA. U.S.A. 336A3509AA
CUNTDN sH. F'L sH. nu. 1
Figure D- 7. M Frame Hardware Drawing 336A3509 (Sneer AA)

D-2
BACK BASE
CDDDRS REMOVED>
I SHP1
FRDNT vIEw
INSIDE CARD BDX
PCCA
§plA
SH1 I DCFB
1 ~2TBH~16 DR
SDCI
.
CPT CPTA
I
CPTX
2
ETBH-15
CPTAX
I
TCCB
FAN3
SP1 f
I SPCA
sncc
/
I FAN1 FAN2
m
[Jn
PA
soE:\J'.111 /1 in /Iea 13 FZEIv'.|4 RE\,L7 PRINTS TO ENGINEER

ADDED SH1 GENERAL ELECTRIC M FR AM E
REVE REVS ISSUED CDMPANY
H-08-93
DRIVE SYSTEMS NEPAL
Rave REVS MADE BY
W.DINKEL
SALEM, VA. U.S.A. 336A3509AB
cnnTnn sn FL SH. nu. 1
_|
Figure D- 7. M Frame Hardware Drawing 336A3509 (Sheet AB)
D-3
L1 LE L3
I I I
TYPICAL - ALL VDLTAGES CFRDNT VIEW - DEDRS DPEN)
DSW
K1 KE K3I
l
L1 LE
I
L3 LARGE REACTDRS
CT1
*
-=:
IK1 K KG3
I ->
CTR
M
p1(+)
I o» l
1
4 4
SMALL
L12 LI4 I REACTDRS L16
I 1
I DC
I
FU 3 4 7 8 LEG n
11 12
FUSES
I I I I I
I<+>
.P
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SCR SCR EQ
-
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LE
(-> (~> (->
-
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I I I I
FU 1 2 5 6 9 10
. I I II
I
I
L11 LI I
L15
.I i I pa(->
'I
REd/J RE\Lq REML7 PRINTS TD ENGINEER

GENERAL ELECTRIC M FRAME
REVS RE\A5 ISSUED CDMPANY
H-08-93 DRIVE SYSTEMS DEP1
REVS REVS MADE BY
W.DINKEL
SALEM, VA. u.s.A. 336A3509AD
CUNLUN so FL. SH. nu. 1 J
Figure D- 1. M Frame Hardware Drawing 336A3509 (Sheet AD)
D-4
I I
TYPICAL SCR CELL APPLICATIDN - 600V
(FRDNT vIEw
®
C2 C4 C6
@ @
I
1
(+5
o
E R1
0 1
(+)
o
E R5 1
(+)
o
E I RE
1 2 RE 1 E R6 1 E R10
B I

SCR SCR SCR
1
1
o
2
2
r
R3
R4
i 1
1
o
2
2
R7
R8
11
11
o
2
Hz
2
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RH
F2122
® ®
.
<-> (-> (
C1 C3 C5
@
1 2E R30
®
1 2E R31
C30
R32 1
2
NOTE= C1-C6 & R1-R12 ARE THREE PHASE SCR SNUBBER CIRCUITS.
C30 & R30-R32 IS THE DC LINE FILTER
Ru/.1 RD/.4 REV] PRINTS TD ENGINEER

RE\L2 RE\L5 ISSUED CDMPANY
H-08-93 DRIVE SYSTEMS DEPT
RENHB RE\/5 MADE BY
w. DINKEL
SALEM vm use. 336A3509AE
cnnrn~ so FL so nu 1
Figure D- 1. M Frame Hardware Drawing 336A3509 (Sheet AE)
D-S
TYPICAL SCR CELL APPLICATIEIN - 1000V
(FREINT VIEW)
ca C4 CO
@ ® @
1 (+>
o
C+)
o _
(+)
T
1
.O
1 2 R1 1 2 R5 1 2 RE
1 2 RE 1 E RE 1 2 R10
PHASE 1 PHASE a PHASE 3

SCR SCR SCR
I 1 E
2 R3 1 2 R7 1 a2 R11
I 1
o
2 R4
I
1
o
2
I
R8 1
o
2 R12
(-> (-> (->
C1 C3 C5
® @ @
1 2 R13 1 2 1 R17 1 2 R21
R14 R1B R22
R15 R19 R23
R16 1
R20 I R24
NQTE, C1-C6 & R1-R24 ARE THREE pHASE SCR SNUBBER CIRCUITS.
In
REV.1 REV.4 REV.7 PRINTS TD ENGINEER

REVS REV.5 ISSUED CDMPANY
11-08-93
DRIVE SYSTEMS DEPT.
REVS Revs MADE BY
w SALEM, VA. U s.A. 33E)A3'509AF`
DINKEL ::NNT,DN sH. FL SH. nm, 1
Figure D- 7. M Frame Hardware Drawing 336A3509 (Sheet AH

D-6
DC2000 Dig-nal Adjustable Speed Drive GEH-6005
TYPICAL REVERSING SCR BRIDGE (LEFT SIDE vlEw)

V"l""""""l"""""""""""°""""""'"'"'"'"1
l I
1 K1 (+) K2 C+) K3 (+) I
I I TYPICAL
-H 'IF
I R1 `2F '3F .
`;(
|
:> R5 RE
I
I
I
I
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R2
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(-) (-> <-) (FRONT
I
I PHASE 1 SCR PHASE 2 SCR PHASE 3 SCR
L---___-_____________________________________________ J
I vIEw
TYPICAL NON-REVERSING SCR BRIDGE (LEFT SIDE VIEW)

F-----------------------l---l-------""""""-""'"l*"-1
g I
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R12
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1 PHASE 1 SIR PHASE 2 siR PHASE 3 SIR
L_____________________________________________ J
I VIEW)
I
I '
!REVS nE\n4 REvn7 PRINTS TO ENGINEER
!
GENERAL ELECTRIC M FRA mE
REv.E REVS ISSUED CDMPANY
01-26-95
DRIVE SYSTEMS DEP1
IREV3 REV.6 MADE BY
.LA. FINCH
SALEM VA. USA. 336A3509AH
1
' 1
CUNLUN so FL SH. nu 1
Figure D- 1. M Frame Hardware Drawing 336A3509 (Sheet AH)
D-7
No tes:
D-8
.us
APPENDIX E
ELEMENTARY DIAGRAM, C OR CX FRAME DRIVE WITH DCFB BOARD
E-1. INTRODUCTION Table E- 1. C or CX Frame Drive With DCF8 Board

Elementary Diagram Sheet Summary
Figure E-1 contained in this appendix provides a sample
elementary diagram for a C or C Extension (CX) frame Sheet Description
DC2000 Digital Adjustable Speed Drive that contains a BA Ac power circuit.
DCFB board. Figure E-1 was produced from GE
drawing 246B2386AA. BB Dc output.
On the elementary diagram, internal and external wire BC CPT and CPTA connections.
numbers identify the elementary diagram sheet where
that wire odginates. For example, wire number BC01 BD Panel-mounted field supply.
.
originates O11 sheet BC, line 01
EA Control board interconnections.
NOTE
EB, EC Ac and do feedbacks (DCFB
Drive elementary diagrams may change with connecUonsL
product upgrades and revisions. The elemen-
EE SCR gating (PCCA, PCN, PCR
tary diagram contained in this appendix is
connections).
current as of the issue date of this manual.
FA Vu FD SCR bridge.
Table E-1 summarizes the contents of each page of the
elementary diagram. Table E-2 lists terminal board 2TB
connections.
E-1
Table E-2. Terminal Board 2T8 Connections,

C or CX Frame Drive vwzn DCFB Board
Terminal Description
1 Field A do ( + ) .
2 Field A do 1-1.
3 Thermal switch, 190° - optional.
5 Field ac in.
6 Field ac in.
7, 8 Not connected.
9 Voltage feedback, motor A ( + ) .
10 Voltage feedback, motor A (-).
12 Thermal switch, 170° - optional,
13 CPT 115 V ground.
14 CPT 115 v.
15 Current feedback, motor A ( + J.
16 Current feedback, motor A (-).
17 Blower switch.
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
21 Field A shunt ( + ) .
22 Field A shunt (-).
23 Voltage feedback, motor B ( + ).
24 Voltage feedback, motor B (-}.
25 Current feedback, motor B ( + ) .
26 Current feedback, motor B (-).
27 MDB coil driver.
28 MDB coil driver.
29 Field B shunt ( + ) .
30 Field B shunt (-)-
31 CPTA 115 V ground.
32 CPTA 115 v.
E-2
A B E D E F E H J K L M N P D R s
1 01 DI
D3 03
B5 05
07 07
Ac PQWFR CTRCIITT
me *an
D9 [A44] EBCDIJ 09
11
L1
FUN
Cr
KG V as ale * as
c71>¢
I I
MA
ul
PDVER
CONVERTER
_pi
- ' D a n a 8841] u
13 EA46J EBCD3] EEBE1] 13
15
LE
FUE
co Kg V ** {BD35] EBD69]
an me
MA
I. xiii 15
FDR DETAILS
17 [ A431 SEE 17
19
L3
FUN
Cl'TI
K3 l [BD37] [8D71]
be* cease
CTE!!
_1 L
MA
| .
SHEET
FA-FB .p
a
EBB27] [BB57] 19
r
I
21 [E823] 2]
\ 1::pL
23 [1EC36] as
as E5
E7 27
29 29
31 31
33 33
35 35
37 37
39 39
3 PHASE c NTRDL 0 ER (230, 460. R 575 AE)
41 41
Alex
43 EA11] 43
be ace
45 [ A151 45
47
**
L A191 47
49 BF BF 49
a 3
51 51
ETB
.r 7
53 A J I/w IICASIJ 53
BLDVER
ss 1 lJ [CA54] 55
2T:B
18
$7 57
EENTRIFUCAL sw1Tr:H
(CLOSED WHEN BLIJVER
$9 IS RUNNING) 59
61 UPTIDNAL FAPL FAPL

FAN -of -a
o
$1
63 $3
FAN 1
A
65 U 65
67 67
sos CT'S ARE PRESENT DNLY IN REVERSING DRIVES
59 * ale c NTR L PA ER MAT CDME FROM KL2.3 IF VDLTAGE ACCEPTABLE DR
MAY BE SEPAR TELY FED TD TDP r BLD ER AND CPT l:uSES
$9
71
A DEPENDS Dn RATING
71
73 Q-FRAMF
73
1 OR E MUFFIN FANS FDR CARDS (2 IF > 460V DR CEIMMDN XF)
75 1 TARZAN
75
ALL FEED FROM FAPH (DAISY CHAINED7
77 cx FRAMF 77
2 MUFFIN FANS FEED FROM FAPL
79 79
Figure E- 7. Sample Elementary Diagram, C or CX Frame Drive Vwth DCF8 Board (Sheet BA)
E,3
A 8 c D E F G H J K L M N P D R s
01 D1
03 03
05 D5
ngmnpn
07 07
MQTQR A DA1
09
PI
SH A
I D9
Fw
[8A11]
11 EEC13J 11
EECDBJ [8D20J
13
13
15
CEBEB]
_ )
MDTDR A
15
17 [EB30] 17
[BD37]
19 19
21 21
23 E3
E5 25
27
P2
as
[8A19]
E9 a
31 3
33 3
35 3
37 3
39 3
41 4
43 4
45 4 I
47 4
4g 4 I
51 5l
53 5 I
55 5 r
r
57 5
59 5a
61 6l
53 6 a
65 6 s
$7 sr
69 6a
I
71 1
73 73
75 75
77 77
79 7g
|
Figure E- 1. Sample Elementary Diagram, C or CX Frame Drive With DCFB Board (Sheet BB)
E-4
an at CPT AND CPTA CDNNECTIDNS
m [BA11] 01
* an
up [8A15] 03
05 D5
,r
07 so'
I
€'C:PTFU1
z;
§'cpTFua
,K
F CPTAFU1
J
PTNF1Ja
D7
U
U9 09
11 11
13 13
are
is * >- 15
-<( `.
I
17 17
19
21
t:p7x $10 9 7 V meals*
CPTAX "lo 9 7 T 12 19
21
B/V B/R B/Y B
23 E3
Bow B/R B/Y
n l ,
B 23DVAC 23GVAC
25 ESDVAC 23DVAC CPTA 25
CPT
27 27
29 E9
I
.LR5
|
31 1; )R~r § F ' B L / v
1 4-.SA 2
R R/Y R
...r
8 115V
'~1 4.sA
BL/W 31
/
E
,5 4 5
33 33
CPTFU3 CPTAFU3
35 35
37 6
A
1
A
4
A
5
A AA
1 2
[8E27]
as %12 ETB ETB 37
CPTPL EBE29] 31 32
:Es-wJ [BE59] [BE6lJ
39 39
41 41
43 43
45 45
47 47
49 49
51 * 460VAC CDNNEETZUNS SHDVN ABDVE

FDR 230VAC - REMDVE CDNNEETING JUMPER
51
BETWEEN 9-7. CONNECT AS FDLLDVS=
53 -
9 TD BDTTDM FUN
-
7 TO BDTTDM ru1
DN 8UTH
CPT AND CPTA.
) 53
55 55
57 57
59 59
SOOVAC CPT PIRMARY
61
Q
CONNECTIONS CPTAFUE 61
63
65
67
CPTFUI
10
T8/~r*
CPTFU2
CPT
1 CPTAFU1
IN Qii A
CPTA
63
SS
67
69 $9
*a¢cunnEcTmns TO FUL2 DPTIDNAL-DEPENDING DN VOLTAGE
71 71
***0PTIDNAL = NDT AVAILABLE QN C AND G FRAMES
73 73
75 75
77 77
79 7
Figure E-1. Sample Eiementary Diagram, C or CX Frame Drive Vwz'h DCFB Eoard (Sheet BC)
E-5
A 8 c D E F 5 H J K L M N P Q R s
01 01
03 03
05 05
PANEL MDUNTED FIELD SUPPLY
D7 07
D9 DO
11 11
13 13
15 NRP/NRX 24A 15
1FPLX
17 MFCA 17
INTERNAL EXTERNAL
EEBBBJ MQUNT MQUNT
19 (1 .
(2
<3
IR w
R
w
FPL-1
FPL-2
'w
n
P1El
p1c1
1,__E
SH I
FP TB1
19
21 FPL-3 n nam / EQ :88151 21

(4 '75
'15 R
FPL-4 n NECI
4 w
$ I
23 e55 *.nR
5 FPL-5 D P251 I
I 23
( P FPL-6 n P2C1 1
A w
25
(7
Q
9
l= R
FPL-7
FPL-8
">
H
N]G1
NICI I
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27
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PIG
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0UTFUT
E9
31
I
/
/
33 .r 33
ETB FU2
** 5 AC INPUT I/
/I
35 [BA15] u.& 35
*x aT FU3 VDLTS I/
37 [BA19] 5 rr-r EDUVAC /I FN ETB2
u EBBEDJ 37
MAX /I
R +
39 zs8sas SP ,f 39
SHUNT FBI
w
41 [EB65] SN 41
43 I 43
45 45
47 PANEL MDUNTED r1ELD SUPPLY BEEE* 47

(FDR SECOND MDTDR VHEN USED)
49 49
NRP/NRX 24A
2FPLX
51 51
MFCB
INTERNAL EXTERNAL
EXTERNAL
53 [EB44] UHUNT MEMRI
MDLJNI 53
55
i1:
(E-
IRww FPL-l
FPL-E
FPL-E
Fr~
nq
P1G1
P1C1
II »»'2
SH
SH
FP
55
<3. __2
I
FPL-3
FPL-3 H
f\ N251
N251 [8844]
so <4 J' R
A w_ FPL-4
FPL-4 P n28I
NEC] // 57
1 (5 /
w
'r R
'r FPL-5 D P251 //
//
6 R II
59
(7 x. Ww
.u FPL'6 w pain
')P251 II
ff 59
<
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FPL-7 \\
N]G1
//
II
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FPL-9 FA n1c1
n1c1 // 61
II
63
*E PIG
PIC
II
//
//
63
1] //
DC
NIU .f
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// DUTPUT
65 NIE
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//
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67 // 6
//
ff
FU2 l// s
69 ** AC INPUT //
I
[BA15] H'n
fl"1l
FU3 VDLTS
VDLTS ifif
71 ** FN
7
[BA19] EID-
D - SDDVAC
SDDVAC /I
/I [8B49]
73 MAX /
/ 7
/
/
EEB67] +
+ Sp
SP /
/
/
/
75 SHUNT
SHUNT FBK 7
[EBSQ] SN
77 7
79 7
aleaceaae DPTIDNAL Alex : FIELDS SUPPLY PDVER FROM K1.K2 IF VDLTAGE ACCEPTABLE
Figure E- 1. Sample Elementary Diagram, C or CX Frame Drive With DCF8 Board (Sheet BD)
E-6
A B c D E F G H J K L M N P Q R s
01 01
03 D3
0 ave are *
D5
SPCA
as ale * SLCC ale ** AREPL DR DLAN
D5
D7 Cl 07
10PL
D9 09
C
2PL
11 11
|
13 7PL 3PL
13
15
17
. 15
17
19 19
3PL
I SDCC
21
23
IMETERS auealeals
MET1
A
IIPLX A
A 7PL
A.
DCFB
DR
SDCI
21
23
U Le 11PL4
METER 1
SPL
25 as
1\\,
E7 MET2 A
5 11P
11PL5 E7
(\ << L5 METER E 1PL
29 29
2 ¢
~».\
"\
31 MET3
6
S l1PLS
A 31
LJ x( METER 3
33 33
s
3/(
35 MET4
A. 35
.
7 2PL
2PL
C/ \\( 11PL7
11PL7
METER 4 ii
37
l 8
\.(
11PL8
CUM
£5 37
39
39
1 » 4PL TCPL
41 BPL SPL
41
43 43
lI
ETB3E-(VITH CPTA>
45 2TB14-CND CPTA) 45
7[BC37]
4 2TB31-(WITH CPTA) 47
ETB13-(ND CPTA)
49
o _:pn CPH BPL 1OPL SPL 6PL 49
51 RTBA ** * LTB *** 3TB 4PL

51
DR
RPL DPTPL STBA
53
53
55 55
57
$7
ZPL II
59 59
61 so
63 63
PTCT BEBE TCCB x x
65 65
2PL
E] JKK
$7 67
TCPL
69 69
3PL
71 71
73 73
0 USED DNLY UN SLCC EI.
75
A USED QNLY DN SDCC G1 75
77 E PANEL MDUNTED
as *
77
Exaouo DNLY
79 ale ans * u 0PT]0NAL 79
Figure €- 1. Sample Elementary Diagram, C or CX Frame Drive Mtn DCFB Board (Sheet EA]
E-7
- s
A 8 c D E F G H J K L M N P U R
Of D1
Ar: s. nr, FrrUBAC1<S
03 D3
05 DCFB DS
TCPL
D7 V1-V2 07
V1 swf 1pL-11
[FA,B,3D] VCD v
DO DO
V2
[FA.B,36]
11 JP1 1:
V3 via-va 3 oTCPL
[FA,B,4D]
13 SV2 SYNC 2 oIPL-29 13
u1
15 15
TCPL
17 V1-V3 17
sw3 IPL-12
VCD I.
19 19
l
21 21
P1A Pa-PE 1pL~13
[BA13]
23 sw4 VCD E3
P2A 1PL-37
EBAEIJ
25 'l' QTP37 25
as 2T:B VMIA-B 27
9 VM1A sis IP--39
[8815] VCD
.B
29 I VMIB 29
E88191 L..
31 ETB 31
E3 MEA VMEA-IB ANAL E 1PL-D6
[8844]
33 E B SVS 33
4 VMEB
[8848] |-
35
'r MA-Cn~TA=:TS 35
37 NC 37
NRP FPL
9 [BIJ19]
1PL-19 #1
39 IC 39
FIRING NRX PPLL2
[NC]
41
FIRING V
IN 41
NPLL2
[NC]
43 ENC 43
NRP arpL
EBD54]
1PL-18 #E
45 EC 45
FIRING 4PL-3,45
KG
47
1PL-34
K1
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U
49 -| .CNPL°1 49
51
53
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$3
2 + R
55 r I
1; £35221 55
MACPL RTB
1pL-36 3 _ w 2B
57 L
in
CBES5] 57
K1 MACPL 2T B
(P24V3 4 + IR
59 c
[BES3] 59
't v
$1 5;
ETB
1 R IFIPL-1
#1 SHUNT r:
63 EBD40] 2 1PL-9 63
E1 B VCD
65 [8D41] I' a w IFIPL-E

65
ETB 'T
' 9 R IFEPL-1 #2 SHUNT VCD
67 [BD75] a $7
21 8 1pL-40
D V IFEPL-2 VCD
69 [BD76] 69
al*
71 71
r
`-.J CEINT. DN SHEET EC
73 73
75 7s
77 77
I
79 * * ale DPTEMAL 79
I
I
Figure E- 1. Sample Elementary Diagram, C or CX Frame Drive Vwth DCFB Board (Sheet EB)
E-8
i A B c D E F G H J K L M N P 1: R s
DO 01
DO Das
CONT. pROM SHEET EB 03
05 05
,r-. JP5
it I Q
07 2TB JP3
R 1A1pL-1 07
rs81s1'§'
D9 I
DO
vM
.| IPL-DB
ISEIL
11
2 s
13 [8314]]L§
27s
w IA1PL-2
JP4
JPG I _é
a_:
FE
I I 11
13
15 JP6
15
17
17
JP10
19 ETB JPB
19
R IAEPL-1
A ,
7
21
188451-§ 9
TT
it P
L ISDL
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s "§
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23
as
25
2TB
[BB4-3]al5
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T JP9
é
g n
l
JP12 I .R
5_I
4
as
27 JP11
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29
1PL I FVD
REV 5PL 29
I
31
33
l GPA
31
33
35 ACCT
IEPL CURRENT ANAL G IPL-1 35
[BA23] FEEDBAEK
37 AT7EN.
I so 37
39
CPTPL 39
[BA38]
7A FU2 SQPL
41
43
-
-m- u
"
7A FU3
II CRawl
CR55
"II 41
43
45 +sv (TP .. p5>

+15V (TP - p15>
45
47 -15v (TP N15)
47
+24V (7P FU2)
49 -24v (TP FUN)
49
51
51
53
53
55
55
57
57
59
59
61
$1
63
63
65 LT1
65
LJ
67 FU1
67
m
69 0.5A FAPL-2
FAPL-1 69
115
71 VAL: 71
73
73
75
75
77
77
79
79
Figure E- 1. Sample Elementary Diagram, C or CX Frame Drive With DCF8 Board (Sheet EC)
E-9
I A B c D E F G H J K L M N P 0 R s I
D1 D1
03 03
05 O5
07 07
DO 09
11 11
13 13
15 15
17 17
19 19
21 PCC 21
(PCCA)
23 P1A
* P15 PI E3
REMUVE JUMPERS we
25 p1A-p13 PEA PEB P2 25
P2A-PEB :
27 27
E9 29
I
1FPL'2 w l:F__ED]
31 SCR IF 31
1FPL-1 R
- [F_18J
33 33
_2FPL-2_W
[F_20]
35 SCR 2F
BFPL-LR T
I |.
cF_183
35
37 37
3FPL-2 w [F__ED]
r l
39 SER 3F 39
3FPL-1 R
F RVARD [F_1BII
4]
I
s
I 'I 41
GATE PULSE 4rpL-2 I w
TRANSFORMERS [F_ 46]
43 SCR 4F 43
4FPL'1 R
[F_44]
45 45
5FpL-2 w [F_46]
47
49
[1EC3D}
SPL
SCR 5F
5FPL'llR
6rpL-2'v
i w
[F_44]
IF_46]
47
49
51 SCE Si '51
6FPL"1 R
'l {F_443
53
T 53
1RPL~a . w
*4.5 [FB50J
55 SCR OR 55
1RPL-J R
[FB52]
57 57
ERPL-EIn
[FB50J
59 SCR ER
ERPL-1IR T
A IFB5E]
59
$1 61
3RpL-2 w LFBSDJ
l
63 * BE as
REVERSE
SCR 3R
3RPL-1 IR [FB52]
so
65 < 65
GATE PULSE 4RpL-2 w
TRANSFIJRMERS [FB24]
$7 SCR 4R 67
4RpL-R
I [FB26]
69 69
SRPL-2 V
[FBE4]
71 SCR SR 71
5RpL-1IR A
[FB26]
73
ERPL-2 Iw [FBE4]
73
SCR SR 75
6RpL-1IR
h. [FB26]
77 77
I
79 79
Alex * DPTIDNAL
Figure E- 7. Sample Elementary Diagram, C or CX Frame Drive Vwth DCFB Board (Sheet EE)
E-10
f . . . . " . . . _ . . ¢ . _ ._..
A 8 c D E F 5 H J K L M N P Q R S
01 SIR BRTTIGF
SOOVAC MAXIMUM
0x I
NGN REVERSING
03 03
D5 D5
PI
»
07 07
D9 D9
11 11
13 13
15 15
17 17
R R
[EE32] 1P [E[36]R 1 [EE40]
19
21
[EE3D]
V
SCR
IF
*V 5.551
I
I
PIA
I
[££34]V SCR
BF
: g
E-QQ!
1555
Lassen ' SCR
3F
I
*r:aaa
I
LTE2QI
I
|
19
21
E3
J
I oegj
|-
Lt=lAcs
IACS 13Ar:S 23
25 39 l39 ]39 25
40w 1 40w how
.. Tm TEA T3A
27 E7
I
|
29
&'ieE'iTe9
31 L I
[EBDB]
: II
!_0_.a8~_ _£31
33
35 AC INPUT
p ER
A
4
4
DC
UTPUT
P WER DES 1 33
35
I
37 500
L* 3T
[END]
39
1 I
40w
39
[EBLEJ
4] II 41
43
[EE44 ] R or ,runs
[EE4B] R 1I
TEB
[EES2] R
T38
43
45
w 39 'as Las 45
[EEG 40W [EE46] w 40V l
40w
SCR SCR [EE5D]' SCR
47 4F 4ACS :5ncs
3 SF B* 'ISACS
1
to 47
49
* v E.5§
:I ceq:
a161'1055]
I 1
* :-I0.2§;
I I
I 1 I I 49
51
I
L10-2Q LIE 51
PaA
5:3 n
53
55 55
57 57
59 59
61 61
63 FU4
63
PE
v LLJ:
65 ss
67 u~. HIGH TEMPERATURE ALARM
I c170~F:~ (OPENS N ALARM) 67
TgV***
69 69
ETB 2TB
11 12
71 71
THYRIST 2 HEA7 SINK
73 THERMAL SWITCH
73
i HILSH TEMPERATURE TRIP
75
77
I
ETB
T$*V3E?FilE
l
2TB
(19D°F> (OPENS N TRIP)
75
3 4 77
79 * LIJCATED N PCCA CARD
* DPT] NAL
79
I
Figure E- 7. Sample Elementary Diagram, C or CX Frame Drive vwth DCFB Board (Sheet FA)
E-11
Of VAR RR1T1G*' 01
EODVAC MAXIMUM
REVERSING
as 03
05 05
PI
9 iv
07 D7
D9 go
11 11
13 13
15 15
L
I I-
17 17
R r R
[EE32] R A 11 [EE36] I r [EE4DJA \
lr
19 PIA *I"'E.§5 *'IE.5é1 19
E1
[ E E 3 D ] \ SIR
_SIF
gCR*I
4R
--
0.25
g
[EE34]
w
.52F
SCR SCR I
5R I
I
I u egg
I
I [EE3B]
w
SCR
3F
SCR I
BR IL
I
I E§§
I
I
E1
/ / /
I|. 0.221
--.J
as
w 1A s w
ZACS
V
BACS as
[EE66] A C [EE70] [EE74]
25
EEEGBJ
R 4 D
39
40V EEE72]
R 1»
39
40W [EE76]
R in
39
40w
25
A, 1 T1A TEA TSA

27 27
29
31 lHv,
1
\
[EBDB]
[EDDBJ
DC
=
*lola§'11a9
1n.aa _..g 31 I_:

33
1
EUTPUT
1
DCS 33
|
poWER
I
35 AC INPUT 4
35
PCNER
EEBIDJ
37 if(¢f\ 50D j 37
4DV
39 39
EEBIEJ
41 5,van 41
8<
43 TIB TaB T38 43
R R
4 >- 6
I
EEE44] R [EE483 9 [EE52]
45
lEE42]
v I
M
A
1
SCR SCR
1R
-. 1R
39
40V [EE46] w
4ACS
SCR SCR
ER
39
40w
5Acs
EEE50]
w
SCR
I SCR
39
40w
SACS
45
47 4F :L 5F 6F 47
I
T
I
1-
*r
*a *TI I'I 0.253I
/ 1
0.E21
/ I
0_2 be
49
[EE54]
w
I
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L"::22§2
I 1 I
I
[EESB]
W I
I 0.2a1}
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I
[EE62]
w 1 I 49
I
|. L L20.233
51 51
R R
PEA [EE60] rEEs41 *L
I
R lb
[EE56] :> v
53 53
55 55
57 57
$9 59
61 61
63 FU4 63
l. Ur ITT
.pa
I
ss S
57 .ac HIGH TEMPERATURE ALARM 6

I Tsv *DE* <1v0°F) (DPENS DN ALARM)
69 6 I
ETB ETB
11 12
71 7
THYRISTDR HEAT SINK
73 THERMAL SWITCH 7
HIGH TEMPERATURE TRIP
75 Tsv * me * c19o~F> CDPENS DN TRIP)
7
2TB OTB
77 3 4 7
79
***if LDCATED DN PCCA CARD
DPTIGNAL
7
Figure E- 7. Sample Elementary Diagram, C or CX Frame Drive vwrn DCF8 Board (Sheet F8)
E-12
A 8 c D E F G H J K L M N P D R S
I 01 SCP nnrpnr WTTH 1P1PNP eARn

46DVAC WITH SEPERATE TRANSFORMER D1
NON REVERSING
03 03
D5
05
s 9
PI
07 I
07
09
D9
11
11
13
13
15 V 15
17
R R R 17
[EE32J A lr
[EE36] 1 .I
* r - ..-- .----\|
- -
\.-I~1vJ
\.»I~1vJ
1 ; - ;
f . ;l
f
19 P1A
I x * vI "1 19
cas3onw "1 I I
[E[34]V
T"
SCR SCR [EE3B:IV
[EE3BJW I
I I SCR I I
21 ' =1r»' I
I
I
I 5 2F l-'U.1 II 3F I I 21
I I I I
I 0.1 I I I
I I I I
23 I I
I I I I
I
I I I I E3
L
I I I
I 40 | I I
25
27
. T1A Mi:
I
L
10w I
_-.|
I
TEA aim:
|
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4D I
Wall
. . - . |
I
T3A
Li
3AC
r
1
L.
40 I
10wl
.|
25
1
27
I
29
tsnoen
*r'"
I
129
I
31 1 ' In I
I 0.1
I
131
DC I
I I
33 OUTPUT I
4
\
PDWER I Isa
35 AC INPUT
PDVER
4
4
I
I
I
I
:
135
I I
37 I I
EEB1D] 1500 I37
IIUV I
39
s 1 1
0 L___-J
\
I 39
[2-:81a]
[2-:me]
41 L 1
I
41
43
[EE44] R II
T18 SAC
r' " 1
» R
:z:4eJR .:
,I
TEB 5AC
u r' ___, [easel
R
9
T38 SAC
r*
43
45
[EE42]
V
I
I 40 :
10M/I [EE46]
v : 40 I w
r
I
I
40 I
10V I
-1
45
47 |-
SCR
OF
I
I
l
I
I = . SCR
5F
*:
I
I
lDVI
I
[EE50] SCR
_S SF
I
I
I
I 47
I
*
1.
*I 0.1 I D.I I
I
I 0.1 I
I
I I I I
49 I I I 1
I I
I I I I 49
I I I I
L ..__| L ___|
$1 L --J
$1
PEA
53 lu
53
55
55
57
57
$9
59
61
61
63 FUN
PE
63
D JY
65
$5
67 ii! HIGH TEMPERATURE ALARM

Tsw
T $V*** *** (170°F) cnpEns un ALARM) 67
69
ETB ETB 69
1: L2
71
71
THYRISTDR HEAT SINK
73 THERMAL SVITCH
73
75 Tow*asale r190~F> (DPENS UN TRIP)
75
2T8 ETB
77
3 4 77
79 as Le::ATen UN 1a1pcR CARD
*** DPTIDNAL 79
Figure E- 1- Sample Elementary Diagram, C or CX Frame Drive Vwth DCF8 Board (Sheet FC)
E-13
A 8 C D E F G H J K L FE N P Q R s
SER BRIDGE WITH LELPCP CARD D1

D1
46DVAC WITH SEPERATE TRANSFORMER
REVERSING
03 03
OS D5
n
PI
Q
D7 07
09 D9
11 11
13 13
15 9 D l 15
17 17
R P1A R R
11 1» r * 'I R
[EE4D] s
[EE32] L
I [EE361
19 19
w r"---» w sc:R
r"--"1 w r' """'|
[EE3D] SIR SCR I I [EE34] SCR 1 I [EE3B] SCR SCR I I
21 NF 4R rl I
l
.,_ g EF SR : ' - , 0.1 1I 5 3F OR I I
0.1 II 21
..0.1 I
* * I I
/ /
1 I
/
I
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as w l I
w I I
wA l I 23
I I I I LEE741 I I
[EE66] [EE7D] 40
as
EEEBBI
R T I I
| .
I
LE
I
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R
IP
I
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4D
kw
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|
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R
n LJ
I
I
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IDV :
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25
27
of T1A IAC T2A EAC T3A 3AC 27
1
* f - - - - ' 129
29 1
I
canoes I I
31 L |
I I
I
1 0.1 71 31
I
DC l I
I I
I
DUTPUT 1 133
33 I PDWER I 1
1
I I
I I
35 AC INPUT | 135
POWER I I
EE810]
37 L I r | I 'see
I
' I3
I
1
1.
|
L1P!_.'] 7
39 39
{E8l2]
41 l 41
43
45
[EE44] R
T
*x w
T1B
n
aAC
LJ r '
I
I
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4D I
now I
I
rsz4sJ
R
Il »
Tas SAE
LJ r
:
-_-I
40 I
I
XDV I
[EE5E]
Lzzsm
R
w
3 T38 SAC
I'
I
I
--'\
40 I
my:
43
45
47
[EE421 SCR
4F
SIR
IR
|
I
I I
I
CEE46JW
5
SCR
5F
SCR
ER
I
g I
l
_ SCR
S 6F
SCR
ER |
I
I
47
ale
*1I *I
/
*|
/ I
D.1 I 1
/ I
D.1 I
I I I I I I
49 I I1 I I I I 49
w I I w I I w I I
[EE54] [EE5B] [EE6El
T I
L.---J L .......J L --.I
51 51
53 rcsssn R
+ > pammII
PaA
masse:
[EE60]
R Il r [EEB4]
R
in
53
55 55
57 57
59 59
61 B
Fu4 6
63 PE
In v 1'l-12
65 6
67 #p
HIGH TEMPERATURE ALARM s
Tsw *ass* (170°FJ (DPENS UN ALARM:
69 6
ETB ETB
11 12
71 7
THYRISTDR HEAT SINK
73 THERMAL SVITCH 7
75 rslw *** (190'F> (OPENS DN TR1P>

7
ETB 2TB
77 3 4 7
79 * LOCATED DN 1zlpcR CARD

*ave* DPTIDNAL
7
Figure E- 1. Sample Elementary Diagram, C or CX Frame Drive With DCFB Board (Sheet FD)
E-14
_jll:_;..d.
( APPENDIX F
ELEMENTARY DIAGRAM, C OR CX FRAME DRIVE WITH SDCI BOARD
F-1. INTRODUCTION Table F- 1. C or CX Frame Drive worn SDC/ Board

E/emenraw Diagram Sheet Summary
Figure F-1 contained 'm this appendix provides a sample
elementary diagram for a C or C Extension (CX) frame Sheet Description
DC2000 Digital Adjustable Speed Drive that contains BA Ac power circuit.
an SDCI board. Figure F-1 was produced from GE
drawing 246B2386AB. BB Dc output.
that wire originates. For example, wire number BCO1 BD Panel-mounted field supply.
originates 011 sheet BC, line 01.
BE Internal core-mounted field supply
NOTE (on SDC|)-
Drive elementary diagrams may Mange with EA Control board interconnections.

EB, EC Ac and do feedbacks (SDCI
connections).
EE SCR gating (PCCA, PCN, PCR
Table F-1 summarizes the contents of each page of the connections).
elementary diagram. Table F-2 lists terminal board 2TB FA . - FD SCR bridge.
connections.
F-1
Table F-2. Terminal Board 2TB Connections,

C or CX Frame Drive with SDC/ Board
I
2 Field A do (-).
5 Field ac in.
6 Field ac in.
7, 8 Not connected.
9 Voltage feedback, motor A ( + ).
10 Voltage feedback, motor A 1-1.
t2 Thermal switch, 170° - optional.
14 CPT 115 v.
15 Current feedback, motor A ( + ) .
17 Blower switch.
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
F-2
A 8 c D E F G H J K L M N p D R s
D1 D1
D3 03
D5 D5
07 D7
09
Al: pgwgn r::a;u1T *
ale
[A44]
ass*
EBCDIJ DO
11
L1
FUI
_
»- .- K1 I cT ale MA
PDVER
PDVER Pl
CBB11] 11
L
J
CDNVERTER
me *ale
J
CDNVERTER
13
15
LE
FU2
= 11
KG n [A46]
**
[BC03]
[8D35] EBF35]
BEBE
MA
|| :: EW
13
15
FDR DETAILS
17 E A48] SEE 17
19
L3
FU3
|
K3 I EBD37J EBF37J gTg*
** * * MA
I
I.
SHEET
FA-FD pa
[BB27] 19
J L
21 21
v \ CPL
23 [EB70] 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
3 PHASE CDNTRDL PDWER (eau, 460, DR 575 VAN)
41 41
43
* an
[All]
in* 1 •
43
45
47
[AIS]
**
E A191 w I
45
47
49 BF BF I BF 49
?
1 2 3
51 $1
ETB
7
A L;
53 lu [CA51] 53
B-DVER
55 1 r. Q [CA54] 55
2TB
57
18
CENTRIFUCAL SWITCH
57
(CLOSED WHEn BLOWER
59 IS RUNNING) 59
61 DPTIDNAL FAPL FAPL

$1
FAN -1 -2
63 A 63
FAN 1
65 U ss
67
* CT's ARE PRESENT ONLY IN REVERSING DRIVES
$7
69 as at gDNTRUL PDVER MAY EDME FRDM K1.2.3 IF VOLTAGE ACCEPTABLE DR

69
MAY BE SEPARATELY FED TO TDP DF BLOWER AND CPT FUSES
71
A DEPENDS DN RATING
71
73 Q-FRAM;
73
1 DR 2 MUFFIN FANS FDR CARDS ( 2 IF > 46DV DR CDMMDN xF>
75 1 TARZAN
7:
ALL FEED FROM FAPH (DAISY CHAINED)
77 CX FRAMF
77
E MUFFIN FANS FEED FRDm FAPH
79 79
Figure F- 7. Sample Elementary Diagram, C or CX Frame Drive With SDC/ Board (Sheet BA)
F-3
D1
D1
D3 D3
05 05
UG QIJTPIJT
07 07
.
»4nTqR A
DAY
DO SH A 09
w:~+
PI
[BA111
11
13
L I *J
4
[EB55]
[EB53]
[BD20]
[BF203 @
11
13
E* J MUTDR A
15 c, 15
1* 3
17 17
[8037:
[BF37] @ 19
19
21 21
23 E3
25 25
E be]
27
29
caA1sJ
P2 V as
Z9
31 31
33 33
35 35
37 37
39 39
41 41
43 43
45 45
47 47
49 49
51 51
$3 53
55 55
57 57
59 59
51 61
63 6
$5 6
67 6
69 6
71 7
73 7
75 7
Q FDR INTERNAL 10A SUPPLY DN SDC!
77 * 2TB9 AND 2TB1D ARE VIREO TD PLPE UR MDTDR ARMATURE PER INSTRUMENTATIDN 7
REQUIREMENTS EXCEPT IF PCCA 121 AND/DR 122 CARD IS USED
79 7
xxx DPTIDNAL
Figure F- 1. Sample Elementary Diagram, C or CX Frame Drive win SDC/ Board (Sheet BE)
F-4
A 8 c D E -r G H J K L H N P D R S
we me CPT AND CPTA C NNECTI NS
D1 umm 01
D3
* BE
{BA151 D3
DS 05
I
07 .L L z z D7
CPTFU1 I :CPTFU2 CPTAFU1 CPTAFU2
a'
09 D9
11 11
13 13
*
15 * 15
-<<->
17 17
*xsane
19 CPTAXvIO '7 me 19
CPTX Vw v9 'r
'J 12
21 21
23 B/Y ;B
23
8/V B/R IB/Y B 23DVAC 230VAC
a3ovAI: CPTA
as CPT
230VAC 25
27 E7
29 29
R Y or
I' i
L;
I
31 (
-J- ,.v-
.ii 2.2: £5- R R/Y R is 115V
4.6A
l:BL/W 31
s 4 5
1 AS
33 33 I
CPTFU3 ]CPTAFU3
35 35
i
37 6
A A
4
A
5
A A
1 2
is"
[BE27]
in"
rseesn aTe ETB 37
EPTPL 31 32
[EC40]
39 39
41 41
43 43
45 45
47 47
49 49
$1
FDR 230 AC _
460 AC c N ECTIDNS SHE N ABU E
REM E C NNEETING JUMPER
BET EEN 9-7. c NNECT AS F LLO S:
51
53 --
9 TO B TT M run
7 1 BDTTDM FU1
E B TH
CPT AND CPTA.
$3
55 ss '
57 57 I
59 59
SODVAC CPT PIRMARY
$1 CDNNECTIDNS $1
CPTAFUE
63
SS
$7
CPTFUI n CPTFU2
CPT
CPTAFUI
I CP7A
63
65
67
69 69
3E*CBNNECT] NS T FULL DPTI NAL-DEPENDING N v LTAGE
71 71
9E**0PTIDNAL = NDT AVAILABLE GN c AND G FRAMES
73 73
75 75
77 77
79 79
Figure F-1. Sample Elementary Diagram, C or CX Frame Drive mm SDC/ Board (Sheet BC)
F-S
Of D1
03 03
D5 D5
PANEL MDUNTED FIELD SUPPLY *BEBE
07 07
(MAY HAVE A 10A INTERNAL SUPPLY SEE SH. DIBPD
DO
11
13
15
NRX 24A
IFPLX MFCA
17 INTERNAL EXTERNAL 17
Mr;UNT MDUNT
19 EEBE9] rPL-1 n P1G1
£2 I 19
2]
.,3
-<1
FPL-2
FPL-3
n P1C1
n N251
SH
1w 2 . FP ETB]
r\ [:BBl5] 21
-*u\ . FPL-4 n nacl /
5 /
23 r-re6; I FPL-5 D P251 /
/
I E3
: I FPL-6 D p2:1
I
f
I
25 . 17' FPL-7 I
D N1G1 E5
Val | /
FPL-B D I
27
i"",9
*E w1 PIG
N1C1
/
f
\ I U D II
R I
E7
PIC I
l ,gm all
w /'
DC
29
"IR
\. L1 NIE / 29
I »-.H NIC I
I
l]UTPUT
31
is r
I 31
I
f'
I
/
33 / 33
35
**
[BA153
RTB
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53
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57
59
61
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65
67
69
71
73
75
77
79
PT] NAL an = FIELDS SUPPLY PDVER FR M KLK2 IF DLTAGE ACCEPTABLE
Figure F- 1. Sample E/emen tary Diagram, C or CX Frame Drive With SDC/ Board (Sheet BD)
F-6
A B c D E F G H J K L M N P 0 R S
01 D1
03 D3
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INTERNAL CDRE MDUNTED FIELD SUPPLY aneaueaoe
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57
57
59
59
61
61
63
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67
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69
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75
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Figure F- 1. Sample Elementary Diagram, C or CX Frame Drive With SDC/ Board (Sheet BH
F-7
Dl 01
03 03
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75 75
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79 as BE l
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Figure F- 1. Sample Elementary Diagram, C or CX Frame Drive Vwth SDC/ Board (Sheet EA)
F-8
A 8 c D E F G H J K L M N P 0 R S
D1 DO
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Figure F- 1. Sample Elementary Diagram, C or CX Frame Drive with SDC/ Board (Sheet EB)
F-9
I
01
D1
SDCI 03
D3 CONT. FR M PRE SHEET
05
DO r=
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63 63
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71 71
73 73
75 75
77 77
79 79
Figure F- 7. Sample Elementary Diagram, C or CX Frame Drive lmz'h SDC/ Board (Sheet EC)
F-10
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Figure F-1. Sample Elementary Diagram, C or CX Frame Drive Vwth SDC/ Board (Sheet EE)
F-11
A B c D E F G H J K L M N P D R S
D1 SCR BRIDGE WITH PCBA gAps 01

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F-12
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Figure F- 1. Sample Elementary Diagram, C or CX Frame Drive wfm SDC/ Board (Sheet F8)
F-13
D1 SIR BRIDGE WITH lplpf:la r:ARD 01

460VAC WITH SEPERATE TRANSFDRMER
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Figure F- 7. Sample Elementary Diagram, C or CX Frame Drive With SDC/ Board (Sheet FC/
F-14
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Figure F- 7. Sample Elementary Diagram, C or CX Frame Drive VW:/1 SDC/ Eoard /Sheet FD)
F-15
Notes:
F-16
APPENDIX G
ELEMENTARY DIAGRAM, G FRAME DRIVE WITH DCFB BOARD
G-1. INTRODUCTION Table G- 7. G Frame Drive With DCF8 Board

Figure G-1 contained in this appendix provides a sample
elementary diagram for a G frame DC2000 Digital Sheet Description
Adjustable Speed Drive that contains a DCFB board. BA Ac power circuit.
Figure G-1 was produced from GE drawing
246B2387AA. BB Dc output.
on the elementary diagram, internal and external wire BC CPT and CPTA connections.
that wire originates. For example, wire number BC01 BD Panel-mounted field supply.
BE Contactor drivers.
NOTE
Drive elementary diagrams may change with
EB, EC Ac and do feedbacks
(DCFB connections).
current as of the issue date of this manual. EE SCR gating (PCCA, PCN, PCR
connections).
Table G-1 summarizes the contents of each page of the
elementary diagram. Table G-2 lists terminal board 2TB FA - FD SCR bridge.
connections •
-.-a-H"
G-1
Table G-2. Terminal Board 2TB Connections,

G Frame Drive With DCFB Board
2 Field A do (-).
3 Thermal switch, 'l 90°
4- Thermal switch, 190°
5 Field ac in.
6 Field ac in.
7 Field ac in.
8 not connected.
9 Voltage feedback, motor A ( + l.
14 CPT 115 v.
15 Current feedback, motor A ( + ).
17 Blower switch.
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
21 Field A shunt ( + ).
23 Voltage feedback, motor B ( + ) .
24 Voltage feedback, motor B (-).
25 Current feedback, motor B ( + ) .
26 Current feedback, motor B (-).
27 MDB coil driver.
28 MDB coil driver.
30 Field B shunt (-).
31 CPTA 115 v ground.
32 CPTA 115 v.
33 CPTPLP24 - optional.
34 CPTPLN24 - optional.
35 CPTPLCOMM - optional.
G-2
A 8 c D E F G H J K L M N P Q R s
01 D1
03 03
05 os
07 07
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Ar: przvgn l¢1R:uu
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11
L
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CONVERTER
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13 l EBCDBI [EB21] 13
15
L2 o f
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AL.» KG 1 [8D35] [8D69]
X* *Ne
MA
| |
15
I FDR DETAILS
17
I
[BD37J [8D71]
I
I
I
FU3
K3
as* * be ocTane MA
\ .
SEE
SHEET
P2
17
19 L3 t o ¢*1: # v i
l; FA-FB [BBE7] [BB57] 19
21
J L
J"""IL i |
L [E823l E1
\ ICPL
E3 [1EC36] 23
as 25
27 27
29 29
31 31
33 33
35 35
37 37
39 3g
41 41
43 43
45 4-5
47 47
49 4-9
51 51
53 $3
55 55
$7 DPTIDNAL FAPL FAPL 57

FAN
$9 59
***
FAN 1
61 U 61
63 63
65 65
67 67
69 69
71 ale cr's ARE PRESENT DNLY IN REVERSING DRIVES 71

xx CDNTRGL PDWER MAY COME FRDM L1.a3 IF VDLTAGE ACCEPTABLE
73 DTHERVISE WILL BE SEPARATELY FED TD TDP up BLOl»/ER AND CPT FUSES 73
an ** UPTIDNAL
75 75
77 77
79 7
Figure G- 1. Sample E/ementary Diagram, G Frame Drive with DCF8 Board (Sheet BA;
G-3
G.
A 8 c D E F H J K L M N P Q R S
01 01
03 03
05 D5
nr: UIJTPUT
07 07
MUTUR A
DO SH A MDA Alex D9
P
:BAI1J 1 q
UP
1] EEC13J [8E16] 11
:Eco8J EBD203
13 [EBEB] 13
_MDT0R A
15 -J 15
17 EEBSDJ 17
[8n37]
19 19
E1 21
23 E3
25 as
E7 27
pa
[BA19]
29 E9
31 31
33 33
35 35
37 37
MIITDR B
-JE **
FXTFRNAL To r:QRF_
39 39
SH 8 MDB anus
P1 v
4] [BA11] in 41
[ECE5] EBE49]
43 [R [8D55] 43
[EC20]
[EB32]
45 MDTDR B 45
47 47
[E834]
49 [8D72] 49
$1 51
53 53
55 55
57 57
P2
59 E8A19] 59
61 61
63 63
65 65
67 67
69 69
71 71
73 73
75 75
77 77
aus* = DPTIDNAL DC CDNTACTDR MDUNTED [N PANEL
79
*** = OPTIDNAL
7
I-7gure G- 1. Sample Elementary Diagram, G Frame Drive Vwth DCF8 Board (Sheet BB)
G-4
A B c D E F G H J K L M N P D R s
01
**
[BALI]
CPT AND CPTA CDNNECTIDNS
01
* we
[BA15]
D3 03
05 05
D7 . ».
1
I 113-
CPTFU2 EPTAFU\ jupCPTAI'-'UE D7
09
v CPTFU1
D9
11 11
13 13
al(-
15 e->>- 15
17
V
17
***
19
CPT *'10 9 l, CPTA "up 9 v7 " 1a 19
21
as I 8/v
23DVAC
B/R B/Y
E30VAC
8
B/W
E30VAC
B/R B/Y
EGOVAC
B
21
23
25 as
CPT CPTA
as E7
29 29
1.
Y I |
R
. l
31 AR/Y
4 in
*s 115V BL/W R/Y R or 8 115V BL/V
4.6A 2 31
A ] 4.6A AS
33
6 4 5
33
CPTFU3 CPTAFU3
35 | 35
37 6
A A
4
A
5
A AA
11 2
go8 ETB
14 2TB ETB 37
CPTPL [BE27] [BE29J 31 32
[EC40] [BES9] EBE61]
39 39
41 41
43 43
45 45
47 47
49 49
51 * 460VAC CUnNECTIDNS SHDVN ABOVE

FDR 23DVAC -
REMDVE CDNNECTING JUMPER
51
BETWEEN 9-7. CDNNECT AS F'DLLDVS=
53 -
9 TO 8gTTOM FU2 DN BDTH 53
-
7 TD BDTTDM FU1 CPT AND CPTA.
55 55
57 $7
59 $9
CPT PIRMARY
AC
61 CONNECTIONS 61
Q
3600V
CPT CPT CPTA CPTA

63 FU1 rua FU1 run 63
12
65
A
T» ss
67 CPT CPTA 67
69 69
**¢DNNECT1DNg TD FUL2 DPTIDNAL-DEPENDING DN VOLTAGE
71 71
ale ale ale upTIunAL = NDT AVAILABLE DN c AND G FRAMES
73 73
75 75
77 77
79 79
Figure G- 7. Sample Elementary Diagram, G Frame Drive With DCFB Board (Sheet BC)
G-5
D1 D1
03 03
05 05
PANEL MOUNTED FIELD SUPPLY
07 07
go D9
11 11
13 13
15 NRP/NRX 24A 15
;FPLX
17 MFCA 17
INTERNAL EXTERNAL
LEB3S3 runual
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37 E8A193 g u u BDDVAC ,I FN
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41 EE865] IV SN 4
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45 4
47 PANEL menu~TEn r1ELn 'SUPPLY *** 4

(FDR SECDND MUTQR VHEN USED)
49 4 ¢
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2FPLX
51 5
MFCB
INTERNAL EXTERNAL
:
53 FSB44J Ml1UNI MqUNT 5
C2` FPL-1 N p161
55 £31 FPL-2 5 P1C1 SH 5
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57 -<€5' FPL-4 r\ NEC1 r 5
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59 -<€7
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71 FU3 VDLTS if 7i
x x
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73 MAX / 7I
R /
EEB67] + SP ,'
75 SHUNT FBK 7 s
EEBé91 W .. SN
77 7r
79 7;
xx * DPTIDNAL Alex : FIELDS SUPPLY POWER FRDM L1,L2 [F VDLTAGE ACCEPTABLE
I
Figure G-7. Sample Elementary Diagram, G Frame Drive l/wth DCF8 Board (Sheet BD)
G-6
01 CDNTAQTDR DRTVFTRS
MAY BE EITHER HLGH ER Law SPEED VERSION D1
D3
03
D5
05
D7 r.N~TA;TQN gqrvw me mm ***

07
D9
09
11 CDBA DR CPCA *an MDA
11
MACPL MPL OTB
13 R ' ws 1 5 3
y<
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39
41
43
CFINTACTUR nnwrn FUR MOB *** 41
43
45 CDBA DR EPCA ** MDB
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61 EBC36] r I
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65 RMPL
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67
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71 L__I_ _ - e u -...---J
71
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75
* REMDVE FDR DB e. CONNECT BOTH
N01PL-1 CDS) TO ITB-1 (MC) AND
73
Ng1PL-2 <DB> To ITB-2 (MD) 75

77
seam CDNTACTDR DRIVERS CAN BE EITHER 77
SLDV (USING cpl:A> DR lAsT :uslnG :Dana
79
* me * DPTIDNAL 79
Figure G- 1. Sample Elementary Diagram, G Frame Drive Vwth DCFB Board (Sheet BE)
G-7
01 D1
D3 03
5 x x x
DS * BK * SLCC 9RCPL
05
SPCA
O7 E 07
1DPL
D9 i D9
E
11 ;PL
11
13 7PL 3PL
13
15 15
17 17
19 19
3PL
21 SDCC DCFB
muns*** A A 7PL DR
21
MET1 l1PLX ZN SDCI
as MET1
A. 23
re "¢\
11PL4
METER 1
25
I MET2
1
14
SPL
25
27 £3 E7
re 5 HPL5
11PL5 1PL
X
\ METER 2
29
a2 29
31 MET3
MET3
A.
r \ sQKE 11PL6 31
33
35
I (5
MET4
3QE--
\(- J
METER 3
33
7
ZN 35
f)
f) xi M T R 4
METER 11 2PL
I
\
37
39
8
Q,
\(
\
i 11PL7
MPLS
E E
CDM
Es 37
4PL TCPL
39
41 BPL SPL 41
43 43
III
aT83a-(WITH CPTA)
45 ETBI4-(ND CPTA) 45
O
47[BC37] 47
2TB31-(WITH CPTA>
2TB13-(ND CPTA)
l
49 c> 49 l
CPN | CPH BPL DPL
||
BPL
BPL SPL
51 RTBA
RTBA *me xas * LTB m ** STB 4PL
$1
DR
RPL 0PTPL
0PTPL STBA
53 53
55 55
57 57
a2PL
L
I
59 59
61 EXURB
I 61
<1>§<a> T(3>
63
65
ca
[:<1 w~J1l 9 +PTCT
I1+PTCT x
as x
an TCCB **
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63
65
11 -
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ii] JKK aPL
67 g 67
TCPL
69
71
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13-
Ea'
3PL 6
7 l
73 e 7
75
C USED DNLY UN SLCC GLa3.
g USED UNLY UN SDCC G1 7
77 Ii] PANEL MDUNTED

7
x * EXE000 UNLY
79 an ** 5. DPTIDNAL
7
I
Figure G- 1. Sample Elementary Diagram, G Frame Drive Vwth DCFB Board (Sheet EA)
G-8
A B C D E F G H J K L M N P Q R s
I 1 01
AC n up prrnRAcgg 01
03
03
US DCFB
A TCPL 05
07
[FPb8,3D]
VI
v1-va
SVI I
VCD
Vp _
01 L 11 07
D9
crmmasn va D9
11 JP1
V3 we-va 3 TCPL 11
rFA.B,40J
13 1 SV2 2 .1pL-29
SYNC 13
¢. 1
15
TCPL 15
17 V1-V3
so: 1PL-12
.1pL-12 17
VCD
19
19
21 f
P1A P1-PE 1PL-13 21
[8A13]
»
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PQA VCD 23
renal: 1PL-37
1PL-37
v.
25 | ,Tp37
25
27 ETB VM1A-8
?
[8815]21*08
VM1A sws 1PL-39 E7
A VCD
29 VMIB
[BB]9} n 29
4 .u
31 2TB
VMEA wan-B ANALOG 1PL-06 31
:8844]€3 JI
33 are
're SVS
4 VM2B
VM2:B 33
[8g48]5 r.
35
35
37
IFPL 37
NRP
39 1pL-19 #1 T [BD19J
39
i FIRING I NRX
FIRINE
PPLL2
[NC]
41
NPL1.2 41
[NC]
43
NRP EFPL 43
IPL-1B [BD54]
45 #2
FIRING ~4pL-34: 45
47 K1 KG CQJPL-1
CEIPL-1
IPL-34 4pL-1
4pL-1 47
L) One
49 -I I :hpa-1
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51
$3
IPL-35 -l-l<< CNPL-2
CNPL-2
MACPL
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MACPL ETB
55 2 + R 2? [BEEEJ 55
57 IPL-36 -
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59 (P24V) I
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61
ETB $1
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R 1F1PL-1
63 [BD4UJ g1
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65 :BD41J
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R 1FEPL'1 #2 SHUNT VCD
67 [BD75] 29 67
an
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69 [BD76] ;n0 69
»
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71
J _x
73 :URL DN SHEET EC
73
75
75
77
77
79 *BE* IJPTIDNAL
79
Figure G- 7. Sample Elementary Diagram, G Frame Drive With DCF8 Board (Sheet EB)
G-9
A B c D E F G H J K L M N P Q R S
D1 D1
03 DCFB
CENT. I-'REM SHEET EB 03
D5 05
/"_
J
JP5 ad
2TB JPG
07
T R IA1PL-1 07
D9
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33 33
ACCT
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37 ATTEN.
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39 39
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41 -azu-
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47 -l5V (TP n15>
47
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49 -aw <7p FU3) 49
51 51
53 53
55 55
57 57
59 59
61 61
63 63
65 LT1 65
f':
$7
69
ru1
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1
67
69
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ale*ale
73 73
HEAInKI
FAN
75 r \
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77 FAN
77
79 *** x DPTIDNAL 79
Figure G- 1. Sample Elementary Diagram, G Frame Drive with DCFB Board (Sheet EC/
G10
A 8 C D E F G H J K L M N P Q E s
D1 DO
03 03
D5 05
07 07
09 09
11 11
13 13
15 15
17 17
19 19
per:
21 (PCCA)
21
23 PIA ® PIB PI ETB

® 3
as
REMOVE JUMPERS | |
I I L.
®
|
p1A-p18
25 pas P2 ETB
PEA-P2B PEA as
J L.J r an
27 27
29 29
I 1FPL~'E w
[F_2D3
31 SCR IF 31
1FPL-1 R
[F._1BJ
33 33
aFPL-a | w
[F_20]
35 SCR at 35
2FF'L~1 R
[F__1B]
37 37
3FPL-2.V
[F_20J
39
41
FURWARD
GATE PULSE
TRANSFORMERS
SCR 3F
3rpL-1 R
4FpL-2 v
I
A
[F_18J
[F'_46J
39
41
43 SER 4F 43
4FPL'1 R
I' [F_44]
45 45
5FPL'2,V
[F_46]
47
49
IIECBDJ
5PL
SCR SF
5FPL°1~R
6pPL-2 w
1 [F_44]
[F_46J
47
49
51
53
_ SCR or
SrPL-1.R
1RpL-2 w
I
r.
[F_44]
[FB50]
51
53
55 SCR IR 55
IRPL~1 R
r; [FBS2]
57
1
57
aRPL-2 w [FB50]
59 SCR ER 59
BRpL-IIR
EFBSEJ
61 61
3RPL'2 w
teasm
63 BHK* SCR 3R 63
3RPL-1 R
REVERSE [FB5E]
65 65
GATE PULSE 4RPL"2lV
[FB24]
1
TRANSFORMERS
67 SCR 4R 57
42PL-1 R
Lrnaszl
69 69
SRPL-2 w
LFBa4J
71 SCR 5R 71
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[FBE6]
73 73
SRPL-2 w
[FB24]
75 SCR SR 75
6RpL~1 R
\ [FB26]
77 77
79 I 79
X*KOPTIONAL
Figure G- 1. Sample Elementary Diagram, G Frame Drive Witn DCF8 Board (Sheet EE)
G-11
A 8 C D E F G H J K L M N P 0 R S
D1 gag Rnrnlir D1
eoovAr: MAXIMUM
NON REVERSING
D3 03
05 D5
P1
0 Q
07 I 07
09 09
11 11
13 13
0
15 15
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POWER DCS
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39
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51
l
JJPQ
P2A
I |
53 53
55 vv
55
57 57
59 59
.
61 61
63 FU4 63
as o P2
65 65
67 HIGH TEMPERATURE ALARM 67
69
T§wxasa»e l (170'F) CDPENS DN ALARM)
69
ETB ETB
11 12
71 71
THYRISTDR HEAT SINK
73 THERMAL swiTcH 73
\;`¢ HIEH TEMPERATURE TRIP
(19D'F) (UPENS DN TRIP)
|
75 Tsw 75
2TB ETB
77 3 4 77
79 * LDCATED DN PCC CARD

*** DPTIDNAL
7
Figure G- 7. Sample Elementary Diagram, G Frame Drive Vwth DCFB Board (Sheet FA)
G-12
A 8 c D E
a
F G H J K L M N P Q R s
01 :ran `HR\'11FIF
SDDVAC MAXIMUM D1
REVERSING
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07
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09
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67 Riga HIGH TEMPERATURE ALARM

mn 67
TSW x x x (17D'F) (DPENS ALARM)
59
ETB 2TB 69
11 12
71
71
THYRISTDR HEAT SINK
73 THERMAL sv1TcH
73
75 Tsv
Tsv E190°F) (UPEND Dn TRIP)
75
77 ETB ETB
3 4 77
79 *
aleanex
LUCATED DN PCC
DPTIDNAL
conn
79
Figure G- 1. Sample E'/ementary Diagram, G Frame Drive Vwth DCFB Board (Sheet FB)
G-13
m SIR BRIDGE WITH 1?1P£R CARD 01

450VAC WITH SEPERATE TRANSFDRMER
NON REVERSING
03 03
05 DS
al I D
PI
07 07
go DO
11 11
13 13
15
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67 HIGH TEMPERATURE ALARM 67

Tsw *** {17D'FJ (OPENS DN ALARM)
69 69
ETB ETB
11 12
71 71
THYRISTDR HEAT SINK
41!
u 4 HIGH TEMPERATURE TRIP
Tow (190~F) (DPENS DN TRIP)
75 75
2TB ETB
77 77
3 4
79 ace LOCATED DN PCC CARD

*** DPTIDNAL
79
Figure G- 1. Sample Elementary Diagram, G Frame Drive With DCF8 Board (Sheet FC)
G-14
A B c 1: E F G H J K L M N P Q R s
01 siR BRIDGE WITH 1alpf;n CARD
46DVAC WITH SEPERATE TRANSFERMER Ol
REVERSIN5
03
03
05
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07
07
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67 r.{". HIGH TEMPERATURE ALARm

amass*
TSW BE ** C17D'FJ CUPENS DN ALARM) 67
69
ETB ETB 69
1: 1E
7]
71
THYRISTDR HEAT SINK
73 THERMAL SVITCH
73
..,.»;
4. HIGH TEMPERATURE TRIP
75 Tsv (19D°F) (OPENS DN TRIP)
75
77 ETB aTn
3 4 71
9 an LDCATED DN PCC CARD
7 annex DPTIDNAL 79
Figure G- 1. Sample Elementary Diagram, G Frame Drive With DCF8 Board (Sheet FD)
G-15
Notes:
G-16
lu,
I
APPENDIX H
ELEMENTARY DIAGRAM, G FRAME DRIVE WITH SDCI BOARD
H-1. INTRODUCTION Table H- 7. G Frame Drive Vwz'h SDC/ Board

Figure H-1 contained in this appendix provides a sam-
ple elementary diagram for a G frame DC2000 Digital Sheet Description
Adjustable Speed Drive that contains an SDCI board. BA Ac power circuit.
Figure H-1 was produced from GE drawing
246B2387AB . BB Do output.
that wire originates. For example, wire number Bcol BD Panel-mounted field supply.
NOTE
BF Internal core-mounted field
Drive elementary diagrams may change with supply (on SDCI).
tary diagirani contained in this appendix is
current as of the issue date of this manual. EB, EC Ac and de feedbacks (SDCI
connections).
Table H-1 summarizes the contents of each page of the
elementary diagram. Table H-2 lists terminal board EE SCR gating (PCCA, PCN, PCR
2TB connections. connections).
FA - FD SCR bridge.
H-1
Table H-2. Terminal Board 2TB Connections,

G Frame Drive Vwth SDC/ Board
I
2 Field A do (-).
3 Thermal switch, t90°~
4 Thermal switch, 190°.
5 Field ac in.
6 Field ac in.
7 Field ac in.
8 Not connected.
9 Voltage feedback, motor A l + l .
14 CPT 1 15 v.
15 Current feedback, motor A ( + } .
17 Blower switch.
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
H-2
D1 D1
D3 D3
05 os
_
U7 D7
Ac PQVER CIRC1;1T
BF BE
09 man# [BC01]
11
L1
DSW ru1
K1 I CTIBE MA
» PDVER .pt
[8B11]
of
11
II * ans CONVERTER
13
:
I
FU2
l
[BCD3]
**
[BD35] [BF35J MA
13
15
L2
ii-<>-m
K2 Alex
I -ES- 1:
: FDR DETAILS
17
:
I
FUN
1
[BD37] [BF37]
me
crease HA
SEE
SHE£T
17
19
L3
" ~; I-LJ!
K3 Alex
I FA-FD .pa [88a7] 19
21 21
23 \ CPL
EEB70] E3
25 E5
27 27
29 ET
31 31
33 33
35 35
37 37
39 39
41
41
43 43
45
45
47
47
49 49
$1
$1
53 53
'55 55
57 57
59 59
61 DPTIDNAL FAPL FAPL

FAN D 61
63 63
FAN 1
*xx
I
65 R/ 65
67 67
69 69
71 be CT'S ARE PRESENT DNLY IN REVERSING DRIVES 71
73
an * CDNTRUL puwarz MAY CDME FRDM L1.2,3 IF VDL7AGE ACCEPTABLE
DTHERWISE WILL BE SEPARATELY FED TD TDP nr BLDVER AND CPT FUSES 73
me as me OPTIONAL
75 75
77 77
79 79
Figure H- 1. Sample Elementary Diagram, G Frame Drive Vwth SDC/ Board (Sheet BA)
H-3
D1 OL
03 03
D5 05
DC =1UTPUT
D7 D7
MQTQR A
D9
PI
SHA MDA * as D9
[BAM]
"Tb 1
11
13
Lr an l I EEBSSJ
[EB53]
[8E16]
[8D20]
[8F20] Q
11
13
rave I MUTUR A
15 up 15
E* J
17 17
[BD37]
19 [BF37J © 19
E1 21
23 as
as 25
E au
E7
E8A19]
P
a V ev
29 29
31 31
33 33
35 35
37 37
39 39
41 41
43 43
45 45
47 47
49 49
$1 51
53 53
55 55
57 iv
59 59
61 61
63 63
65 65
67 $7
69 69
71 71
73 73
75 7
@ FDR INTERNAL 10A SUPPLY DN SDC]
77 * ETB9 AND 2TB10 ARE WIRED TD PLP2 DR mQTDR ARMATURE PER INSTRAMENTATIDN REQUIREMENTS 7
xx UPTIDNAL DE CDNTACTDR MDUNTED IN PANEL
79 7
BE x x DPTIDNAL
Figure H- 7 . Sample Elementary Diagram, G Frame Drive Vwth SDC/ Board (Sheet BB)
H-4
A 8 c D E F G H J K L M N P Q R S
* an CPT AND CPTA C NNECTI NS
1 01 EIAIU-_
* as
D1
03 [BA151
03
D5 05
D7 ~i'. 1 07
-:p1ru1 CPTFU2 :LEPTAFUI CPTAFUE
09 D9
11 11
13 13
*
15 * 15
-<e->
17 17
amass
19 CPTA kw 7 *of la
T
19
CPT 10 7 $12
21 21
E3 B/V B/R IB/Y 8

B/.w B/R IB/Y 8 a3DVAL:
as
230VAC
25 230V AC 23DVAC
25
27 CPT :PTA
E7
B9 Z9
31 LE 1;R / £2 - B 115V BL/W

1 45A * 2
R 1 R B 115v IBL/W 31
4.sA
E 4 5 $2
33 CPT CPTA 3:-J
FU3 ]ru3
35 35
I
37 6
A
4
A
5
A A
1 a
Q58 §4TB 2TB ETB
rBEa7J EBE29] 31 37
[EC4D] CPTPL 32
39 39
41 41
43 43
45 45
47 47
49 49
51 51
$3 53
55 55 I
57 57
59 59
61
- 600VAC CPT PIRMARY
c NNECTIDNS $1
63
CPT I
FU1
CPT
FUE r CPTA
FUI l
CPTA
run | is
-» 0
65
y; T?\
TQ. TH
_n 12
65
67 CPT CPTA $7
69 69
me CDNNECTI NS T ru1,a QPTIDNAL-DEPENDINQ DN DLTAGE
71 71
ale*ale pTIDNAL = NDT A AILABLE DN C AND G FRAMES
73 73
75 75
77 77
79 79
Figure H- 7 . Sample Elementary Diagram, G Frame Drive Vwth SDC/ Board (Sheet BC)
H-5
A B c D E F' G H J K L M N P D R S
D1 D1
03 D3
05 DS
PANEL MDUNTED FIELD SUPPLY'***
07 or
(MAY HAVE A mA INTERNAL SUPPLY SEE SH. 01Br)
09 DO
11 n
13 13
15 NRX 24A 15
IFPLX MFCA
17 INTERNAL EXTERNAL 17
-; MDIJNI MQUNT
|
19 canes; FPL~1 N P151 19

-a3 FPL-2 q P1C1 SH
21 ""I" FPL-3 n N251 s
1 _, E l.
FP 2T81
[8815] 21
-"s . FPL-4 q NEC! /
I
E3 ""¢ rPL-5 \ PEGS I E3
'"i FPL'6 n PECI I
/
f
25 `"9 FPL-7 n N151 I 25

I
-"Q FPL-B D NICI /
w I
27 -a I-
I- R
PIG
A
f E7
-am PIC
IT
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M w
\¢ r DC
ET NIG I 29
\_42 R I
OUTPUT
NIC I
I
31 I 31
/I
,I
33 33
** 2TB run /
35 [BA15]
5
L EIB- Ac INPUT / as
ETB FU3 VELTS II
**
37 [8A19] E cr- 60gVAC ,I FN a L.
Ta
E8B20] 37
MAX /
R +
I
/
39 EEB4BJ SP I 39
SHUNT FE(
w
41 [EB50] SN 41
43 43
45 45
47 47
49 49
51 51
53 53
55 55
57 57
59 $9
61 61
63 63
65 65
67 67
69 69
71 71
73 7
75 7
77 7
79 7
*** DPTIDNAL xx = FIELDS SUPPLY PDVER FRDM LLL2 IF VDLTAGE ACCEPTABLE
Figure H- 1. Sample Elementary Diagram, G Frame Drive With SDC/ Board (Sheet BD/
H-6
A B C D E F G H J K L M N P D R s
D1
CENTACTQR TJRTVERS
MAY BE EITHER HIGH DR LET SPEED VERSION 01
D3
03
O5
D5
07 CQNTAQTQR NR1VER FNR rnA 3F*5E

07
09
D9
11 CDBA up CPCA x x MDA

11
MACPL MPL 1TB
13
[EB45J A
R
al
1
I
'Q _____ ______ I -<
5 3 13
24V r ' "II
15 w a2 PSN I
I I I
I
I
6 4 15
[EB43] A M/.>.` I I g
I
I I I 7
17
:
|
I
I .
I
I
I
5 17
19
1TB
I "---|
l : L..._
I 3% I 8 6 19
I I
|
/
01 I 1 I I
21 1 l I I 9 7
* 2
PSP I
I
I
:
I
I
|
|-- _'T -»
I
I
I
-<< I
LJ
21
I 10
--C
l.
23 I 8
I 1 I / 23
I I
H I I I I
25 [BC36] L I r I I 11 9 25
I I I / (1TB9-1T810 ARE USED
115VAC/105VDC
__
27 EBCSSJ L
12 CPN I
I
I
I
I
I
I
I
I
I
I'
l
I
i I
I
I
1
I
12
x(
10
L.)
INTERNALLY DN CDBA
SD ARE NOT AVAILABLE
FDR DTHER USEJ ET
29 I I
I I l I 29
I I I I
I I
QEL
RMPL I I
31 I
1 :CONT ACTUR
I
31
:Q
1 I
-$1
-)\
I CDIL II
•I
33
2
-I-< I I
35 1 I I
I
I 3
~ _<
F
I
I . I
I
35
37 L_ _Ir " - _ _ _ _ J
37
I
39 [BB123
39
41
41
43
43
45
45
47
47
49
49
51
51
53
53
55
55
$7
57
59 59
61
6]
63
es
SS
6s
$7
$7
69 69
71 71
73 73
* REMOVE FDR DB a. CDNNECT BDTH
75 NDIPL-1 (DB) TO 1TB-1 (MC) AND
NMPL-a (DB) TD 1TB-2 CMD) 75
77
** CDNTACTDR DRIVERS CAN BE EITHER
sLow (USING CPCA) UR rAs1- cus1nrs f:nBA)
77
79
* * as DPTIDNAL 79
Figure H- 7. Sample Elementary Diagram, G Frame Drive vwzn SDC/ $oard (Sheet BE)
H-7
A 8 c D E F G H J K L M N P 0 R s
ox D1
DO D3
05 D5
INTERNAL CURE MUUNTED FIELD SUPPLY x x x
D7 (DN sncn D7
D9 D9
1: 11
13 13
15 SDCI 10A 15
1FPLX MFCA
17 INTERnAL EXTERNAL 17
mum; !DUal
19 [EB29] _<<; FPL-1 D plGl 19
E -- FPL~2 D P1C1 SH ETB]
1._ .a FP ,_
21 -((4'
I FPL-3 A
N251 I [BB\5] 21
-<($l FPL-4 D nEC /
/
23 2" FPL-5 D PEGI I

/
E3
-((7 FPL-6 D P2E1 /
I
25 -<<B FPL-7 n N151 /
I 25
_(go w FPL-B p N1C1 /
**
/
27
-< u
-< I w *lw . RR
PIG
PIC
/
/ E7
IR
I
29 -< H *I w NIG I
I DC 29
_ 1*R
NIC
I
I OUTPUT
I
31 / 31
/
/
/
33 I 33
2TB FUN /I
x*
35 EBAIIJ 5 u D AC INPUT /I 35
2TB FUN VDLTS al ETBE
**
37 [8A15J s EI}- SDDVAC /I
MAX /
FN
v :Buena 37
R +
39 [EB4B] SP /z 39
SHUNT FBK.
41 [EB50]
w SN 41
43 43
45 45
47 47
49 49
51 51
53 53
55 55
'57 57
59 59
61 B1
63 $3
65 65
67 67
69 69
71 71
73 73
75 75
77 7
79 7
** * OPTIONAL me : FXELDS SUPPLY PDVER FROM L1.L2 IF VOLTAGE ACCEPTABLE
Figure H- 7. Sample Elementary Diagram, G Frame Drive With SDC/ Board (Sheet BF)
H-8
A 8 C D E 'F G H J K L M r~. P D R s
01
D1
03
03
0 be * ale
05
SPCA
* **
*an * SLCC ARCPL
05
07 El
1DPL 07
09
D9
on
1: aPL
n
13 7PL 3PL
13
15
15
17
17
19
3PL 19
21 SDCC DCFB
METERS means A LS 7PL 21
DR
E3 MET1 11PLX A SDCI
4,< 11PL4
LL as
'>
'3 METER 1
25 5PL
1 25
<
27 META
s II 27
re
Rx HPL5
11PL5
I METER 2 1PL
29
I META
e 29
31 £)
re s~.€ 11PL6 31
METER 3
33
35
I MET4
3
\\ \\
rr
33
7 £5 35
K i .M T 4 u
2PL
HPL7 E ER
.
37 11PL7
\\ 9 z
£3 37
\(
\ CDM
39 11PLB
i APL TCPL
39
41 BPL DPL
41
43
43
45 T 45
2TBl4
47[BC37] o
2TBl3 47
49EBC37l u
CPN I CPH BPL IDPL BPL
BPL GPL 49
51 RT8A
RTBA * *an **
* LTB *** 3TB 4PL
51
DR
RPL DPTPL STBA
$3
53
55
55
57
EPL 57
59
59
61
61
63
*
*Alex 63
PTCT
PTCT TCCB **
65
aPL is
E]
E]
ITeL
JKK
67
67
$9
69
71
71
73
73
75 0 USED DNLY DN SLCC uLan.
A USED DNLY UN SDCC G1 75
77 E] PANEL MOUNTED
77
** EX2DDO ONLY
79 x x * II DPTIDNAL
7g
Figure H- 1. Sample Elementary Diagram, G Frame Drive Vwth SDC/ Board (Sheet EA)
H-9
Dl Dl
D3 03
05 SDCI 05
07 V1-V2 07
VI 1
LPL-5
[FA.8.C.D303 VMAG
09 09
EFA,B,C,D37]
va
1] 11
V3 va-v3
[FA.B,C,D40J
1PL'E9
13 SYNC 13
15 15
17 V1-V3 17
1PL-S
VSEQ
19 19
21 21
SPL-E6 DCP P1-Pa
lPL-13
23 VCO E3
SPL-25 DUN
5PL-25
25 25
PPL-1
as NRX
E7
29
1PL-19 FIRING PPL-2
NPL°1 I [BD19]
[BD19J 29
31
NPL-2
1 31
K1 K2
MA
33 U nswc r CNPL-1
33
35
CNPL-'E
1 L_?
HE
I
O
.I-
I
35
\
'Je
37 37
39 KG 39
HAND 4PL4
4PL4
-41
-41 MAN: 4PL3
4PL3
41 J? 41
MACM 4PL5
K1 . ETB
43 paw I' MACPL-E'R 19 43
1PL"35 u :BE24J
45
47 BE ETB
=1 1F'1PL-I
MACPL-1
1
v
ED
[BE2E] 45
47
[BF4gj [BD4D] :o f
TB
ETB VCD FIN1 IF lPL-9
49 all p p,g w 1r1pL-2
1F]PL-B
49
[BF41J [BD41J
51 51
ETB
5 R ..]A1PL'1
53 E8816] I, FIND IA 1PL-0
53
TB
ETB VCD
w 1A1pL-2
55 [BB14] 'E1
55
57 57
IPL 5PL
59 GPA [EE4B] 59
I
61 61
1CPL-1
__
63 ATTEN 63
3 T C C A IL3
1 * L P 1
swf
1CPL-2
65 65
67 67
p--3
~1::p--3
~1::
ATTEN ACCT1 [Ll IPL-2
69 swf 69
ICPL-4
ICPL-4
:8AESJ
71 71
73 __/ 73
CDNT. ON SHEET
75 7
77 7
79 * = FDR INTERNAL I A SUPPLY DN SDCI 7
Figure H- 1. Sample Elementary Diagram, G Frame Drive Vwth SDC/ Board (Sheet EB!
H-10
D1
Of
03 s0c1
c NT, FREIM PRE SHEET D3
05
f\ os 4
».J'
07
D7
09
DO
11
11
13
13
15
15
17
17 '
19
19 |
21
21
E3
23
25
P VER SUPPLIES 25
CPTPL
E7 9
FU5 7A I
27
-ann- :Jones
29
FU6 7A ZN
-cn- ucRa9
31
+5v (TP-P5)
31
33 +15v <Tp-p15:
-15V (TP-N15) 33
35 +24v (TP-FU5)
-24V (TP-FU6) 35
37
37
39
39
41
41
43
LT1 *CARD
me as 43
45
RACK 45
FANS
47 :*-kg
FAPL-1
FAPL~2 41
0.5A 115VAC
49
i Rx 49
51
51
53
53
55
55
57
57
59
59
61
61
63
63
65
$5
67
67
69
69
71
71
73 *ass* = [IPT1IIINAL
73
75
75
77
77
79
79
I
Figure H- 7. Sample Elementary Diagram, G Frame Drive mtn SDC/ Board (Sheet EC)
H-11
A 8 c D E F G H J K L M N P D R S
DO D1
D3 03
os 05
D7 07
09 09
r
11 11
13 13
15 15
17 17
19 19
21
I-JUMPERS p1A-p18 T 21
I PEA-P2B 1
I ONLY QN 308PCS DR PCCA I
23
PCC :i ®P1A I PIB P1 OTB
23
25 CPCCA-FA,FB)
C3D8PES-FA.FB) :
I W§\-GE
P2Apas pa: I
I PI
2
ETB
25
I o
E7 (121PCR-FE,FD)
I
I
._J
L___-______.._._____l
Fl V~l1-LP2l
I E7
29 ET
1FPL-2 w
{F_20]
31
® REMOVE JUMPERS
PLA-P1B
SCR 1F
1FPL-1
1 [F_lB]
31
33
35
P2A-PEB
SCR 2F
EFPL-2 v
T [F_20]
33
35
EFPL-1
R A [FIB]
37 I 37
3FpL-2 V
39 SCR 3F
3FPL-1 R
A [F_2D1
3 -
[F_18J
41 FWD in. 4
4rpL-2 w [F_461
43 SCR 4F 4
4FPL-1 R
[F_44]
45 4
5rpL-2 v [F_46J
I i
47 SER SF 4
SPL SFPL-1 R
[EB23] n [F_44]
49 4 ¢
BFPL-'E v
[F_46]
51 SCR 6F s
6FPL"] R
[F_44]
53 5
1RPL-2 v
A [FB.FD50]
ss SCR IR
1RPL-1 R 1 [FB,FD5E]
5
g
57 5
2RPL-2 v
A [[.'8.FD50]
59 SCR ER 5
ERPL-1 R
[FB,FD52]
61
3RPL-E
I v 6
fFB,FD5D]
63 SCR 3R 6
3Rp.-1l R
xxx [FB,FD5E]
65 REV 4
6 i
PL'2 V
4R A [FB,FDE4]
67 SCR 4R S
4RPL'1 R l
t 'F tFa,F9e6§
69 6 I
SRPL-2! v [FB,FDE4]
71 SCR SR 7l
5RpL-1 R
[FB,FD26]
73 7I
BRPL-2 v
4 [FB,FIDE4]
75 SCR SR 7 I
6RPL°°1 R
[FB.FD26]
77 an seas = DPTIEINAL
7 r
79 7 a
Figure H- 1. Sample Elementary Diagram, G Frame Drive Vwth SDC/ Seward (Sheet EE)
H-12
A 8 c D E F E H J K L M N P Q R s
D1 SCP aernnf WITH f¢Qapr;s CARD DR PCBA CARD
SSDVAC MAXIMUM 01
NDN REVERSINE
03
D3
D5
D5
`l
PI
07
07
09
go
11
11
13
13
15
15
n
17
R R ii
[EE32J 0 l [EE36J » [EE4D] R I I
P1A
* -- *F 'Him
19
V w *vl 5.551I 19
21
l:£E3D]
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21
L-.EEQI
23 EACS
IACS 3ACS E3
25 39 39 39 25
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27
29
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31 i EEDDBJ
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I
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I I
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I
33 UTPUT
P ER DCS r: 33
35 AC INPUT
p ER 35
37 SDD
EEBIDJ 37
39
1 I r
I
40V
39
[5812]
41 1 1I
41
43
[EE44] R
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T38 43
45
47
[EE4E]
w
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4AES
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I 39
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SACS
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49 I
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53
53
t
55
55
57
57
59
59
61
6]
63 FU4
P2 63
65
65
67 -v HIGH TEMPERATURE ALARM

Tsw *** I (:l70'F> (OPENS Dn ALARM) $7
69
2TB 2TB 69
11 12
71
71
THvR1sruR HEAT SINK
73 THERMAL SVITEH
73
*A HIGH TEMPERATURE TRIP
75 Tow (190'F) (UPENS N TRIP)
15
77 ETB ETB
3 4 77
79 as LDCATED N pcc CARD
* ** DPTIDNAL 79
Figure H- 1. Sample Elementary Diagram, G Frame Drive wfzn SDC/ Board (Sheet FA)
H-13
A B z: D E F G H J K L M N P Q R S
01 SCP BRIUGF VITH 3nepr:s CART) D1

SDDVAC MAXIMUM
REVERSING
03 no
05 D5
PI
T
D7 07
D9 09
11 11
13 13
15 15
II
17 17
R R r R
[EE32] as [EE36]
19
21
[EE3n]
w
SCR
IF OR
-H P1A
SCR* V*
I I
[EE34]
w
»
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at v 5R
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I {EE383
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BF
SCR I
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21
23
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27 27
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DC I
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UTPUT
P ER DCS 33
35 AC INPUT 35
P VER
Zulu:
37 \ I $00 37
40w
39 39
[E:B1E]
Ann.--.
41 I
41
43 T18 TRB T38 43

,R r 1 R
.
r
(EE44J R
45
V
39
4ow w I40W
39
w 39
40w
45
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I
1R , 4ACS ER QSACS , , or 3R ISACS 47
47 3 4F v ."5F v
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53 53
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55 55
57 57
59 59
$1 51
63 FU4 63
a
*PE
65 65
67 HIGH TEMPERATURE ALARM E7

TSW *** c170~r> < PENS EIN ALARM)
69 69
ETB ETB
11 12
71 71
THYRISTEIR HEAT SINK
73 THERMAL SVITCH 73
'J
Tsw (190°F) c PENS DN TRIP)

l 75 75
ETB ETB
77 3 4 77
LOCATED N PCC CARD

79
* DPT] NAL
79
Figure H- 1. Sample Elementary Diagram, G Frame Drive With SDC/ Board (Sheet FB)
H-14
D1 sun BRIDGE WITH 1a1pl;2 snap
460VAC WITH SEPERATE TE NSF E are D1
NDN REVERSING
03
03
D5
PI
os
9
1
D7 I
07
DO
09
>
11
11
13
13
15
15
17 'r
[EE323
R
1 s [EE36]
R
_ [EE40]
R
I
17
19
21
[EE3D:l l \ i SCR
IF
*FE
I
P1A
[EE34] \ SCR
or
n '
'
g 10 1
'°-v
I
l
I
I
[EE3BJ w
'w SCR
* P
I
I
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I
I
I
19
I I , at I .L 0 1 | 21
g *0.1 I
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T I
23 .T I
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27 I
29 -. '1
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I r
31 i I
I 0.1
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DC I I
33 I I
DUTPUT I I
P WER I ,as
I I
35 AC INPUT l I
P ER r 135
I I
37 I _|
[EB10] | 500 I_I37
39
l i v ; I my
I.----.J
39
[EB12]
41 1 I I' I
I
41
43
4AC
45
[EE44] R A
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I w
I
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R
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U ft
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[EE52]
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43 I
[EE4E] w4 I
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45
47 . SDR
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55
$7
57
59
59 )
$1
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63 FU4
pa 63
.r
65
65
$7 HIGH TEMPERATURE ALARM
e7
T§wxealeale C1`/D°F) (CIPENS N ALARM)
59
2T:B 2TB $9
11 12
71
71
THYRISTEIR HEAT SINK
73 THERMAL SVITCH
73
75 ¥§v (19D'F) CDPENS HN TRIP)
75
ETB ETB
77 3 4 77
79 ans LUCATED N PCC CARD
DIE BE* 0PTI NAL 79 l
I
Figure H- 1. Sample Elementary Diagram, G Frame Drive worn SDC/ Board (Sheet FC)
H-15
D1 so BRIDGE W[TH 121pQn QARD
DL
4-SDVAC WITH SEPERATE TRANSFORMER
REVERSING
03 03
D5 os
's 9
P1
07 07
DO D9
11 11
13 13
9
15 15
17
19
[££32]
R
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P1A
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|
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17
w. r"*--1 w w r-
19
A r "'°"'-l
r"'°"'-l
=
[EE3D] '°"1
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21 I IF 4R I
I
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I
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27
T1A mc " TaA 2AC IT3A 3AC E7
29 o r " ' " 129

I
[CDDB] I 1
31 L or It I
I 0.1 °'l 31
1
DC I I
I I
33 DUTPUT I 133
pclwER I l
I l
35 AC INPUT I 135
PDVER
[EB10] I I
37 i I I . II
I'sou ' I137 L
L10lu'__J
39 39
roman
41 i 1 1
I
41
43 T18 4AC T28 SAC T3B EAC 43

6 R R
[£E44] R *--I [EE4B3
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SCR I
IR
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I
I
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LEE4SJ
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SCR SCR
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I
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I
:
[EESO]
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SCR
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aus,
I 47
D.1 I'
/
0.1 | 0.1
/
I I I I I
49 I I I ! v 49
w w I I
FZE54J I I
EEESBJ L ___} :Essen n I I
I
L .._..J L __.|
51 PEA 51
R R R
EEESS] as o [EE60] :r [EEB4] 9
53 53
55 55
57 57
59 59
61 B1
63 FU4 63
, » PA
GS 65
67 .gr HIGH TEMPERATURE ALARM

Tsv *** C17D'F) CDPENS DN ALARM)
67
69 69
ETB 2TB
11 1a
71 71
THYRISTDR HEAT SINK
73 THERMAL SVITCH
73
»
u in HIGH TEMPERATURE TRIP
75 To C190'F) CDPENS DN TRIP)
75
2TB ETB
77 3 4 77
79 BK LOCATED DN PCC CARD 79

x x * 0PT]0NAL
Figure H~ 1. Sample Elementary Diagram, G Frame Drive With SDC/ Board (Sheet FD)
H-16
APPENDIX I
ELEMENTARY DIAGRAM, J FRAME DRIVE WITH DCFB BOARD
1-1. INTRODUCTION Table I- 1. J Frame Drive With DCFB Board

Elementary Diagram Sh set Summary
Figure 1-1 contained in this appendix provides a sample
elementary diagram for a J frame DC2000 Digital Ad- Sheet Description
justable Speed Drive that contains a DCFB board. Fig- BA Ac power circuit.
ure 1-1 was produced from GE drawing 246B2358AD .
BB Do output.
On the elementary diagram, internal and external wire
numbers identify the elementary diagram sheet where BC CPT and CPTA connections.
that wire originates. For example, wire number BC01
originates 011 sheet BC, line 01. BD Panel-mounted field supply.
NOTE BE Contactor drivers.
Drive elementary diagrams may change with EA Control board interconnections.

EB, EC Ac and do feedbacks (DCFB
connecUonsL
ED SHVI connections
Table 1-1 summarizes the contents of each page of the
elementary diagram. Table 1-2 lists terminal.board 2TB EE SCR gating (PCCA connections).
connections.
FA -- FD SCR bridge.
FG Power converter components .
FH Motor connections.
1-1
Table /-2. Terminal Board 2TB Connections,

J Frame Drive With DCF8 Board
I
1, 2 Not connected.
4 Thermal switch, 190°
5-8 Not connected.
9 Voltage feedback, motor A ( + ) ; high-voltage terminal board for voltages greater than 600 V.
10 Voltage feedback, motor A (-), high-voltage terminal board for voltages greater than 600 V.
14 CPT 115 v.
15 Current feedback, motor A ( + l . high-voltage terminal board for voltages greater than 600 V.
16 Current feedback, motor A (-), high-voltage terminal board for voltages greater than 600 V.
17 Blower switch.
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
21 Field A shunt l + ) .
23 Voltage feedback, motor B ( + ); high-voltage terminal board for voltages greater than 600 v.
24 Voltage feedback, motor B (-), high-voltage terminal board for voltages greater than 600 V.
25 Current feedback, motor B ( + ) , high-voltage terminal board for voltages greater than 600 V.
26 Current feedback, motor B (-l; high-voltage terminal board for voltages greater than $00 v.
27 MDB coil driver.
28 MDB coil driver.
30 Field B shunt (-).
31 CPTA 115 V ground.
32 CPTA 1 15 v.
1-2
A B E D E F G H J K L M N P Q R S
Ol 01
03 03
as DS
07 07
AC PM/ER cracgrr
D9 Qaleaseass UK BE xx xx 09
DSV I-[A44] EBCDI] EBD35]
L1 K1 P1
11 .;.<, [BB123 EBB41]
I
I
PDVER T [ED21]
11
13 I
I
I- E
A*4 ale * aus#
6] [8€03]I8337][8pB9 J
** K2
CDNVERTER
CDNVERTER
13
I
15
LE 1192
* -|D+<-
-Div 15
I
**
.
I FUR DETAILS
17 I *NG SEE 17
I
L3 I -rA4a1 [BD7lJ K3
SHEETS
PA
19 \ & ¢ FA-FF 0 E8BEBJ C8857] 19
I
[ED23]
21 21
23 as
25 as
27 Z7
29 29
31 31
33 33
35 35
37 37
39 39
41 41
CONVERTER COOLING 3 PHASE CDNTRDL PDVER ( a s , 460, DR 575 VAC)
43 ** 43
cAn] •
I
|
45 me 45
47
49
:A1s:
**
rA19J I T |
s
r 47
49
BF BF BF BF BF BF BF
51 1 2 3 1 2 oF Q?" 2 3 $1
53 53
55 *** BLDVER
amass
BLOWER
xxx
BLDVER
55
1 2 3
57 57
2TB
59 1; [CA51] 59
DPTIDNAL 2TB ETB ETB
61 FANS 14 r ECA54] 61
FAN 1 8LVR1 BLVR2 BLVR3 63
.
63
re' CENTRIFICAL SWITCH
FAN 2 (CLGSES WHEN BLDWER
ss is RUNNING) 65
FAN 3
67 67
\J""
69 69
11 71
73
all * CDNTRDL PDVER MAY COME FROM 10.2.3 IF VDLTAGE ACCEPTABLE DR DESIRED
DTHERVISE VILL BE SEPARATELY FED TO TDP DF BLDWER AND CPT FUSES. 73
* * as : DPTJDNAL
75 75
E PANEL MDUNTED
77 77
79 79
Figure I- 1. Sample Elementary Diagram, J Frame Drive vwth DCF8 Board (Sheet BA)
1-3
A 8 C D E F G H J K L M N P Q R s
D1 01
D3 03
05 D5
07 D7
DC DUTPUT MQTQQ A
09
SHP1
IE
mays; P1A
D9
11
[BAM]
P
1
SHA
I
?1
MDA
1
11
13 [BE161
13
w
15 CED35] IED25] tanaon 15
MDTDR A
R
17 cE033] C) 17
1g EED27] 19
EBD37J
21 21
as E3
25 25
E7 E7
P2
[BA19]
29 29
31 31
33 33
35 35
** ii
37 mnTng n FXTFRNM To cnnr 37
39
E s»-m1
E
xanax MTB 39
41 CBA11]
PI
SHB
1 MDB
1
[8E4B]
Q
O 41
43 43
w
[ED41] EED29] EBD55]
45 MDTDR B 45
R
[ED39] C. l
47 47
[EDBU
[8D7E]
49 4
51 5
53 5
55 5
P2
57 C8A19] 5
59 5
61 6
63 6
65 6
67 5
SEE SHEET 01FH FOR PDSSIBLE MDTDR CDNFIGURATIDNS
69 6
71 7
73 7
75 7 I
77 ale * K = DPTIDNAL 7
[]= PANEL MDUNTED
79 7 I
Figure I- 1. Sample Elementary Diagram, J Frame Drive Vwth DCF8 Board (Sheet 88)
1-4
A B c D E F G H J K L M N P 0 R s
an ale CPT AND CPTA C NNECTI NS
01 EBAIIJ D1
I
* BK
03 E8A15] D3
05 05
J _/
I IM
07 _Q.. 07
A
jLCPTFu1 CPTFU2 :PTAFU1 CPTAFUE

09 go
11 11
13 13
*
15 * 15
17
! *ale* _L 17
19
21
CPTX *ID
T
i I " 12
CPTAX v10 12 19
21
B/V B/R B/Y B
23
1 Bow a B/R B/Y ,B
as
E3DVAC EBDVAC
25 EBDVAC 23DVAC CPTA 25
CPT
E7 E7
I 29
r v Y
in . v
29
£1 AY*
, , 1 1 al
-é= LB I
31 T5 115V
1 4.6A
LBLN
*E
R R/Y R
I
8 115V
1
4.sA
BL/W
2
31
33
6 4 s
33
CPTFU3 ICPTAFU3 l
l
35 35
A 2TB 2T8
<1n
»>
37 s 1 a 13 14 ETB ETB 37
CPTPL {BE27J EBE29] 31 32
[EC40] [BE59J [BE6l]
39 39
41 41
43 43
45 45
47 47
49 49
$1 * 46DVAE c NNECTIDNS SHE ABC E

F R 230 AC - REMO E CDNNECTING JUMPER
51'
s.
BET EEN 9-7_ CDNNECT AS r LL VS=

I 53 - 9 T B TT M run
,. 7 TO BUTTQM FU1
DN B TH
CPT AND CPTA. )
$3
55 55
57 57
59 59
SOOVAC CPT PIRMARY
$1 C NNECTI NS 61
CPTAFU2
63 CPTFUI n CPTFU2 CPTAFU1 63
65
67
--10
T8/Y
CPT
.
-»12
TB nm of CPTA
ss
$7
69 69
C[JNNECT] NS T FULL DPTIDNAL-DEPENDING N DLTAGE
71 71
axle*apnnr~mL
73 73
75 75
77 77
79 79
Figure I- 7. Sample Elementary Diagram, J Frame Drive vwm DCF8 Board (Sheet BC)
1-5
D1 D1
D3 D3
05 05
07 PANEL MIIIUNTED FIELD SUPPLY

as be * 07
DO D9
11 11
13 1:-I
15 15
1FPLX NRX/NRP 75A
17 IN ERNAL EXTERNAL 17
MFCA
MQUNT mqpwj
19 [E838] TB1 SH TB4 19
-<<; 10 I l u.
I
* _ - I
|
so;
1
FP
[BB15]
I
E] -<<3 V
FPL-2 N Plcl .f
r 21
-(<4 1§ FPL-3 F NEG1 I
23 -*K5
-<<S
i R
v i
13 FPL-4
FPL-5
'H N2C1
D p2G1 I
r
I
I
23
25 -<(7
-<<8
Et R
V
1?
14
FPL-6
FPL-7
D P2Cl
P N151 I
I
I
l
25
E7 -<€9 FPL-B n N1C1 I 27

1
E P[G I'
29
-< 11
T. PIC I
I
29
-<<- Z NIG I
I
31 -< 8 NIC I
I DC
UTPUT
31
I
f
33 I
I 33
I
xx TB4 FU1
35 L8A11J - L_! AC4 AC INPUT
LTS .f
I
I
:as
me TB4 rua I
/
FN
TBA
37 C8A15] I P - Q A55 SDFJVAC
MAX
I • [BBEDJ 37
/
.f
/
39 I 39
I
[EB63]
4] [EBSS] B 41
43 43
45 45
PANEL MDUNTED FIELD SUPPLY x x x
47 (F R SEC ND MDTDR HEN USED) 47
49 NRX/NRP 75A 49
aFPLX
I I
INTERNAL EXTERNAL MF c8
51 MDILNI M NT 51
[EB44]- TBI sH TB3
53 w I? FPL-l plGl
1
*r
apP
9 [B844J 53
1
'n
R
! 3 PPL-2 I* P101 .v
55 v I is» FPL'3 D nEG I
I
55
57
1 R
1g_
viii
FPL-4
FPL-5
D N2E1
D P251 I
I
I
I
$7
. R
V
u
14
FPL~'S n PECK
I
f
l
59 FPL-7 D N151 59
T R 11? rPL-B D N1Cl I
I
m 5 I
61 PIG I 61
s7 PIC
r
I
J DC
UTPUT
63 o NIE I 53
S I
[E I
I
65 I 65
I
.
f
67 TB3 1 67
ale an FU1 I
[BA15] fr"1> ACT AC INPUT r
. VDLTS I
69 ale
rBA19J
* TB3 rUn
u=n-- AC5 SIJDVAC I
r
FN
TB3
• [BB49J
69
I
MAX I
71 I 71
I
R T 51 1+ I
f
73 [EB67]
CEB69J
5v
A1 P
TB1
. a_s ) SP
N
I
sHuNT F BK
73
75 75
77 77
79
ale as * DPTIEINAL * as z FIELD SUPPLY PIJWER FREIM KLKE IF VDLTAGE ACCEPTABLE R IF DESIRED
79
Figure I- 7. Sample Elementary Diagram, J Frame Drive With DCF6' Board (Sheet BD)
1-6
D1 CVINTACTIIR n»2rvcRs
MAY BE EITHER HIGH DR LDW SPEE0 VERSION 01
DO
oa
D5
D5
qr1N1ACTI'1Q 'IRIYPQ PTT?
MDA u m :
D7
07
09
DO
11 CDBA UR CPCA xx MDA

11
MACPL MPL ITB
13 5
R
15
EEB55]
24V
A >;
L T ** +i 13
17
LE8SQJ v 5
PSN
I
I
: .L7
Il
_of 15 I
| I 17
<€- -of
19
L__ I
8
| I
1TB
21 re1
:I
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I
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9
19
v 21
as
e PSP 1 _L I \$- -of
23 a---
T
g 10 e
11 CPH
I
I I << 23
25
27
[BC36]
115VAC/1D5VDC
12
| J
CPN
I» __ I
I
11
~ -of is
[BC36] Pr r' I be
I
l I -<< dID E7
29 I
I
E 29
I| :
O
31 RMPL a
.1 'CEINTACT R 31
cum I
\
or
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v 1
33
a -II-( < 33
o r g .s
35
I I
1
I
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. , |
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39 :saw
39
41
41
;l1l~JTArtTI'1re npavqn run m38 ac-neue
43
43
45 CUBA DR I:=ca :eau MDB
45
MACPL MPL 1TB
47
R 1 5 3 47
[E859] J.
\.\
.f
r--°"*~-----~ I,
-_o-_
I I __.L I -.(
49 24V
w `2 PSN Io F T
I
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6 4 49
[E857]
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or 4
I I L)
51
53
1TB
- " |
I
I
I
I
I
I
i~--x
I
l
l
I
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7
8
_Of
6
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. -<< 53
55
ave
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1
I I
I
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Lu
7 55
$7 I
_a2 I
I
I I
I
10
L)
U l I B
59 rscasn
o11 :PH I I
I
o |
|
I
I
a \
11
- _.O._
<sTB9-:Tino ARE USED
57
6]
l15VAC/IDSVDC
cscssn 0
12 CPN I I
I
I P--*
g
1
I
I
I 1a
9
(<- --o-_
10
INTERNALLY DN CDBA
go ARE NDT AVAILABLE
FDR THER USE.)
59
I
I
I
I
I
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61
63 I
I
I
I 63
65 RMPL
I
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I
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re
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1 I NTACTDR I 65
..)\ 1 I I
67 C IL
-¢H< , I I
I
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I 67
-Ra p
|
|
1
I
|
|
69
I 3 |
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|
I
|
I
69
71 ~( . . . _ _ J1
L . . . .| . . - . . _ _
71
' |
73 [BB41]
* REV E F R DB B- C NNEET BDT
73
75 r\ 1pL-1 (DB) T ITB-1 <mc> AND
h IPL-E (DB) TD ITB-E (MD) 75
77 BE* CDNTACTDR DRIVERS CAN BE EITHER 77
SLDV (USING CPCA) GR FAST (USING CDBA)
79
* as be DPTI NAL 79
Figure I- 7. Sample Elementary Diagram, J Frame Drive lath DCFB Board (Sheet BE)
1-7
A 8 c D E F G - H J K L M N P Q R s
D1 »
D1
03 03
In x an as
DS
SPCA
* ass we SLCC * * ale ARCPL DE DLAN
05
D7 U 07
1UPL
09 09
D
aPL
11 11
13 7PL 3PL 13
la n 15
17 17
19 19
SPL
21 SDCC DCFB 21
METERS as BE ale A A 7PL DR
MET1
MET1 11PLX A sneer
B3 4 11PL4
£5 E3
f`¥
kw u( METER 1
25
I 1\i\
¥\
,
5PL
25
27 MET2
5,<
5 11PL5
am IPL
E7
METER E
|
I
so
29 29
2 .»
2,,
31 MET3
MET3 ZN
A 31
6 11PL6
I
6\(~< . METER 3
i
33
33 , .
1.
33
35 MET4
MET4 ZN
A 35
r"»
r"» 7
METER 4 . 2PL..
rr
37
39
l B
Be
d L
11PL7
11PL8
CDM
Ll
A 37
39
4PL TCPL
41 BPL 6PL 41
43 I 43
I
aTs3a-(w1TH CPTA)
45 ETB14-(ND CPTA) 45
c
EBC3 1 47
47 7 aT831-cw1TH CPTA>
aT813-:nu CPTA>
49 BPL 10PL 49
c CPN CPH BPL 6PL
51 RTBA *Alexale * LTB *** 3TB

DR
4PL
51
RPL DPTPL
CIPTPL ST8A
STBA
53 53
55 55
57 57
2PL
I I
59 |
59
61 $1
63 63
PTCT *BF l TCCB was*
65 ss
E JKK 2PL
67 57
T::PL
69 69
3PL
71 71
I
73 73
U USED EINLY DN SLCC G1.E.3.

75 75
A USED ONLY DN SDCC G1
77 E PANEL MDUNTED 77
are EXEOOD DNLY
79 *Anne I
DPTIDNAL 79
Figure I- 1. Sample Elementary Diagram, J Frame Drive Vwth DCFB Board (Sheet EA)
1-8
D1
m
03
D3
05 DCFB
TCPL D5
07
[EDOS]
VI I v1-va
SVI
VCD
IPL-11 07
D9
V2 09
EEDIDJ
11 JP1
V3 11
13
15
EEDIEJ I l
I
via-va
sea SYNC I
i
3 TCPL
1 L-29
2u P
u l
13
TCPL 15
17 V1-V3
sva 1pL-12 17
VCD
19
19
21
P1A 1PL-13 21
IEDEIJ I P1'P2
23
P2A
l sv4 . VCD
23
[ED23] 1PL-37
25 ITPQ7
25
27 VMIA-B
VMIA sys 1PL-39 27
[ED25] VCO
29 vnu;
[ED27] E9
31
M2A VM2A-B ANAL 5 1PL-D6 31
[EDE9]
33 SIS
VM2B 33
[ED31]
35
35
37
NRP FPL 37
39 1PL-19 #1
FIRING T i
1 NRX I PPL1,2
[8Dl9]
39
41
43
I FIRING
NPLL2 41
431
r
NEP 2FPL
45
47
1PL-18
1PL-34
#E
F'[RING
K1
4PL-3,4,5
CPTPL-1
m :1ans4J
45
47
l
T4pL-1
'J
49 CNPL'1
I 49
51 s 'CnPL-3
lPL-35 51
I MACPL ETB
$3 l 'iv u
A cszasa 53
ss
MACPL
2 + R I, A ETB
4? [BEE1] 55
57 1pL-36
D
K1
MACPL
a
MACPL
_w A
ETB
as [BE55] 57
2TB I
59 CPE4V) I' 4 R 7
+ A Q rBE53J 59
61
2T:B 61
63
31 R 1F1PL-1 (+>
liBD40II iv
VCD IPL-9 63
2.TB
2 w 1F1pL-2 <->
65 [BD413 I ii
aTla 65 l
[8D75] 29 Rl1F2PL-I (+)
67
57
a. t8 w 1F2PL-2 <-> VCD
1pL-40
69 [BD76]
4 69
71
71
73 r: NT. DN SHEET EC _,f
73
75
75
77
77
79
| 79
a
Figure f- 1. Sample Elementary Diagram, J Frame Drive vwm DCF8 Board (Sheet EB)
1-9
A B c D E F' G H J K L M N P D E s
D1 D1
03 DCFB 03
CDNT. PRDM SHEET EE
D5 D5
JP5
07
R IA1PL-1
J>3 ,_A 07
D9
[ED33]
s r § 0 9
11
TT L g VL
g g
g ISDL
1 L~DB
P
13 EED35J
v IAIPL-2
3
5
T JP7 I 11
13
JP4 a
15 JP6 is
17 17
JPID
19
R ]A2PL-1
JPB -A 19
A
21
[ED39]
HE; » 5* p _ 21
II
#n __3 | VIA'
V50 I ISDL L 10
23
..,_ § s 3
23
as E€D41]
w IAEPL'2 » 3
JPG
JPIE §_J 25
27 JP11
E7
29 FWD 29
1PL REV SPL
GPA
31 31
33 33
35 **
EED49J
CPL ATTEN.
l ANALDG 1p--1
35
SV7
37
39
.I 37
CPTPL 39
LBC37J t 7A FU2 SQPL
-u-
41
7A FU3
D CR51
l [ED37] 41
43 -D- co CR55 43
45 +5V (TP -- P5>

45
+15V <TP ..
.. p1S>
47 -15V (TP ~15:»
47
+24v (TP FUN)
49 -e4v (7P Fu3)
49
51 51
53 53
55 55
57 57
59 59
$1 51
63 63
SS LT1 65
.--*
67 FU1 67
3
D.5A FAPL-2
69 69
FAPL-1
<-n5-,
71 VAC 71
73 O 73
75 CARD 75
RACK
U
77 FANS 77
Alex = REVERSING DRIVES DNLY

79 O 79
(IF REQUIRED)
Figure I- 7. Sample Elementary Diagram, J Frame Drive win DCFB Board (Sheet EC)
1-10
Dl 01
03 SHVI 03
OS 05
JP09
07
L1 °1 fé's .
I VI D7
..
EFA,B.C.D30II 1 I :Ewan
D9
LE
JP1D 01 IE "3 I
V2 DO
[F'A.8.C,]J37] i I EEBIDJ
11
L3
JP11 °1 TO °3 V3 11
:rA.s,c,n4oJ I I
1 [EB12]
13 13
FA _1:1 LT1
:rA,n,n:,na3J
15 15
FB LT2
rr».B,r:.n39:l -u
17 17
FC LT3
[FA.8,C.D4€] -E r
19 19
JP12 °1 °a #3
p1+ ! i PIA
21 [BA131 I I [E822] 21
JPl3 °1 a is l
23 [8A21]
pa-
I I
I
l PaA
[EB24] E3
l
2 TB JP14 °1 QE ¢3
25 [BB15]
9 M1A+ (+3
V-I L VM1A
IIEBEBJ as
2 TB JP15 01 $2 #3
27 [BB19]
D
r,
v|18- (->
I I L VVII8
EEB30] 27
E TB JPl6 01 j as I
E9 C8844J I
3 MEA (+3
I VMEA
Ta EEBBEJ 29 l
I
.
2 TB JPI7 Of #3
31 [8848]
E TB
4
I *.
M28 (-> I
I I VM2B
[E834] 31
5 R DCIPL-1 <+) IAIPL-1 R
33 E8BIS3
E Tal
5 w 0L:1pL-a <-)
VCE] ISDL
1A1pL-2 w'T room
[EC08] 33
35 188141 35
4*
SQPL
37 [EC44J 37
ETB
[BB45]el-5 R DCaPL-1 (+> IA2PL-1 R
39 I tzcaon 39
\
/.
41
ETB
[8843]'3§' w DCEPL-2 c->
I 1"P VCEI ISDL
IA2PL-2 w
A EECZSJ 41
43 tFB,FN3aJ
w
I CTIPL-1
JP1 . z
,n2 43 I
45 * me R l:71pL-a
45
[F:B,F:D32J
4 ac
47 JPG I -O1 JP4 47
CPL
EEC36]
49
v CTBPL-1
JP7 A
4
2~
1 JPS * an 49
[FEFD43]
51 =3 51
an * R CT3PL~E
>:a
53 [FB,FD43J 2¢ 53
JPG 1 >1 JP6
55 55
57 57
59 59
61 61
63 63
65 65
67 67
69 69
71 71
73 73
75 75
U
77 77
1
79 ** : REVERSING DRIVES ONLY 79
Figure I- 1. Sample E/ementary Diagram, J Frame Drive Vwth DCFB Board (Sheet ED)
1-11
A B C D E F G H J K L M N p Q R s
D1 01
03 O3
05 is
D7 D7
D9 09
11 11
13 13
15 is
17 17
19 19
21 21
23 r I as
be
25 P1A P1B PI 25
...J L_
27
..;RJ an
m
27
PEA PEB pa
PCCA
'Qi' ' .-_1
E9
N"
29
1 1FPL'2 w [F_3D]
31 G5 - REVERSING SCR lF 31
G6 - NDN REVERSING 1FPL-1 R
[F_18]
33
* NQTEI
REMDVE JUMPERS
EFPL-2 w
[F_20J
33
35 SER 2F 35
P1A-P1B
PEA-P2B .
EFPL'-1 . R
[F_1B]
37 37
I
3FPL~2 V
\
(F__20]
39 SCR 3F 39
3FpL-IIR
[F_1BJ
41 FWD 41
4FPL"2IW
A [F_46]
43 SCR 4F 43
4FpL-1IR
[F_44J
45 45
5FpL-2 V
[F__46]
47 SCR 5F 47
5PL 5FPL'1 R
[EC3D] £F_44]
49 49
sFpL-a.w
[F_46]
51 SCR SF
SFPL-1 ~R T
4 [F_44]
51
53 53
1 1RPL-2 v
A [FB,FD50]
55 .SCR OR 55
1RPL-1 R
A [FB,FD52]
57 57
ERPL°E w
[FB,FD5D]
59 SCR ER 59
ERPL-1 R
[FB,FD52]
61 51
3RPL-2 w {FB,FD5D]
63 SCR 3R 63
3RPL-1 R
[FB,FD5E]
65 REV
annex
4RPL'2 w T [FB,FD24J
65
67 SCR 4- 67
4RPL-1 R
[FB,FDE6]
4
69 69
5RPL~2 v [FB,FDE4]
f l
71 SCR SR 71
SRPL-1 R
/\
frarnasi
73 73
6RPL'2 w
75 SCR SR
6RPL-1 R
T EFBJ-l]JE4]
EFB,F]l36]
75
A
77 77
79 79
Anne = DPTIDNAL
Figure /- 7. Sample €/ementary Diagram, J Frame Drive Vwth DCFB Board (Sheet EE)
1-12
F B c D E F G H J K L M N P Q R s
SCR BRIDGE
01
-
eoovac 77mm CELLS
NON-REVERSING
D1
03
03
D5
05
> 9
PI
07
07
D9
L12 L14 L16
I DO
;-._230
11
11
13 T
13
I R30-32
15
FU3
**
FU4
** 5 FU7
BK*
FUB
** FU11
* an rule
as BE 15
17
R R 17
[EE3E] [EE36] 1»
[EE4D] R
19
w 19
[EE3D] SCR [E[34] w SCR [EE3B] w _i s
SCR
TR
2] |. IF' 5 EF' 3F 21
R
23 3,4- R
7,8 11.12 23
25
P
11
as
1>
27
C23 R23 27
29 al r"1
Rex CEI 29
31
K1
L. FU2I. n-11
[EDOS]
Q U O i 11
31
DC
33 [ED14] UUTPUT
PDWER 33
35
35
INPUT T [50103 REE C22
KB
37 POWER _
¢
u_..U :; "1 -Ii I
37
ruaa
39 [ED16J 39
K3 [ED12]
41
L 11
FUN
I
41
43 rams:
> R 43
[EE44J R I
[EE48] as [EE52] R
45
47
[EE42]
V
»
SCR
4F
R
LE £EE46]
w
SCR
R
5.6 [EE50]
V T SCR
R
7,5
45
.J. 5F SF 47
49
C1 ca cs
49
$1
51
» r In nr
53
55
FU1
* ave
rue
as as E
_.rus
*ale
FU6
ale is
. FU9
j**
FU1D
*
ale
53
55
57 s :» I
I 57
\
59 4
q
L11 < L13 L15 59
1
61 J 4 I $1
63
P
63
n JF IP 2
65
$5
67
67
0£0 Ag; 0th HI TEMPERATURE ALARM
69 arsv* BE *ETSW* as *aTs»/'*,F (170 r) cupzns UN ALARM)
PHI PHa PH3 69
71 ETB 2TB
THERMAL
11 é as 71
DETECTGRS
73
73
G 50 \. ,_u mg" H1 TEMPERATURE TRIP
'row (190 r> CDPENS DN TRIP)
I
15 Tsw Tsv
PHI PHI PH3 75
77 2TB 2TB
3 °4 77
79 * i i * FUSE RATING/USE BASED Dn CURRENT REQUIREMENTS
* * * , . DPTIDNAL 79
Figure I- 1. Sample Elementary Diagram, J Frame Drive Vwth DCFB Board (Sheet FA)
1-13
I A
SCR BRIDGE
B c D E F G H J K L M N P Q R S
01
m
600VAC -
77mm CELLS
REVERSING 03
03
D5 D5
P1
07
D9
I
.>
07
09
L12 L14 L15
|-
LL.C30
11
n.
11
13
TFu3 FU4 FU7 FUB .FUN Fula
_ 13
LRBD-32
15 me *ale as * sue * E #if * me 15
I
17 17
R I R
[EE32] EE36] [EE4D] 0
19
czzsln
w [EE34] \ sore I:EE3B]
w
SCR SCR
i C6 19
SCR SCR
T SCR
T T
»
21 IF OR 2F 5R S 3F 6R 21
T 1 /
R I
23 l§,4 [pa v l 11.12 E3
[EESBJV :zoner w [EE74]
25
27
rzzsan
R
or [EE72]
R
I :>
C23 Ras
[EE76]
R
£
25
E7
29 -u LJ E9
[EDO8] R21 cat
KL CT1
r
31
I
L 31
R w FU21 DC
[ED43] EUTPUT 33
33 [ED46] -[ED14]
PDVER
35 35
came: R22 car
INPUT
37 PA:IWER
KG 1 I 37
ruaa
39 I-.[€]]16] 39
IEDIEJ
41
K3 CT3 1 .I 41
v FU23 .. [ED1BJ
:EDS1 ]
43 [znéaz 43
R R `»
[€z4411 A [EE4B] cease]
45 R R 45
[EE42] \ SCR SCR ]1.a [EE46} \ SCR SCR ]5.6 [EE50] l SCR SCE lg.1o
47 4F IR SF ER or OR 47
C1 CO C5
49
[EE54] ' g [EE5B]
w
F
:Essen
v I /
49
51
53
[EE56] R
I *I
A
IFUI FU2
LEESDI
R
I1 ru5
I
Fews
CEEB4]
R
FU9 IFUID
I
51
53
55 meals * we *BE male * all T ** 55
57
I $7
59 $9
L11 L13 L15
61 61
63 63
PA
L
ss 65
67 67
HI TEMPERATURE ALARM
69 aTv
PHI
* **aTsv
PHe
* *"!aTsw°!§Q*
PH3
(17D r> ( PENS DN ALARM)
69
2T:B . 2T8 71
71
THERMAL
11 * u. 12
DETECT RS
73 73
\loG H1 TEMPERATURE TRIP
&\¢
"5
TSW TSV TSV (190 F ) (OPENS TRIP)
75 75
PHI PHE PH3
2TB ETB
77 3 4 77
79 **= 79
xxx _ FUSE RATING/USE BASED DN CURRENT REQUIREMENTS
DPTIDNAL
Figure I- 7. Sample Elementary Diagram, J Frame Drive Vwth DCFB Board (Sheet FB)
1-14
DC2000 Digital Adjustable Speed Drive GEH~600S
A 8 c D E r G H J K L M N P Q R s
D1 SCR BRIDGE 01
601-1g00VAC - 77 mm CELLS
NDN-REVERSING
03 03
05 D5
07
DO ".
T
•
"IDCFU1
L T d DC
Et 07
go
L12 L14 L15
SNUBBER
11 11
13 13
FU3 FU4 Fu7 FUN FUll ruaa
15 ** me * an as an an *BE arm 15
17 17
R R R
EEE32] [EE36! [EE40]
19
21
SEEBGJ w
>
SER
IF
l C2
[EE34]
w
SIR'
EF
[EE38]
w
SCR
1 19
3F 21
R R R
23 I 5-9 I 13-16 El-24 23
25 as
l r> :> *>
27 E7
29 E9
[ED08]
31
K1
L..- Fu--o [ED14]
FUEl
31
DC
33 DUTPUT 33
PDVER
35 35
INPUT I EEDIDJ
K2
37 PM/ER r :r o [ED16] 37
FU22
39 39
K3 reamen
41 0 > IT" ,. [ED18] 41
ruaza
43
[EE44]
E
T In r
[EE4B]
R
A 1 R .: rL cszsz:
r E
E 1»
43
I
I
45 I
V R v R w R 45
[EE42] 4 SCR 1-4 [EE46] SCR 17-E0
47 7
.5 OF _g SF A QF 47
C1 cs
49 49
51
53
1> 9 Ur T 51
53
FU1 . FU2 ._,rus FU6 Fun FU10
32; **
1
3** J in* *
55
51
T
J xsane
lr
Q ale Alex 55
57
59 4
59
LIE 4
L13 L15
61 4 TO DC 61
SNUB8ER
63
DCFU2 E 63
» PE
65 65
67 67
a \; u P =<' H1 TEMPERATURE ALARM
NSISE a r v *S*
a T v Helen Alex-lu aTs\P!§
aTs\.P!§ (170 F> (DPENS DN ALARM)
69 69
PHI PH2 PH3
2TB . ETB
71
THERMAL
11 * ¢
12 71
DETECTDRS
73 73
0$m1
-s c ,y ,.
e.,.n. H1 TEMPERATURE TRIP
75 Tsv Tow
Tsw Tsw (190 F> (DPENS DN TRIP)
75
PH]
PH] PH2 PH3
77
aT. .aT8
3 4 77
@= PANEL MUUNTED
79 * * . FUSE RATING/USE BASED DN CURRENT REQUIREMENTS 79
ale als a\e= DPTIDNAL
Figure I- 1. Sample Elementary Diagram, J Frame Drive vwth DCF8 Board (Sheet FC!
"I.15
1*Tv~"
GEH~6005 DC2000 Digital Adjustable Speed Drive
A B C D E F G H J K L M N P D R S
D1 SCR BRIDGE 01
601-1000vAF: 77mm CELLS
REVERSING
03 D3
D5 PI 05
l
he/ f
07 07
:DCFU1
r
I
09 TD DC D9
.>> L12 L14 L15 SNUBBER
11 11
Do as
13
15
_
1**
FU3 il-'U4
aus
FU7
* an
FUB
** I
FUll
BE * 4
FU12
* we
13
15
17 17
R R
[EE32] IP {EE36] CEE40J
19
rszauz w SER SCR
C2
[EE34] l SCR SCR
I [EE3B] l SCR
C6 19
21 5 IF 4R
R X
at 5R T R
3F
SCR
$7 BR
R
21
as w ls-e 113-16
l
a1-24 23
EEEBEJ rEE7D1` [EEN] A
25
27
(EE68]
R
I» [EE72] I' > [EE76]
R
1 l as
27
E9 E9
K1 [EDOS]
31
CT1
1
V
11 "=»--o [ED14]
Fuel
31
DC
{ED43} DUTPUT
33 [ED46] 33
I
POWER
35 35
INPUT [ED10]
37 PEIVER
KG I > I: o [ED16] 37
FUN
39 39
CT3 I' [ED12]
K3
41
'To |
IR [ED5D]
'¥'¥"_ D II n:n--o IEDIB5 41
FUN
43 Lensal I 43
R
[EE44] R 1» [EE4B] [EE52] R
45 R 45
[EE42I
V R w
11-4 EEE46] I 9-[2 EEESDJ l7-a0
47
SCR
"* 4F ¢ ?oR Q
SCR
5F
SCR
ER
SCR
so
SCR
OR 47
l i's
49
I 51 [EE54J
w / C1
R
[EESB]
w /
C3
[EE62]
w I
49
53
[EE56] R 1>
FU1 Fua
[EEED]
R
I FU5 rue
[EE64]R
FUN Fun
51
53 |
55 .'J ** ** an ale as ass I

** ace * ss I
57 57
59 59
L11 L13 L15
S] TO DC E1
SNUBBER
DCFU2
63 pa 63
s
65 65
67 67
c u \; » H1 TEMPERATURE ALARM
69 2Tsv me Trev ***2T;w!~ (170 F) 1 PENS DN ALARM)
69
PHI PHE PH3
ETB ETB
71 11 °Lz 71
THERMAL
DETECT RS
73 73
\.
s
H1 TEMPERATURE TRIP
75 Trev TSV TSV (190 r> ( PENS DN TRIP)
75
PHI PHE PH3
2TB 1 2T:B
77 3 J 4 77
= .PANEL MOUNTED
79 * * , . FUSE RATING/USE BASED N CURRENT REQUIREMENTS 79
alsale>¢= IIPTIDNAL .
Figure I- 7. Sample Elementary Diagram, J Frame Drive vwrn DCFB Board (Sheet FD)
1-16
J
DC2000 Digital Adjustable SpeedDrive GEH-6005
A 8 r: D E F G H J K 'L M N P Q R S
1.p.. 01
POWER CMNV5RT5R CUMPUN5NTS
01
FDR 77mm CELL SIZE
03 as'
D5 D5
SOOVAC 1000VAC 1500VAC
07 07
09 09
11 11
13 CS Cl.2,3.4,5,6 . CL2,3,4,S,6. c1.E.3,4,5,e.. 13

SCR D.25MFID 0.25MFD D.25MF3
SNUBBER
15 CAPACITDR 15
17 17
19 19
21 RS R1'2. 3-4, 5-6 R1-4, 5-e, 9-12.

R1-4, 9-12.
21
.
. SCR 7-8. 9-lu,
9-1IJ, 11-12 13-15, 17-e0, 21-24
SNUBBER
23 RESISTDR an o TDTAL ED O TDTAL
23
as 25
27 1 27
29 FU FUI-2. 3-4. 586, 7-B, FU1-2. 3-4, 5-6, 7-8. 29

LEG. 9°10.. 11-12
9°I0.. 9-lD, 11-12
FUSES
31 1250A EACH 1000A EACH
31
33 33
35 35
37 FU relax, as, as
rua; rual, 22, 23 Fu21 as, as 37
AC LINE 4A EACH 6A EACH
FILTER
39 FUSES 39
41 41
43 43
45 CA CEIM EEM23 EXTERNAL 45

AC LINE 0.25MFD C
FILTER D.25MFD
47 CAPACITDR 47
49 49
51 51
53 RA R2L 22.23 EXTERNAL 53

AC LINE 10 n
O TBTAL R
FILTER 20 n TUTAL
55 RESISTDRS 55
57 57
59 59
61 CD C30 EXTERNAL 61
DC LINE 0.5MFD
FILTER
63 63
65 65
67 67
69 RD
RD 31, 32
R30, 3L
RBC EXTERNAL
EXTERNAL
69
DC LINE ISD n
FILTER
71. TDTAL
Tl:ITAL 71
73 73
75 75
DC
SNUBBER NONE DCFU1, DCFUE
77 FUSE 77
SA EACH
79 79
Figure I- 1. Sample Elementary Diagram, J Frame Drive Vwth DCFB Board (Sheet FG)
1-17
1
D1 1
D1
DCEDDD LINK DCEUDO
03 SHPT MDA SHP1 MDA 03
P1 A PI
a; Tb |
go I _q
n F* " I 'M I
of.
v
|
II u U LE P1A(+) u P1A(+>
DS PDVER PDVER 05
CDNVER. CDNVER.
ASSEMBLY ASSEMBLY
07 CQNF LINK CDNF 07
C pa A P2
DO v u LJ L, pat-> x.. u pa(-> go
11 1 I 11
13 SHM1 MDB SHM1 MDB

A 13
go II '1I =»so» n
"1;
JI
°§ n Q u Q m1B(+) Q t41B(+>
15 DCEDDD LINK 0ca000 15
SHP1 MDA SHP1 MDA
17
PI
§ I A
'T I r~
A
r~
"T p1A<+>
PI `1 I L_, P1A{*) [7
PDVER PDVER
CDNVER. CDNVER.
19
2]
ASSEMBLY
CDNF n LINK
A
ASSEMBLY
CDNF.
19
21
PA
Q u v R) P2(")
F PA
v PE(-)
_I
9
23 23
LINK
25 25
I A I a I
27 °§§b °:§b ET
V
L. L- J m1s(+) » LJ m18<+)
DCEODD LINK DCEDU0
29 PI A PI 29
° s
°§ F I L. .; U P1A(+) I*
0?:x a%
0: »s> u P1A(+>
31 PDVER POWER 31
CDNVER. CDNVER.
ASSEMBLY ASSEMBLY
33 CDNF. LINK CDNF 33
P2
r*
A
r~
H pa
35 r°f pa-> 9 u. pa(-> 35
37 37
39 39
41 DC200D LINK DC200D 41

SHP1 MDB SHP1 MDB
A
to 1-
P1 r : P1
43 o=5 °I r~ V* r* p1A<+) of LE 1 L.. PiA(+> 43
PDVER PDVER
CDNVER. CENVER.
45 ASSEMBLY ASSEMBLY 45
CDNF. LINK CDNF.
47
J pa l
MDA
'1 l
A K PA
MDA
1*
47
L. I u u U pa-) u L» pa(-)
49
51
I I 49
51
53 53
DCEDDD LINK DCEDDD
55 SHP1 MBA $5
A
`1:
P1 PI
°§% L. v u LJ p1A(+) o- - _
o egg., Q P1A<+>
57 PDVER POWER 57
CDNVER. CHNVER.
CCINVER.
ASSEMBLY ASSEMBLY
59 CDNF LINK CDNF. 59
L pa A P2
61 LJ u u LJ pa(-> LJ u pa(-> 61
63 63
65 B5
67 iv
59 69
71 71
73 7
75 7
77 7
79 7
Figure I- 1. Sample Elementary Diagram, J Frame Drive Vwth DCF8 Board (Sheet FH)
1-18 s
APPENDIX J
ELEMENTARY DIAGRAM, J FRAME DRIVE WITH SDCI BOARD
J-1. INTRODUCTION Table J- 1. J Frame Drive Vwth soc/ Board

Elementary Diagram Sh set Summary
Figure 1-1 contained in this appendix provides a sample
elementary diagram for a J frame DC2000 Digital Ad- Sheet Description
justable Speed Drive that contains an SDCI board. Fig- BA .Ac power circuit.
ure J-1 was produced from GE drawing 246B2358AE.
BB Dc output.
On the elementary diagram, internal and external wire
numbers identify the elementary diagram sheet where BC CPT and CPTA connections.
that wire originates. For example, vidre number BC01
originates on sheet BC, line 01. BD Panel-mounted field supply.
NOTE BE Contactor drivers.
Drive elementary diagrams may change with .EA Control board interconnections.
EB, EC Ac and do feedbacks (SDCI
tary diagram contaihed in this appendix is
connections).
ED SHVI connections
Table J-1 summarizes the contents of each page of the
elementary diagram. Table 1-2 lists terminal board 2TB EE SCR gating (PCCA connections).
connections.
FA, FB SCR bridge.
FG Power converter components.
FH Motor connections.
J-1
Table J-2. Terminal Board 2TB Connections,

J Frame Drive With SDC/ Board
1,2 Not connected.

5-8 Not connected.
9 Voltage feedback, motor A ( + ) ; high-voltage terminal board for voltages greater than 600 V.
10 Voltage feedback, motor A (-); high-voltage terminal board for voltages greater than 600 V.
14 CPT 115 v.
15 Current feedback, motor A ( + l : high-voltage terminal board for voltages greater than 6OO V.
16 Current feedback, motor A (-). high-voltage terminal board for voltages greater than 600 V.
17 Blower switch.
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
22 Field A shunt ( - ) .
I
J-2
I D1 D1
03 D3
05 D5
07 07
M pgvgn qzngurr
09 *DSV* * *K xx Alex 09
F-[A44] [BC01] [8D353
L1 '; K1 P1
11 , [B812] 11
I
PGWER
13 I
I
** .ass we x an
I-[A46] I81)37][8€03]
CONVERTER
13
L2 I K2
15 ~:
I
*. -{Z>+<- 15
I
| FDR DETAILS
17
19
L3 n c
|
s
I
vEK*B] K3
SEE
SHEETS
FA-FB PA
EBBEBII
17
19
21 21
E3 23
25 25
27 27
E9 29
31 31
33 33
35 35
37 37
I
I
39 39
I
41 41
c N ERTER CE 'ING 3 PHASE CDNTRUL P0 ER (230, 460. UR 575 VAC)
43 xx 43 |
cAm 9
45
47
xx
(:1151
asks
LA19J
I
i
0
E
I l
45
47
49 l I 49
_8p BF BF .BF BF BF BF BF BF
51 L 1 a 3 F1
1-
a 3 1 E ~3 51
\
53 53
55 xxx *areas as * * 55
BLDVER BLEIVER BLDWER
1 2 3 ZTB 51
57
17ccA51J
Le
59 59
ETB
PTIDNAL ETB ETB 1
61 FANS so 1 ;
r. [C s4:s1
A ~°--°DQ A
FAN 1 BLVR1 BLVR2 BLWR3
63 63
EENTRIFICAL swiTcH
FAN 2 (CLDSES HEN BL ER
65 IS RUNNING) 65
FAN 3
67 nu: 67
69 69
71 71
CDNTR L P0 ER MAY E ME FR M KL2.3 ii LTAGE ACCEPTABLE DR DESIRED.
73 THER ISE lLL BE SEPARATELY FED TO TDP DF BL ER AND CPT FUSES. 73
ax- an * = DPTIDNAL
75 75
PANEL MOUNTED
77 77
79 79
Figure J- 1. Sample Elementary Diagram, J Frame Drive Vwth SDC/ Board (Sheet 8A)
J-3
A 8 C D E F
5° H J K L M N P Q R s
01 D1
03 03
05 05
07 07
DC QQTPQT Ml',ITFIR A
DO DO
SHP] BKBEBK P1A
11
13
CBA11]
PI
L ,
|
SHA
v' I MBA
11
EBELSJ
v
1]
13
15
v [EB55] [ ale an ] [EDEN 15
MDTDR A
E
17 [EB53] 17
19 E ** J [BD37]
19
21 21
23 23
as as
E7 EH 3 27
P2
:BAt9J
29 29
31 31
33 33
35 35
37 37
39 39
41 4
43 4
45 4
47 4
49 4
51 5
53 5
55 5
57 5
59 5
61 6
63 SEE SHEET UIFH FOR PDSSIBLE MGTDR CDNFIGURATIDNS 6
65 6 i
67 s
69 sI
71 7l
73 7l
75 * * . 2TB9 AND aTB10 ARE VIRED TD P1.Pa on MDTDR ARMATURE 7>

DEPENDING DN INSTRUMENTATIDN REQUIREMENTS.
77 *** s UPTIDNAL 7 |
79 7?
I
Figure J- 1. Sample Elementary Diagram, J Frame Drive win SDC/ Board (Sheet B8)
J-4
as an CPT AND CPTA CDNNECTIDNS
0x [BA111 D1
an
[8A151
*
03 03
05 D5
I
07
DO
T
r 1'
CPTFU1
é L
CPTFUE
Ii'
pTnrul
c if
CPTAFU2
07
09
11 11
13 13
*
15 * <->>- 15
7
6
17 17
annex
19 EPTAX '-'10 9 7 *Ne 19
CPTX "'10 9 7 1a
I
v
21 21
23 8{w. A B/R B/Y 8

B/W B/R B/Y 8
23
23UVAC 230VAC
25 230vAC 230VAC CPTA 25
CPT
27 27
29 29
.
-=*=-181
E
f 1 1 1
1;
I
R y XRs 11sv BL/W R/Y 8nw

ii
31 4.6A 2 8 115V 31
4.sA
*1 2
33 4
33
CPTFU3 CPTAFU3
35 35
I i :n
A A A
A A A qgn
37
[EC40]
39
_ CPTPL
CPTPL
s 4 5 1 2 [BE27]
4
[BEE9]
aTB
31
aTs
32
37
39
41 41
43 43
45 45
47 47
49 49
51 * 46DVAC CDNNECTIDNS SHDVN ABDVE

FDR a3ovAr: - REMDVE CDNNECTING _JUMPER
51
53
.
BETWEEN 9-7. CDNNECT AS FOLLEVS= _
- 9 TO BDTTDM FUN DN BDTH $3
- 7 TD BDTTDM FU1 CPT AND CPTA_
55 55
$7 57
59 59
soovAc CPT PIRMARY
61
Q Q
61
I2
CDNNECTIDNS
CPTAFu2
63 CPTFU1 cprFua CPTAFU1 63
ID 1a 1D
65
T8/y~ |
T, Tm. 65
67 CPT CPTA 57
69 69
* X CDNNECTIDNS TD FUL2 DPTIDNAL-BEPENDING DN VDLTAGE
71 11
73
*** DPTIDNAL
73
75 75
77 77
79 7g
Figure J- 1. Sample Elementary Diagram, J Frame Drive With SDC/ Board (Sheet BC)
J-S
01 01
03 03
05 D5
07 *Alex
PANEL MDUNTED FIELD SUPPLY 07
09 09
11 11
13 13
15 15
NRX 75P»
17 17
1FPLX »¢F'$A
19
21
eases:
_ (L -
_
2
INTERNAL
M
TB1
wQi
2
NT
FPL-1
EXTERNAL
MUUNT
n P1G1
r
SH
1r=.,E FP
»'
.
TBA
[BB15J
19
21
E3
f?
-<(3
*fr-
*or
(3
- K
I':
13
16
rPL-2
FPL-3
[` P1C1
D N261 I
f
I
E3
I
-<(5
--((5
I
1§
1; FPL-4 \ NECI I
25 -<<6
-.is I rPL~5 P P2G1 I
r
25
-4;7
-47 P2C1 I
FPL-6
27 -<<B
€B
is FPL-7
'N
N151 1
I
'\
r E7
29
\_-<<9
-<€9
\-up
-<<10 ARE
A 'é§ • FPL-B
PIG
N n1r:1
I
I
I
ET
\-a11
-'n *'52v 2
V
PIC
I
I
I
7O
31 \-412 NIE DC
-<<1a
-(<
52 S § NIC
I
,r
DUTPUT
31
A I
I
33 f 33
f
*ale T84 FU1 f
.
AC INPUT
.
35 [BA11] 9 in AC4 I 35
v1:LTs
37
**
EBA15J
TB4 FU2
l_'__*'
AC5 soovAl: I
/
/
J'
FN TB4
[BBED] 37
MAX I
.1
39 I
R TB]-1 I 39
I
[EB48] + SP
11
1 *. r
41 CEB50] v r
T81-2
.. SN ) SHUNT FBK 41
43 43
45 45
47 47
49 49
51 51
$3 53
55 55
57 57
59 59
61 61
63 63
65 65
67 57
69 69
71 71
73 73
75 75
77 77
79
* * * gpT10NAL as ale = FIELD SUPPLY PDWER FRDM KLK2 IF VDLTAGE ACCEPTABLE DR IF DESIRED 79
Figure J- 1. Sample Elementary Diagram, J Frame Drive vwzn SDC/ Board (Sheet BD)
J-6
A B c D E F G H J K L M N P D R s
D1 QQNTAQTQR DRIVERS
MAY BE EITHER HIGH BR LDV SPEED VERSION D1
03
03
D5
05
07 QDNTAQTIJR nR;v§R FHR MBA *** 07
09
as
11 CDBA DR CPCA xx MDA
11
MACPL MPL 1TB
13 R x1
[EB4-3] no r - - - 5 3 13
I
| I
I
(
24V l"-°
W :we
15 I I 6
w e PSN I T' 4 15
[EB45] I |
---4--<
17 ! I
!
A
|
I
l
|
I
I
I
\(
7 5 17
19
1TB
,_.1
1
" 1
I
I
I
I
!
I Ia
L_.
I
I
I
i 1
I
I
4
8
I L/
6 19
21 I !
I
I
I
I
1
<<
9
| 7 21
[_.,@ PSP I
an E I I I J. 1 LJ
E3 I I r~ -_ _ I
-C I I I I I N 8 23
n
11 CPH
I
I
I
I
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Figure J- 1. Sample Elementary Diagram, J Frame Drive vwtn SDC/ Board (Sheet FH/
J-16
APPENDIX K
ELEMENTARY DIAGRAM, K FRAME DRIVE
K-1. INTRODUCTION NOTE
Figure K-1 contained in this appendix provides a sample Drive elementary diagrams may change with
elementary diagram for a K frame DC2000 Digital product upgrade and revisions. The elemen-
Adjustable Speed Drive. The drive shown is a 6-pulse tary diagram contained in this appendix is
lineup with one master drive andIve follower drives current as of the issue date of this mamial.
(no control redundancy). Figure K-1 was produced
from GE drawing 246B2359AA. Note that elementary diagram sheet numbers beginning
with 01 apply to the master drive, sheet numbers be-
On the elementary diagram, internal and external wire ginning with 02 apply to the #2 drive, and so on. Be-
numbers identify the elementary diagram sheet where cause the follower drives (drives #2 through #6) are
that wire originates. For example,.wire number identical, only the elementary diagram sheets for the
01BA04 originates on sheet 01BA, line 04. master drive (dive #1) and drive #2 are included in this
appendix.
K-1
GEH-6005 DC2000 Due: Adjustable Speed Drive
BRIDSE _AYDUT
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K-2
\
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Figure K- 1. Sample Elementary Diagram, K Frame Drive (Sheet oo,4.4/
K-3
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Figure K- 7. Sample Elementary Diagram, K Frame Drive (Sheet O 18A)

K-4
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K-S
GEH-6005 DC2000 Digital Aqiusrable Speed Drive
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K-6
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K-7
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GEH-6005
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O2BC)
K-9
Notes:
K-10
APPENDIX L
ELEMENTARY DIAGRAM, M FRAME DRIVE WITH DCFB BOARD
L-1 . INTRODUCTION Table L- 1. M Frame Drive With DCF8 Board

Figure L~l contained 'm this appendix provides a sample
elementary diagram for an M frame DC2000 Digital Sheet Description
Adjustable Speed Dive that contains a DCFB board. BA Ac power circuit.
Figure L-1 was produced from GE drawing
246B2388AA. BB Dc output.
on the elementary diagram, internal and external wire BC CPT and CPTA connections.
that wire originates. For example, wire number BC01 BD Internal core-mounted field supply.
originates on sheet BC, line 01.. -
NOTE
EB, EC Ac and do feedbacks ¢DCFB
product upgrades and revisions. The elemen- -
connections).
current as of the issue date of this manual. ED SHVM connections
Table L-1 summarizes the contents of each page of the EE SCR gating (PCCA connections).
elementary diagram. Table L-2 lists terminal board 2TB
connections. FA - FD SCR bridge.
\
I
L-1
Table L-2. Terminal Board 2TB Connections,

M Frame Drive Vwth DCFB Board
1. Field A de ( + ) .
2 Field A do (-}_
3 Thermal switch, 190°
5 Field ac in.
6 Field ac in.
7 Field ac in.
8 Not connected .
9 Voltage feedback, motor A ( + ) ; high -voltage terminal board for voltages greater than 600 V.
10 Voltage feedback, motor A (-); high -voltage terminal board for voltages greater than 600 v.
t1 Thermal switch, 170° - optional.
12 Thermal Switch, 170° - optional.
1.3 CPT 1 t 5 v ground.
14 CPT 115 v.
15 Current feedback, .motor A (1 +), high-voltage terminal board for voltages greater than 600
v.
16 Current feedback, motor A.(2), high-voltage terminal board for voltages greater than 600 V.
17 Blower switch-
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
21 Field A shunt (1 + ) .
22- Field A shunt (2).
23 Voltage feedback, motor B ( + ) ; high-voltage terminal board for voltages greater than 600 V.
24 Voltage feedback, motor B (-); high-voltage terminal board for voltages greater than 600 v.
25 Current feedback, motor B ( t + ); high-voltage terminal board for voltages greater than 600
v. .
26 Current feedback, motor B (2), high-voltage terminal board for voltages greater than 600 v.
27 MDB coil driver.
28 MDB coil driver.
29 Field B shunt (1 +~)-
30 Field B shunt (2).
31 CPTA 1 15 V ground.
32 CPTA 1 15 .v.
33 - 36 Not connected.
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Figure L- 7 . Sample Elementary Diagram, M Frame Drive wth DCF8 Board (Sheet ED/
L-11
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L-12
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GEH-6005
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Figure L- 1. Sample Elementary Diagram, M Frame Drive With DCF8 Board (Sheer FA)
L-13
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Figure L- 7. Sample Elementary Diagram, M Frame Drive nth DCFB Board (Sheet FB;
L-14
GEH-6005
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Figure L- 7. Sample Elementary Diagram, M Frame Drive Vwth DCF8 Board (Sheet FC)
L-15
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an SCR BRIDGE
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Figure L-7. Sample Elementary Diagram, M Frame Drive Vwth DCFB Board (Sheet FD)
DC2000 Digital Adjustable SP€€d Drive
GEH-6005
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79
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Figure L- 1. Sample Elementary Diagram, M Frame Drive
Vwth DCF8 Board (Sheet FG/
L-17
Notes:
L-18
APPENDIX M
ELEMENTARY DIAGRAM, M FRAME DRIVE WITH SDC! BOARD
m-1. INTRODUCTION Table M- 7. M Frame Drive Vwth SDC/ Board

Figure M-1 contained in mis appendix provides a sam-
ple elementary diagram for an M frame DC2000 Do Sheet Description
Digital Adjustable Speed Drive that contains an SDCI BA Ac power circuit.
board. Figure M-1 was produced from GE drawing
246B2388AB . BB Do output.
that wire originates. For example, wire number BC01 BD Internal core-mounted field supply.
originates on sheet BC, line 01.
NOTE
product upgrades and revisions. The elemen- EB, EC Ac and do feedbacks (SDCI
connections).
current as of the issue date of this manual. ED SHVM connections
Table M-1 summarizes the contents of each page of the EE SCR gating (.PCCA connections).
elementary diagram. Table M-2 lists rernninalboard
2TB connections. FA, FB SCR bridge.
M-1
Table M-2. Terminal Board 2T8 Connections,

M Frame Drive With SDC/ Board
2 Field A do (-)-
4 Thermal switch, 190°,
5 Field ac in.
6 Field ac in.
7 Field ac in.
8 Not connected.
9 Voltage feedback, motor A l + ) : high-voltage terminal board for voltages greater than 600 V.
10 Voltage feedback, motor A (-); high-voltage terminal board for voltages greater than $00 V.
13 CPT 1 15 V ground.
14 CPT 1 15 v.
15 Current feedback, motor A (1 +); high-voltage terminal board for voltages greater than 600
v.
16 Current feedback, motor A (2), high-voltage terminal board for voltages greater than 600 v.
17 Blower switch.
18 Blower switch.
19 MDA coil driver.
20 MDA coil driver.
21 Field A shunt (1 +).
22 Field A shunt (2).
23 - 30 Not connected.
31 CPTA 1 15 V ground.
32 CPTA 1 15 v.
3.3 36 Not connected.
M-2
DC2000 Digital Adjustable Speed Dirive GEH-6005
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Figure M- 1. Sample Elementary Diagram, M Frame Drive vwth SDC/ Board (Sheet BA)
M-3
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Figure M- 7. Sample Elementary Diagram, M Frame Drive with SDC/ Board (Sheet BB)
M-4
GEH-6005
A 8 C D E F E H J K L M N P s
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Figure M- 1. Sample Elementary Diagram, M Frame Drive Vwth SDC/ Board (Sheet F8)
M-14
GEH-6005
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Figure M- 1. Sample Elementary Diagram, M Frame

Drive Vwtn SDC/ Board (Sheet FG)
M-15
Notes:
M-16
\ APPENDIX N
I
PERIODIC MAINTENANCE
n-1. INTRODUCTION l
CAUTION l
Because the DC2000 drive has no moving pans except

for relays, contactors, fans, and blower motors, mini-
mum preventive maintenance is required. This appendix Do not use high-pressure comprised air to
provides recommended periodic maintenance for the remove dust and dirt, as this may damage
equipment. components.
3. Inspect cabinet air alters, if equipped. Shake tilters

WARNING clean or replace, as required.
u
4. Check rightness of all electrical and mechanical

The equipment contains a potential hazard of connections. Tighten or replace any crimp-style
electric shock or burn. Only adequately lugs that have loosened during operation. Tighten
trained personnel who are thoroughly famil- or replace all loose or missing hardware.
iar with the equipment and the instructions
should maintain the equipment. 5. Inspect wiring for wear (fraying, chipping, or
nicks). Repair minor defects with a good grade of
electrical tape, or replace if necessary.
N~2. PREVENTIVE MAINTENANCE
6. Inspect printed wiring board plugs, wiring, and
COIIIICCIZOIS IO CIISUIG correct searing.
Preventive maintenance helps prevent, detect, and cor-
rect conditions that could cause equipment malfunction.
7. Inspect fans and blower motors (if equipped) for
It includes inspections for damage and wear, tests, and
correct operation and rotation. Ensure that air pas-
cleaning of equipment at regular intervals.
sages are clear. Section N-3 provides information
The schedule for preventive maintenance depends on the life expectancy of the cooling fans used in
the equipment.
largely upon the environmental conditions around the
equipment. As a guide, it is suggested that preventive
8. Inspect contacts on open (as opposed to sealed)
maintenance be performed at least once every two
contactors and relays. Discoloration and rough
months in bad environments; and on scheduled shut-
contact surfaces are normal. Refer to the compo-
downs in good environments.
nent publication supplied with the equipment for
further information.
The following functions should be performed at regular
intervals.
If beads formed caused by severe arcing, dress the
contact faces with a fine file. Do not use sandpaper
1. Turn off all power to the equipment to be in-
or emery cloth to dress the contacts, and never oil
spected and maintained. Test equipment using
any pan of the power unit. Identify and eliminate
multimeter to ensure that power is off.
the cause of the arcing.
2. Using a vacuum cleaner with a non-metallic nozzle
or low-pressure dry compressed air, remove dust
and dirt from cabinets and electrical components .
N-1
N-3. COOLING FANS Note that in earlier units, the Muffin Mn5 used were
equipped with sleeve bearings. The life expectancy of
The drive may include cooling falls for the printed wir- these fans is considerably less than that of fans equipped
ing boardenclosuxes and heatsinks. Muffi1n° fans are with ball bearings. For example, at 20 °C, 90% of
typically used to cool the board enclosures, while Tar- muffin fan units with sleeve bearings are expected to be
zan° fans are typically used to cool the heatsinks. operating after approximately 90000 hours (approxi-
mately 10.3 years) of continuous duty. At 50 °C, 90%
The life expectancy of these fans is determined by the of the units are expected to be running after approxi-
ambient temperature. The ions are rated at the continu- mately 40000 hours (approximately 4.5 years) of con-
ous duty life (in hours), after which 90% of the units dnuous duty.
continue to operate at a given ambient temperature .
For Tarzan fans, at 20 °C, 90% of the units are ex-
For example, at an ambient temperature of 20 °C pected to be operating after approximately 42500 hours
(68 °F), 90% of Muffin fan units with ball bearings are (approximately 4.9 years) of continuous duty. At 50 °C
expected to be operating after approximately 95000 (122 °1=), 90% of the units are expected to be running
hours (approzdmately 10.8 years) of continuous duty. after approximately 18000 hours (approximately 2.1
At SO °C (122 °F), 90% of the units are expected to be years) of continuous duty .
running after approximately 70000 hours (approxi-
mately 8.0 years) of continuous duty .
N-2
i
APPENDIX o
WARRANTY PARTS AND SERVICE
.
O-1 WARRANTY TERMS O-2. OBTAINING PARTS AND SERVICE UNDER
WARRANTY ,
The GE Drive Systems Terns and Conditions brochure
details product warranty information, °mcludLing the To obtain warranty replacement parts or service assis-
Warranty period and parts and service coverage. tance, contact the nearest GE Service Office .
The brochure is included with the customer documenta- Please have the following information ready to exactly
tion. In may also be obtained separately from the nearest identify the part and application:
.
GE Sales Office or authorized GE Sales Representative
. GE requisition number
. Drive serial number and model number
Pan number and description
0-1
Notes:
GE Motors &
Industrial Systems
Industrial Systems-
Drivo Systems & Turbine Controls
Genet# E7ectric Company
1501Haanoke Boa/evard
Salem, VA 24153-6499 USA
T01
Industrial Systems-
Drive Systems & Turbine Controls
Header Commonis General Electric Cunpany
Technical Publications, Roan 191
1501 Roanoke Blvd.
Genera/ Henri: Emmy
We welcome comments and suggestions to make this publication more usefuL

Name 'Telephone Number
Company Name Fax Number
Address Job Site
ICE Requisition Number
Publication No. Issue Revision Date lTuday's Date

l
GFNERAL cnmmEmTs'
ExceIIent G0od FaI r Poor
Contents O O o O
Organization O O o o
Technical accuracy o o o O
Clarity O O O o
Completeness O O O o
Drawings, figures, and tables o o O o
Referencing and tables of contents o O O O
Readability o O o O
SPECIFIC COMMENTS.(Correctinns, information that could be expanded, and so on)
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Other suggestions for improving this publication:
As compared to publications from other mandacturers of similar products, how would you tate this document?
O Superior O Comparable O Inferior O Do not know
Indicate the type of userlreader function that best describes you:

O System Integrator O llistributur o OEM O lnsiallatinn
O Programmer O Maintenance o Dperator O Other {please specify)
Detach, told, and mail.

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Place
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Drive Systems & Turbine Controls
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....

Operation and Mainten

Gperation and Maintenance

Printed in the United States of America.

ARCNET is a registered trademark of Datapolmt Corporation.

SAFETY SYMBOL LEGEND

Section/Subject Page Section/Subject Page

CHAPTER 1. OVERVIEW 4-4. Controller Operation.......................... ......4-2 .

TABLE OF CONTENTS Continued

Section/Subject Page SeetionlSubject Page

6-18. STBA Board I/O .................................. 6-36

5-4.16.1. Configurable Hardware............... 5-40

TABLE OF CONTENTS Continued

Section/Subject Page Section/Subject Page

7-6.7 SDCI Board Testpoints..........................7-14

10-3.1. CLST Blocks .......... .. . 10-2

10-4. LCP History Buffer .............................. 10-4

8-3.2. Using the Drive Contigurator........... 8-2

11-2. Replacing Boards .............................. 11-1

11-3.2.1. Removing Defective SCR .................. 11-3

TABLE OF CONTENTS Continued

SectionlSubiect Page Section/Subject Page

APPENDIX D. HARDWARE DRAWINGS, APPENDIX K. ELEMENTARY DIAGRAM,

APPENDIX E. ELEMENTARY DIAGRAM, APPENDIX L. ELEMENTARY DIAGRAM,

APPENDIX F. ELEMENTARY DIAGRAM, APPENDIX M. ELEMENTARY DIAGRAM,

APPENDIX G. ELEMENTARY DIAGRAM, APPENDIX n. PERIODIC MAINTENANCE

APPENDIX J. ELEMENTARY DIAGRAM,

Figure Page Figure Page

5-21• SPCB Card Layout................................5-46 C-1. J and K Frame Hardware Drawing

D-1. M Frame Hardware Drawing 336A3509 D-2

F-l. Sample Elementary Diagram, C or CX

Table Page Table Page

LIST OF TABLES Continued

Table Page Table Page

Elementary Diagram Sheet Summary 1-1

1-2. Terminal Board 2TB Connections, J Frame

1-1. DEFINITION AND SCOPE Chapter 8 - Software Adjustments

Appendix E - Elementary Diagiram, C or CX Frame Appendix 0 - Warranty Parts and Service

The power converter section consists of an SCR bridge -

RECEIVING, HANDLING, AND STORAGE

2-1. INTRODUCTION If assistance is needed, contact:

This chapter contains guidelines and precautions for Industrial Systems-

d. No rodents. 2-4. UNPACKING

CAUTION 2-5. TIME LIMITATIONS

The above specifications apply to shipping and storage

INSTALLATION AND INITIAL STARTUP

3-1 . INTRODUCTION . Electromagnetic radiation or noise introduced by:

Ambient temperature range: 0 °C (32 °F) to

Vibration or shock 3-4. CABLING AND WIRING

. Rapid temperature changes

. Power line fluctuations

Nominal line frequency: 50 or 60 Hz, i2% 3-4.3. Wiring Level Separations

To prevent signal interference caused by electrical

• High-level signals (Level H), which consist of de 3-4.6. Commons

The following requirements ensure correct distance

For distances up to 4 feet, maintain a minimum

Fuse information and nomenclature

• Within pillboxes and junction boxes, use grounded

1/4-20 4 a. Check that the motor and controller voltages