UNIT I

BASIC STRUCTURE OF COMPUTERS

 Functional units

 Basic operational concepts

 Bus structures

 Performance and metrics

 Instructions and instruction sequencing

 Hardware

 Software interface

 Instruction set architecture

 Addressing modes

 RISC

 CISC
BASIC STRUCTURE OF COMPUTERS:
Computer Organization:

It refers to the operational units and their interconnections that realize the
architectural specifications.
It describes the function of and design of the various units of digital computer that
store and process information.

Computer hardware:

Consists of electronic circuits, displays, magnetic and optical storage

media, electromechanical equipment and communication facilities.

Computer Architecture:

It is concerned with the structure and behaviour of the computer.

It includes the information formats, the instruction set and techniques for
addressing memory.

Functional Units

A computer consists of 5 main parts.

Input
Memory
Arithmetic and logic
Output
Control Units

Functional units of a Computer

 Input unit accepts coded information from human operators, from
electromechanical devices such as keyboards, or from other computers
over digital communication lines.
The information received is either stored in the computers memory for
later reference or immediately used by the arithmetic and logic circuitry to
perform the desired operations.
The processing steps are determined by a program stored in the memory.
Finally the results are sent back to the outside world through the output
unit.
All of these actions are coordinated by the control unit.
The list of instructions that performs a task is called a program.
Usually the program is stored in the memory.
The processor then fetches the instruction that make up the program from
the memory one after another and performs the desire operations.

1.1 Input Unit:

 Computers accept coded information through input units, which read the
data.
 Whenever a key is pressed, the corresponding letter or digit is
automatically translated into its corresponding binary code and transmitted
over a cable to either the memory or the processor.
Some input devices are
 Joysticks
 Trackballs
 Mouses
 Microphones (Capture audio input and it is sampled & it is
converted into digital codes for storage and processing).
1.2.Memory Unit:
It stores the programs and data.
There are 2 types of storage classes
 Primary
 Secondary
Primary Storage:
It is a fast memory that operates at electronic speeds.
Programs must be stored in the memory while they are
being executed.
The memory contains large no of semiconductor storage
cells.
Each cell carries 1 bit of information.
The Cells are processed in a group of fixed size called
Words.
To provide easy access to any word in a memory,a distinct
address is associated with each word location.
 Addresses are numbers that identify successive locations.
The number of bits in each word is called the word length.
The word length ranges from 16 to 64 bits.
There are 3 types of memory.They are

 RAM(Random Access Memory)

 Cache memory
 Main Memory

RAM:
Memory in which any location can be reached in short and fixed amount of time
after specifying its address is called RAM.
Time required to access 1 word is called Memory Access Time.

Cache Memory:

The small,fast,RAM units are called Cache. They are tightly coupled with
processor to achieve high performance.

Main Memory:
The largest and the slowest unit is called the main memory.

1.3. ALU:
Most computer operations are executed in ALU.
Consider a example,
Suppose 2 numbers located in memory are to be added. They are brought
into the processor and the actual addition is carried out by the ALU. The sum may then
be stored in the memory or retained in the processor for immediate use.
Access time to registers is faster than access time to the fastest cache unit in
memory.
1.4. Output Unit:
Its function is to send the processed results to the outside world. eg.Printer
Printers are capable of printing 10000 lines per minute but its speed is
comparatively slower than the processor.

1.5. Control Unit:

The operations of Input unit, output unit, ALU are co-ordinate by the
control unit.
The control unit is the Nerve centre that sends control signals to other
units and senses their states.
Data transfers between the processor and the memory are also controlled
by the control unit through timing signals.
The operation of computers are,
 The computer accepts information in the form of programs and
data through an input unit and stores it in the memory.
  Information stored in the memory is fetched, under program
control into an arithmetic and logic unit, where it is processed.
 Processed information leaves the computer through an output unit.
 All activities inside the machine are directed by the control unit.

BASIC OPERATIONAL CONCEPTS:

The data/operands are stored in memory.

The individual instruction are brought from the memory to the processor, which
executes the specified operation.

Eg:1 Add LOC A ,R1

Instructions are fetched from memory and the operand at LOC A is fetched. It is then
added to the contents of R0, the resulting sum is stored in Register R0.

Eg:2
Load LOC A, R1

Transfer the contents of memory location A to the register R1.

Eg:3
Add R1 ,R0

Add the contents of Register R1 & R0 and places the sum into R0.
Fig:Connection between Processor and Main Memory
Instruction Register (IR):

 It holds the instruction that is currently being executed.

 It generates the timing signals.

Program Counter (PC):

It contains the memory address of the next instruction to be fetched for execution.

Memory Address Register (MAR):

It holds the address of the location to be accessed.

Memory Data Register (MDR):

 It contains the data to written into or read out of the address location.
 MAR and MDR facilitates the communication with memory.

Operation Steps:

 The program resides in memory. The execution starts when PC is point to the first
instruction of the program.
 MAR read the control signal.
 The Memory loads the address word into MDR.The contents are transferred to
Instruction register. The instruction is ready to be decoded & executed.

BUS STRUCTURES:

A group of lines that serves as the connection path to several devices is called a
Bus. A Bus may be lines or wires or one bit per line.
The lines carry data or address or control signal.

There are 2 types of Bus structures. They are

Single Bus Structure
Multiple Bus Structure
 3.1.Single Bus Structure:

It allows only one transfer at a

time. It costs low.
It is flexible for attaching peripheral
devices. Its Performance is low.

3.2.Multiple Bus Structure:

It allows two or more transfer at a

time. It costs high.
It provides concurrency in
operation. Its Performance is
high.

Devices Connected with Bus Speed

Electro-mechanical decvices
(Keyboard,printer) Slow

Magnetic / optical disk High

Memory & processing units Very High

The Buffer Register when connected with the bus, carries the information during
transfer. The Buffer Register prevents the high speed processor from being locked to
a slow I/O device during a sequence of data transfer.

PERFORMANCE:

For best performance, it is necessary to design the compiler, machine instruction

set and hardware in a co-ordinate way.

Elapsed Timethe total time required to execute the program is called the elapsed time.
It depends on all the units in computer system.
Processor TimeThe period in which the processor is active is called the processor time.
It depends on hardware involved in the execution of the instruction.

Fig: The Processor Cache

A Program will be executed faster if the movement of instruction and data

between the main memory and the processor is minimized, which is achieved by using
the Cache.

Processor clock:

ClockThe Processor circuits are controlled by a timing signal called a clock.

Clock CycleThe cycle defines a regular time interval called clock cycle.

Clock Rate,R =1/P

Where, PLength of one clock cycle.

Basic Performance Equation:

T = (N*S)/R

Where, TPerformance Parameter

RClock Rate in cycles/sec
NActual number of instruction execution
SAverage number of basic steps needed to execute one machine instruction.
To achieve high performance,

N,S<R

Instruction Set: CISC AND RISC:

The Complex instruction combined with pipelining would achieve the best
performance.
It is much easier to implement the efficient pipelining in processor with simple
instruction set.

Simple
Simple Instruction
Instruction set
Set

RISC
RISC CISCCISC

(Reduced Instruction Set Computer) (Complex Instruction Set Computer)

It is the design of the instruction set It is the design of the instruction set
of a processor with simple instruction of a processor with complex instruction.

High level
Machine
Language Compiler
Program instruction
Translated into
INSTRUCTION AND INSTRUCTION SEQUENCING

A computer must have instruction capable of performing the following operations. They
are,

 Data transfer between memory and processor register.

 Arithmetic and logical operations on data.
 Program sequencing and control.
 I/O transfer.

Register Transfer Notation:

The possible locations in which transfer of information occurs are,

Memory Location
Processor register
Registers in I/O sub-system.

Location Hardware Binary Eg Description

Address
Memory LOC,PLACE,A,VAR2 R1[LOC] The contents of memory
location are transferred
to. the processor register.
Processor R0,R1,…. [R3][R1]+[R2] Add the contents of
register R1 &R2 and
places .their sum into
register R3.It is
.called Register Transfer
Notation.
I/O Registers DATAIN,DATAOUT Provides Status
information

Assembly Language Notation:

Assembly Language Description

Format
Move LOC,R1 Transfers the contents of memory location to the processor
register R1.

Add R1,R2,R3 Add the contents of register R1 & R2 and places their sum
into register R3.
 Basic Instruction Types:
Instruction Syntax Eg Description
Type
Three Address Operation Add A,B,C Add values of variable
Source1,Source2,Destination A ,B & place the result
into c.
Two Address Operation Source,Destination Add A,B Add the values of A,B
& place the result into
B.
One Address Operation Operand Add B Content of
accumulator add with
content of B.

Instruction Execution and Straight–line

Sequencing: Instruction Execution:
There are 2 phases for Instruction Execution. They are,

 Instruction Fetch
 Instruction Execution
Instruction Fetch:
The instruction is fetched from the memory location whose address is in PC.This is
placed in IR.
Instruction Execution:
Instruction in IR is examined to determine whose operation is to be performed.
Program execution Steps:

To begin executing a program, the address of first instruction must be placed in

PC.
The processor control circuits use the information in the PC to fetch & execute
instructions one at a time in the order of increasing order.
This is called Straight line sequencing.During the execution of each
instruction,the PC is incremented by 4 to point the address of next instruction.
Fig: Program Execution

Branching:

The Address of the memory locations containing the n numbers are symbolically
given as NUM1,NUM2…..NUMn.
Separate Add instruction is used to add each number to the contents of register
R0.
After all the numbers have been added,the result is placed in memory location
SUM.
Fig:Straight Line Sequencing Program for adding ‘n’ numbers

Using loop to add ‘n’ numbers:

Number of enteries in the list „n‟ is stored in memory location M.Register R1 is

used as a counter to determine the number of times the loop is executed.
Content location M are loaded into register R1 at the beginning of the program.
It starts at location Loop and ends at the instruction.Branch>0.During each
pass,the address of the next list entry is determined and the entry is fetched and
added to R0.

Decrement R1
 It reduces the contents of R1 by 1 each time through the loop.

Branch >0 Loop

A conditional branch instruction causes a branch only if a specified condition is

satisfied.

Fig:Using loop to add ‘n’ numbers:

Conditional Codes:

Result of various operation for user by subsequent conditional branch instruction

is accomplished by recording the required information in individual bits often called
Condition code Flags.

Commonly used flags:

  N(Negative)set to 1 if the result is –ve ,otherwise cleared to 0.
 Z(Zero) set to 1 if the result is 0 ,otherwise cleared to 0.
 V(Overflow) set to 1 if arithmetic overflow occurs ,otherwise cleared to 0.
 C(Carry)set to 1 if carry and results from the operation ,otherwise cleared to 0.

ADDRESSING MODES

The different ways in which the location of an operand is specified in an instruction is

called as Addressing mode.

Generic Addressing Modes:

 Immediate mode
 Register mode
 Absolute mode
 Indirect mode
 Index mode
 Base with index
 Base with index and offset
 Relative mode
 Auto-increment mode
 Auto-decrement mode

Implementation of Variables and Constants:

Variables:

The value can be changed as needed using the appropriate instructions.

There are 2 accessing modes to access the variables. They are

 Register Mode
 Absolute Mode

Register Mode:

The operand is the contents of the processor register.

The name(address) of the register is given in the instruction.

Absolute Mode(Direct Mode):

The operand is in new location.

The address of this location is given explicitly in the instruction.
Eg: MOVE LOC,R2

The above instruction uses the register and absolute mode.

The processor register is the temporary storage where the data in the register are accessed
using register mode.
The absolute mode can represent global variables in the program.

Mode Assembler Syntax Addressing Function

Register mode Ri EA=Ri

Absolute mode LOC EA=LOC

Where EA-Effective Address

Constants:

Address and data constants can be represented in assembly language using Immediate
Mode.

Immediate Mode.

The operand is given explicitly in the instruction.

Eg: Move #200 ,R0

It places the value 200 in the register R0.The immediate mode used to specify the value
of source operand.

In assembly language, the immediate subscript is not appropriate so # symbol is used.

It can be re-written as

Move #200,R0

Indirection and Pointers:

Instruction does not give the operand or its address explicitly.Instead it provides
information from which the new address of the operand can be determined.This address
is called effective Address(EA) of the operand.
Indirect Mode:

The effective address of the operand is the contents of a register .

We denote the indirection by the name of the register or new address given in the
instruction.

Fig:Indirect Mode Add (A),R0

Add (R1),R0

B
…

Operand

Operand

Address of an operand(B) is stored into R1 register.If we want this operand,we can get it
through register R1(indirection).

The register or new location that contains the address of an operand is called the pointer.

Mode Assembler Syntax Addressing Function

Indirect Ri , LOC EA=[Ri] or EA=[LOC]

Indexing and Arrays:

Index Mode:

The effective address of an operand is generated by adding a constant value to the

contents of a register.
The constant value uses either special purpose or general purpose register.
We indicate the index mode symbolically as,

X(Ri)

Where X – denotes the constant value contained in the instruction

Ri – It is the name of the register involved.

The Effective Address of the operand is,

EA=X + [Ri]
The index register R1 contains the address of a new location and the value of X defines
an offset(also called a displacement).

To find operand,

First go to Reg R1 (using address)-read the content from R1-1000

Add the content 1000 with offset 20 get the result.

1000+20=1020

Here the constant X refers to the new address and the contents of index register
define the offset to the operand.
The sum of two values is given explicitly in the instruction and the other is stored
in register.

Eg: Add 20(R1) , R2 (or) EA=>1000+20=1020

Index Mode Assembler Syntax Addressing Function

Index X(Ri) EA=[Ri]+X

Base with Index (Ri,Rj) EA=[Ri]+[Rj]
Base with Index and offset X(Ri,Rj) EA=[Ri]+[Rj] +X

Relative Addressing:

It is same as index mode. The difference is, instead of general purpose register, here we
can use program counter(PC).

Relative Mode:

The Effective Address is determined by the Index mode using the PC in place of
the general purpose register (gpr).
This mode can be used to access the data operand. But its most common use is to
specify the target address in branch instruction.Eg. Branch>0 Loop
It causes the program execution to goto the branch target location. It is identified
by the name loop if the branch condition is satisfied.

Mode Assembler Syntax Addressing Function

Relative X(PC) EA=[PC]+X

Additional Modes:

There are two additional modes. They are

  Auto-increment mode
 Auto-decrement mode

Auto-increment mode:

The Effective Address of the operand is the contents of a register in the

instruction.
After accessing the operand, the contents of this register is automatically
incremented to point to the next item in the list.

Mode Assembler syntax Addressing Function

Auto-increment (Ri)+ EA=[Ri];

Increment Ri
Auto-decrement mode:

The Effective Address of the operand is the contents of a register in the

instruction.
After accessing the operand, the contents of this register is automatically
decremented to point to the next item in the list.

Mode Assembler Syntax Addressing Function

Auto-decrement -(Ri) EA=[Ri];

Decrement Ri

CISC
Pronounced sisk, and stands for Complex Instruction Set Computer. Most PC's use CPU
based on this architecture. For instance Intel and AMD CPU's are based on CISC
architectures.
Typically CISC chips have a large amount of different and complex instructions. The
philosophy behind it is that hardware is always faster than software, therefore one should
make a powerful instruction set, which provides programmers with assembly instructions
to do a lot with short programs.
In common CISC chips are relatively slow (compared to RISC chips) per instruction, but
use little (less than RISC) instructions.

RISC
Pronounced risk, and stands for Reduced Instruction Set Computer. RISC chips evolved
around the mid-1980 as a reaction at CISC chips. The philosophy behind it is that almost
no one uses complex assembly language instructions as used by CISC, and people mostly
use compilers which never use complex instructions. Apple for instance uses RISC chips.
Therefore fewer, simpler and faster instructions would be better, than the large, complex
and slower CISC instructions. However, more instructions are needed to accomplish a
task.
An other advantage of RISC is that - in theory - because of the more simple instructions,
RISC chips require fewer transistors, which makes them easier to design and cheaper to
produce.
Finally, it's easier to write powerful optimized compilers, since fewer instructions exist.

RISC vs CISC

There is still considerable controversy among experts about which architecture is better.
Some say that RISC is cheaper and faster and therefore the architecture of the future.
Others note that by making the hardware simpler, RISC puts a greater burden on the
software. Software needs to become more complex. Software developers need to write
more lines for the same tasks.
Therefore they argue that RISC is not the architecture of the future, since conventional
CISC chips are becoming faster and cheaper anyway.
RISC has now existed more than 10 years and hasn't been able to kick CISC out of the
market. If we forget about the embedded market and mainly look at the market for PC's,
workstations and servers I guess a least 75% of the processors are based on the CISC
architecture. Most of them the x86 standard (Intel, AMD, etc.), but even in the mainframe

territory CISC is dominant via the IBM/390 chip. Looks like CISC is here to stay …
Is RISC than really not better? The answer isn't quite that simple. RISC and CISC
architectures are becoming more and more alike. Many of today's RISC chips support
just as many instructions as yesterday's CISC chips. The PowerPC 601, for example,
supports more instructions than the Pentium. Yet the 601 is considered a RISC chip,
while the Pentium is definitely CISC. Further more today's CISC chips use many
techniques formerly associated with RISC chips.