1.

INRODUCTION

Multipliers are one of the most significant blocks in computer arithmetic and are generally
used in different digital signal processors. There is growing demands for high speed multipliers
in different applications of computing systems, such as computer graphics, scientific calculation,
image processing and so on. Speed of multiplier determines how fast the processors will run and
designers are now more focused on high speed with low power consumption. The multiplier
architecture consists of a partial product generation stage, partial product reduction stage and the
final addition stage. The partial product reduction stage is responsible for a significant portion of
the total multiplication delay, power and area. Therefore in order to accumulate partial products,
compressors usually implement this stage because they contribute to the reduction of the partial
products and also contribute to reduce the critical path which is important to maintain the
circuit’s performance.
This is accomplished by the use of 3-2, 4-2, 5-2 compressor structures. A 3-2 compressor
circuit is also known as full adder cell. As these compressors are used repeatedly in larger
systems, so improved design will contribute a lot towards overall system performance. The
internal structure of compressors are basically composed of XOR-XNOR gates and multiplexers.
The XOR-XNOR circuits are also building blocks in various circuits like arithmetic circuits,
multipliers, compressors, parity checkers, etc. Optimized design of these XOR-XNOR gates can
improve the performance of multiplier circuit. In present work, a new XOR-XNOR module has
been proposed and 4-2 compressor has been implemented using this module. Use proposed
circuit in partial product accumulation reduces transistor count as well as power consumption.
Addition and multiplication are widely used operations in computer arithmetic; for addition
full-adder cells have been extensively analyzed for approximate computing Liang et al. has
compared these adders and proposed several new metrics for evaluating approximate and
probabilistic adders with respect to unified figures of merit for design assessment for inexact
computing applications. For each input to a circuit, the error distance (ED) is defined as the
arithmetic distance between an erroneous output and the correct one. The mean error distance
(MED) and normalized error distance (NED) are proposed by considering the averaging effect of
multiple inputs and the normalization of multiple-bit adders. The NED is nearly invariant with
the size of an implementation and is therefore useful in the reliability assessment of a specific
design. The tradeoff between precision and power has also been quantitatively evaluated.
However, the design of approximate multipliers has received less attention. Multiplication
can be thought as the repeated sum of partial products; however, the straightforward application
of approximate adders when designing an approximate multiplier is not viable, because it would
be very inefficient in terms of precision, hardware complexity and other performance metrics.
Several approximate multipliers have been proposed. Most of these designs use a truncated
multiplication method; they estimate the least significant columns of the partial products as a
constant. An imprecise array multiplier is used for neural network applications by omitting some
of the least significant bits in the partial products (and thus removing some adders in the array).
A truncated multiplier with a correction constant is proposed.
 2. COMPRESSOR

Braun Multiplier :-

Figure 2.2 4x4 Braun Multiplier

Above figure shows structure of 4*4 Braun Multplier. An n*n bit Braun Multiplier requires n(n-
1) adders and n2 AND gates. In these technique each partial product can be added to previous
sum of partial products by using row of adders. The Carry-out signals are shifted one bit to the
left and then added to the sum of the first adder which is adition of partial product bits. The
shifting of carry-out bits to the left is done by carry-save adder. As carry bits are passed
diagonally downward to the next adder stage, there is no horizontal carry propagation for the first
four rows. Instead, the respective carry bit is “saved” for the subsequent adder stage.
Braun Multiplier has some drawback that, the number of components required in building the
Braun Multiplier increases quadratically with number of bits. This makes Braun Multiplier
inefficient. The delay of Braun Multiplier is dependent on full adder cell and also on final adder
in last row. In this multiplier array, a full adder with balanced carry and sum delays is desirable
because sum and carry both are in critical path.
2.2 Baugh-Wooley Multiplier:-
Baugh-Wooley Multiplier are used for both unsigned and signed number multiplication. Signed
Number operands which are represented in 2’s complemented form. Partial Products are adjusted
such that negative sign move to last step, which in turn maximize the regularity of the
multiplication array. Baugh-Wooley Multiplier operates on signed operands with 2’s
complement representation to make sure that the signs of all partial products are positive. To
reiterate, the numerical value of 2’s complement numbers, suppose X and Y can be obtained
from following product terms made of one AND gate.

Variables with bars denotes prior inversions. Inverters are connected before the input of the full
adder or the AND gates as required by the algorithm. Each column represents the addition in
accordance with the respective weight of the product term.

2.3 Multiplier using Bypassing circuitary:-

In these technique, The main idea of our approach is based on the observation that most modern
multipliers produce a large number of signal transitions while adding zero partial products. If,
any bit of the multiplier is zero that row of adders need not to be activated, since corresponding
partial product is zero. The adders of these multiplier, however perform summation of the zero
partial products and, as result, exhibit redundant signal switching. The increased activity of the
internal nodes results in unnecessary power dissipation.
To disable this adder rows we have to bypass the partial product of previous adder row to
next adder row. It modifies the unnecessary transitions and bypass inputs to outputs when
corresponding partial product is zero. Multiplexers are used at the output of full adder to pass the
partial product directly when it is zero to the next stage.

Figure 2.3 4*4 Bypass Multiplier

The tri-state buffers, placed at the inputs of the adder cell, disable signal transitions in those
adding cells which are bypassed. The output carry-bits c are passed downwards, instead of to the
right.
2.4 Multiplier using Adder-Subtractor Unit(ASU) :-
In these technique, higher power reduction can be achieved if the operand contains more number
of 0’s than 1’s. In this approach it was propose Binary / Booth Recoding Unit which will force
operand to have more number of zeros. The advantage here is that if operand contains more
successive number of ones then Binary / Booth Recoding unit converts these ones in zeros.
Adder-Subtractor Unit also removes the extra 2’s complement addition circuitry needed. Use of
look up table is again an added advantage to this design.
The switching activity of the component used in the design depends on the input bit
coefficient. This means if the input bit coefficient is zero, corresponding row or column of
adders need not be activated. If operand contains more zeros, higher power reduction can be
achieved. We proposed a Binary / Booth Recoding Unit which will force operand to have more
number of zeros.
Figure 2.4 4*4 ASU Multiplier
Figure shows the 4x4 low power ASU multiplier structure. This technique will be very useful as
we go for higher width of the multiplicand specially when there are successive numbers of ones.
Each ASU will work as an adder or subtractor depending upon the sign bit of sign register. For
multiplication with b it will make ASU to work as subtractor and with 0 and 1, it will work as an
adder. The great advantage of this technique is that we don’t need extra addition circuitry to add
sign extension bits when multiplicand bit is –1. In the upper row of architecture we need to and
sign bits with b0.
Since when sj=1 and b0=0, if not added produces wrong outputs. At the bottom, ASU
will work as half adder or subtractor depending upon the sign bits. For higher width of
multiplicand smart adder chain will continue.
Figure 2.5 Adder Subtractor Unit

Figure 2.6: - Smart Adder (SA)

The Modified Full Adder-Subtractor Unit is constructed as shown in figure. If aj is zero,
FA is disabled. Here sj is a sign bit of operand. Structure of smart adder is shown in figure.
2.5 Signed Number Multiplication:-
As we seen in unsigned multiplication, user has to input number as well as sign, so for
total operation of this multiplier we required more hardware and more switching operation hence
the switching power, i.e. dynamic power will be more for Unsigned Multiplication.
In Signed Multiplication, directly user has to enter signed number, so there is no need to
enter separate sign bit for all four numbers. The only difference between Signed number and
Unsigned number is the range of the number. As, we saw earlier in section 3.1 the range of the
Unsigned number is from 0 to 2ⁿ-1. So, the range of the Signed Number is from –2ⁿ -1 to +(2ⁿ -1-
1).
2.5. Representation of Negative Numbers:-
For fixed-point number in a radix r system, we have to determine way of negative number to be
represented. Two different forms are commonly used:-
1. Sign and Magnitude Representation.
2. Complement Representation.
1.Sign and Magnitude Representation:-
In this form of representation sign and magnitude are represented separately. First digit is sign bit
and the remaining (n-1) bits are magnitude. In binary case, ‘0’ is represented as positive and ‘1’
is represented as negative. In the non-binary case, value 0 and (r-1) are assigned to the sign digit
of positive and negative number, respectively. In the binary case all 2n sequences are utilized.
The 2n-1 sequence from 00----0 to 01----1 represents positive number, while the remaining 2n-1
sequences from 10----0 to 11----1 represents negative number. A major disadvantage of the
signed-magnitude representation is that the operation to be performed may depend on the signs
of the operand. For example, when adding a positive number X and a negative number –Y, we
need to perform the calculation X+(-Y). If, Y>X, then we should obtain as a final result –(Y-X).
For that we have to perform (Y-X) ,i.e., switch the order of operands and perform subtraction
rather than addition, and then attach minus sign to it.
Example:- +7 would be 111 and then a 0 in front so 00000111 for an 8-bit representation. -9
would be 1001 (+9) and then a 1 so 10001001 for an 8-bit representation
2. Complement Representation:-
In complement representation, numbers are represented as two’s complement in the binary
section. In this method, positive number is represented in the same way as signed-magnitude
method. It is most widely used method of representation. Positive numbers are simply
represented as a binary number with ‘0’ as sign bit. To get negative number convert all 0’s to 1’s
, all 1’s to 0’s and then add ‘1’ to it. Suppose, a number which are in 2’s complement form and
we have to find its value in binary, then if number starts with ‘0’ then it is a positive number and
if number starts with ‘1’ then it is a negative number.
If, number is negative take the 2’s complement of that number, we will get number in
ordinary binary. Let us take, 1101. Take the 2’s complement then we will get 0011.
 As, number is started with ‘1’ it is negative number and 0011 is binary representation of
positive 3. So, the number is -3. Similarly, we are representing other negative numbers in 2’s
complement representation.
Suppose we are adding +5 and -5 in decimal we get ‘0’. Now, represent these numbers in
2’s complement form, then we get +5 as 0101 and -5 as 1011. On adding these two numbers we
get 10000. Discard carry, then the number is represented as ‘0’ In this signed multiplication we
had modified the Complex Multiplication strategy, normally we are having Four Multipliers and
three adder/subtractor blocks.

3:2 Compressor:
Multipliers are essential component in different circuits, particularly in arithmetic
operation such as compressors, parity checkers and comparators. Multipliers consist of three
fundamental parts: a partial product generator, a partial product reduction and a final fast adder
part. A booth encoder is used to generate the partial products and partial product are reduces to
two rows using compressor circuits. Finally, fast adder is used to sum the two rows.
The partial product reduction part of multiplier contributes maximum power
consumption, delay and layout area. Various high speed multipliers use 3-2, 4-2 and 5-2
compressors to lower the latency of partial product reduction part. These compressors are used to
minimize delay and area which leads to increase the performance of the overall system.
Compressors are generally designed by XOR-XNOR gates and multiplexers. A compressor is a
device which is used to reduce the operands while adding terms of partial products in multipliers.
An X-Y compressor takes X equally weighted input bits and produces Y-bit binary number. The
most widely and the simplest used compressor is the 3-2 compressor which is also known as a
full adder. A 3-2 compressor has three inputs X1, X2, X3 and generates two outputs, the sum and
the carry bits. The block diagram of 3-2 compressor is shown in figure.
 Fig: 3:2 Compressor

Fig: 3:2 Compressor Truth Table

A 3-2 compressor cell can be implemented in many different logic structures. However,
in general, it is composed by three main modules. The first module is required to generate XOR
or XNOR function, or both of them. The second module is used to generate sum and the last
module is to produce carry output. The 3-2 compressor can also be implemented as full adder
cell when its third input is taken as the Carry input from the preceding compressor block or X3 =
Cin. The basic equation of 3-2 compressor is:

X1+X2+X3=Sum+2*carry.............................(1)
 Fig: Conventional 3-2 compressor

Fig: Improved 3-2 Compressor architecture

The conventional architectures of 3-2 compressor shown in figure 2(a), it has two XOR
gates in the critical path. The sum output is generated by the second XOR and carry output is
generated by the multiplexer (MUX). The equations governing the conventional 3-2 compressor
outputs are shown below:
 The 3-2 compressor architecture shown in figure 2(b) has less delay as compared to other
architectures, as some of the XOR circuits are replaced by the multiplexer circuits. In this
compressor the select bit at multiplexer present before the input arrives, so reduces the delay.
Thus the switching time of the transistors in the critical path is decreased. This minimizes the
delay to a significant amount. This architecture shows critical path delay of Δ-XOR +Δ-MUX.
Output functions of modified 3-2 compressor circuit are shown by the equations as given:
 3. PROPOSED MODEL

The overall structures and the details of the suggested dual-quality approximate compressors are
described.
A. Exact 4:2 Compressor
To reduce the delay of the partial product summation stage of parallel multipliers, 4:2 and
5:2 compressors are widely employed. Some compressor structures, which have been optimized
for one or more design parameters (e.g., delay, area, or power consumption), have been
proposed. The focus of this paper is on approximate 4:2 compressors. First, some background on
the exact 4:2 compressor is presented. This type of compressor, shown schematically in Fig. 1,
has four inputs (x1–x4) along with an input carry (Cin), and two outputs (sum and carry) along
with an output Cout. The internal structure of an exact 4:2 compressor is composed of two
serially connected full adders.
In this structure, the weights of all the inputs and the sum output are the same whereas the
weights of the carry and Cout outputs are one binary bit position higher. The outputs sum, carry,
and Cout are obtained from
sum = x1⊕x2⊕x3⊕x4⊕Cin (1)
carry = (x1⊕x2⊕x3⊕x4)Cin + (x1⊕x2⊕x3⊕x4)x4 (2)
Cout = (x1⊕x2)x3+(x1 ⊕ x2)x1. (3)

Fig. 3. Block diagram of the proposed approximate 4:2 compressors. The hachured box in
the approximate part indicates the components, which are not shared between this and
supplementary parts.

B. Proposed Dual-Quality 4:2 Compressors

The proposed DQ4:2Cs operate in two accuracy modes of approximate and exact. The
general block diagram of the compressors is shown in Fig. 3. The diagram consists of two main
parts of approximate and supplementary. During the approximate mode, only the approximate
part is exploited while the supplementary part is power gated. During the exact operating mode,
the supplementary and some parts of the approximate parts are utilized. In the proposed
structure, to reduce the power consumption and area, most of the components of the approximate
part are also used during the exact operating mode.

Fig. 4. (a) Approximate part and (b) overall structure of DQ4:2C1.

We use the power gating technique to turn OFF the unused components of the
approximate part. Also note that, as is evident from Fig. 3, in the exact operating mode, tristate
buffers are utilized to disconnect the outputs of the approximate part from the primary outputs. In
this design, the switching between the approximate and exact operating modes is fast. Thus, it
provides us with the opportunity of designing parallel multipliers that are capable of switching
between different accuracy levels during the runtime. Next, we discuss the details of our four
DQ4:2Cs based on the diagram shown in Fig. 3. The structures have different accuracies, delays,
power consumptions, and area usages. Note that the i th proposed structure is denoted by
DQ4:2Ci . The basic idea behind suggesting the approximate compressors was to minimize the
difference (error) between the outputs of exact and approximate ones. Therefore, in order to
choose the proper approximate designs for the compressors, an extensive search was performed.
During the search, we used the truth table of the exact 4:2 compressor as the reference.
1) Structure 1 (DQ4:2C1): For the approximate part of the first proposed DQ4:2C structure, as
shown in Fig. 4(a), the approximate output carry (i.e., carry_) is directly connected to the input
x4 (carry_ = x4), and also, in a similar approach, the approximate output sum (i.e., sum_) is
directly connected to Fig. 5. (a) Approximate part and (b) overall structure of DQ4:2C2. input x1
(sum_ = x1). In the approximate part of this structure, the output Cout is ignored. While the
approximate part of this structure is considerably fast and low power, its error rate is large
(62.5%).
The supplementary part of this structure is an exact 4:2 compressor. The overall structure
of the proposed structure is shown in Fig. 4(b). In the exact operating mode, the delay of this
structure is about the same as that of the exact 4:2 compressor.

Fig. 5. (a) Approximate part and (b) overall structure of DQ4:2C2.

2) Structure 2 (DQ4:2C2): In the first structure, while ignoring Cout simplified the internal
structure of the reduction stage of the multiplication, its error was large. In the second structure,
compared with the DQ4:2C1, the output Cout is generated by connecting it directly to the input
x3 in the approximate part. Fig. 5 shows the internal structure of the approximate part and the
overall structure of DQ4:2C2. While the error rate of this structure is the same as that of
DQ4:2C1, namely, 62.5%, its relative error is lower.

Fig. 6. (a) Approximate part of DQ4:2C3 and (b) overall structure of DQ4:2C3.
3) Structure 3 (DQ4:2C3): The previous structures, in the approximate operating mode, had
maximum power and delay reductions compared with those of the exact compressor. In some
applications, however, a higher accuracy may be needed. In the third structure, the accuracy of
the approximate operating mode is improved by increasing the complexity of the approximate
part whose internal structure is shown in Fig. 6(a). In this structure, the accuracy of output sum_
is increased. Similar to DQ4:2C1, the approximate part of this structure does not support output
Cout. The error rate of this structure, however, is reduced to 50%.
The overall structure of DQ4:2C3 is shown in Fig. 6(b) where the supplementary part is
enclosed in a red dashed line rectangle. Note that in this structure, the utilized NAND gate of the
approximate part (denoted by a blue dotted line rectangle) is not used during the exact operating
mode. Hence, during this operating mode, we suggest disconnecting supply voltage of this gate
by using the power gating.

Fig. 7. (a) Approximate part of DQ4:2C4 and (b) overall structure of DQ4:2C4.

4) Structure 4 (DQ4:2C4): In this structure, we improve the accuracy of the output carry_
compared with that of DQ4:2C3 at the cost of larger delay and power consumption where the
error rate is reduced to 31.25%. The internal structure of the approximate part and the overall
structure of DQ4:2C4 are shown in Fig. 7. The supplementary part is indicated by red dashed
line rectangular while the gates of the approximate part, powered OFF during the exact operating
mode, are indicated by the blue dotted line.
Note that the error rate corresponds to the occurrence of the errors in the output for the
complete range of the input.
The output quality is determined by the error distance (ED) parameter, which is the
difference between the exact output and the output of the approximate unit. In addition to the
ED, there are other closely related parameters, namely, normalized ED (NED) and mean relative
ED (MRED), which are more important in determining the output quality.
MULTIPLIER REALIZED BY THE PROPOSED COMPRESSORS
In this section, first, the accuracy metrics considered in this paper are introduced. Next,
the accuracy of 8-, 16-, and 32-bit Fig. 8. Reduction circuitry of an 8-bit Dadda mutiplier. Dadda
multipliers realized by the proposed compressors is studied. A proper combination of the
proposed compressors may be utilized to achieve a better tradeoff between the accuracy and
design parameters. As an option, the use of both DQ4:2C1 and DQ4:2C4 for the LSB and MSB
parts in the multiplication, respectively, is suggested here.
The results for this multiplier are denoted by DQ4:2Cmixed. These multipliers are
compared by the approximate Dadda multipliers implemented by two prior proposed
approximate 4:2 compressors discussed as well as the configurable multiplier suggested in. In
addition, some stateof- the-art approximate multiplier designs, which do not use approximate
compressors, are considered. These multipliers include 32-bit unsigned ROBA (U-ROBA), SSM
with a segment size 8 (SSM8), and DRUM with a segment size 6 (DRUM6). The general
structure of the reduction circuitry in an 8-bit Dadda multiplier, which makes use of 4:2
compressors, is drawn in Fig. 8.

Fig. 8. Reduction circuitry of an 8-bit Dadda mutiplier.

4. SIMULATION RESULTS
 5. INTRODUCTION TO VLSI

Very-large-scale integration (VLSI) is the process of creating integrated circuits by

combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s

when complex semiconductor and communication technologies were being developed. The

microprocessor is a VLSI device. The term is no longer as common as it once was, as chips have

increased in complexity into the hundreds of millions of transistors.

5.1 Overview:

The first semiconductor chips held one transistor each. Subsequent advances added more

and more transistors, and, as a consequence, more individual functions or systems were

integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten

diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic

gates on a single device. Now known retrospectively as "small-scale integration" (SSI),

improvements in technique led to devices with hundreds of logic gates, known as large-scale

integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved

far past this mark and today's microprocessors have many millions of gates and hundreds of

millions of individual transistors.

At one time, there was an effort to name and calibrate various levels of large-scale

integration above VLSI. Terms like Ultra-large-scale Integration (ULSI) were used. But the huge

number of gates and transistors available on common devices has rendered such fine distinctions

moot.
 Terms suggesting greater than VLSI levels of integration are no longer in

widespread use. Even VLSI is now somewhat quaint, given the common assumption that all

microprocessors are VLSI or better.

As of early 2008, billion-transistor processors are commercially available, an

example of which is Intel's Montecito Itanium chip. This is expected to become more

commonplace as semiconductor fabrication moves from the current generation of 65 nm

processes to the next 45 nm generations (while experiencing new challenges such as increased

variation across process corners). Another notable example is NVIDIA’s 280 series GPU.

This microprocessor is unique in the fact that its 1.4 Billion transistor count,

capable of a teraflop of performance, is almost entirely dedicated to logic (Itanium's transistor

count is largely due to the 24MB L3 cache). Current designs, as opposed to the earliest devices,

use extensive design automation and automated logic synthesis to lay out the transistors,

enabling higher levels of complexity in the resulting logic functionality. Certain high-

performance logic blocks like the SRAM cell, however, are still designed by hand to ensure the

highest efficiency (sometimes by bending or breaking established design rules to obtain the last

bit of performance by trading stability).

5.2 What is VLSI?

VLSI stands for "Very Large Scale Integration". This is the field which involves packing

more and more logic devices into smaller and smaller areas.
 VLSI

 Simply we say Integrated circuit is many transistors on one chip.

 Design/manufacturing of extremely small, complex circuitry using modified

semiconductor material

 Integrated circuit (IC) may contain millions of transistors, each a few mm in size

 Applications wide ranging: most electronic logic devices

5.3 History of Scale Integration:

 late 40s Transistor invented at Bell Labs

 late 50s First IC (JK-FF by Jack Kilby at TI)

 early 60s Small Scale Integration (SSI)

 10s of transistors on a chip

 late 60s Medium Scale Integration (MSI)

 100s of transistors on a chip

 early 70s Large Scale Integration (LSI)

 1000s of transistor on a chip

 early 80s VLSI 10,000s of transistors on a

 chip (later 100,000s & now 1,000,000s)

 Ultra LSI is sometimes used for 1,000,000s

 SSI - Small-Scale Integration (0-102)

 MSI - Medium-Scale Integration (102-103)

 LSI - Large-Scale Integration (103-105)

  VLSI - Very Large-Scale Integration (105-107)

 ULSI - Ultra Large-Scale Integration (>=107)

5.4 Advantages of ICs over discrete components:

While we will concentrate on integrated circuits , the properties of

integrated circuits-what we can and cannot efficiently put in an integrated circuit-largely

determine the architecture of the entire system. Integrated circuits improve system characteristics

in several critical ways. ICs have three key advantages over digital circuits built from discrete

components:

 Size. Integrated circuits are much smaller-both transistors and wires are shrunk to

micrometer sizes, compared to the millimeter or centimeter scales of discrete

components. Small size leads to advantages in speed and power consumption, since

smaller components have smaller parasitic resistances, capacitances, and inductances.

 Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip

than they can between chips. Communication within a chip can occur hundreds of times

faster than communication between chips on a printed circuit board. The high speed of

circuits on-chip is due to their small size-smaller components and wires have smaller

parasitic capacitances to slow down the signal.

 Power consumption. Logic operations within a chip also take much less power. Once

again, lower power consumption is largely due to the small size of circuits on the chip-

smaller parasitic capacitances and resistances require less power to drive them.
5.5 VLSI and systems:

These advantages of integrated circuits translate into advantages at the system level:

 Smaller physical size. Smallness is often an advantage in itself-consider portable

televisions or handheld cellular telephones.

 Lower power consumption. Replacing a handful of standard parts with a single chip

reduces total power consumption. Reducing power consumption has a ripple effect on the

rest of the system: a smaller, cheaper power supply can be used; since less power

consumption means less heat, a fan may no longer be necessary; a simpler cabinet with

less shielding for electromagnetic shielding may be feasible, too.

 Reduced cost. Reducing the number of components, the power supply requirements,

cabinet costs, and so on, will inevitably reduce system cost. The ripple effect of

integration is such that the cost of a system built from custom ICs can be less, even

though the individual ICs cost more than the standard parts they replace.

Understanding why integrated circuit technology has such profound influence on the design

of digital systems requires understanding both the technology of IC manufacturing and the

economics of ICs and digital systems.

Applications

 Electronic system in cars.

 Digital electronics control VCRs

 Transaction processing system, ATM

 Personal computers and Workstations

  Medical electronic systems.

 Etc….

5.6 Applications of VLSI:

Electronic systems now perform a wide variety of tasks in daily life. Electronic

systems in some cases have replaced mechanisms that operated mechanically, hydraulically, or

by other means; electronics are usually smaller, more flexible, and easier to service. In other

cases electronic systems have created totally new applications. Electronic systems perform a

variety of tasks, some of them visible, some more hidden:

 Personal entertainment systems such as portable MP3 players and DVD

players perform sophisticated algorithms with remarkably little energy.

 Electronic systems in cars operate stereo systems and displays; they also

control fuel injection systems, adjust suspensions to varying terrain, and

perform the control functions required for anti-lock braking (ABS) systems.

 Digital electronics compress and decompress video, even at high-definition

data rates, on-the-fly in consumer electronics.

 Low-cost terminals for Web browsing still require sophisticated electronics,

despite their dedicated function.

 Personal computers and workstations provide word-processing, financial

analysis, and games. Computers include both central processing units (CPUs)

and special-purpose hardware for disk access, faster screen display, etc.
  Medical electronic systems measure bodily functions and perform complex

processing algorithms to warn about unusual conditions. The availability of

these complex systems, far from overwhelming consumers, only creates

demand for even more complex systems.

The growing sophistication of applications continually pushes the design and

manufacturing of integrated circuits and electronic systems to new levels of complexity. And

perhaps the most amazing characteristic of this collection of systems is its variety-as systems

become more complex, we build not a few general-purpose computers but an ever wider range of

special-purpose systems. Our ability to do so is a testament to our growing mastery of both

integrated circuit manufacturing and design, but the increasing demands of customers continue to

test the limits of design and manufacturing

5.7 ASIC:

An Application-Specific Integrated Circuit (ASIC) is an integrated circuit (IC)

customized for a particular use, rather than intended for general-purpose use. For example, a chip

designed solely to run a cell phone is an ASIC. Intermediate between ASICs and industry

standard integrated circuits, like the 7400 or the 4000 series, are application specific standard

products (ASSPs).

As feature sizes have shrunk and design tools improved over the years, the maximum

complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over

100 million. Modern ASICs often include entire 32-bit processors, memory blocks including

ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a

SoC (system-on-a-chip). Designers of digital ASICs use a hardware description language (HDL),

such as Verilog or VHDL, to describe the functionality of ASICs.

 Field-programmable gate arrays (FPGA) are the modern-day technology for building a

breadboard or prototype from standard parts; programmable logic blocks and programmable

interconnects allow the same FPGA to be used in many different applications. For smaller

designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC

design even in production.

 An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized

for a particular use, rather than intended for general-purpose use.

 A Structured ASIC falls between an FPGA and a Standard Cell-based ASIC

 Structured ASIC’s are used mainly for mid-volume level design. The design task for

structured ASIC’s is to map the circuit into a fixed arrangement of known cells.
 6. INTRODUCTION TO XILINX

6.1 Migrating Projects from Previous ISE Software Releases:

When you open a project file from a previous release, the ISE® software prompts you to

migrate your project. If you click Backup and Migrate or Migrate Only, the software

automatically converts your project file to the current release. If you click Cancel, the software

does not convert your project and, instead, opens Project Navigator with no project loaded.

Note: After you convert your project, you cannot open it in previous versions of the ISE

software, such as the ISE 11 software. However, you can optionally create a backup of the

original project as part of project migration, as described below.

To Migrate a Project

1. In the ISE 12 Project Navigator, select File > Open Project.

2. In the Open Project dialog box, select the .xise file to migrate.

Note You may need to change the extension in the Files of type field to display .npl

(ISE 5 and ISE 6 software) or .ise (ISE 7 through ISE 10 software) project files.

3. In the dialog box that appears, select Backup and Migrate or Migrate Only.

4. The ISE software automatically converts your project to an ISE 12 project.

Note If you chose to Backup and Migrate, a backup of the original project is created at

project_name_ise12migration.zip.

5. Implement the design using the new version of the software.

Note Implementation status is not maintained after migration.

6.2 Properties:

For information on properties that have changed in the ISE 12 software, see ISE 11 to

ISE 12 Properties Conversion.

6.3 IP Modules:

If your design includes IP modules that were created using CORE Generator™ software

or Xilinx® Platform Studio (XPS) and you need to modify these modules, you may be required

to update the core. However, if the core netlist is present and you do not need to modify the

core, updates are not required and the existing netlist is used during implementation.

6.4 Obsolete Source File Types:

The ISE 12 software supports all of the source types that were supported in the ISE 11

software.

If you are working with projects from previous releases, state diagram source files (.dia),

ABEL source files (.abl), and test bench waveform source files (.tbw) are no longer supported.

For state diagram and ABEL source files, the software finds an associated HDL file and adds it

to the project, if possible. For test bench waveform files, the software automatically converts the

TBW file to an HDL test bench and adds it to the project. To convert a TBW file after project

migration, see Converting a TBW File to an HDL Test Bench.

6.5 Using ISE Example Projects:

To help familiarize you with the ISE® software and with FPGA and CPLD designs, a set

of example designs is provided with Project Navigator. The examples show different design
techniques and source types, such as VHDL, Verilog, schematic, or EDIF, and include different

constraints and IP.

To Open an Example

1. Select File > Open Example.

2. In the Open Example dialog box, select the Sample Project Name.

Note To help you choose an example project, the Project Description field describes

each project. In addition, you can scroll to the right to see additional fields, which

provide details about the project.

3. In the Destination Directory field, enter a directory name or browse to the

directory.

4. Click OK.

The example project is extracted to the directory you specified in the Destination

Directory field and is automatically opened in Project Navigator. You can then run processes

on the example project and save any changes.

Note If you modified an example project and want to overwrite it with the original

example project, select File > Open Example, select the Sample Project Name, and specify the

same Destination Directory you originally used. In the dialog box that appears, select Overwrite

the existing project and click OK.

6.6 Creating a Project:

Project Navigator allows you to manage your FPGA and CPLD designs using an ISE®

project, which contains all the source files and settings specific to your design. First, you must

create a project and then, add source files, and set process properties. After you create a project,
you can run processes to implement, constrain, and analyze your design. Project Navigator

provides a wizard to help you create a project as follows.

Note If you prefer, you can create a project using the New Project dialog box instead of

the New Project Wizard. To use the New Project dialog box, deselect the Use New Project

wizard option in the ISE General page of the Preferences dialog box.

To Create a Project

1. Select File > New Project to launch the New Project Wizard.

2. In the Create New Project page, set the name, location, and project type, and

click Next.

3. For EDIF or NGC/NGO projects only: In the Import EDIF/NGC Project page,

select the input and constraint file for the project, and click Next.

4. In the Project Settings page, set the device and project properties, and click

Next.

5. In the Project Summary page, review the information, and click Finish to

create the project

Project Navigator creates the project file (project_name.xise) in the directory you

specified. After you add source files to the project, the files appear in the Hierarchy pane of the

6.7 Design panel:

Project Navigator manages your project based on the design properties (top-level module

type, device type, synthesis tool, and language) you selected when you created the project. It

organizes all the parts of your design and keeps track of the processes necessary to move the

design from design entry through implementation to programming the targeted Xilinx® device.
Note For information on changing design properties, see Changing Design Properties.

You can now perform any of the following:

 Create new source files for your project.

 Add existing source files to your project.

 Run processes on your source files.

Modify process properties.

6.8 Creating a Copy of a Project:

You can create a copy of a project to experiment with different source options and

implementations. Depending on your needs, the design source files for the copied project and

their location can vary as follows:

 Design source files are left in their existing location, and the copied project

points to these files.

 Design source files, including generated files, are copied and placed in a

specified directory.

 Design source files, excluding generated files, are copied and placed in a

specified directory.

Copied projects are the same as other projects in both form and function. For example, you can

do the following with copied projects:

  Open the copied project using the File > Open Project menu command.

 View, modify, and implement the copied project.

 Use the Project Browser to view key summary data for the copied project and

then, open the copied project for further analysis and implementation, as described in

6.9 Using the Project Browser:

Alternatively, you can create an archive of your project, which puts all of the project

contents into a ZIP file. Archived projects must be unzipped before being opened in Project

Navigator. For information on archiving, see Creating a Project Archive.

To Create a Copy of a Project

1. Select File > Copy Project.

2. In the Copy Project dialog box, enter the Name for the copy.

Note The name for the copy can be the same as the name for the project, as long as you

specify a different location.

3. Enter a directory Location to store the copied project.

4. Optionally, enter a Working directory.

By default, this is blank, and the working directory is the same as the project directory.

However, you can specify a working directory if you want to keep your ISE® project

file (.xise extension) separate from your working area.

5. Optionally, enter a Description for the copy.

The description can be useful in identifying key traits of the project for reference later.

6. In the Source options area, do the following:

Select one of the following options:

  Keep sources in their current locations - to leave the design source files in their

existing location.

If you select this option, the copied project points to the files in their existing location. If

you edit the files in the copied project, the changes also appear in the original project, because

the source files are shared between the two projects.

 Copy sources to the new location - to make a copy of all the design source files and

place them in the specified Location directory.

If you select this option, the copied project points to the files in the specified directory. If you

edit the files in the copied project, the changes do not appear in the original project, because the

source files are not shared between the two projects.

Optionally, select Copy files from Macro Search Path directories to copy files from

the directories you specify in the Macro Search Path property in the Translate Properties dialog

box. All files from the specified directories are copied, not just the files used by the design.

Note: If you added a net list source file directly to the project as described in Working

with Net list-Based IP, the file is automatically copied as part of Copy Project because it is a

project source file. Adding net list source files to the project is the preferred method for

incorporating net list modules into your design, because the files are managed automatically by

Project Navigator.

Optionally, click Copy Additional Files to copy files that were not included in the

original project. In the Copy Additional Files dialog box, use the Add Files and Remove Files

buttons to update the list of additional files to copy. Additional files are copied to the copied

project location after all other files are copied.To exclude generated files from the copy, such as

implementation results and reports, select

6.10 Exclude generated files from the copy:

When you select this option, the copied project opens in a state in which processes have

not yet been run.

7. To automatically open the copy after creating it, select Open the copied project.

Note By default, this option is disabled. If you leave this option disabled, the original

project remains open after the copy is made.

Click OK.

6.11 Creating a Project Archive:

A project archive is a single, compressed ZIP file with a .zip extension. By default, it

contains all project files, source files, and generated files, including the following:

 User-added sources and associated files

 Remote sources

 Verilog `include files

 Files in the macro search path

 Generated files

 Non-project files

6.12 To Archive a Project:

1. Select Project > Archive.

2. In the Project Archive dialog box, specify a file name and directory for the ZIP

file.

3. Optionally, select Exclude generated files from the archive to exclude

generated files and non-project files from the archive.

 4. Click OK.

A ZIP file is created in the specified directory. To open the archived project, you must

first unzip the ZIP file, and then, you can open the project.

Note Sources that reside outside of the project directory are copied into a remote_sources

subdirectory in the project archive. When the archive is unzipped and opened, you must either

specify the location of these files in the remote_sources subdirectory for the unzipped project, or

manually copy the sources into their original location.

7. INTRODUCTION TO VERILOG

In the semiconductor and electronic design industry, Verilog is a hardware description

language(HDL) used to model electronic systems. Verilog HDL, not to be confused
with VHDL (a competing language), is most commonly used in the design, verification, and
implementation ofdigital logic chips at the register-transfer level of abstraction. It is also used in
the verification ofanalog and mixed-signal circuits.

Overview

Hardware description languages such as Verilog differ from software programming

languages because they include ways of describing the propagation of time and signal
dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and a
non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a
state-machine update without needing to declare and use temporary storage variables (in any
general programming language we need to define some temporary storage spaces for the
operands to be operated on subsequently; those are temporary storage variables). Since these
concepts are part of Verilog's language semantics, designers could quickly write descriptions of
large circuits in a relatively compact and concise form. At the time of Verilog's introduction
(1984), Verilog represented a tremendous productivity improvement for circuit designers who
were already using graphical schematic capturesoftware and specially-written software programs
to document and simulate electronic circuits.

The designers of Verilog wanted a language with syntax similar to the C programming
language, which was already widely used in engineering software development. Verilog is case-
sensitive, has a basic preprocessor (though less sophisticated than that of ANSI C/C++), and
equivalent control flow keywords (if/else, for, while, case, etc.), and compatible operator
precedence. Syntactic differences include variable declaration (Verilog requires bit-widths on
net/reg types[clarification needed]), demarcation of procedural blocks (begin/end instead of curly braces
{}), and many other minor differences.

A Verilog design consists of a hierarchy of modules. Modules encapsulate design

hierarchy, and communicate with other modules through a set of declared input, output, and
bidirectional ports. Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks,
and instances of other modules (sub-hierarchies). Sequential statements are placed inside a
begin/end block and executed in sequential order within the block. But the blocks themselves are
executed concurrently, qualifying Verilog as a dataflow language.

Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and strengths (strong, weak, etc.). This system allows abstract modeling of shared
signal lines, where multiple sources drive a common net. When a wire has multiple drivers, the
wire's (readable) value is resolved by a function of the source drivers and their strengths.

A subset of statements in the Verilog language is synthesizable. Verilog modules that

conform to a synthesizable coding style, known as RTL (register-transfer level), can be
physically realized by synthesis software. Synthesis software algorithmically transforms the
(abstract) Verilog source into a net list, a logically equivalent description consisting only of
elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a
specific FPGA or VLSI technology. Further manipulations to the net list ultimately lead to a
circuit fabrication blueprint (such as a photo mask set for an ASIC or a bit stream file for
an FPGA).
 History

Beginning
Verilog was the first modern hardware description language to be invented. It was created
by Phil Moorby and Prabhu Goel during the winter of 1983/1984. The wording for this process
was "Automated Integrated Design Systems" (later renamed to Gateway Design Automation in
1985) as a hardware modeling language. Gateway Design Automation was purchased
by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway's
Verilog and the Verilog-XL, the HDL-simulator that would become the de-facto standard (of
Verilog logic simulators) for the next decade. Originally, Verilog was intended to describe and
allow simulation; only afterwards was support for synthesis added.

Verilog-95
With the increasing success of VHDL at the time, Cadence decided to make the language
available for open standardization. Cadence transferred Verilog into the public domain under
the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later
submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

In the same time frame Cadence initiated the creation of Verilog-A to put standards
support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone
language and is a subset of Verilog-AMS which encompassed Verilog-95.

Verilog 2001
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that
users had found in the original Verilog standard. These extensions became IEEE Standard 1364-
2001 known as Verilog-2001.

Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for
(2's complement) signed nets and variables. Previously, code authors had to perform signed
operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-
bit addition required an explicit description of the Boolean algebra to determine its correct
value). The same function under Verilog-2001 can be more succinctly described by one of the
built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL's
generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation
through normal decision operators (case/if/else). Using generate/endgenerate, Verilog-2001 can
instantiate an array of instances, with control over the connectivity of the individual instances.
File I/O has been improved by several new system tasks. And finally, a few syntax additions
were introduced to improve code readability (e.g. always @*, named parameter override, C-style
function/task/module header declaration).

Verilog-2001 is the dominant flavor of Verilog supported by the majority of

commercial EDA software packages.

Verilog 2005
Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of
minor corrections, spec clarifications, and a few new language features (such as the uwire
keyword).

A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed
signal modeling with traditional Verilog.

SystemVerilog

SystemVerilog is a superset of Verilog-2005, with many new features and capabilities to aid
design verification and design modeling. As of 2009, the SystemVerilog and Verilog language
standards were merged into SystemVerilog 2009 (IEEE Standard 1800-2009).

The advent of hardware verification languages such as OpenVera, and Verisity's e

language encouraged the development of Superlog by Co-Design Automation Inc. Co-Design
Automation Inc was later purchased by Synopsys. The foundations of Superlog and Vera were
donated to Accellera, which later became the IEEE standard P1800-2005: SystemVerilog.

In the late 1990s, the Verilog Hardware Description Language (HDL) became the most
widely used language for describing hardware for simulation and synthesis. However, the first
two versions standardized by the IEEE (1364-1995 and 1364-2001) had only simple constructs
for creating tests. As design sizes outgrew the verification capabilities of the language,
commercial Hardware Verification Languages (HVL) such as Open Vera and e were created.
Companies that did not want to pay for these tools instead spent hundreds of man-years creating
their own custom tools. This productivity crisis (along with a similar one on the design side) led
to the creation of Accellera, a consortium of EDA companies and users who wanted to create the
next generation of Verilog. The donation of the Open-Vera language formed the basis for the
HVL features of SystemVerilog.Accellera’s goal was met in November 2005 with the adoption
of the IEEE standard P1800-2005 for SystemVerilog, IEEE (2005).
The most valuable benefit of SystemVerilog is that it allows the user to construct reliable,
repeatable verification environments, in a consistent syntax, that can be used across multiple
projects
Some of the typical features of an HVL that distinguish it from a Hardware Description
Language such as Verilog or VHDL are
 Constrained-random stimulus generation
 Functional coverage
 Higher-level structures, especially Object Oriented Programming
 Multi-threading and interprocess communication
 Support for HDL types such as Verilog’s 4-state values
 Tight integration with event-simulator for control of the design
There are many other useful features, but these allow you to create test benches at a
higher level of abstraction than you are able to achieve with an HDL or a programming language
such as C.
System Verilog provides the best framework to achieve coverage-driven verification (CDV).
CDV combines automatic test generation, self-checking testbenches, and coverage metrics to
significantly reduce the time spent verifying a design. The purpose of CDV is to:

 Eliminate the effort and time spent creating hundreds of tests.

 Ensure thorough verification using up-front goal setting.

 Receive early error notifications and deploy run-time checking and error analysis to
simplify debugging.

Examples

Ex1: A hello world program looks like this:

module main;
initial
begin
$display("Hello world!");
$finish;
end
 endmodule
Ex2: A simple example of two flip-flops follows:

module toplevel(clock,reset);
input clock;
input reset;

reg flop1;
reg flop2;

always @ (posedge reset or posedge clock)

if (reset)
begin
flop1 <= 0;
flop2 <= 1;
end
else
begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule
The "<=" operator in Verilog is another aspect of its being a hardware description
language as opposed to a normal procedural language. This is known as a "non-blocking"
assignment. Its action doesn't register until the next clock cycle. This means that the order of the
assignments are irrelevant and will produce the same result: flop1 and flop2 will swap values
every clock.

The other assignment operator, "=", is referred to as a blocking assignment. When "="
assignment is used, for the purposes of logic, the target variable is updated immediately. In the
above example, had the statements used the "=" blocking operator instead of "<=", flop1 and
flop2 would not have been swapped. Instead, as in traditional programming, the compiler would
understand to simply set flop1 equal to flop2 (and subsequently ignore the redundant logic to set
flop2 equal to flop1.)

Ex3: An example counter circuit follows:

module Div20x (rst, clk, cet, cep, count, tc);

// TITLE 'Divide-by-20 Counter with enables'
// enable CEP is a clock enable only
// enable CET is a clock enable and
// enables the TC output
// a counter using the Verilog language

parameter size = 5;
parameter length = 20;

input rst; // These inputs/outputs represent

input clk; // connections to the module.
input cet;
input cep;

output [size-1:0] count;

output tc;

reg [size-1:0] count; // Signals assigned

// within an always
// (or initial)block
// must be of type reg

wire tc; // Other signals are of type wire

// The always statement below is a parallel

// execution statement that
// executes any time the signals
// rst or clk transition from low to high

always @ (posedge clk or posedge rst)

if (rst) // This causes reset of the cntr
count <= {size{1'b0}};
else
if (cet && cep) // Enables both true
begin
if (count == length-1)
count <= {size{1'b0}};
else
count <= count + 1'b1;
end

// the value of tc is continuously assigned

// the value of the expression
assign tc = (cet && (count == length-1));

endmodule
Ex4: An example of delays:
...
reg a, b, c, d;
wire e;
...
always @(b or e)
begin
a = b & e;
b = a | b;
#5 c = b;
d = #6 c ^ e;
end

The always clause above illustrates the other type of method of use, i.e. the always clause
executes any time any of the entities in the list change, i.e. the b or e change. When one of these
changes, immediately a is assigned a new value, and due to the blocking assignment b is
assigned a new value afterward (taking into account the new value of a.) After a delay of 5 time
units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible store. Then
after 6 more time units, d is assigned the value that was tucked away.

Signals that are driven from within a process (an initial or always block) must be of type reg.
Signals that are driven from outside a process must be of type wire. The keyword reg does not
necessarily imply a hardware register.

7.3 Constants

The definition of constants in Verilog supports the addition of a width parameter. The basic
syntax is:

<Width in bits>'<base letter><number>

Examples:

 12'h123 - Hexadecimal 123 (using 12 bits)

 20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)
 4'b1010 - Binary 1010 (using 4 bits)
 6'o77 - Octal 77 (using 6 bits)

7.4 Synthesizable Constructs

There are several statements in Verilog that have no analog in real hardware, e.g.
$display. Consequently, much of the language can not be used to describe hardware. The
examples presented here are the classic subset of the language that has a direct mapping to real
gates.

// Mux examples - Three ways to do the same thing.

// The first example uses continuous assignment
wire out;
assign out = sel ? a : b;
// the second example uses a procedure
// to accomplish the same thing.
reg out;
always @(a or b or sel)
begin
case(sel)
1'b0: out = b;
1'b1: out = a;
endcase
end
// Finally - you can use if/else in a
// procedural structure.
reg out;
always @(a or b or sel)
if (sel)
out = a;
else
out = b;

The next interesting structure is a transparent latch; it will pass the input to the output
when the gate signal is set for "pass-through", and captures the input and stores it upon transition
of the gate signal to "hold". The output will remain stable regardless of the input signal while the
gate is set to "hold". In the example below the "pass-through" level of the gate would be when
the value of the if clause is true, i.e. gate = 1. This is read "if gate is true, the din is fed to
latch_out continuously." Once the if clause is false, the last value at latch_out will remain and is
independent of the value of din.
EX6: // Transparent latch example
reg out;
always @(gate or din)
if(gate)
out = din; // Pass through state
// Note that the else isn't required here. The variable
// out will follow the value of din while gate is high.
// When gate goes low, out will remain constant.

The flip-flop is the next significant template; in Verilog, the D-flop is the simplest, and it can be
modeled as:

reg q;
always @(posedge clk)
q <= d;

The significant thing to notice in the example is the use of the non-blocking assignment.
A basic rule of thumb is to use <= when there is a posedge or negedge statement within the
always clause.

A variant of the D-flop is one with an asynchronous reset; there is a convention that the
reset state will be the first if clause within the statement.

reg q;
always @(posedge clk or posedge reset)
if(reset)
q <= 0;
else
q <= d;
The next variant is including both an asynchronous reset and asynchronous set condition; again
the convention comes into play, i.e. the reset term is followed by the set term.

reg q;
always @(posedge clk or posedge reset or posedge set)
if(reset)
q <= 0;
else
if(set)
q <= 1;
else
 q <= d;
Note: If this model is used to model a Set/Reset flip flop then simulation errors can result.
Consider the following test sequence of events. 1) reset goes high 2) clk goes high 3) set goes
high 4) clk goes high again 5) reset goes low followed by 6) set going low. Assume no setup and
hold violations.

In this example the always @ statement would first execute when the rising edge of reset
occurs which would place q to a value of 0. The next time the always block executes would be
the rising edge of clk which again would keep q at a value of 0. The always block then executes
when set goes high which because reset is high forces q to remain at 0. This condition may or
may not be correct depending on the actual flip flop. However, this is not the main problem with
this model. Notice that when reset goes low, that set is still high. In a real flip flop this will cause
the output to go to a 1. However, in this model it will not occur because the always block is
triggered by rising edges of set and reset - not levels. A different approach may be necessary for
set/reset flip flops.

Note that there are no "initial" blocks mentioned in this description. There is a split
between FPGA and ASIC synthesis tools on this structure. FPGA tools allow initial blocks
where reg values are established instead of using a "reset" signal. ASIC synthesis tools don't
support such a statement. The reason is that an FPGA's initial state is something that is
downloaded into the memory tables of the FPGA. An ASIC is an actual hardware
implementation.

7.5 Initial Vs Always:

There are two separate ways of declaring a Verilog process. These are the always and
the initial keywords. The always keyword indicates a free-running process. The initial keyword
indicates a process executes exactly once. Both constructs begin execution at simulator time 0,
and both execute until the end of the block. Once an always block has reached its end, it is
rescheduled (again). It is a common misconception to believe that an initial block will execute
before an always block. In fact, it is better to think of the initial-block as a special-case of
the always-block, one which terminates after it completes for the first time.

//Examples:
initial
 begin
a = 1; // Assign a value to reg a at time 0
#1; // Wait 1 time unit
b = a; // Assign the value of reg a to reg b
end

always @(a or b) // Any time a or b CHANGE, run the process

begin
if (a)
c = b;
else
d = ~b;
end // Done with this block, now return to the top (i.e. the @ event-control)

always @(posedge a)// Run whenever reg a has a low to high change
a <= b;
These are the classic uses for these two keywords, but there are two significant additional
uses. The most common of these is an alwayskeyword without the @(...) sensitivity list. It is
possible to use always as shown below:

always
begin // Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
end // Keeps executing - so continue back at the top of the begin

The always keyword acts similar to the "C" construct while(1) {..} in the sense that it will
execute forever.

The other interesting exception is the use of the initial keyword with the addition of
the forever keyword.

7.6 Race Condition

The order of execution isn't always guaranteed within Verilog. This can best be
illustrated by a classic example. Consider the code snippet below:

initial
a = 0;
initial
b = a;
initial
begin
#1;
$display("Value a=%b Value of b=%b",a,b);
end
What will be printed out for the values of a and b? Depending on the order of execution of the
initial blocks, it could be zero and zero, or alternately zero and some other arbitrary uninitialized
value. The $display statement will always execute after both assignment blocks have completed,
due to the #1 delay.

7.7 Operators

Note: These operators are not shown in order of precedence.

Operator Operator Operation performed

type symbols
~ Bitwise NOT (1's complement)

& Bitwise AND

Bitwise Bitwise OR
|

^ Bitwise XOR

~^ or ^~ Bitwise XNOR

! NOT

Logical AND
&&

|| OR

& Reduction AND

Reduction Reduction NAND

~&

| Reduction OR
 ~| Reduction NOR

^ Reduction XOR

~^ or ^~ Reduction XNOR

+ Addition

- Subtraction

- 2's complement
Arithmetic
* Multiplication

/ Division

** Exponentiation (*Verilog-2001)

> Greater than

< Less than

>= Greater than or equal to

<= Less than or equal to

Relational
== Logical equality (bit-value 1'bX is removed from comparison)

!= Logical inequality (bit-value 1'bX is removed from comparison)

=== 4-state logical equality (bit-value 1'bX is taken as literal)

!== 4-state logical inequality (bit-value 1'bX is taken as literal)

>> Logical right shift

Shift Logical left shift

<<

>>> Arithmetic right shift (*Verilog-2001)

 <<< Arithmetic left shift (*Verilog-2001)

Concatenation { , } Concatenation

Replication {n{m}} Replicate value m for n times

Conditional ?: Conditional

7.8 System Tasks:

System tasks are available to handle simple I/O, and various design measurement functions. All
system tasks are prefixed with $ to distinguish them from user tasks and functions. This section
presents a short list of the most often used tasks. It is by no means a comprehensive list.

 $display - Print to screen a line followed by an automatic newline.

 $write - Write to screen a line without the newline.
 $swrite - Print to variable a line without the newline.
 $sscanf - Read from variable a format-specified string. (*Verilog-2001)
 $fopen - Open a handle to a file (read or write)
 $fdisplay - Write to file a line followed by an automatic newline.
 $fwrite - Write to file a line without the newline.
 $fscanf - Read from file a format-specified string. (*Verilog-2001)
 $fclose - Close and release an open file handle.
 $readmemh - Read hex file content into a memory array.
 $readmemb - Read binary file content into a memory array.
 $monitor - Print out all the listed variables when any change value.
 $time - Value of current simulation time.
 $dumpfile - Declare the VCD (Value Change Dump) format output file name.
 $dumpvars - Turn on and dump the variables.
 $dumpports - Turn on and dump the variables in Extended-VCD format.

 $random - Return a random value.

8. CONCLUSION