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    Assignment 3: VLSI Design (MEL G621) Jaiswal Akshay 2019H1230053G

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    Piyush Parashar
    1. The document describes the design of a 1-bit full adder circuit using a PMOS to NMOS ratio of 1.75:1 to match the pull-up and pull-down resistance of a unit inverter. 2. Transient simulation was performed on the schematic design and layout to calculate propagation delay and contamination delay before and after layout versus schematic (LVS) and parasitic extraction. 3. Observations showed that delays increased after parasitic extraction due to added resistances and capacitances in the layout, and delays could potentially be reduced by optimizing the layout.

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    Assignment 3: VLSI Design (MEL G621) Jaiswal Akshay 2019H1230053G

    Uploaded by

    Piyush Parashar
    43 views9 pages
    1. The document describes the design of a 1-bit full adder circuit using a PMOS to NMOS ratio of 1.75:1 to match the pull-up and pull-down resistance of a unit inverter. 2. Transient simulation was performed on the schematic design and layout to calculate propagation delay and contamination delay before and after layout versus schematic (LVS) and parasitic extraction. 3. Observations showed that delays increased after parasitic extraction due to added resistances and capacitances in the layout, and delays could potentially be reduced by optimizing the layout.

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    2019H1230053G_A3

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    1. The document describes the design of a 1-bit full adder circuit using a PMOS to NMOS ratio of 1.75:1 to match the pull-up and pull-down resistance of a unit inverter. 2. Transient simulation was performed on the schematic design and layout to calculate propagation delay and contamination delay before and after layout versus schematic (LVS) and parasitic extraction. 3. Observations showed that delays increased after parasitic extraction due to added resistances and capacitances in the layout, and delays could potentially be reduced by optimizing the layout.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    43 views9 pages

    Assignment 3: VLSI Design (MEL G621) Jaiswal Akshay 2019H1230053G

    Uploaded by

    Piyush Parashar
    1. The document describes the design of a 1-bit full adder circuit using a PMOS to NMOS ratio of 1.75:1 to match the pull-up and pull-down resistance of a unit inverter. 2. Transient simulation was performed on the schematic design and layout to calculate propagation delay and contamination delay before and after layout versus schematic (LVS) and parasitic extraction. 3. Observations showed that delays increased after parasitic extraction due to added resistances and capacitances in the layout, and delays could potentially be reduced by optimizing the layout.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 9

    Assignment 3

    VLSI Design (MEL G621)


    JAISWAL AKSHAY
    2019H1230053G
    Task 1: Using the ratio of size of PMOS and NMOS obtained in assignment 2 and with target
    to make pull-up and pull-down resistance equal to that of unit inverter in worst case, design 1-
    bit full adder.
    Task 2: Perform transient simulation by applying periodic pulse waveform as input with
    period=10 ns, rise time= 0.1 ns, fall time = 0.1 ns and pulse-width=5 ns. Vary delay of pulse
    such that all input combinations are verified. Calculate the propagation delay and contamination
    delay of circuit.
    Task 3: Draw the layout of 1-bit full adder designed above and recalculate above parameters for
    layout using post-layout simulations.
    Task 4: List your observations.
    Task 1:
    The ratio of PMOS to NMOS obtained in assignment 2 was 1.75:1 for symmetric inverter. Now
    to make 1 bit full adder with pull-up and pull-down resistance equal to that of a unit inverter we
    use the same ratio to design the adder.

    Figure 1.1 Schematic for 1 bit full adder.

    Figure 1.2 Symbol for 1 bit full adder.


    Task 2 :
    1) Transient simulation was carried out using Verilog AMS.
    2) Stimulus and capture block were created using Verilog AMS.

    Figure 2.1 Test circuit to perform Transient analysis.

    Figure 2.2 Transient analysis simulation output.


    Figure 2.3 Delay of 1 bit full adder (without RC extraction).

    Contamination Delay = 25.3075 ps.


    Propagation Delay = 52.2497 ps.
    Task 3:

    Figure 3.1 Layout of 1-bit full adder.

    Figure 3.2 No DRC error found.


    Figure 3.3 No LVS error found.

    Figure 3.4 Schematic and layout matched.


    Figure 3.5 QRC Run successful.

    Figure 3.6 Layout of AV Extracted parasitic resistances and capacitances.


    Figure 3.7 Transient analysis for AV extracted circuit.

    Figure 3.9 Delay Value for AV extracted Layout.

    Contamination Delay = 51.8976 ps.


    Propagation Delay = 86.8627 ps.
    Task 4 :
    Observations.
    1) The schematic designed is of mirror adder in which the size of the carry circuit is
    optimized for speed. All other transistors in sum stage is kept of minimum size. The size
    of the carry circuit is kept three to four times that of the sum stage as it has to drive its
    internal gate capacitances as well as the gate capacitance of the adder cell.
    2) The contamination delay(minimum delay) and propagation delay(maximum delay)
    depends on the layout designed and increases after av extraction due to addition of the
    RC components in the layout.
    3) Verilog AMS is used to design stimulus and capture block which calculates the accurate
    delays.
    4) The delays can be further decreased by designing an optimum layout with short metal
    wire lengths and less use of vias.

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