Journal of the Korean Physical Society, Vol. 59, No. 2, August 2011, pp.

412∼415

Design of a 100 V High-side n-channel LDMOS Transistor for Breakdown

Voltage Enhancement

Kunsik Sung and Taeyoung Won∗

Department of Electrical Engineering, School of Engineering, Inha University, Incheon 402-751, Korea

(Received 19 April 2011)

In this paper, we discuss on the optimal design of a high-side n-channel lateral double-diffused
metal-oxide-semiconductor field-effect transistor (LDMOSFET) whose breakdown voltage is over
100 V with a 0.35-µm bipolar-complementary metal semiconductor- double diffused metal oxide
semiconductor process. The proposed nLDMOSFET was fabricated and tested in order to confirm
the features of a deep N+ sinker and the gap between the drift region (DEEP N-WELL) and the
center of the source. The surface was a implanted by the N-layer for a high breakdown voltage
and simultaneously a low specific on-resistance. The computer simulation of the proposed high-side
LDMOS exhibited a Breakdown voltage of 115 V and a specific on-resistance of as low as 2.20
mΩ·cm2 , which is consistent with the experimental results.

PACS numbers: 77.22.Jp, 81.07.Bc, 85.30.Tv, 85.30.-z

Keywords: LDMOS, High-side, BCDMOS, RESURF
DOI: 10.3938/jkps.59.412

I. INTRODUCTION age up to 80 V. However, the SOI process has short-

comings, such as high production cost and high process
Bipolar-Complementary metal semiconductor-Double temperature, which results in high power consumption.
diffused metal oxide semiconductor (BCD) process is In this paper, we propose a novel high-side n-channel
widely used in a variety of areas such as large displays LDMOS field-effect transistor with a breakdown voltage
(TVs and monitors), small displays (hand-held and mo- over 100 V while keeping the thermal budget for the
bile), POE (power-on-ethernet), and storage controller conventional 0.35-µm BCD process. The proposed n-
chips. Recently, many companies have made an effort to channel LDMOSFET has a deep N+ sinker and a struc-
combine power management, logic, audio and communi- ture with a gap of 5.5 µm between the DEEP N-WELL
cation functions in a single chip. Therefore, much larger and the center of the source, the surface of which is im-
logic content has been integrated into BCD technology planted with an n-layer for a high breakdown voltage and
[1–7]. The process involves a high-voltage DE (drain- simultaneously for a low specific on-resistance. In addi-
extended) CMOS, a LDMOS (lateral double-diffused tion, the proposed process requires no additional process
MOS), a BJT (bipolar junction transistor), a low-TC steps other than one mask step and ion-implantation,
(temperature coefficient) resistor, a 1 ∼ 2 fF/µm2 MIM which allows integration with logic CMOS and all the
(metal-insulator-metal) capacitor, and so on. other existing components.
When the n-channel LDMOS is operated in the high-
side mode, the source voltage can be raised above the
substrate voltage because the source is connected to the II. EXPERIMENTS AND DISCUSSION
load of the next stage. In order to resolve this electrical
isolation problem, a NBL (n+ buried layer) is purposely In order to devise an optimized LDMOS structure, we
inserted beneath the source region, which prevents the performed a 1D/2D process and device simulations with
punch-through phenomen between the source and the Synopsys TSUPREM-4 and MEDICI. In this work, we
substrate. The NBL, however, tends to limit the break- made a deep N+ sinker and varied the size of the gap
down voltage (BVdss) because the high doping concen- between the drift region (DEEP N-WELL) and the cen-
tration of the NBL drives out the extension of the deple- ter of the source for a fixed P-EPI layer with a thick-
tion region. In order to resolve this limitation, scientists ness of 8.1 µm and a doping concentration of 1 × 1015
have proposed to utilize the SOI (silicon-on-insulator) atom/cm3 , respectively.
substrate for implementing the LDMOS devices for volt- Figure 1 presents a diagram illustrating cross-sectional
views of the conventional LDMOS structure and the pro-
∗ E-mail: [email protected]; Fax: + 82-32-862-1350 posed structure with/without a deep N+ sinker under
-412-
Design of a 100 V High-side n-channel LDMOS Transistor · · · – Kunsik Sung and Taeyoung Won -413-

Fig. 1. (Color online) Cross-sectional view of the high-side LDMOS: (a) conventional structure, (b) proposed structure
without a deep N+ sinker, and (c) proposed structure with a Deep N+ Sinker.

Fig. 4. (Color online) Breakdown characteristics for the

Fig. 2. (Color online) Doping profiles for the (a) conven- proposed and the conventional high-side LDMOS structures
tional structure, (b) proposed structure without a deep N+ with the same drift region lengths.
sinker, and (c) proposed structure with a deep N+ sinker.

P-body and the NBL are denser than there of the pro-
posed one at VDS = 70 V, which implies that a higher
electric field, which limits the breakdown voltage, ex-
ists in the depletion region for the conventional high-side
LDMOS. We should note that, in contrast to the DEEP
N-WELL, the proposed LDMOS experiences has a gap
which mitigates the electric field crowding due to lower
doping concentration of P-EPI (1 × 1015 atom/cm3 ).
Figure 4 presents diagrams illustrating the breakdown
Fig. 3. (Color online) Potential distribution at VDS = 70 characteristics for the proposed and the conventional
V for the (a) conventional structure, (b) proposed structure high-side LDMOS structures. The simulation results
without a deep N+ sinker, and (c) proposed structure with a shows that the breakdown point of the proposed device
deep N+ sinker.
shifts from 70 V to 115 V when we change the device
structure from the conventional device to the proposed
one.
study. Referring to Fig. 2, we can see that a carefully-
optimized gap (P-EPI) is inserted between the P-body
and the DEEP N-WELL. Figure 3 presents a diagram
III. EXPERIMENTAL RESULT
illustrating the electric potential lines of the proposed
structure, with the conventional one for comparison.
The potential distribution reveals that the equi-potential We fabricated 100-V high-side LDMOS transistors in
lines of the conventional high-side LDMOS between the our 0.35-µm BCD process. One additional mask layer
-414- Journal of the Korean Physical Society, Vol. 59, No. 2, August 2011

Fig. 5. (Color online) Experimental breakdown voltage

Fig. 7. (Color online) Experimental IDS -VDS and break-
and specific on-resistance for the proposed 100-V high-side
down voltage characteristics for 100-V high-side LDMOS
LDMOS as functions of the gap between the DEEP N-WELL
transistors.
and the source center.

Fig. 6. (Color online) Experimental breakdown voltage

and specific on-resistance for the proposed 100-V high-side Fig. 8. (Color online) Simulated impact ionization for the
LDMOS as functions of the gap between the N-layer and the proposed high-side 100-V LDMOS and the conventional LD-
source center. MOS at VDS = 70 V.

was used for the surface n-layer. Figure 5 shows the tors. The devices show good performance up to VG = 8
characteristics of the breakdown voltage and the specific V and VDS = 100 V. Generally, the on-state breakdown
on-resistance (RON,sp ) as functions of the DNWELL gap voltage of the LDMOS is lower than the off-state break-
from the source center. The breakdown voltage and the down voltage due to the Kirk Effect [8]. The surface
specific on-resistance are proportional to the DNWELL n-layer not only reduces the on-resistance but also effi-
gap. The proposed high-side LDMOS provides a break- ciently reduces the Kirk Effect to ensure a high on-state
down voltage of 110 V and a specific on-resistance of breakdown voltage. New paragraph figures 8 presents
2.20 mΩ·cm2 for a gap of 5.0 µm. New paragraph figure a schematic diagram illustrating the impact ionization
6 presents a schematic diagram illustrating the break- rate at 1.3 µm from the surface of the N-channel LD-
down voltage and the specific on-resistance (RON,sp ) as MOS transistor. Referring to Fig. 8, we see that the
a function of the N-layer gap from the source center for proposed device has a maximum impact ionization as
a DNWELL gap of 4.5 µm. Referring to Figure 6, we low as 2.44 × 1016 cm−3 s−1 at VDS = 70 V whereas
can see that the specific on-resistance is proportional to the conventional one has a value of 6.69 × 1019 cm−3 s−1
the DNWELL gap. However, the breakdown voltage re- at the same condition, which implies that the proposed
main almost unchanged. Therefore, we can see that the LDMOS reduces the carrier generation near the drain at
N-layer reduces the specific on-resistance while minimiz- high VGS and VDS to ensure a high on-state breakdown
ing the change in the breakdown voltage. New paragraph voltage [9–13]. New paragraph Fig. 9 shows the simu-
Figure 7 shows the forward IDS -VDS and the breakdown lated device structure and the impact ionization rates at
characteristics for the 100-V high-side LDMOS transis- VDS = 30, 50, and 70 V. The high impact ionization
Design of a 100 V High-side n-channel LDMOS Transistor · · · – Kunsik Sung and Taeyoung Won -415-

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This work was supported by the Inha University Re-
search Fund. The authors would like to express spe-
cial thanks to Dong-Bu Semiconductor for fabricating
the LDMOS devices.