2006:284 CIV

MASTER'S THESIS

Real Time Phase

Locked Loops

Hans Eklund

Luleå University of Technology

MSc Programmes in Engineering

Electrical Engineering
Department of Computer Science and Electrical Engineering
Division of Signal Processing

2006:284 CIV - ISSN: 1402-1617 - ISRN: LTU-EX--06/284--SE

Real Time Phased Locked Loops

HANS EKLUND

Department of Computer Science and Electrical Engineering

Lulea University of Technology
[email protected]

September 2004 to March 2005

 Abstract

This report covers a master thesis in signal processing. It deals with solving a
problem in a special type of audio encoder used in the Swedish speech newspaper
system. However, design methods and algorithms developed or investigated are
rather general. A large part of the report covers the fundamental theory of
phase locked loops and can be regarded as a beginners introduction to the field.
Along the way, the theory aims at a software implementation, and therefore
tries to deal with such specific matters. Also the issues with implementing a
time critical system in digital hardware is outlined and a custom method for
achieving phase-lock is presented. A successful implementation was made on a
digital signal processor based hardware platform.
Contents

1 Introduction 1
1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The audio encoder . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Phase locked loops 5

2.1 Building blocks of the LPLL . . . . . . . . . . . . . . . . . . . . . 6
2.2 Phase signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 A linear model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3.1 Phase detector . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3.2 Voltage controlled oscillator . . . . . . . . . . . . . . . . . 10
2.3.3 Divide by N circuit . . . . . . . . . . . . . . . . . . . . . . 11
2.3.4 The loop filter . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.5 The final linear model . . . . . . . . . . . . . . . . . . . . 16
2.4 Non linear properties . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.4.1 Unlocked behavior . . . . . . . . . . . . . . . . . . . . . . 19
2.4.2 Design criterion from a non-linear point of view . . . . . . 21
2.5 The Software Phase Locked Loop . . . . . . . . . . . . . . . . . . 22
2.5.1 Discretizing the LPLL . . . . . . . . . . . . . . . . . . . . 22
2.5.2 Hardware specific issues . . . . . . . . . . . . . . . . . . . 24

3 Results 29
3.1 Matlab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2 Real-time hardware implementation . . . . . . . . . . . . . . . . 30
3.2.1 Hardware specification . . . . . . . . . . . . . . . . . . . . 30
3.2.2 Developing environment . . . . . . . . . . . . . . . . . . . 30
3.2.3 Measurements . . . . . . . . . . . . . . . . . . . . . . . . 32

4 Conclusion 35

A Program code 36

iii
iv
List of Figures

1.1 Functional description of the coder. . . . . . . . . . . . . . . . . . 2

1.2 Spectral contents of baseband FM-radio, the MPX signal. . . . . 2
1.3 Scrambling audio by Vestigial sideband modulation. . . . . . . . 3

2.1 Complex representation of two signals. The arrows move around

since their phase (angle) is a function of time. The speed of the
rotation is the frequency of the sinusoids. . . . . . . . . . . . . . 5
2.2 Block diagram of a linear PLL. . . . . . . . . . . . . . . . . . . . 6
2.3 A few signals applied to a PLL. Observe the relationship between
frequency and phase signals. (a) Frequency step. (b) Frequency
ramp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 A simple control system with a regulator, process and feedback. . 9
2.5 Bode diagram of the filter types mentioned. (top) Passive lag
filter. (mid) Active lag filter with Ka = 10. (bottom) PI-filter,
observe the high gain near DC. . . . . . . . . . . . . . . . . . . . 14
2.6 Linear model of the PLL. . . . . . . . . . . . . . . . . . . . . . . 14
2.7 Step response of the LPLL error function for various damping
factors ζ when system is set to follow at half the frequency of the
input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8 Amplitude response of the LPLL for various damping factors, ζ,
plotted against normalized frequency ω/ωn . . . . . . . . . . . . 18
2.9 The various ranges of interest for a linear PLL. . . . . . . . . . . 20
2.10 The pull-in process for a LPLL implemented in software. it fi-
nally settled at 21 × π = 65.97 radians out of phase. . . . . . . . 21
2.11 Analog PI filter and its digital counterpart created using the
bilinear transform. . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.12 An SPLL with secondary oscillator controlled by a phase ad-
justing subsystem. The dashed line is the adjustments made at
specific times decided by the parameter decision block, and not
at system sampling instances. . . . . . . . . . . . . . . . . . . . . 26
2.13 Improvement in signal quality due to a slower loop filter switched
in when system is locked in frequency. . . . . . . . . . . . . . . . 28

3.1 The signals of importance in a discrete linear PLL. It is locked

to a noisy input of 4.1 kHz. . . . . . . . . . . . . . . . . . . . . . 31
3.2 Spectrogram of input and output to the SPLL implemented on
a DSP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

v
3.3 Oscilloscope dump of the SPLL input at 19 kHz and the in phase
locked half frequency output. . . . . . . . . . . . . . . . . . . . . 34
3.4 Oscilloscope dump of the FFT of the SPLL output. 10dBV per
square. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

vi
Acknowledgement

Thanks goes to the Rubico AB founders Anders and Per for having
me as their Master Thesis student and for their support in every
aspect. Thanks to James Leblanc for valuable insights and patience
in this long drama. Also, hats off for Robert Selberg for acting
as the thesis opponent. Thanks to the percolator for keeping the
coffee warm and aromatic. Finally, thanks to all the staff, current
and past, at Rubico for being around for support and laughter.

Hans Eklund, September 2006.

vii
viii
Chapter 1

Introduction

Engineering is all about development. This master thesis uses new technology
to improve an old system. In this case the new technology are digital signal
processors - DSP. The system in need of improvement is the Swedish speech
newspaper distribution system.

1.1 Overview
The speech newspaper system has been available since mid nineteen eighties
and makes newspapers available to the visually impaired. Newspaper staff read
and record the written articles, advertisements, radio and TV tableaus etc. The
speech newspapers are distributed by mail on a tape, or via an ordinary FM
network, taking advantage of unused channel capacity during night.
The technique used in several parts of the current system were developed
during that time. One part sits in between the recording studio and the FM
link. That part scrambles the speech in a certain way to ensure only subscribers
of the speech newspaper can listen to it. Currently, the scrambling is performed
by analog electronics that has to be tuned once a year. It has now been proposed
that the old audio encoder may be replaced by a more flexible digital system.
Using a digital method to scramble the audio is attractive in several aspects.
First and foremost, the aspect of quality. Using the old analog equipment
requires regular service and tuning of parameters. With a digital platform the
way the audio gets encoded does not change with time. Second, the new coder
platform is flexible and will be easy to upgrade for future demands.

1.2 The audio encoder

The audio encoder consists of a few interconnected filters and a modulation
method as shown in Fig. 1.1. First, the audio is band limited by a sharp band-
pass filter. The filter cancels frequencies below 40 Hz and above 6.3 kHz. The
signal can now be modulated onto a 9.5 kHz carrier and then low pass filtered
to suppress the upper sideband, this scheme of modulation is called Vestigial
Sideband (VSB) modulation. VSB modulation is basically a compromise be-
tween Single Sideband (SSB) and Dual Sideband (DSB) modulation. All three
2

are common in analog communications theory, see [1] for details. The effect
is that the frequency contents will be reversed if not decoded correctly, high
pitch sound will become low and vice versa, as seen in Fig. 1.3. Before sending
the modulated audio to the external FM network, a disturbing 1 KHz tone is
added to further decrease the hearability. At the heart of the scrambling al-

VSB Modulation

Audio 40 Hz - 7 kHz Lowpass Encoded

input bandpass filter output

9.5 kHz
MPX tone 1 kHz
input PLL tone

Figure 1.1: Functional description of the coder.

gorithm is the VSB modulation that shifts the spectrum, as described earlier.
The audio has to be modulated upon a signal at half the frequency of a 19 KHz
tone available in the so called MPX signal. The MPX signal is the baseband
information signal in the FM system with spectral contents roughly as seen in
Fig. 1.2. How do we generate a signal, locked in phase, at exactly half the
frequency? And what method is suitable for a software implementation?

Audio (Mono) DSB-SC RDS

carrier
Pilot

L+R L- R (lower L-R (upper

sideband) sideband)

0 15 19 23 38 53 57 f in kHz

Figure 1.2: Spectral contents of baseband FM-radio, the MPX signal.

1.3 Objectives
The coding method in the system is obsolete in many ways. The coding is
performed in a way that is really sub par when it comes to security, but for
the application it works. If the system would be replaced by an entirely digital
one, the coding method would be of another kind. However since the coder has
to be backward compatible with old receivers, the new coder has to be able to
1.3 Objectives 3

Baseband information signal after 40−7KHz bandpass.

40

20

−20
−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1
4
x 10
Spectrum of signal after modulation upon 9.5Khz carrier.
40
Magnitude [dB]

20

−20
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2
4
x 10
Spectrum of signal after VSB filter.
40

20

−20
−2 −1.5 −1 −0.5 0 0.5 1 1.5 2
Frequency[Hz] x 10
4

Figure 1.3: Scrambling audio by Vestigial sideband modulation.

implement the analog scrambling described above. Most of the blocks in the
coder are more or less trivial to implement, such as filters and the modulation.
As hinted above, the block that needs extra attention is the synchronization
block used to synthesize the 9.5 kHz signal before the VSB modulation scheme.
The company that wanted this thesis to be made initially had experience,
equipment and software already available for a specific platform. So the solution
had to be tailored for that particular target. Therefore, the main objective of
the thesis was to investigate the possibility of implementing the synchronization
block in a DSP for a real time application.
The specifications on what to be accomplished where quite clear though.
The audio input was to be modulated onto a carrier at exactly half the frequency
of the 19 kHz MPX-signal and at a specific phase shift. Early on a possible
solution to the problem was seen. It was concluded that a phase locked loop
might do the job, if properly designed. However, the field of phase-locked loops
4

is deep and somewhat intricate. A thorough study on the subject was made to
lay the foundation to the design.

1.4 Outline
The report is structured into two main blocks. An introduction and design
guide to phase locked loops with en emphasis on software implementation comes
first. The chapter after is shorter and provide a presentation of a working
implementation of the theory. Last of all the results are discussed and further
work are suggested.
Chapter 2

Phase locked loops

A Phase-locked loop is a device that makes one system track another. It syn-
chronizes an output signal with a reference in frequency and in phase. Here
one system is the pilot tone from the MPX-signal and the other is our own syn-
thesized signal. Both are periodic functions of time, sinusoids or square waves.
However, instead of viewing the two signals as functions of time, think of them
as phasors in the complex plane. As complex phasors, the two signals are two
vectors rotating around the plane. Fig. 2.1 demonstrates the concept. The

Im{zn}

j(w1t)
z1 = e

z2 = ej(w2t)
q1
q2
Re{zn}

Figure 2.1: Complex representation of two signals. The arrows move around since their
phase (angle) is a function of time. The speed of the rotation is the frequency
of the sinusoids.

phase at any instant is a function of time, in general

Z t
θn (t) = ωn (t)dt.
−∞

The phase is the property of interest for the PLL designer. As an example,
assume the first vector is rotating at constant angular frequency ω1 (t) = ωc . To
make the new, generated signal follow the input signal, the new one has to adjust
6 Phase locked loops

its phase to minimize the distance to the reference, that is the phase error,
denoted as θe . Adjusting its phase is done by either increasing or decreasing its
angular frequency. When both vectors are moving about at the same rate we
say they are locked to each other. In the locked state the phase error between
the two systems are zero or constant, depending on the system design. If the
reference signal deviates from its current angular frequency and a phase error
develops, a control system acts upon the second system to make the phase error
smaller. The control system locks the phase of the output to the input, hence
the name - Phase locked loop.
Phase locked loops are used mainly in two fields of application. When
analog signals are modulating a high-frequency carrier the PLL is needed to
demodulate the received signal back to the baseband. Classical modulation
schemes include amplitude modulation (AM), frequency modulation (FM) and
phase modulation (PM). An important application was found in 1950, the color
subcarrier in television systems was recovered with the use of a PLL.
The other important application is in the field of frequency synthesis, that is
creating a signal with correct and stable frequency. The synthesis application
is commonly found in the sending part of communication systems where the
carrier is created for bandpass signaling. By synthesis we mean that a signal
from an oscillator is fed to the PLL and the output is a signal with another
frequency.
In this thesis, the application is frequency synthesis and the PLL described
below is designed for that purpose. It does not differ much from the PLL used in
receivers, the main difference is a parameter used to set a multiplication/division
ratio of the input frequency.

2.1 Building blocks of the LPLL

Lets have a closer look at the first class of PLLs - Linear PLLs (LPLL). There
are other types of PLLs, digital PLLs (DPLL) and All-digital PLLs (ADPLL).
All of which can be implemented as the last class - the Software PLL (SPLL)
- a phase locked loop that is running on a processor controlled by a suitable
program. Linear PLLs consists mainly of four components as seen in Fig. 2.2.
First the phase of the generated signal and the phase of the reference input

uin(t)
Phase Loop VCO
uout(t)
detector filter
ufb(t)

Frequency
divider

Figure 2.2: Block diagram of a linear PLL.

2.2 Phase signals 7

has to be compared somehow. One way of achieving that is to do a simple

multiplication and a subsequent filtering operation done by the loop filter, which
is the second component of the LPLL. The filter poles and zeros has to be chosen
carefully to make the PLL act as desired. The filtered phase signal is then fed to
a voltage controlled oscillator (VCO). The VCO is an oscillator working around
a quiescent frequency. The deviation from that frequency is determined by the
control-signal fed to it. The last block is the frequency divider, it divides (or
multiplies) the frequency that is fed back to the phase detector. It is often
called ’divide by N circuit’.
To make a PLL cope with design specifications, care has to be taken when
choosing the three components. When implementing a LPLL using analog
components, the designer is most often left with pre manufactured mixers and
VCO. In that case the filter becomes the main design issue. Assuming that,
lets have a look at a model of the LPLL. Despite its name, the Linear PLL is
not as linear as one may think. However, a linear model can be made as a first
approximation. But before delving into a linear model we must make a few
things clear.

2.2 Phase signals

As pointed out by Best [2], phase signals are a source of much trouble when
understanding phase locked loops. For the PLL designer a signal such as

A1 sin(ω1 t + θ1 (t)) (2.1)

carries its information, not in the amplitude A1 , not in its frequency ω1 , but
in the phase θ1 (t). To clarify what happens in phase when the frequency is
changed in a certain way, a few examples might help. Assume that the frequency
is constant, ω0 for t < 0 and then abruptly changes frequency by ∆ω at t = 0.
That is, makes a frequency step as seen in Fig. 2.3a. After t = 0 the reference
frequency can be written as

u1 (t) = A1 sin((ω0 + ∆ω)t) = A1 sin(ω0 t + θ1 ) (2.2)

That is, the phase θ1 can be expressed as

θ1 (t) = ∆ωt (2.3)

We clearly see that the phase signal θ1 is a ramp with slope ∆ω. That reminds
us of an important relationship to always bare in mind, the angular frequency
of a signal is the first derivative of its phase with respect to time,
dθ1
ω1 = .
dt
So whatever is done in frequency, expect the phase signal to be the integral
of the frequency action. Another example, if the signal changes frequency lin-
early, that is, makes a frequency ramp, the phase of the signal will increase
quadratically, see Fig. 2.3b.
8 Phase locked loops

(a) − Frequency step (b) − Frequency ramp

Amplitude 1 1

0 0

−1 −1
−1 0 1 −1 0 1
Frequency of signal Frequency of signal
0.02 0.2
rad/s

0.01 0.1
0 0
−1 0 1 −1 0 1
Phase of signal Phase of signal
50 200
rad

0 0
−50 −200
−1 0 1 −1 0 1
time time

Figure 2.3: A few signals applied to a PLL. Observe the relationship between frequency and
phase signals. (a) Frequency step. (b) Frequency ramp.

2.3 A linear model

Considering input and the output of the PLL are phase signals, we can do the
system analysis using the transfer function H(s). Hence, we consider the system
linear with respect to phase relationships. We also assume that the LPLL is
locked and remains so in the near future. The Laplace transforms of the input
and output phase functions, θin (t) and θout (t) respectively, defines the transfer
function
Θout (s)
H(s) = . (2.4)
Θin (s)

The function H(s) is now a phase transfer function, and the model is only valid
for small changes in phase of the reference, if the phase error becomes too big
too fast, the LPLL will unlock and a non-linear process takes place. Although
that process is described by a cumbersome non-linear differential equation it
can be understood on an intuitive level.
To express H(s) we must know the transfer functions of the three building
blocks of the LPLL, as seen in Fig. 2.2. As stated earlier, a PLL is nothing but
a control system for phase signals, therefore we can rely on basic control theory
when explaining the linear model. A control system with a regulator in series
with a process has a well known transfer function when the process output is
fed back and subtracted from the system input as in Fig. 2.4.
2.3 A linear model 9

Regulator Process

uin(t) + e(t) uout(t)

Gr(s) Gp(s)
-
ufb(t)

Gg(s)

Feedback system

Figure 2.4: A simple control system with a regulator, process and feedback.

Let the regulator have the transfer function Gr (s) and the process in need
of regulation have the transfer function Gp (s). The system transfer function is
then described by
Gr (s)Gp (s)
H(s) = . (2.5)
1 + Gr (s)Gp (s)Gg (s)
Such a relationship is derived by any basic text on control theory, such as [3]. In
the PLL case the regulator is the loop filter and the process in need of regulation
is the VCO.

2.3.1 Phase detector

Reviewing Fig. 2.2, and as earlier stated the input to the LPLL is usually a
sine wave,
uin (t) = Uin sin(ωin t + θin ).
The signal generated by the VCO, fed back through the divider is another
sinusoid,
uf b (t) = Uf b sin(ωf b t + θf b ).
The phase difference between the two signals are obtained by multiplying the
two signals and then filtering the result. That is the sole operation of the phase
detector. The behavior has to be modeled in a linear fashion. Assuming the
PLL is close to locked or locked in frequency, we have ω = ωin = ωf b and the
operation becomes

ud (t) = Uin sin(ωt + θin )Uf b sin(ωt + θf b ) (2.6)

By trigonometric simplification using the relation

1
sin(α) sin(β) = (cos(α − β) − cos(α + β)),
2
the output of the phase detector becomes

Uin Uf b
ud (t) = (cos(θin − θf b ) − cos(2ωt + θin + θf b )). (2.7)
2
10 Phase locked loops

The first term is the wanted ”dc” component. The higher order component
cos(2ωt + θin + θf b ) will be canceled by the subsequent filter, hence they can be
neglected in the linear model. The output can then be simplified to

ud (t) = Kd cos(θe ) (2.8)

Where Kd = Uin Uf b /2 and θe = θin − θf b . This is a non-linear relation. Zero

phase error should correspond to zero output of the detector. Likewise, small
errors in phase should correspond to small outputs from the detector. A solution
to this is obtained by making uin (t) and uf b (t) π/2 radians out of phase, that is,
replacing uf b (t) for example with a cosine function. The trigonometric relation
1
sin(α) cos(β) = (sin(α − β) + sin(α + β))
2
explains the operation. In place of Eq. 2.35, the input/output relationship of
the phase detector will be
Uin Uf b
ud (t) = (sin(θin − θf b ) + sin(2ωt + θin + θf b )). (2.9)
2
Again neglecting the higher order component, the simplified input/ouput rela-
tionship becomes
ud (t) = Kd sin(θe ). (2.10)
And for small errors in phase, the assumption

ud (t) ≈ Kd θe (2.11)

is valid. The LPLL simulated in Chapter 3 below behaves as predicted by the

above theory; the feedback uf b (t) is always π radians out of phase with the
input uin (t) when the phase error θe is close to zero.
Concluding the phase detector discussion, the linearized model is just a zero-
order block having gain Kd = Uin Uf b /2. Remark: the loop filter is actually a
part of the phase detector in the linear model since it cancels the higher order
components. We will deal with the filter properties right after the derivation of
the VCO model.

2.3.2 Voltage controlled oscillator

The VCO generates a square or sinusoidal signal, which frequency depends on
the input signal level. It operates around a quiescent frequency ωc , preferably
close to the signal that we want to lock on. If the VCO output u( out), is
sinusoidal it depends on the input uf (filter output, not to be confused with
the feedback signal, uf b ) in the following way:

uout = cos((ωc + Ko uf (t))t). (2.12)

The parameter Ko is called VCO gain, and is specific to the selected VCO. It
has to be considered when designing PLLs in hardware when the VCO is not
designed from scratch, but chosen suitably. K0 has the dimension rad s−1 V −1 .
2.3 A linear model 11

When designing the PLL in software it can be arbitrarily chosen since the filter
design will accommodate for it. More on determining constants in section 2.3.5.
However, what we need is the transfer function of the VCO. As seen in Eq. 2.12
the angular frequency of the VCO is
ωout (t) = ωc + Ko uf (t)
But we do not want to express the VCO frequency, we want the phase transfer
function. Therefore, by definition, the phase θout (t) is given by integration of
the frequency variation K0 uf (t).
Z Z
θout = K0 uf dt = K0 uf dt

The laplace transform for integration over time is 1/s. The laplace transform
for the output phase θout is then
K0
Θout (s) = Uf (s) (2.13)
s
The transfer function of the VCO is then simply
Θout (s) K0
= (2.14)
Uf (s) s
Therefore the VCO is nothing but an integrator for phase.

2.3.3 Divide by N circuit

The classical linear PLL used for frequency synthesis is suppose to generate a
periodic signal of frequency
N
ωout (t) = ωin (t). (2.15)
M
Where N and M are integers. Analog linear PLL implements the integer divi-
sion in frequency by counting and triggering on every N pulses, and there by
generating a square wave at N times lower frequency. That is not a problem
since the fundamental component of the square wave is the one that locks to the
reference input, remembering that the loop filter cancels the higher components
in the square wave as well. A divider before the PLL input makes the signal
have M times lower frequency in the same way. Selecting the divide ratios N
and M suitably, any division ratio can be obtained.
In this thesis another method is used since the PLL is implemented in
software. With that method the M-divider can be discarded since N can be a
fractional number. When locked, ωf b = ωin , therefore
ωout (t) = N ωf b (t). (2.16)
The relationship described by Eq. 2.16 has to be modeled for the phase signals
in the linear model. The relationship is simple, but the derivation is done for
the sake of completeness. From
Z
θ(t) = ω(t) dt,
12 Phase locked loops

and integrating both sides of Eq. 2.16

θout (t) = N θf b (t)

The transfer function for the N-divider is then

θf b (t) 1
= = Kn (2.17)
θout (t) N
Acting upon the phase signal in the feedback is simply a gain factor Kn .

2.3.4 The loop filter

So far we have assumed that a filter exists in the LPLL to cancel higher order
components so the wanted dc term, the phase error, can be used to control the
VCO. However the loop filter has another function. Viewing the LPLL as a
control system for phase signals, the loop filter is the regulator. Bertil Thomas
[4] mentions that in control theory the regulator mainly has two tasks. One is
to compensate for disturbances that affects the system. The other is to take
necessary actions when the desired value is changed. In the PLL case, the
desired value is the current phase of the input signal. When determining how
well a regulator can cope with the two tasks several properties can be studied.
Properties such as static accuracy, speed and stability.
As this paper deals with the design of an audio coder and its clear specifi-
cations, the discussion will be taken to solve that problem and not the general
one since it is beyond the scope of this thesis.

Closed loop performance demands

The choice of the loop filter is critical to the system performance. Beginning
with the specifications of the coder a few hard demands has to be met. The
coder has to modulate the audio input onto a carrier operating at exactly half
the frequency of the FM pilot tone. The divide by N-circuit described above
make that behavior possible.

Static accuracy Since we can only tolerate a small phase difference or drift
between the pilot tone input and the half frequency output we have defined the
demand of static accuracy: zero remaining error when the input is changed.
It has to be asymptotically zero independently how the input is changed. The
regulator has to cope with whatever action is done at the input.

Speed Another important property of a control system is the speed. When

the desired value is changed in some manner, it takes some time for the output
of the system to change and finally settle at the new value. Several measures
of speed exists and one common is the rise time. The rise time is defined
as the time it takes for the output to go from 10% to 90% of its final value.
Remembering that we are dealing with a linearized model of an actual system,
other non-linear properties of the LPLL defines the settling speed when the
system unlocks and has to work towards a locking state. More on such effects
2.3 A linear model 13

below. Also speed and stability are contradictory demands, higher speed implies
smaller stability margins and vice versa. I let the speed demand be defined as:
as fast as possible when stability demands are met. Defining the speed of the
system comes down to make the closed loop system have a suitable damping
factor.

Stability This is probably the most important, and therefore the most com-
plex part of the entire paper. As hinted above the actual behavior of the LPLL
is described by a non linear differential equation. The complete system stabil-
ity and how the filter affects it in all situations is not theoretically derived or
predicted by this thesis due to its high complexity. Instead testing and simula-
tions of the system is made to ensure that the system is stable even when in its
non-linear mode of operation. The linear part of the stability problem however,
can be analyzed using the properties of linear systems using the model derived
in this chapter. Stability issues is discussed further below, once the filter type
is selected.

Selecting a filter

The selection of the correct loop filter implies the selection of the type and
order of the filter so the closed loop system type and order can accommodate
the above demands. Type refers to the number of poles in the transfer function,
the order is the same as the highest degree of the characteristic equation. Best
[2] mentions three basic filter types common in PLL applications, seen in Fig.
2.5. Clearly they are all low pass filters with different cutoff frequencies. The
first is called passive lag filter. Its transfer function F(s) is given by

1 + sτ1
F1 (s) = (2.18)
1 + s(τ1 + τ2 )

The second type has a similar transfer function, but has an additional gain term
Ka , given by
1 + sτ2
F2 (s) = Ka (2.19)
1 + sτ1

The last type of filter suggested is commonly referred to as a ”PI” filter. PI

stands for proportional and integrating action, taken from control theory. Its
transfer function is
1 + sτ2
F3 (s) = (2.20)
sτ1

But how do we motivate the selection of one and not the other? The criterion
of static accuracy is zero phase error. A filter that fulfills that criterion will be
a strong candidate. The phase is defined as Θe = Θin − Θf b , seen in Fig. 2.6.
14 Phase locked loops

Magnitude (dB) −10

−20

−30
−3 −2 −1 0 1 2
10 10 10 10 10 10
Frequency (rad/sec)

20
Magnitude (dB)

10

−10
−3 −2 −1 0 1 2
10 10 10 10 10 10
Frequency (rad/sec)

40

30
Magnitude (dB)

20

10

−10
−3 −2 −1 0 1 2
10 10 10 10 10 10
Frequency (rad/sec)

Figure 2.5: Bode diagram of the filter types mentioned. (top) Passive lag filter. (mid) Active
lag filter with Ka = 10. (bottom) PI-filter, observe the high gain near DC.

Phase detecor Loop filter VCO

Qin(s) + Qe(s)
Kd
Ud(s)
F(s)
Uf(s) _K 0
Qout(s)
s
-
Qfb(s)

Kn

Feedback gain

Figure 2.6: Linear model of the PLL.

2.3 A linear model 15

By looking at the error signal Θe as a system output, we can define a phase

error transfer function as
Θe (s) 1
E(s) = = . (2.21)
Θin (s) 1 + Kd F (s) Ks0 Kn
Knowing the error transfer function, we can find the error function θe (t) for any
given input θin (t) since
Θe (s) = Θin (s)E(s), (2.22)
by inverse transformation of Θe (s). But since we want to find the error as time
goes to infinity, the final error, we can take a shortcut by using the final value
theorem of laplace transforms:

Assume that g is causal and that G = L{g} is rational. If all poles to sG(s)
has negative real part, then
lim g(t) = lim sG(s)
t→+∞ s→+0

It gives us the opportunity to find the error as time goes to infinity without
having to transform Θe (s) back to the time domain.
Tracking frequency means that the frequency of the feedback signal uf b (t)
has to be adjusted correctly by the VCO if a new frequency suddenly appears
in the reference uin (t). That is, the system senses a frequency step. Now recall
that a frequency step, as in Fig. 2.3, really is a phase ramp for our linear system.
Therefore we know what our system has to deal with to follow specifications.
The laplace transform of the a phase ramp input is
Cv
Ri (s) = ,
s2
as given by any laplace transform table, or derived by any text on linear systems
such as [5]. Cv is the frequency difference in radians per second at the phase
detector. If a the phase ramp is applied to our error transfer function as in Eq.
2.22, we have the Laplace transform of the error as
Cv 1 Cv
Θe (s) = Θin (s)E(s) = 2 K
= 2 (2.23)
s 1 + Kd F (s) s Kn
0 s + Kd K0 F (s)Kn s
Now following the final value theorem we get
Cv
lim θe (t) = lim sΘe (s) = lim s (2.24)
t→+∞ s→+0 s→+0 s2 + Kd K0 F (s)Kn s
The final expression is then
Cv
lim θe (t) = lim (2.25)
t→+∞ s→+0 s + Kd K0 F (s)Kn

Any filter transfer function F (s) can now be inserted in Eq. 2.25 to obtain the
final error when the system is subject to a phase ramp. A generalized filter
transfer function can be expressed as
N (s)
F (s) = . (2.26)
D(s)sn
16 Phase locked loops

Where N (s) and D(s) are the nominator and denominator polynomials respec-
tively. in the laplace domain, sn are poles at s = 0. Inserting Eq. 2.26 into Eq.
2.25 gives us
Cv Cv D(s)sn
θe (∞) = lim = lim (2.27)
s→+0 N (s)
s + Kd K0 D(s)s s→+0 sn+1 D(s) + Kd K0 Kd N (s)
n Kn

Inspection of Eq. 2.27 tells us that if n ≥ 1 the limit will approach zero as time
goes to infinity. We can therefore state that if we want our LPLL to track the
reference phase with zero phase error, a filter pole in s = 0 is needed.
For example,the first filter suggested by Best [2]. Inserting Eq. 2.18 into
2.25 gives us
Cv Cv
lim θe (t) = lim 1+sτ1 = , (2.28)
t→+∞ s→+0 s+ Kd K0 1+s(τ Kn Kd K0 Kn
1 +τ2 )

1+sτ1
by observing that 1+s(τ 1 +τ2 )
→ 1 as s → 0. That filter does not reduce the
error to zero, however it may very well do if the loop gain(Kd K0 Kn ) is kept
high enough. The second filter, F2 has a similar transfer function and yields a
similar final error, reduced by the amplification factor Ka . The third suggested
filter, the ”PI filter” of Eq. 2.20 has a pole in s = 0 and should be a candidate
capable of reducing final error to zero. The error is calculated as
Cv
lim θe (t) = lim =0 (2.29)
t→+∞ s→+0 s + Kd K0 1+sτ
sτ1 Kn
2

by observing that the filter part 1+sτsτ1

2
→ ∞ as s → 0. The pole in s = 0
provides the filter with, at least theoretically, infinite gain at DC and therefore
the system reduces any remaining phase error to zero eventually.
Concluding the filter discussion, as motivated above the filter type for this
particular LPLL application will be of the ”PI” type,
1 + sτ2
F (s) =
sτ1
What remains in the filter design is selecting the constants τ1 and τ2 appropri-
ately. This will be done in the next section.

At this point, we have covered the four main blocks of the linear model
of the LPLL. By closing the loop and seeing it as a feedback control system,
the final analysis can be made. The filter and amplification constants can be
selected to give the system its desired overall characteristics.

2.3.5 The final linear model

Summarizing the blocks covered above, as depicted in Fig. 2.6, the phase
transfer function is
Θout (s) Kd F (s) Ks0 Kd 1+sτ
sτ1
2 K0
s
H(s) = = = (2.30)
Θin (s) 1 + Kn Kd F (s) Ks0 1 + Kn Kd 1+sτ
sτ1
2 K0
s
2.3 A linear model 17

by remembering the general transfer function for control theory as in Eq. 2.5.
When analyzing the closed loop it is convenient to put the transfer function on
a special form, the so called normalized form, by making the dominator be

D = s2 + 2ζωn s + ωn2

where ωn is the natural frequency and ζ is the damping factor. Simplifying Eq.
2.30 further,

Kd K0 (1 + τ2 s) Kd K0 (1+τ
τ1
2 s)

H(s) = = Kd Kn K0 τ2 Kd Kn K0
(2.31)
τ1 s + Kd Kn K0 (1 + τ2 s) s2 + τ1 s + τ1

Then the substitution can be made:

s
K0 Kd Kn ωn τ2
ωn = ζ= (2.32)
τ1 2

The final phase transfer function can then be written as

1 2
Kn (2ωn ζs + ωn )
H(s) = (2.33)
s2 + 2ωn ζs + ωn2

Also, the phase error transfer function, Eq. 2.21 can be rewritten in terms of
the defined damping factor and natural frequency as

1 s2
E(s) = 1 − H(s) = (2.34)
Kn s + 2ωn ζs + ωn2
2

From this point, using Eq. 2.33 it is easy to investigate the transient response
of the PLL as we would on any control system. The parameters ωn - the natural
frequency, and ζ - the damping factors, are key design parameters. Once they
are determined, the filter parameters τ1 and τ2 can be obtained and the PLL
design is complete. A system with a high damping factor is said to be over
damped and the response may become sluggish. If the damping factor is too
low, as in an under damped system, the system may become oscillatory. Setting
ζ = √12 is usually a good tradeoff between speed and stability. We see how the
damping factor ζ affects the step response of the error function in Fig. 2.7.
18 Phase locked loops

0.8

0.6
e

←ζ=2.00
θ

0.4 ←ζ=0.71
←ζ=0.30
0.2

←ζ=0.05
0
0 0.05 0.1 0.15 0.2
Time[sec.]
Figure 2.7: Step response of the LPLL error function for various damping factors ζ when
system is set to follow at half the frequency of the input.

How about criterions for determining a suitable natural frequency? When

designing a PLL for frequency synthesis purposes it is vital that the signal
generated is pure. Looking at the amplitude response of the closed loop in Fig.
2.8, we could view the PLL as a filter. Recall that the double frequency tone

20

10
|E(jω)|(dB)

−10 ←ζ=2.00
←ζ=0.71
−20
←ζ=0.30
−30
←ζ=0.05
−40
−1 0 1 2
10 10 10 10
ω/ω
n

Figure 2.8: Amplitude response of the LPLL for various damping factors, ζ, plotted against
normalized frequency ω/ωn

generated by the phase detector is nothing but noise for this application. The
2.4 Non linear properties 19

tone will affect the VCO and make it tremble around its desired frequency.
Therefore we may want to narrow down the bandwidth of the system to make
the damping high at that double frequency. This is where the noise criterion
comes into the picture.
A low loop bandwidth will reject high frequency noise fed into, or created in
the system. But how low can it be set? For this particular PLL implementation
the input signal is most likely to be stable and it does not contain any baseband
information that needs to be preserved. If we were to design an FM receiver we
would have to consider the bandwidth of the baseband signal when determining
the natural frequency.
Determining a correct natural frequency ωn implies determining some im-
portant non linear properties of the LPLL. A brief overview of non linear LPLL
behavior will be covered in the next section and if it has any implications on
how the filter parameters will be calculated.

2.4 Non linear properties

A linear phase-locked loop actually has important non linear properties as well
as linear ones. When the reference frequency and the VCO has different fre-
quencies we say that the LPLL is in its unlocked mode and the linear model
derived above is not valid. We will not derive the non linear equation since it
is quite intricate.
As Best [2] states, it is not of major concern to know exactly what the LPLL
does when it is in the unlocked state. He mentions three important questions
though.

• Under what conditions will the LPLL get locked?

• How much time does the lock-in process need?

• Under what conditions will the LPLL lose lock?

The answers to those questions are not given by theoretical derivation of math-
ematical relations, instead experiments was conducted to ensure that the LPLL
performed well enough for the task. However the question of a suitable natural
frequency of the system still remains to be answered.

2.4.1 Unlocked behavior

The LPLL has four important stability regions. The regions are defined as
certain deviations in frequency from the quiescent frequency of the VCO and
how fast the reference frequency changes, as seen in Fig. 2.9. The following
definitions are taken from [2], with additional comments:
20 Phase locked loops

DwH Hold range

DwP Pull-in range

DwPO Pull-out range

DwL Lock range

w0

Figure 2.9: The various ranges of interest for a linear PLL.

1. The hold range ∆ωH . This is the range where the PLL can statically
maintain phase tracking. That is, if the reference frequency deviates this
far from the designed quiescent frequency the LPLL will unlock and the
phase error will go to infinity. This is independently of the speed the
frequency was changed.

2. The pull-in range ∆ωP . This is the range within which an LPLL will
always become locked if unlocked. This range can be infinite if the correct
filter is used. The pull-in process is slow and will be explained below.

3. The pull-out range ∆ωP O This is the dynamic limit for stable operation
of a PLL. If tracking is lost within this range, an LPLL normally will lock
again. This process is slow if it is a pull-in process. This defines how large
a frequency step the LPLL can handle without unlocking.

4. The lock range ∆ωL . This is the frequency range within which a PLL
locks within a single-beat note between reference frequency and output
frequency. It is independent of the speed the phase was changed, just as
long as it does not exceed this range.

The definitions are not specific to his book, but are standard terms among PLL
designers. However they do not apply to the other types of PLLs mentioned,
the digital PLL and the all-digital PLL.
As a vivid example of the non-linear behavior, an actual pull-in process
simulated in Matlab is shown in Fig. 2.10. The LPLL is initially locked in
phase (π/2 rad out of phase as explained above). At t = 1 a large frequency step
(larger than the pull-out range) is applied and the LPLL loses phase tracking,
but since the reference is within the pull-in range, the LPLL will try to pull the
VCO closer to the reference.
2.4 Non linear properties 21

Difference between input phase and feedback phase

60

50
Phase[rad]

40

30

20

10

0.9 1 1.1 1.2 1.3 1.4 1.5 1.6

Time[s]

Figure 2.10: The pull-in process for a LPLL implemented in software. it finally settled at
21 × π = 65.97 radians out of phase.

After the pull-in process, the linear locking phase takes place and it settles
at N × π out of phase, which is a true phase lock. In the unlocked state,
the phase detector modulates the VCO in a nonharmonic way. That implies
that the output of the VCO is nonharmonic. The frequency of the VCO is
then sometimes closer to the reference, and sometimes further from it. That
is, we have a time dependent frequency difference. But the frequency of the
VCO varies in such way that is more often closer to than further from the
reference. Therefore, in each cycle, the average frequency is slightly shifted
towards the reference. This asymmetry of the VCO causes it to change the
average frequency even faster towards the reference. The VCO is pulling itself
in.

2.4.2 Design criterion from a non-linear point of view

Depending on the choice of filter, the PLL will stay unlocked or slowly work
towards its locked state. It can be shown that a LPLL designed with filter
having a pole in s = 0 always becomes locked eventually. We can state that it
has infinite pull-in range. If speed is never an issue, the afore mentioned natural
frequency parameter ωn can be set very low to make the system minimize the
phase jitter noise. However if speed is crucial a trade off has to be found between
noise and speed. For the application under consideration the bandwidth will be
set low, making it slow and low noise. For quite stable 19 kHz input, a natural
frequency of around 20-50 hz proved to produce a pure input and still provide
a fast enough lock-in process.
22 Phase locked loops

2.5 The Software Phase Locked Loop

2.5.1 Discretizing the LPLL
After covering the theory of linear PLLs, a discrete model can now be made,
suitable for implementation on a digital signal processor. The fundamental rule
to follow when digitizing a signal or system is the Nyquist criterion. It states:
the sampling frequency has to be at least twice the highest frequency of the
signal if we want to avoid aliasing.
When moving from a continuous to a discrete model a discrete model of a
continuous system, we take one step closer to a working software implementa-
tion. However, it is not the final step. The target hardware platform has to
be taken into consideration. The hardware specific issues will be covered in the
next section, right after dealing with the discretized models.

Discrete phase detector

The phase detector is the part where aliasing effects may occur if we are not
careful. Since the phase detector is a multiplier, the output when subject to
two sinusoids is, as defined above,
Uin Uf b
ud (t) = (cos(θin − θf b ) − cos(2ωt + θin + θf b )). (2.35)
2
By observing the second term, cos(2ωt + θin + θf b ), the sampling frequency
has to be extended. The phase detector doubles the bandwidth requirements.
Therefore, the sampling frequency has to be four times the highest frequency
in the system to avoid aliasing. Depending on the frequency characteristics
of the input we may or may not have to extend the criterion. If it is pure
sinusoid and the resulting aliased frequency content does not affect the following
systems negatively it might suffice with twice the sampling frequency after all.
Problems arise when the aliased contents comes close to DC. It will then affect
the Software Controlled Oscillator (SCO) since the signal passes the discrete
low pass filter.

Discrete low pass filter

The loop filter has to be discretized in a suitable manner. Since minimum
complexity from a computational time viewpoint is wanted, an Infinite Impulse
Response (IIR) filter is the filter type to use. Also, since an analog filter model
is readily available, the design of the IIR filter is straightforward. An analog-to-
digital transformation has to be performed. Several such transformation exists,
among them are the Impulse Invariant Transform, The Backward Difference
Method and the Bilinear Transform. Porat[6] explains the theory behind them
and concludes that the bilinear transform is superior to other methods. It is
suitable for all filter types since it preserves the order and stability of the analog
filter. Also, the continuous frequency and phase responses is directly mapped
to the discrete ones. The bilinear transform is defined by the substitution
2 z−1
s← · (2.36)
T z+1
2.5 The Software Phase Locked Loop 23

An additional operation called pre-warping is also performed when using the

bilinear transform to overcome the frequency warping introduced since the bi-
linear transform maps ω = ±∞ to θ = ±π, see [6] for details. Any filter design
tool or the MATLAB command bilinear takes care of the transform correctly.
For example, when transforming the PI-filter suggested above to the z-domain,
the result becomes
b0 + b1 z −1
F (z) = . (2.37)
1 + a1 z −1
Where the wanted discrete filter coefficients are calculated as

a0 = 1

a1 = −1
µ ¶
T 1
b0 = 1+
2τ1 tan(T /2τ2 )
µ ¶
T 1
b1 = 1−
2τ1 tan(T /2τ2 )
After transforming Eq. 2.37 back to the discrete time domain, the following
difference equation is the result,

a0 uf [n] = b0 ud [n] + b1 ud [n − 1] + a1 uf [n − 1]. (2.38)

The filtered output uf [n] is then used to control the total phase in the SCO. The
expression ’total phase’ will be explained below. The analog PI filter described
above and its digital version can be seen in Fig. 2.11.
Amplitude resp.
100
Analog
Magnitude [dB]

Digital
50

−50
−5 0 5
10 10 10
Frequency [Hz]
Phase resp.
50
Phase [deg]

−50

−100
−5 0 5
10 10 10
Frequency [Hz]

Figure 2.11: Analog PI filter and its digital counterpart created using the bilinear transform.
24 Phase locked loops

Software controlled oscillator and divide-by-N block

The SCO is implemented in a quite specific manner. Instead of directly con-
trolling an oscillator as in the analog case above, it is possible to count the total
phase of the synthesized signal. That can be achieved by initiating a variable
to zero and then add phase to it. Recall from the LPLL theory in section 2.3.2,
the VCO is nothing but an integrator for phase and also recall that discrete
integration is simply a sum. The total phase can therefore, in the discrete case,
be written as
φ2 [n + 1] = φ2 [n] + (ω0 T ) + (K0 uf [n]T ) (2.39)
Equation 2.39 extrapolates the phase at the next sample instance by adding
more phase to the current phase. The phase contribution of the center frequency
term is ω0 T . The last term K0 uf [n]T represents the additional phase needed
to decrease the phase error detected by the phase detector. The time step is
T = 1/F S. The SPLL output will be synthesized by letting u2 [n] = sin(φ2 [n])
and feeding that signal to the digital to analog converter.
Before the extrapolated SCO feedback in discrete time is created, the model
is slightly adjusted to incorporate the divide by-N block at this point. It is
done by letting u2 [n + 1] = sin(Kn φ2 [n + 1]). This will ensure that the output
phase is always N=1/Kn times the input as derived in section 2.3.3.

2.5.2 Hardware specific issues

Up to this point, neither the LPLL design discussion nor the SPLL extension has
taken any of the hardware related problems into account. When implementing
algorithms for a specific hardware, another layer of problems have to be solved.
In the following subsections the most important problems are outlined and if
possible, dealt with.

Fixed point number representations

Only a finite number can be represented on any hardware platform and this
has to be considered at all time. Floating point hardware have many upsides.
Large numbers or small numbers with high precision can be represented. In
addition algorithms tend to be easier to implement in contrary to a fixed point
environment. However floating point hardware tend to be more costly. The
target for this particular implementation is a less expensive fixed point DSP
platform. Therefore the algorithm has to take that into consideration.
In the SCO case, if we add more phase to that highest value, the variable
overflows and the largest negative number will be the result. One solution to
this is to wrap the phase by subtracting 2π from the total phase when it exceeds
2π, because
sin(φ2 n) = sin((k2πφ2 ) n).
Where k is an integer number of revolutions around the unit circle. Another
solution is to take advantage of the overflow effect and use that for wrapping.
By representing the highest positive number by π and the most negative number
2.5 The Software Phase Locked Loop 25

by −π the wrapping is done by the overflow, since

sin(π + a) = sin(−π + a).

See [7], or any basic textbook on digital systems for details on the subject of
number representation and overflow.
Another problem when dealing with fixed point hardware is the limited pre-
cision in fractional numbers, mainly concerning filter coefficients. Rounding
off a high precision filter coefficient from a filter design tool may result in a
malfunctioning filter. This is an important subject and the depth is beyond
the scope of this report. Filter of higher order are more likely to fall into this
category and it is vital to implement the filter in a manner that reduces the
risk with low precision coefficients. The question of suitable filter structures
comes up. The direct form of IIR filters are seldom used directly in implemen-
tations, instead the filter is reordered into a sequence of second order sections.
Such an arrangement is called Cascade form. The loop filter implementation
in this thesis is of second order only and hence the filter cannot be reduced in
complexity.

Computation time
This is simply the question of available computing time versus the time needed
by the algorithm. In a system like a PLL, the entire algorithm has to be
run at each sampling instance. An accurate prediction of the execution time
needed by the algorithm is probably cumbersome to do on beforehand. Instead
implementing the algorithm in a high level language and then measuring the
cycles needed in a suitable simulation/test environment, or on a general purpose
CPU, like a workstation. If it does not meet the timing requirements, suitable
optimizations in low level assembly might be needed or as a last resort, change
the target hardware to a faster one.
A sample-by-sample based algorithm that does not finish in time is easily
detected. Since each sample arrives at a fixed rate, and will be processed by a
prioritized interrupt, the processor will have to stop the algorithm calculations
for the previous sample to serve the interrupt. Serving the interrupt most likely
implies running a new cycle of the algorithm. Therefore the algorithm will never
be run completely on any sample, also the interrupt call stack will be full and
results will be undefined at best, probably the processor will hang. At any case,
the PLL output will speak for itself.
If other tasks is to be run on the hardware at the same time, a user interface
for example, the designer may want to consider using a real-time operating
system that handle resources and help the algorithm with timing issues. The
subject of real-time systems cover this, and an in depth study is beyond the
scope of this text.

Codec delay
The hardware interfacing with the outer world feeds the processor with samples
at a fixed sample rate. This hardware is in this case called a codec and consists
26 Phase locked loops

of one or several Analog to Digital Converters (ADC) and Digital to Analog

Converters (DAC). The ADC employs oversampling and digital anti-alias fil-
tering. This takes time. In data sheets it is mentioned as ’Codec group delay’.
In addition, an SPI (Serial Peripheral interface) bus is used for communication
with the host processor. Therefore the delivery of samples is done with a no-
ticeable delay. The delay is fixed for all frequencies within the operating range
and may extend to hundreds of microseconds. Remember that a fixed group
delay corresponds to a linear phase shift. For example, a group delay of 1 ms
at 19 kHz shifts the phase by 19 cycles or 6840 degrees, clearly not negligible.
In the case of a software PLL that has to be locked in phase at all time this
proved to be a quite troublesome issue.
The solution to the problem actually made the internal SPLL demands to
be relaxed to only be locked in frequency, since locking in phase becomes a false
truth when compared to the external signal. The solution became to connect
a phase adjusting system behind the SPLL, comparing the original signal with
the one generated by the SPLL and then simply adjust a final output to match
the phase of the main input, compensated for any divisions/multiplications of
phase made in the feedback. Practically it was solved by feeding the SPLL
feedback signal to the DAC and then sample it again using the ADC.
The phase adjusting system makes use of the phase accumulator in the
SPLL, as seen in Fig. 2.12. It works by making subtractions or additions when

Sampled domain
SPLL
uin(t) uin[n] uout[n]
ADC Phase Loop
SCO(f2[n])
delay detector filter

ufb[n] Frequency uout(t)

SCO(f2[n]+Sfm) DAC
multiplier delay

DAC Frequency
delay multiplier

fm
ADC Phase Slow MA Parameter
delay detector filter decision

Figure 2.12: An SPLL with secondary oscillator controlled by a phase adjusting subsys-
tem. The dashed line is the adjustments made at specific times decided by the
parameter decision block, and not at system sampling instances.

needed to the total phase defined by Eq. 2.39. With this method of an external
phase adjustment, any phase differences introduced, inside or outside the SPLL
is compensated for. The phase of the final output is therefore an adjusted
2.5 The Software Phase Locked Loop 27

version of Eq. 2.39:

φ3 [n + 1] = φ3 [n] + (ω0 T ) + (K0 uf [n]T ) + φm , (2.40)

But since φ2 , the accumulator for the SPLL, can not be touched, we keep a
separate accumulator φ3 . It will really be φ2 + Σφm since both are set to zero
at start. In plain text, this means that φ3 follow φ2 in frequency but adds a
small correcting phase shift. The adjusted phase is then fed to a sine generator
that generates the final output.
The parameter decision block is implemented as a threshold device, making
the phase corrections be

φm = KL ug [m], ug > |L|

and
φm = 0, ug [m] <= |L|
where ug [m] being the filtered output of the secondary phase detector. L being
a predefined threshold. If the phase difference is driven below the threshold,
the filter before the parameter decision block is made slower to suppress jitter
and increase accuracy. A very slow moving average filter worked well for this
implementation. If the error was still not small enough the same routine was
performed again until the phase error was reduced below a certain desired
minimal phase error. Also, if the phase error increased above the threshold
the slow filter was released. The parametric low pass filter was necessary to
maintain speed while the error was large, and to maintain accuracy when the
error became smaller.

Switched filter technique

Another useful application of the secondary phase detector is that the synthe-
sized signal at 1/N times the input frequency can be made more pure. When
locked in frequency and in phase as detected by the external phase detector,
the loop filter in the SPLL can be made slower(more narrow band) once locked
in order to reduce the jitter introduced by the phase detector. If the SPLL
unlocks, the filter is set to its original state and the SPLL begins its pull-in
process to acquire frequency lock again. The results of this operation can be
seen in Fig. 2.13.
28 Phase locked loops

Spectrum of signal source

−20
−40
−60
−80
−100
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
4
x 10
Spectrum of output whithout additional loop filter
0
−20
−40
−60
−80
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
4
x 10
Spectrum of output with additional filter in place
0
−20
−40
−60
−80

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5

Frequency[Hz] x 10
4

Figure 2.13: Improvement in signal quality due to a slower loop filter switched in when
system is locked in frequency.
Chapter 3

Results

This report has up to this point covered the theory of linear phase locked loops
and an additional discussion on how to implement them in software. A work-
ing SPLL was designed using the methods presented in the previous chapter.
To gain understanding in how the SPLL operates, tests and experiments were
conducted using Matlab mostly. However, as the SPLL design began to look
promising, the developing process where continued on the target hardware sim-
ulation platform.

3.1 Matlab
The Matlab implementation began with allocations of signals and result data
vectors. Main design parameters such as SCO center frequency and filter nat-
ural frequency were set. Before simulation the analog filter design were dis-
cretized using Matlabs bilinear command. Also the filter constants were
rounded off to emulate the 16-bit fixed point environment on the target hard-
ware. The piece of commented MATLAB program code below show how it was
implemented. It shows the sample-by-sample loop where the SPLL is running.
for(n=2:indEnd-1)
% Phase detector, uin - noisy input sinusoid
ud(n)=uin(n)*ufb(n);

% IIR Filter, fac depends on the accuracy used in the filter

% design, filter constants where rounded off to emulate fixed
% point problem pointed out.
%a(1)*y(n) = b(1)*x(n) + b(2)*x(n-1) + ... + b(nb+1)*x(n-nb)
uf(n)=(b0*ud(n)+b1*(ud(n-1))-a1*uf(n-1))/fac;

% Estimate phase
phi2(n+1)=phi2(n)+w0*Ts+uf(n);

% Non wrapped phase for measurements

phi3(n+1)=phi3(n)+w0*Ts+uf(n);
30 Results

% Wrap phase
if(phi2(n+1)>pi)
phi2(n+1)=(phi2(n+1)-2*pi);
end

% SCO
uout(n+1)=sin(phi2(n+1));

% Feedback
ufb(n+1)=Uf*sin(Kn*phi2(n+1));
end

The signals in the program code can be seen in Fig. 3.1. The center frequency of
the SCO was set to 4 kHz in the example and the input kept a stable frequency
during the first second. After one second the input were stepped up to 4.1 kHz
and the SPLL where allowed to settle. A DC offset can be seen in the signal
uf [n] due to the offset from the center frequency of the SCO.

3.2 Real-time hardware implementation

3.2.1 Hardware specification
When the matlab model proved to be accurate and working, the SPLL was
implemented on a real-time hardware platform, the Analog Devices ADSP-
BF533 EZ-KIT LITE REV 1.5, based upon the Blackfin 533 DSP.
The EZ-KIT LITE has a high quality audio codec built in, the AD1836 is
also made by Analog Devices. It supports four ADCs and 6 DACs at a maxi-
mum sampling frequency of 96 kHz with a resolution of 24-bits. It utilizes high
oversampling and low pass filtering to avoid aliasing. However the same filtering
operation is specified to take up to 1 ms according to the data sheet. At this
point the codec delays, mentioned earlier were discovered. The delay made it
impossible for the SPLL to gain phase lock between the two analog signals(main
input to codec, and output at divided frequency) without an additional phase
correcting system.

3.2.2 Developing environment

The language used for programming the DSP was C exclusively. An excessive
part of the SPLL performance where evaluated on the target hardware using the
debugging tools in VisualDSP++ IDE(Integrated Developing Environment).
In addition, the PC communicated with the DSP via a piece of external
hardware called an In-Circuit Emulator or ICE. ICE hardware is used to debug
the software of an embedded system. The ICE hardware communicated in
turn with the DSP via the JTAG interface. When using the ICE hardware,
debugging went more smooth, stepping code was easy, and data transfer rates
were improved.
3.2 Real-time hardware implementation 31

uin[n] − Noisy input(4Khz)

1

−1
0 5 10 15 20 25 30 35 40
phi2[n] − Wrapped phase
pi

−pi
0 5 10 15 20 25 30 35 40
ufb[n] − Feedback to phase detector
0.5

−0.5
0 5 10 15 20 25 30 35 40
uout[n] − Output at divided frequency
1

−1
0 5 10 15 20 25 30 35 40
u [n] − Phase detector output
d
0.5

−0.5
0 5 10 15 20 25 30 35 40
uf[n] − Filtered phase detector output
0.01

0.005

0
0 5 10 15 20 25 30 35 40

Figure 3.1: The signals of importance in a discrete linear PLL. It is locked to a noisy input
of 4.1 kHz.
32 Results

3.2.3 Measurements
This final section is dedicated to a discussion around a couple of figures that
shows a working SPLL on the DSP hardware described above. The SPLL is set
up to have a center SCO frequency of 10 kHz. The loop filter is a PI-filter with
natural frequency of 20 Hz. A Matlab script was made to test the SPLL with
a sequence of test signals. In the following example, it was set to generate a
sinusoidal signal at 10 kHz which was played back using a PC Audio Card. At
a certain time the frequency was abruptly stepped to 9 kHz. The signal going
into the SPLL was recorded as well as the divided SPLL output. The results of
the experiment can be seen in Fig. 3.2. This is what happened with the SPLL
during the process:

before t = 1.90 The output is phase-locked at half the input frequency. The
input is a low noise sinusoid at 10 kHz. The secondary jitter-reducing
filter is applied as a result of an earlier phase-lock process, therefore the
output is quite pure.

t=1.910 The input makes a frequency step down to 9 kHz. The SPLL senses
the frequency step, the error signal is built up. At this time the jitter-
reducing filter is removed and several disturbing overtone can be seen in
the spectrogram. A pull-in process starts right away.

t=1.920 The pull-in process is visible on the spectrogram as the SCO is in-
creasing and decreasing its frequency, however as described in the theory,
its tendency is in the right direction.

t=1.927 The pull-in process is done and the SPLL is locked in frequency.

t=1.927 - 2.02 As the SPLL is locked in frequency the secondary phase-

locking system becomes active. The vertical ”bars” seen in the spectro-
gram are the results of momentary additions of phase to the SPLL control
signal, as described in section 2.5.2. After each addition the SPLL is al-
lowed to settle for a small amount of time.

t=2.025 The phase-locking subsystem senses that the phase error is smaller
than a certain threshold and stops the correction process. At this point
the secondary jitter-reducing filter is applied in the SPLL.

t=2.03 The SPLL is locked in phase to the input.

A comment on when to apply the jitter-reducing filter can be in order. If the

input is quite noisy the phase detector will at some samples detect a high phase
error. Therefore a suggested solution may be to trigger on the variance of the
error rather than the error directly.
The final figures, Fig. 3.3 and Fig. 3.4 shows the oscilloscope dumps of
another SPLL configuration set to a center frequency of 19 kHz, though the
same loop filter was used, a PI-filter with a natural frequency again set to ωn =
20Hz. It is included to end the report by showing that the SPLL design methods
presented can be used to solve the initial problem stated in the introduction.
3.2 Real-time hardware implementation 33

Figure 3.2: Spectrogram of input and output to the SPLL implemented on a DSP.
34 Results

Figure 3.3: Oscilloscope dump of the SPLL input at 19 kHz and the in phase locked half
frequency output.

Figure 3.4: Oscilloscope dump of the FFT of the SPLL output. 10dBV per square.
Chapter 4

Conclusion

The theory of linear PLL were studied and the most relevant parts were outlined
in this report, as well as design methods for implementing one in software for
a real-time application. A working implementation were tested in both Matlab
and in real-time. The report deals with subjects such as control theory, analog
and digital filter design, C programming and writing of a technical report. The
solution to the codec delay problem were custom made, but proved to work well
for the particular application.
The thesis was very rewarding from both a theoretical and a practical point
of view. Knowledge from a broad range of courses studied during my engineering
education was used throughout the work. Nothing was obvious to start with,
and i find the solution to be creative rather than close to optimal.
As a valuable bonus to the thesis work; i was hired by the firm Rubico and
has by the time of writing worked there for over a year.
Appendix A

Program code

The complete source code used in the thesis is not included since it is owned
by the company that offered this thesis. However, questions regarding the
implementation in general is best answered by sending the author an e-mail.
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[5] Sven Spanne. LINEARA SYSTEM. KFS AB, 3rd edition, 1995.

[6] Boaz Porat. A course in digital signal processing. Wiley, 1997.

[7] Iain Paterson-Stephens Andrew Bateman. The DSP Handbook. Prentice

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