Resume Builder: Silicon Validation Engineer Resume Samples
Resume Builder: Silicon Validation Engineer Resume Samples
Resume Builder: Silicon Validation Engineer Resume Samples
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Guide the recruiter to the conclusion that you are the best candidate for the silicon validation
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builder&utm_content=sidebar&utm_medium=resume-
samples&utm_source=internal&utm_term=silicon-validation-engineer)
Hailey Ruecker
17251 Maggio Canyon , Houston , TX ♦ Phone: +1 (555) 382 1219
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6/17/2019 EXPERIENCE DDR & SOC POST SILICON VALIDATION
Silicon Validation ENGINEER
Engineer Resume Samples | Velvet Jobs
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New York, NY
09/2016 – present
Minutescompliance
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Validation of DDR4, DDR3, RLDRAM3, LPDDR4 and other memory protocols
Create a Resume in JEDEC testing of memory protocols
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firmware and validation test cases in C++ for SOC and memory interfaces
Bench automation, PVT and volume characterization to improve product quality Analyze test results and
identify potential issues, debug and root cause any silicon issues to improve quality and performance of circuits,
hard and soft IPs
Generate test plans and characterization reports for both internal and external customers to clearly illustrate
performance for key protocols/features/circuits
Publish Specs for EMIF and SOC IPs coordinating with cross-functional teams spanning IC Design, SW & IP,
Applications and Marketing for NPI
BSEE or related
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READ OUR COMPLETE RESUME WRITING GUIDES
samples&utm_source=internal&utm_term=silicon-validation-engineer)
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6/17/2019 Silicon Validation Engineer Resume Samples | Velvet Jobs
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6/17/2019 Silicon Validation Engineer Resume Samples | Velvet Jobs
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3+ years of experience with Hardware and Software Debugging Skills 3+years of experience
with Second and Third generation Low Power Double Data Rate (LPDDR2/3) SDRAM Controller
and Physical Layer Technologies
3+ years of experience with Programming in C/C++, Linux Shell Scripting, and Linux Kernel
Programming
Good understanding of the Hardware Principle and Hardware Validation Capabilities; for
example, understand the Peripheral Programming from IC Datasheet and define Validation of
Aforementioned Features
Experience with Network on a Chip (NOC) and System on a Chip (SOC) Concepts and Drivers
Experience with Image, Video, and Graphics Processing and Display Content Control Concepts
Experience with Mobile Industry Processor Interface (MIPI) Physical Layer Technology
Experience with Processor Emulation Tools (preferably Lauterbach) and Scripting, specifically in
the context of Trace and Debug
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6/17/2019
Experience with Secure DigitalSilicon
MMC, embedded
Validation EngineerMMC,
Resumeand Secure
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Experience with Perl, Python, and LabVIEW
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5+ years (with B.Sc.) or 3+ years (with M.Sc.) experience with ASIC Validation
3+ years of experience with Second and Third Generation Low Power Double Data Rate
(LPDDR2/3) SDRAM Controller and Physical Layer Technologies
3+ years of experience with Hardware Principle and Hardware Validation capabilities; for
example, understanding Peripheral Programming from IC Datasheet and Define Validation of
Aforementioned Features
Experience with SOC Functional Power Measurements (Leakage, Standby, Dynamic, etc.)
Experience with Secure Digital MMC, Embedded MMC, and Secure Digital I/O
(SDMMC/eMMC/SDIO) Technologies
Must be team player, able to work independently, quick learner, problem solver
3+ years of experience with Linux Shell Scripting, Linux Kernel Programming; and with Boot-
Code (preferably U-Boot)
3+ years of experience with Hardware Principle and Hardware Validation; for example,
understand the Peripheral Programming from IC Datasheet and define Validation of
Aforementioned Features
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6/17/2019 Silicon Validation Engineer Resume Samples | Velvet Jobs
Post-silicon Validation Engineer
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5+ years (with B.Sc.) or 3 years (with M.Sc.) experience with ASIC Validation
3+ years of the Hardware Principle and Hardware Validation Capabilities; for example,
understand the Peripheral Programming from IC datasheet and define validation of
aforementioned features
Definition and implementation of chip and system verification environment for ICs containing
all peripherals (i.e. SPI, MIPI, SIM Card controller, I2C, NAND flash controller, LPDDR1/2/3
controller...) and interfaces to other ICs
Development of a Hardware Abstraction Layer, Low Level Drivers and Libraries for ICs
Work with SoC development team and platform team for trouble shooting of hardware and
software issues
Execution and Automation of TestCases to increase Test Coverage under different external
conditions
Lab skills (operation of lab equipment, interested and able to work in the lab)
Writing firmware and validation test cases in C++ for SOC and memory interfaces
Bench automation, PVT and volume characterization to improve product quality Analyze test
results and identify potential issues, debug and root cause any silicon issues to improve quality
and performance of circuits, hard and soft IPs
Defining DFT/DFX features for next generation products to enable debug access to complex
circuits to enable characterization
Generate test plans and characterization reports for both internal and external customers to
clearly illustrate performance for key protocols/features/circuits
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6/17/2019
Publish Specs for EMIF and SOC IPsValidation
Silicon coordinating
Engineer with cross-functional
Resume teams spanning IC
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Design, SWBuilder
& IP, Applications and Marketing for NPI
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BSEE or related
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3 years of experience in a post silicon validation role (in SOC, memory interfaces, or related)
Experience with memory interface protocols such as DDR3/4, LPDDR3/4, RLDRAM2/3, QDR
MSEE or related
Experience in RTL design for FPGAs, scripting languages and bench automation
Work with Technology Enablement, DM, PI and Yield engineering teams to understand and
validate technology design rules and prevalent process/design driven fail modes
Define and design experimental electrical DOE test structures to assess design and process
weak points in order to ensure design rule/PDK and process flow robustness
Perform detailed Si validation analysis for the process bring-up at the manufacturing facility.
Analyze test structure data to investigate systematic design driven yield and performance
detractors, followed by root cause analysis and understanding
Compile Si validation reports and communicate Si analysis results to the multiple design and
process development engineering teams
Drive Si validation of critical process and design fail modes to ensure product manufacturability
and customer satisfaction
MS or PhD in Electrical Engineering, Materials Science, Solid State Physics, or other relevant
engineering discipline
1 year Semiconductor industry experience in device, process integration or unit process areas
preferred
Strong layout and design tool experience and good understanding of process and design
layout interactions
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6/17/2019
Understanding of semiconductor fabrication
Silicon process,
Validation Engineer semiconductor
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Jobs and DOE
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Familiarity with design, physical layout tools, experience with Cadence Virtuoso layout
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generation
Strong data analysis, data mining and problem solving skills. Experience with statistical data
analysis packages like JMP
Strong interpersonal skills; team player; able to work effectively in a dynamic, fast paced
environment
Experience with the analog circuit characterization and digital design validation of integrated
circuits
Hands-on Experience working in a lab environment, making power measurements and probing
high speed interfaces
Experience in one or more scripting languages such as python, lua etc. or C/C++/Java,
LabView/LabWindow
3+ months experience with typical lab equipment: Oscilloscopes, Logic analyzers, protocol
analyzers, power supplies, etc
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You will be Builder
working on complex processor SOCs
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Minutes with and maintaining a Xilinx instruction based random test system to
debugging
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ensure high quality of processor SOCs
Able to effectively work across multiple functional teams, different geographies, and
organizations
Knowledge and expertise in CPU mechanism such as caches, TLBs, DMA, out-of-order
execution, virtual memory etc
Component and System verification of ICs baseband, integrated baseband and application
processor with full responsibility for functional quality of SoC
Definition and implementation of chip and system verification environment for ICs containing
all peripherals i.e. SPI, MIPI, SIM Card controller, I2C, NAND flash controller, LPDDR1/2/3
controller... and interfaces to other ICs
Execution and Automation of Test Cases to increase Test Coverage under different external
conditions
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System data analysis and correlation to production testing
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architecture
Post-silicon test for MCU/MPU chips, and the modules/blocks in the chips
Ruby or similar runtime scripting languages familiarity with Hardware verification languages
HVL like SystemVerilog testbench and SystemC Hardware description languages HDL, Verilog
and SystemVerilogInternship experience on post silicon validation, system integration, hands-
on debugging in lab both silicon and on emulation platforms, performance and power analysis
across relevant use cases
Familiarity in SOC troubleshooting, include hands-on experience with schematics, layout and
post silicon debug and real time debugging tools like logic analyzer,
Minimum of 8 years of experience with Verilog / System Verilog design and validation
Minimum of 8 years of experience with High level programming language such as C++, perl,
tcl, python
Minimum of 8 years of experience in Logic and or Mixed signal design and verification
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6/17/2019
Minimum of 8 years of experience
Siliconin Semiconductor
Validation Device
Engineer Resume Physics
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8 years of experience with CMOS circuit / analog circuit design and validation
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of 8 years of experience with NAND 2D or 3D Flash or NOR Flash or Non-Volatile
Memory Experience in Test Mode validation, 1st silicon bring up working with product
engineers PE is a must
Detailed understanding of NAND 2D or 3D Flash or NOR Flash user mode read and write
algorithms and ucode
➢Strong principles, design, and testing with DC-DC, AC-DC and DC-AC converters
➢Experience with bench equipment such as power supply, oscilloscope, signal generator,
electronic load, spectrum analyzer, etc
➢Use LabVIEW, Python, device drivers, GPIB, USB, I2C, SPI, and UART interfaces, etc. is
strongly preferred
➢Working knowledge with finite state machine (FSM), digital design and verification is a plus
➢Ability to work with development team directly to establish project requirements and
develop test plan
➢Must be highly motivated, self-starter with innovation, integrity and attention to details
Understanding test execution through both functional mode and DFX hooks
Strong scripting skills in one of the major languages: eg. Perl, python, Tcl, bash
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Nice-to-haves (in at least one and preferably several)
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Chip design Templates in circuit/physical design (timing closure, power, etc.) or DV
background
(correlating SW signatures to block level tests)
Post silicon physical debug background in speed-path/Vmin, memory arrays, clocking or yield
improvements
Post silicon logic debug background in exercising various DFX features, analyzing
scandump/memdump, suggesting tests in both system level or to DV
Good understanding of boot process, boot-loaders, embedded software, micro-kernel and able
to tweak system tests
Product engineering background and familiarity with ATE coverage, margin, binning, scan
pattern generation, etc
Good IP knowledge in some PHY blocks (eg. DDR, PCIe, USB, etc)
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