Flip-Flops and Timers 1
Flip-Flops and Timers 1
Flip-Flops and Timers 1
B. not change
C. change
D. toggle
Answer: Option B
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3. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to
which configuration feature?
A. asynchronous operation
C. gate impedance
D. cross coupling
Answer: Option D
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B. monostable, bistable
C. astable, toggled
D. bistable, tristable
Answer: Option A
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5. A basic S-R flip-flop can be constructed by cross-coupling which basic logic gates?
A. AND or OR gates
B. astable oscillator
C. racer
D. switch debouncer
Answer: Option D
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7. If both inputs of an S-R NAND latch are LOW, what will happen to the output?
A. The output would become unpredictable.
is: .
What value of C1 will be required if R1 = 1 k , R2 = 1 k , and f = 1 kHz?
A. 0.33 F
B. 0.48 F
C. 480 F
D. 33 nF
Answer: Option B
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B. is free-running
B. bistable
C. astable
D. tristable
Answer: Option A
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11. The truth table for an S-R flip-flop has how many VALID entries?
A. 3
B. 1
C. 4
D. 2
Answer: Option A
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12. What is the significance of the J and K terminals on the J-K flip-flop?
A. There is no known significance in their designations.
The J represents "jump," which is how the Q output reacts whenever the clock goes HIGH
B.
and the J input is also HIGH.
C. The letters represent the initials of Johnson and King, the co-inventors of the J-K flip-flop.
13. Which of the following describes the operation of a positive edge-triggered D-type flip-flop?
A. If both inputs are HIGH, the output will toggle.
B. The output will follow the input on the leading edge of the clock.
The input is toggled into the flip-flop on the leading edge of the clock and is passed to the
D.
output on the trailing edge of the clock.
Answer: Option B
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