Software Radio

Architecture and Technology

Joseph Mitola III

DARPA/ DoD/ Mitre
[email protected]
Then ... Originator
Radio
RF
Communications
Radio
Recipient
Transmitter Receiver
Channel

Source Channel Channel Source

Coder Coder Decoder Decoder

Now ...
External Environment
Source Channel
Evolution
Set Set
Support

Source Service
IF RF/
Coding & INFO-
Modem Process- Channel
& Network SEC ing Access
Decoding Support
Channel Coding & Decoding
Radio Node Joint Control
Multiple Personalities

©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission

2
 Software Radio “Phase Space”
Digital Access Bandwidth

10 GHz
Digital RF
1 GHz
X RF
Software
Radios
100 MHz
V
10 MHz
C Digital IF IF
D

gy
olo
1 MHz

chn
Digital

Te
100 kHz Radios
B
Baseband
10 kHz Digital Baseband
A

1 kHz
ASIC FPGA DSP General A - HF STR-2000
Purpose B - COTS Handset
C - SWR Cell Site
CISC RISC D - SPEAKeasy II
Function Function Function Function V - MIT Virtual Radio
per cm2 per cm2 per cm2 per cm2 [177, 178]
X - Ideal Software Radio
Dedicated Malleable ISA + Memory
Silicon Silicon Memory

©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission

3
 Joint Tactical Radio Architecture?

Up/Down Converter
Receiver/Exciter
Power Amp

VME/VXI
KG-84A/C

SEM-E
Fastlane
Modem

Vocoder
Pentium
KGV-11

Black
Other
PCI

68xx

Red
Industry
Radio Crypto Data Buses Processors Power
Supplies
Hardware
Which Industrial7 “Partner” Will Get There First?

Labs
+ How Can DoD Keep Open Architecture without
Software Becoming Integrator?
HF ALE
8.33 kHZ Vocoder
TDDS/TIBS Fastlane ATM
HAVE QUICK KG-96 Windows NT
UHF - DAMA KY-58 Internet Router
SINCGARS KG-84 A/C SNMP

Waveforms Algorithms Protocols, Formats, Routers

• JTRS Consistent with PMCS IPT Guidance Document

• Implements Open Systems Architecture for all DoD Radios
• Eliminates Stovepipe Radio Buys and Enhances Interoperability
• (Future Value-Added Software-Only Capabilities?) © DoD
4
 Third Generation Drivers

• Wireline Quality
• Mode Control, Error Control, Equalization
• Mobile Information
• Highways, Shopping, Entertainment, Internet
• Tailored Node Capabilities
• Downloads (Vocoder, Power Control…)
• Software-based Deployment

5
Hardware Software Mix

HARDWARE

SO FTW ARE
90 95 00 05

Gansler, J, Defense Management Journal, 1976

6
 Typical System Data Flow Diagram

Ant & RF Channel INFOSEC System User

Control Control Control Control Interface
(ARC) (CC) (IC) (SC) (UI)

Data Bases

Waveform INFOSEC Speech

Processing (WP) Processing (IP) Processing (SP)

Ant ADC
& & FPGA
DSP
------ DCS µc Protocol
RF µc Processing (PP)
µc ... ARC - TX/RX, Power, Polarization...
CC - Allocate Resources, Configure, State Machines
DAC WP - Generation, Timing, Fault Detection, Mod/Demod
IC - Key, Control Bridge to Black Side, Authenticate
µc IP - Encrypt, Decrypt, Transec;
SC - Initialize/ Shutdown, Test, System Status
UI - Commands & Displays
©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission
SP - Codecs; Echo Cancelation, Voice Channel Modems...
PP - Packetization, Routing ...

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 Software Radio Infrastructure
Control Flow Paths Initialize, Check-In, Shutdown,
Create Port, Find_Port, Delete_Port
Object Message Passing Get_Message, Send_Msg, Send_RPC(timeout)
Error Logging, Semaphores, Bus Logic Multicast_Register/Send/Release/Echo
Error(string), Extract_UDP_Socket/_IP/_Port

Load_Path, Load_Command_List
Path_Get_Status/_Type/_Size/_Cmd
Signal Flow Paths Path_Echo,
Path_Open, Path_Close,
Path_TxInit/_TxReset/_TxSetID/_TxLoad/_GetPTR
Path_RxInit/_RxReset/_RxSetID/_RxSetMask/
/_RxContinuous/_RxSnapshot/_GetPTR/_Status
Isochronous Streams Path_Catch, Path_Throw (UNIX/VxWorks)
Device Specific (PCI, VME, DT, Transputer...)

Get_Time, Get_Drift (Inernal vs. GPS)

Clock_Status, Clock_Terminate (Port)
Timing, Frequency & Positioning Clock_Realign(Parameters)
Send_Sync_Manager
Init, Reset(error), Status, Trigger(parameters),
Automatic Realignment TimeUp, TimeDn, TimeEqual, TimeLess, TimeGT
Shutdown, GetRate, FreeList(FIFO), Load, Queue
©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission
Clear, Test, TestStatus
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 Distributed State Machines
Paths and Tests Complete
Close/Deactivate
Idle Suspend
<Mode>Rx
User/
Wait for Instantiation
Fetch
<Mode>Ready Tx/Rx
No Resources/
Fetching Waveform “Unavailable” Setup
<Mode> <Mode>Tx
Finish/
Allocate Wait for Response
OK/ Confirm
Retry RC: Mode
Setup Error
Define Channel RC: Allocate Bypass Hard Faults

Rcv(Freq); Activate
Active Plaintext Rx Operation >Signal, Carrier Idle Squelch
Ready Tx
Lost
Receiving Fade
Active Plaintext Tx Operation Set Up > 12 s
Analog AGC, Sq Bridge

Repeat Per Mode Start CVSD

Idle
Tx
Modem AGC, Sq Crypto-
Instantiated Teardown Receiving AGC, Sq
Sync
Digital

• Control, Behavior, Integration

Tx
• Z.100 Specification and Description Language (SDL)

©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission

9
 Global User
Control Interface
Communications Services Services (Over The Air Downloads) (SC) (UI)

Service Scripts
Applets/ Script Personalities
HAVE
SINCGARS QUICK
Bridging
(S G ) (HQ)
Channel Objects

Radio Applications Agents Ant & RF Channel INFOSEC System User

Control Control Control Control Interface
(ARC) (CC) (IC) (SC) (UI)
Data Bases
Idle
Close/Deactivate
Suspend
<Mode>Rx Channel Waveform INFOSEC Speech
Processing (WP) Processing (IP) Processing (SP)

Setup
<Mode>Ready Tx/Rx
State Machines
<Mode> <Mode>Tx
Protocol
Processing (PP)
Confirm Retry RC: Mode
Setup Error
Bypass Hard Faults
Information Flows
Control Flow Paths

Paths and Tests Complete O bject Message Passing

E r r o r L o g g in g , S e m a p h o re s , B u s L o g i c

Radio Infrastructure Infrastructure State Machines U ser/

Fetch
Wait for Instantiation

No Resources/ S ig n a l F l o w P a t h s
Fetching Waveform “Unavailable”

Finish/
Isochronous Streams
Allocate Wait for Response
Thread Setup and Control OK/
Define Channel RC: Allocate
Timing, Frequency & Positioning

A u tom a t i c R e a l i g n m e n t

Hardware Platform Instruction Set Architecture FPGAs GP Hosts

ASICs DSPs
Operating System

Distributed Layered Virtual Machine

©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission
10
 Resource Parameters
Personality
Mmpy> 100*fs Mmpy> 40*2.5*Wc IPS> 100*Rb

IF Processing Baseband Bitstream Audio

RF Object Object Object ADAC
ADAC
Control
ASIC User
fc, Wa Object
Dynamic Range, fs >2.5 Wc,
Spectral Shape... N>log(SFDR)+2 MFLOPS > {[100*(fs+Wc+Rb)]*4}/106
MEOPS>MFLOPS*2*Efficiency

fs, N DSP - RAM ASIC Rb Host(s)

RF Audio
ADAC MOPS Provided ADAC User
ASIC 50 MIPS, 20 MFLOPS, ASIC
fc, Wa ...
fs, N 50 MEmoryOPS, 100 BusOPS...
Rb

Resource Models Inform Top-Level Tradeoffs

Identifying Simulation, Prototyping, Design and Download Issues
©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission
11
 T1 Multiplexer Benchmark

©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission

12
 Performance Management Process
Performance Management
System Task Subthread Complexity Rate Load
A 1 200 3 600
2 100 5 500
... ...

1 Spreadsheet P(t<t’)

2
3
LAN
4
10
t’/t”
RAM BUS Disk
5.5 Analysis of
DSP CPU Variance
1
0 0.5 0.99
ρk
Critical Resource Model Queueing Model
©1995-98 Mitola’s STATISfaction all rights reserved, Used by Permission
13
 Conclusion
• Leverage the
Commercial Sector
• Partitioning, Layering,
Software Reuse
• Dynamic Resource
Management
• Manage The (R)
Evolution to Software

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