SPICE Examples: Dr. Lynn Fuller

SPICE Examples
ROCHESTER INSTITUTE OF TECHNOLOGY

MICROELECTRONIC ENGINEERING
SPICE Examples
Dr. Lynn Fuller
Electrical and Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY 14623-5604
Tel (585) 475-2035
Fax (585) 475-5041
Dr. Fuller’s Webpage: http://people.rit.edu/lffeee
Email: [email protected]
Dept Webpage: http://www.microe.rit.edu
Rochester Institute of Technology 1-2-2014 SPICE_Examples.ppt

Microelectronic Engineering
© January 2, 2014 Dr. Lynn Fuller Page 1

SPICE Examples
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SPICE Examples
OUTLINE
Introduction
Text Input Files
DC, Transient, AC Analysis
LC Filter
Inverters, NMOS, PMOS, CMOS
Rise Time, Fall Time, Gate Delay
Ring Oscillator
Combinatorial Logic, NOR, 4 to 1 MUX
Inverter with Hysteresis
Oscillators
2 Phase Non Overlapping Clocks
Analog Switch
Op Amps, CMOS, BJT
Waveform Generator
Operational Transconductance Amplifier (OTA)
AM Receiver
References
Homework

SPICE Examples
INTRODUCTION
SPICE (Simulation Program for Integrated Circuit Engineering) is a
general-purpose circuit simulation program for non-linear DC, non-
linear transient, and linear AC analysis. Circuits may contain
resistors, capacitors, inductors, mutual inductors, independent voltage
and current sources, four types of dependent sources, transmission
lines, switches, and several semiconductor devices: including diodes,
BJTs, JFETs, MESFETs, and MOSFETs. Circuits with large numbers
of all types of components can be simulated.
SPICE input files and output files are simple text files (e.g. name.txt)
Input files include a TITLE, circuit description NET LIST, analysis

directives (COMMANDS), and lists of other text files to include
(INC) such as model libraries (LIB) and an END command.

SPICE Examples
INTRODUCTION
PSpice Lite 9.2 is one of the OrCAD family of products, from

Cadence Design Systems, Inc., offering a complete suite of electronic
design tools. It is free and includes limited versions of OrCAD
Capture, for schematic capture, PSpice for analog circuit simulation
and Pspice A/D for mixed analog and digital circuit simulation.
PSpice Lite 9.2 is limited to 64 nodes, 10 transistors, two operational
amplifiers and 65 primitive digital devices. See page 35 (xxxv) of the
PSpice Users Guide.
LT SPICE – is a free SPICE simulator with schematic capture from

Linear Technology. It is quite similar to PSpice Lite but is not limited
in the number of devices or nodes. Linear Technology (LT) is one of
the industry leaders in analog and digital integrated circuits. Linear
Technology provides a complete set of SPICE models for LT
components. Rochester Institute of Technology

SPICE Examples
CREATING THE INPUT FILE
The input file can be generated from a schematic capture program,

or just typed in a text editor such as “Notepad” or “WordPad”
R2
3K 1
*Simple Resistor Divider 2
R1 1 0 2K
R2 2 1 3K
V1 2 0 DC 5 5V + R1
.DC V1 0 5 .1 V1 - 2K
.END
0

SPICE Examples
LTSPICE USING INPUT FILE INSTEAD OF SCHEMATIC
.op is a spice directive to do DC operating point analysis
Resulting Plot
This is a text file located at
C:\SPICE\SimpleExample.txt
SPICE Examples
RC DIVIDER CIRCUIT
R1
20K
Calculate VC as the voltage V1
+ is swept from 0 to 3 volts
3V
+ R2
VC
V1 10K Change the V1 to a 3 volt pulse
- 1 uF
function and plot VC versus
- time.
0
Change the voltage V1 to an
AC voltage source and plot VC
versus frequency

SPICE Examples
DC SPICE ANALYSIS USING LTSPICE
N002
N001
This net list is automatically
Rochester Institute of Technology generated from the schematic

SPICE Examples
TRANSIENT ANALYSIS USING LTSPICE
Right click on voltage source

to get this dialog box

SPICE Examples
AC ANALYSIS USING LTSPICE
Magnitude
Phase
Right click on voltage source

to get this dialog box

SPICE Examples
LC FILTER
Magnitude
Phase
1
f0 =
2 LC


SPICE Examples
NMOS INVERTER WITH RESISTER LOAD


SPICE Examples
NMOS INVERTER RESISTIVE LOADS


SPICE Examples
NMOS INVERTER WITH NMOS LOAD


SPICE Examples
PMOS INVERTER WITH PMOS LOAD

INVERTER USING RIT PMOSFET, Dr. Lynn Fuller, 2-11-2007 Wd/Ld 0.5
*LINE ABOVE IS TITLE
1 Gain =
* Wu/Lu
*START WIN SPICE AND ENTER LOCATION AND NAME OF INPUT FILE
*THIS FILE IS PMOS_INVERTER.TXT
*EXAMPLE: winspice> source c:/spice/PMOS_INVERTER.txt M2
*
*THE TRANSISTOR MODELS ARE IN THE FILE NAMED BELOW Wu/Lu
.INCLUDE E:\SPICE\WINSPICE\RIT_MICROE_MODELS.TXT
* 7
*CIRCUIT DESCRIPTION V1=-10
*
+ 2 M1
*VOLTAGE SOURCES
V1 1 0 DC -10 - Wd/Ld
V2 2 0 DC 0 V2=0 +
* to -10 -
*TRANSISTORS
M1 7 2 0 0 RITPMOS49 L=20U W=60U Gain=1 0
M2 1 1 7 0 RITPMOS49 L=60U W=20U
*
*REQUESTED ANALYSIS
.OP
.DC V2 0 -10 -0.1
.PLOT DC V(7)
Gain=2 Gain=3
* Rochester Institute of Technology
.END Microelectronic Engineering

SPICE Examples
CMOS INVERTER VOUT VS VIN (VTC)
VOUT
+V
VIN VOUT Imax
Voh
+V
Idd
Slope = Gain
PMOS
VIN VO
NMOS Idd
VoL VIN
CMOS 0
0 +V
ViL Vih
Vinv
0 noise margin=ViL-VoL
1 noise
Rochestermargin=VoH-ViH
Institute of Technology

SPICE Examples
MEASURED CMOS INVERTER VOUT & I VS VIN


SPICE Examples
DC SIMULATION OF INVERTER VOUT & I VS VIN
What happens to the voltage transfer curve (VTC) and noise margins when one of
the threshold voltages is changed by 0.3 volts? What happens when width of
transistors is changed.


SPICE Examples
SIMPLE AND ADVANCED SPICE MODEL
* From Electronics II EEEE482 FOR ~100nm Technology

.model EECMOSN NMOS (LEVEL=8
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
* From Electronics II EEEE482 FOR ~100nm Technology
.model EECMOSP PMOS (LEVEL=8
+TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8
*
* From Electronics II EEEE482 SIMPLE MODEL
.model EENMOS NMOS (VTO=0.4 KP=432E-6 GAMMA=0.2 PHI=.88)
*
* From Electronics II EEEE482 SIMPLE MODEL
.model EEPMOS PMOS (VTO=-0.4 KP=122E-6 GAMMA=0.2 PHI=.88)

SPICE Examples
CMOS INVERTER WITH LEVEL 1 SPICE MODEL


SPICE Examples
CMOS INVERTER WITH LEVEL 8 SPICE MODEL


SPICE Examples
SPICE LEVEL-1 MOSFET MODEL

G
CGSO CGDO
S D
COX
p+ p+
RS ID RD
CBD
CBS
CGBO
B
where ID is a dependent current source
Microelectronic Engineering using simple long channel equations.
SPICE Examples
AC MODEL FOR MOSFETS

The SPICE model parameters that effect the AC response of a MOSFET are
the resistance and capacitance parameters shown here:
RS,RS Source/Drain Series Resistance, ohms
RSH Sheet Resistance of Drain/Source, ohms
CGSO,CGDO Zero Bias Gate-Source/Drain Capacitance, F/m of width
CGBO Zero Bias Gate-Substrate Capacitance, F/m of length
CJ DS Bottom Junction Capacitance, F/m2
CJSW DS Side Wall Junction Capacitance, F/m of perimeter
MJ Junction Grading Coefficient, 0.5
MJSW Side Wall Grading Coefficient, 0.5
These are combined with the transistors properties to obtain the internal
resistance and capacitance values for each transistor.
L, W Length and Width
AS,AD Area of the Source/Drain
PS,PD Perimeter of the Source/Drain
NRS,NRD Number of squares Contact to Channel

SPICE Examples
INVERTER LAYOUT
INV/NOR4
W = 40 µm
Ldrawn = 2.5µm
Lpoly = 1.5µm
Leff = 1.0 µm\
Pd=680p
Ad=114u
SPICE Examples
FIND DIMENSIONS OF THE TRANSISTORS

Inverter
NMOS PMOS
L 1.5u 1.5u
W 40u 40u
AD 17ux40u=680p 17ux40u=680p
AS 17ux40u=680p 17ux40u=680p
PD 2x(17u+40u)=114u 2x(17u+40u)=114u
PS 2x(17u+40u)=114u 2x(17u+40u)=114u
Right mouse click on each transistor and add these

values to the properties.

SPICE Examples
RISE TIME AND FALL TIME LTSPICE SIMULATION


SPICE Examples
SIMULATION OF GATE DELAY IN SINGLE INVERTER


SPICE Examples
RING OSCILLATOR, td, THEORY
Seven stage ring oscillator

with two output buffers
td = T / 2 N
td = gate delay
N = number of stages Vout
T = period of oscillation Buffer
Vout
T = period of oscillation

SPICE Examples
MEASURED RING OSCILLATOR OUTPUT
73 Stage Ring at 5V
td = 104.8ns / 2(73) = 0.718 ns


SPICE Examples
SPICE LEVEL-1 MOSFET MODEL

G
CGSO CGDO
S D
COX
p+ p+
RS ID RD
CBD
CBS
CGBO
B
where ID is a dependent current source
Microelectronic Engineering using simple long channel equations.
SPICE Examples
AC MODEL FOR MOSFETS

The SPICE model parameters that effect the AC response of a MOSFET are
the resistance and capacitance parameters shown here:
RS,RS Source/Drain Series Resistance, ohms
RSH Sheet Resistance of Drain/Source, ohms
CGSO,CGDO Zero Bias Gate-Source/Drain Capacitance, F/m of width
CGBO Zero Bias Gate-Substrate Capacitance, F/m of length
CJ DS Bottom Junction Capacitance, F/m2
CJSW DS Side Wall Junction Capacitance, F/m of perimeter
MJ Junction Grading Coefficient, 0.5
MJSW Side Wall Grading Coefficient, 0.5
These are combined with the transistors properties to obtain the internal
resistance and capacitance values for each transistor.

SPICE Examples
RING OSCILLATOR LAYOUTS

17 Stage Un-buffered Output L/W=2/30 Buffered Output
L/W 8/16 4/16 2/16 73 Stage 37 Stage


SPICE Examples
MOSFETS IN THE INVERTER OF 73 RING OSCILLATOR

nmosfet pmosfet
73 Stage Ring Oscillator


SPICE Examples
FIND DIMENSIONS OF THE TRANSISTORS
NMOS PMOS 73 Stage

L 2u 2u
W 12u 30u
AD 12ux12u=144p 12ux30u=360p
AS 12ux12u=144p 12ux30u=360p
PD 2x(12u+12u)=48u 2x(12u+30u)=84u
PS 2x(12u+12u)=48u 2x(12u+30u)=84u
NRS 1 0.3
NRD 1 0.3
Right mouse click on each transistor and add these

values to the properties.

SPICE Examples
LEVEL = 7
*2-15-2009
.MODEL RITSUBN7 NMOS (LEVEL=7
+TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8 NSS=3E11
+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7
*
*2-17-2009
.MODEL RITSUBP7 PMOS (LEVEL=7
+TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8 NSS=3E11 PCLM=5
+VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7 NGATE=5E20
+RSH=50 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94


SPICE Examples
SIMULATED OUTPUT AT 10 VOLTS
Three Stage Ring Oscillator with Transistor Parameters for 73

Stage Ring Oscillator and Supply of 10 volts
td = T / 2N = 3.5nsec / 2 / 3
Microelectronic Engineering td = 0.583 nsec
SPICE Examples
SIMULATED OUTPUT AT 5 VOLTS
Three Stage Ring Oscillator with Transistor Parameters for 73

Stage Ring Oscillator and Supply of 5 volts
td = T / 2N = 5.5nsec / 2 / 3
Measured td = 0.718 nsec @ 5 V
Microelectronic Engineering td = 0.92 nsec
SPICE Examples
RING OSCILLATOR USING LTSPICE
td = T / 2N
= 6.4nsec / 2 / 3
= 1.07 nsec
Measured td
= 0.718 nsec @ 5 V


SPICE Examples
CONCLUSION
Since the measured and the simulated gate delays, td are close to
correct, then the SPICE model must be close to correct. The
inverter gate delay depends on the values of the internal capacitors
and resistances of the transistor.
Specifically:
RS, RS, RSH
CGSO, CGDO, CGBO
CJ, CJSW
These are combined with the transistors

SPICE Examples
VTC FOR THREE INPUT NAND GATE

TRUTH TABLE +V
Va VbVc Vout
0 0 0 1
0 0 1 1 Vout
0 1 0 1 Va M1
0 1 1 1
1 0 0 1 Vb
1 0 1 1 M2
1 1 0 1
1 1 1 0 Vc M3
M3 has Vt = Vto
M1 has Vt = Vto + Body Effect
Thus the Voltage Transfer Curve (VTC) is different
depending on which transistor is going from low to
high (with other two high)

SPICE Examples
3-INPUT NAND- BODY EFFECT
Two inputs high

Sweep M6
Two inputs high Body Effect
Sweep M7
No Body Effect


SPICE Examples
GATE LEVEL SIMULATION OF XOR – ALL/NOR


SPICE Examples
TRANSISTOR LEVEL SIMULATION OF XOR – ALL/NOR


SPICE Examples
4 TO 1 MULTIPLEXER
I0
A
I1
I2 Output
I3
A B Out
Digital signals A and B control
which of the four inputs is 0 0 I0
directed to the output 0 1 I1
1 0 I2
Rochester Institute of Technology 1 1 I3

SPICE Examples
4 TO 1 MUX - GATE LEVEL SIMULATION


SPICE Examples
ANALOG SWITCH
Switch Off Switch On
Analog Input


SPICE Examples
BASIC TWO STAGE OPERATIONAL AMPLIFIER
Layout
Schematic

SPICE Examples
SPICE ANALYSIS OF OP AMP

.incl rit_sub_param.txt
m1 8 9 7 6 cmosn w=9u l=5u nrd=1 nrs=1 ad=45p pd=28u as=45p ps=28u
m3 8 8 4 4 cmosp w=21u l=5u nrd=1 nrs=1 ad=102p pd=50u as=102p ps=50u
vdd 4 0 3
vss 6 0 -3
cprobe 2 0 30p
Rprobe 2 0 1meg
cc 1 2 0.6p
mr1 20 20 4 4 cmosp w=6u l=10u nrd=1 nrs=1 ad=200p pd=60u as=200p ps=60u
mr2 5 5 20 4 cmosp w=6u l=10u nrd=1 nrs=1 ad=200p pd=60u as=200p ps=60u
***************
************* ***dc open loop
gain*********
vi1 9 0 0
13.5kV/V gain vi2 10 0 0
*.dc vi2 -0.002 0.002 1u
.dc vi2 -1 1 0.1m
*****open loop frequency
characteristics*****
*vi1 9 0 0
Rochester Institute of Technology *vi2 10 0 dc 0 ac 1u
Microelectronic Engineering *.ac dec 100 10 1g
.end

SPICE Examples
BASIC TWO STAGE OP AMP - LOADING


SPICE Examples
RIT OP AMP WITH OUTPUT STAGE – W/L

99
M6 M5 M8 M11 M15
W/L W/L W/L
100/2 100/2 W/L W/L 9 686/2 M19
100/2 282/2
3 M12 12
W/L
M16 3800/2
1 +V +V 2
Vin+ Vin- W/L
10 W/L M18
100/2 336/2
40/2 M1 M2 40/2 7 14
6 5 4 W/L RL
M9 M13 100/2
M20
30/2 30/2 13
M14 11 M17
8 W/L
M3 M4 645/2
20/40 90/2 W/L
90/2 90/2 90/2 2600/2
M7 M10

98
W/L Microelectronic Engineering

SPICE Examples
RIT OP AMP WITH OUTPUT STAGE


SPICE Examples
RIT OP AMP WITH OUTPUT STAGE – RL=100
Current +/- 50mA
Voltage gain max ~4000
Offset voltage ~Zero


SPICE Examples
OTHER RESULTS
Voltage Gain for 1 MEG Load

Voltage Gain vs RL
Output Resistance
Gain versus Frequency (Gain Bandwidth Product)
Lowest Supply Voltage
Single Supply Operation
Rail-to-Rail Operation
Offset Voltage
Effect of variation of Vt, temperture
more


SPICE Examples
SIMPLE BJT OP AMP


SPICE Examples
SIMPLE BJT OP AMP


SPICE Examples
BJT OP AMP USE IN ELECTRONICS LAB

VCC = +12 V
10 F RE2
RC1 RC2 RE1
Q3
10 k 10 F Q2N3906 Q2N3904
Q1 Q2 Q6
Q4
100 100 Q2N3904 100
vid ~
vo
6 mA
Q2N3906 100 RL
Q5
Q7
Q2N3906
RC3
Rochester Institute of Technology –VEE = –12 V

SPICE Examples
BJT OP AMP SPICE SIMULATION
Electronics II
Lab Assignment


SPICE Examples
WAVEFORM GENERATOR
R1 VT R2
Rf Rf
+V
C
C
R R
+ -
-
- Vo1 + Vo3
Vo2 +
-V
C
R
Vo1 – SQUARE WAVE
Vo2 – TRIANGLE WAVE
Vo3 – SINE WAVE (approximation)


SPICE Examples
WAVEFORM GENERATOR


SPICE Examples
AM RECEIVER
LC Filter Three Stage Amplifier

Input 10’s of uV Output 100’s of mV

SPICE Examples
AM RECEIVER SIMULATION


SPICE Examples
AM RECEIVER SIMULATION


SPICE Examples
REFERENCES
1. MOSFET Modeling with SPICE, Daniel Foty, 1997, Prentice Hall,
ISBN-0-13-227935-5
2. Operation and Modeling of the MOS Transistor, 2nd Edition, Yannis Tsividis,
1999, McGraw-Hill, ISBN-0-07-065523-5
3. UTMOST III Modeling Manual-Vol.1. Ch. 5. From Silvaco International.
4. ATHENA USERS Manual, From Silvaco International.
5. ATLAS USERS Manual, From Silvaco International.
6. Device Electronics for Integrated Circuits, Richard Muller and Theodore
Kamins, with Mansun Chan, 3rd Edition, John Wiley, 2003, ISBN 0-471-59398-2
7. ICCAP Manual, Hewlet Packard
8. PSpice Users Guide.


SPICE Examples
HOMEWORK – SPICE EXAMPLES
Do SPICE for one of the following:
1. Do a SPICE simulation for one of the more complicated examples

shown in this document.
2. Do a SPICE simulation for a completely different circuit not shown
in this document.


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SPICE Examples

ROCHESTER INSTITUTE OF TECHNOLOGY

Rochester Institute of Technology 1-2-2014 SPICE_Examples.ppt

© January 2, 2014 Dr. Lynn Fuller Page 1

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 2

© January 2, 2014 Dr. Lynn Fuller Page 3

Input files include a TITLE, circuit description NET LIST, analysis

© January 2, 2014 Dr. Lynn Fuller Page 4

PSpice Lite 9.2 is one of the OrCAD family of products, from

LT SPICE – is a free SPICE simulator with schematic capture from

© January 2, 2014 Dr. Lynn Fuller Page 5

CREATING THE INPUT FILE

The input file can be generated from a schematic capture program,

© January 2, 2014 Dr. Lynn Fuller Page 6

LTSPICE USING INPUT FILE INSTEAD OF SCHEMATIC

.op is a spice directive to do DC operating point analysis

© January 2, 2014 Dr. Lynn Fuller Page 8

DC SPICE ANALYSIS USING LTSPICE

© January 2, 2014 Dr. Lynn Fuller Page 9

TRANSIENT ANALYSIS USING LTSPICE

Right click on voltage source

© January 2, 2014 Dr. Lynn Fuller Page 10

AC ANALYSIS USING LTSPICE

Right click on voltage source

© January 2, 2014 Dr. Lynn Fuller Page 11

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 12

NMOS INVERTER WITH RESISTER LOAD

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 13

NMOS INVERTER RESISTIVE LOADS

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 14

NMOS INVERTER WITH NMOS LOAD

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 15

PMOS INVERTER WITH PMOS LOAD

© January 2, 2014 Dr. Lynn Fuller Page 16

CMOS INVERTER VOUT VS VIN (VTC)

© January 2, 2014 Dr. Lynn Fuller Page 17

MEASURED CMOS INVERTER VOUT & I VS VIN

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 18

DC SIMULATION OF INVERTER VOUT & I VS VIN

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 19

SIMPLE AND ADVANCED SPICE MODEL

* From Electronics II EEEE482 FOR ~100nm Technology

© January 2, 2014 Dr. Lynn Fuller Page 20

CMOS INVERTER WITH LEVEL 1 SPICE MODEL

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 21

CMOS INVERTER WITH LEVEL 8 SPICE MODEL

Rochester Institute of Technology

© January 2, 2014 Dr. Lynn Fuller Page 22

SPICE LEVEL-1 MOSFET MODEL