CH10-COA10e - Computer Arithmetic PDF

+
William Stallings
Computer Organization
and Architecture
10th Edition
© 2016 Pearson Education, Inc., Hoboken,
NJ. All rights reserved.
+ Chapter 10
Computer Arithmetic
© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.
+
Arithmetic & Logic Unit (ALU)
 Part of the computer that actually performs arithmetic and

logical operations on data
 All of the other elements of the computer system are there

mainly to bring data into the ALU for it to process and then to
take the results back out
 Based on the use of simple digital logic devices that can store
binary digits and perform simple Boolean logic operations

Control
Signals Flags
ALU
Operand Result
Registers Registers
Figure 10.1 ALU Inputs and Outputs

+
Integer Representation
 In the binary number system arbitrary numbers can be

represented with:
 The digits zero and one
 The minus sign (for negative numbers)
 The period, or radix point (for numbers with a fractional
component)
 For purposes of computer storage and processing we do not

have the benefit of special symbols for the minus sign and
radix point
 Only binary digits (0,1) may be used to represent numbers

Sign-Magnitude Representation
There are several alternative •All of these alternatives involve treating the
most significant (leftmost) bit in the word as a
conventions used to represent sign bit
negative as well as positive •If the sign bit is 0 the number is positive
integers •If the sign bit is 1 the number is negative
Sign-magnitude representation is
the simplest form that employs a
sign bit
•Addition and subtraction require a

consideration of both the signs of the
Drawbacks: numbers and their relative magnitudes to
carry out the required operation
•There are two representations of 0
Because of these drawbacks,

sign-magnitude representation is
rarely used in implementing the
integer portion of the ALU

Table 10.1
Characteristics of Twos Complement Representation and Arithmetic
Range –2n–1 through 2 n–1 – 1

Number of Representations
One
of Zero
Take the Boolean complement of each bit of the corresponding
Negation positive number, then add 1 to the resulting bit pattern viewed as
an unsigned integer.
Expansion of Bit Length Add additional bit positions to the left and fill in with the value
of the original sign bit.
If two numbers with the same sign (both positive or both
Overflow Rule negative) are added, then overflow occurs if and only if the result
has the opposite sign.
Subtraction Rule To subtract B from A, take the twos complement of B and add it
to A.

Table 10.2
Alternative Representations for 4-Bit Integers
Decimal Sign-Magnitude Twos Complement Biased
Representation Representation Representation Representation
+8 — — 1111
+7 0111 0111 1110
+6 0110 0110 1101
+5 0101 0101 1100
+4 0100 0100 1011
+3 0011 0011 1010
+2 0010 0010 1001
+1 0001 0001 1000
+0 0000 0000 0111
–0 1000 — —
–1 1001 1111 0110
–2 1010 1110 0101
–3 1011 1101 0100
–4 1100 1100 0011
–5 1101 1011 0010
–6 1110 1010 0001
–7 1111 1001 0000
–8 — 1000 —
–128 64 32 16 8 4 2 1
(a) An eight-position two's complement value box
–128 64 32 16 8 4 2 1
1 0 0 0 0 0 1 1
–128 +2 +1 = –125
(b) Convert binary 10000011 to decimal
–128 64 32 16 8 4 2 1
1 0 0 0 1 0 0 0
–120 = –128 +8
(c) Convert decimal –120 to binary
Figure 10.2 Use of a Value Box for Conversion

Between Twos Complement Binary and Decimal

+
Range Extension
 Range of numbers that can be expressed is extended by

increasing the bit length
 In sign-magnitude notation this is accomplished by moving

the sign bit to the new leftmost position and fill in with zeros
 This procedure will not work for twos complement negative

integers
 Rule is to move the sign bit to the new leftmost position and fill in
with copies of the sign bit
 For positive numbers, fill in with zeros, and for negative numbers,
fill in with ones
 This is called sign extension

Fixed-Point Representation
Programmer can use the

same representation for
The radix point (binary
binary fractions by scaling
point) is fixed and assumed
the numbers so that the
to be to the right of the
binary point is implicitly
rightmost digit
positioned at some other
location

+
Negation
 Twos complement operation
 Take the Boolean complement of each bit of the integer
(including the sign bit)
 Treating the result as an unsigned binary integer, add 1
+18 = 00010010 (twos complement)

bitwise complement = 11101101
+ 1
11101110 = -18
 The negative of the negative of that number is itself:
-18 = 11101110 (twos complement)

bitwise complement = 00010001
+ 1
00010010 = +18
+
Negation Special Case 1
0 = 00000000 (twos complement)
Bitwise complement = 11111111
Add 1 to LSB + 1
Result 100000000
Overflow is ignored, so:
-0=0

+
Negation Special Case 2
-128 = 10000000 (twos complement)
Bitwise complement = 01111111
Add 1 to LSB + 1
Result 10000000
So:
-(-128) = -128 X
Monitor MSB (sign bit)
It should change during negation

1001 = –7 1100 = –4
+0101 = 5 +0100 = 4
1110 = –2 10000 = 0
(a) (–7) + (+5) (b) (–4) + (+4)
0011 = 3 1100 = –4
+0100 = 4 +1111 = –1
0111 = 7 11011 = –5
(c) (+3) + (+4) (d) (–4) + (–1)
0101 = 5 1001 = –7
+0100 = 4 +1010 = –6
1001 = Overflow 10011 = Overflow
(e) (+5) + (+4) (f) (–7) + (–6)
Figure 10.3 Addition of Numbers in Twos Complement Representation

Overflow
OVERFLOW RULE:
If two numbers are added,

Rule
and they are both positive
or both negative, then
+ overflow occurs if and
only if the result has the
opposite sign.
Subtraction
SUBTRACTION RULE:
To subtract one number

(subtrahend) from Rule
another (minuend), take

+
the twos complement
(negation) of the
subtrahend and add it
to the minuend.
0010 = 2 0101 = 5
+1001 = –7 +1110 = –2
1011 = –5 10011 = 3
(a) M = 2 = 0010 (b) M = 5 = 0101

S = 7 = 0111 S = 2 = 0010
–S = 1001 –S = 1110
1011 = –5 0101 = 5
+1110 = –2 +0010 = 2
11001 = –7 0111 = 7
(c) M =–5 = 1011 (d) M = 5 = 0101

S = 2 = 0010 S =–2 = 1110
–S = 1110 –S = 0010
0111 = 7 1010 = –6
+0111 = 7 +1100 = –4
1110 = Overflow 10110 = Overflow
(e) M = 7 = 0111 (f) M = –6 = 1010

S = –7 = 1001 S = 4 = 0100
–S = 0111 –S = 1100
Figure 10.4 Subtraction of Numbers in Twos Complement Representation (M – S)

subtraction addition subtraction addition
of positive of positive of positive of positive
numbers 0000 numbers numbers 000…0 numbers
1111 0001 111…1
1110 0010
-1 0
1101 -1 0 +1
-2 +2 0011
-3 +3
1100 -4 +4 0100 110…0 –2n–2
n–2
2 010…0
-5 +5
1011 -6 +6
-7 -8 +7 0101 n–1
–2n–1 2 –1
1010 0110
1001 0111 011…1
1000 100…0
-9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 n–1 n–1
–2 2 –1
n–1 n–1
–2 –1 2
(a) 4-bit numbers (b) n-bit numbers
Figure 10.5 Geometric Depiction of Twos Complement Integers

B Register A Register
Complementer
SW
OF Adder
OF = overflow bit
SW = Switch (select addition or subtraction)
Figure 10.6 Block Diagram of Hardware for Addition and Subtraction

1011 Multiplicand (11)
1101 Multiplier (13)
1011
0000
Partial products
1011
1011
10001111 Product (143)
Figure 10.7 Multiplication of Unsigned Binary Integers

Multiplicand
Mn-1 M0
Add Shift and Add

n-Bit Adder
Control Logic
Shift Right
C An-1 A0 Qn-1 Q0
Multiplier
(a) Block Diagram
C A Q M
0 0000 1101 1011 Initial Values
0 1011 1101 1011 Add First

0 0101 1110 1011 Shift Cycle
Second
0 0010 1111 1011 Shift Cycle
0 1101 1111 1011 Add Third

0 0110 1111 1011 Shift Cycle
1 0001 1111 1011 Add Fourth

0 1000 1111 1011 Shift Cycle
(b) Example from Figure 9.7 (product in A, Q)
Figure 10.8 Hardware Implementation of

Unsigned Binary Multiplication
START
C, A 0
M Multiplicand
Q Multiplier
Count n
No Yes
Q0 = 1?
C, A A+M
Shift right C, A, Q
Count Count – 1
No Yes
Count = 0? END Product
in A, Q
Figure 10.9 Flowchart for Unsigned Binary Multiplication

1011
´1101
00001011 1011 ´ 1 ´ 20
00000000 1011 ´ 0 ´ 21
00101100 1011 ´ 1 ´ 22
01011000 1011 ´ 1 ´ 23
10001111
Figure 10.10 Multiplication of Two Unsigned 4-Bit Integers Yielding an 8-Bit

Result

1001 (9) 1001 (–7)
´0011 (3) ´0011 (3)
00001001 1001 ´ 20 11111001 (–7) ´ 20 = (–7)
00010010 1001 ´ 21 11110010 (–7) ´ 21 = (–14)
00011011 (27) 11101011 (–21)
(a) Unsigned integers (b) Twos complement integers
Figure 10.11 Comparison of Multiplication of Unsigned and Twos

Complement Integers

START
A 0, Q-1 0
M Multiplicand
Q Multiplier
Count n
= 10 Q0 , Q-1 = 01
= 11
= 00
A A–M A A+M
Arithmetic Shift
Right: A, Q, Q -1
Count Count – 1
No Yes
Count = 0? END
Figure 10.12 Booth's Algorithm for Twos Complement Multiplication

A Q Q-1 M
0000 0011 0 0111 Initial Values
1001 0011 0 0111 A A - M First

1100 1001 1 0111 Shift Cycle
Second
1110 0100 1 0111 Shift Cycle
0101 0100 1 0111 A A + M Third

0010 1010 0 0111 Shift Cycle
Fourth
0001 0101 0 0111 Shift
Cycle
Figure 10.13 Example of Booth's Algorithm (7 3)

0111 0111
´0011 (0) ´1101 (0)
11111001 1–0 11111001 1–0
0000000 1–1 0000111 0–1
000111 0–1 111001 1–0
00010101 (21) 11101011 (–21)
(a) (7) ´ (3) = (21) (b) (7) ´ (–3) = (–21)
1001 1001
´0011 (0) ´1101 (0)
00000111 1–0 00000111 1–0
0000000 1–1 1111001 0–1
111001 0–1 000111 1–0
11101011 (–21) 00010101 (21)
(c) (–7) ´ (3) = (–21) (d) (–7) ´ (–3) = (21)
Figure 10.14 Examples Using Booth's Algorithm

00001101 Quotient
Divisor 1011 10010011 Dividend
1011
001110
1011
Partial
001111
remainders
1011
100 Remainder
Figure 10.15 Example of Division of Unsigned Binary Integers

START
A 0
M Divisor
Q Dividend
Count n
Shift Left
A, Q
A A–M
No Yes
A < 0?
Q0 0
Q0 1 A A+M
Count Count – 1
No Yes
Count = 0? END Quotient in Q
Remainder in A
Figure 10.16 Flowchart for Unsigned Binary Division

A Q
0000 0111 Initial value
0000 1110 Shift

1101 Use twos complement of 0011 for subtraction
1101 Subtract
0000 1110 Restore, set Q0 = 0
0001 1100 Shift
1101
1110 Subtract
0001 1100 Restore, set Q0 = 0
0011 1000 Shift
1101
0000 1001 Subtract, set Q0 = 1
0001 0010 Shift
1101
1110 Subtract
0001 0010 Restore, set Q0 = 0
Figure 10.17 Example of Restoring Twos Complement Division (7/3)

+
Floating-Point Representation
Principles
 With a fixed-point notation it is possible to represent a range
of positive and negative integers centered on or near 0
 By assuming a fixed binary or radix point, this format allows

the representation of numbers with a fractional component as
well
 Limitations:
 Very large numbers cannot be represented nor can very small
fractions
 The fractional part of the quotient in a division of two large
numbers could be lost

sign of
significand
8 bits 23 bits
biased exponent significand
(a) Format
1.1010001 210100 = 0 10010011 10100010000000000000000 = 1.6328125 220

-1.1010001 210100 = 1 10010011 10100010000000000000000 = –1.6328125 220
1.1010001 2-10100 = 0 01101011 10100010000000000000000 = 1.6328125 2–20
-1.1010001 2-10100 = 1 01101011 10100010000000000000000 = –1.6328125 2–20
(b) Examples
Figure 10.18 Typical 32-Bit Floating-Point Format

+
Floating-Point
Significand
 The final portion of the word
 Any floating-point number can be expressed in many ways
The following are equivalent, where the significand is

expressed in binary form:
0.110 * 25
110 * 22
0.0110 * 26
 Normal number
 The most significant digit of the significand is nonzero

Expressible Integers
Number
–231 0 231 – 1 Line
(a) Twos Complement Integers
Negative Positive
Underflow Underflow
Negative Expressible Negative Expressible Positive Positive
Overflow Numbers Numbers Overflow
Zero
Number
– (2 – 2–23) 2128 –2–127 0 2–127 (2 – 2–23) 2128 Line
(b) Floating-Point Numbers
Figure 10.19 Expressible Numbers in Typical 32-Bit Formats

–n 0 n 2n 4n
Figure 10.20 Density of Floating-Point Numbers

IEEE Standard 754
Standard was developed to

facilitate the portability of
programs from one
Most important floating-point
processor to another and to
representation is defined
encourage the development
of sophisticated, numerically
oriented programs
Standard has been widely

adopted and is used on IEEE 754-2008 covers both
virtually all contemporary binary and decimal floating-
processors and arithmetic point representations
coprocessors

+
IEEE 754-2008
 Defines the following different types of floating-point formats:
 Arithmetic format
 All the mandatory operations defined by the standard are supported
by the format. The format may be used to represent floating-point
operands or results for the operations described in the standard.
 Basic format
 This format covers five floating-point representations, three binary
and two decimal, whose encodings are specified by the standard, and
which can be used for arithmetic. At least one of the basic formats is
implemented in any conforming implementation.
 Interchange format
 A fully specified, fixed-length binary encoding that allows data
interchange between different platforms and that can be used for
storage.

sign biased
bit exponent
trailing
significand field
8 bits 23 bits
(a) binary32 format
sign biased
bit exponent
trailing significand field
11 bits 52 bits
(b) binary64 format
sign
bit
biased
trailing significand field
exponent
15 bits 112 bits
(c) binary128 format
Figure 10.21 IEEE 754 Formats

Table 10.3 IEEE 754 Format Parameters
Format
Parameter
binary32 binary64 binary128
Storage width (bits) 32 64 128
Exponent width (bits) 8 11 15
Exponent bias 127 1023 16383
Maximum exponent 127 1023 16383
Minimum exponent –126 –1022 –16382
Approx normal number range 10–38, 10+38 10–308, 10+308 10–4932, 10+4932
(base 10)
Trailing significand width (bits)* 23 52 112
Number of exponents 254 2046 32766
Number of fractions 223 252 2112
Number of values 1.98 ´ 231 1.99 ´ 263 1.99 ´ 2128
Smallest positive normal number 2–126 2–1022 2–16362
Largest positive normal number 2128 – 2104 21024 – 2971 216384 – 216271
Smallest subnormal magnitude 2–149 2–1074 2–16494
* not including implied bit and not including sign bit
+ Additional Formats
Extended Precision Formats

Extendable Precision Format
 Provide additional bits in the exponent
(extended range) and in the significand
(extended precision)  Precision and range are defined
under user control
 Lessens the chance of a final result that
has been contaminated by excessive  May be used for intermediate
roundoff error calculations but the standard
places no constraint or format or
 Lessens the chance of an intermediate
length
overflow aborting a computation whose
final result would have been
representable in a basic format
 Affords some of the benefits of a larger

basic format without incurring the time
penalty usually associated with higher
precision

Table 10.4
IEEE Formats
Format Type
Format
Arithmetic Format Basic Format Interchange Format
binary16 X
binary32 X X X
binary64 X X X
binary128 X X X
binary{k}
X X
(k = n ´ 32 for n > 4)
decimal64 X X X
decimal128 X X X
decimal{k}
X X
(k = n ´ 32 for n > 4)
extended precision X
extendable precision X

Table 10.5
Interpretation of IEEE 754 Floating-Point Numbers (page 1 of 3)
Sign Biased exponent Fraction Value

positive zero 0 0 0 0
negative zero 1 0 0 –0
plus infinity 0 all 1s 0 ∞
Minus infinity 1 all 1s 0 –∞
quiet NaN 0 or 1 all 1s ≠ 0; first bit qNaN
=1
≠ 0; first bit
signaling NaN 0 or 1 all 1s sNaN
=0
positive normal nonzero 0 0 < e < 255 f 2e–127(1.f)
negative normal nonzero 1 0 < e < 255 f –2e–127(1.f)
positive subnormal 0 0 f≠0 2e–126(0.f)
negative subnormal 1 0 f≠0 –2e–126(0.f)
(a) binary32 format

Table 10.5

Minus infinity 1 all 1s 0 –∞
=1
≠ 0; first bit
=0
positive normal nonzero 0 0 < e < 2047 f 2e–1023(1.f)
negative normal nonzero 1 0 < e < 2047 f –2e–1023(1.f)
(a) binary64 format

Table 10.5

minus infinity 1 all 1s 0 –∞
=1
≠ 0; first bit
=0
positive normal nonzero 0 all 1s f 2e–16383(1.f)
negative normal nonzero 1 all 1s f –2e–16383(1.f)
(a) binary128 format

Table 10.6 Floating-Point Numbers and Arithmetic Operations
Floating Point Numbers Arithmetic Operations
X = Xs ´ BXE ( )
X + Y = X s ´ B XE -YE + Ys ´ B YE üï
ý X E £ YE
Y = Ys ´ BYE ( )
X - Y = X s ´ B XE -YE - Ys ´ B YE ïþ
X ´ Y = ( X s ´ Ys ) ´ B
X E +YE
X æ Xs ö X -Y
= çç ÷÷ ´ B E E
Y è Ys ø
Examples:
X = 0.3 ´ 102 = 30
Y = 0.2 ´ 103 = 200
X + Y = (0.3 ´ 102–3 + 0.2) ´ 103 = 0.23 ´ 103 = 230

X – Y = (0.3 ´ 102–3 – 0.2) ´ 103 = (–0.17) ´ 103 = –170
X ´ Y = (0.3 ´ 0.2) ´ 102+3 = 0.06 ´ 105 = 6000
X ¸ Y = (0.3 ¸ 0.2) ´ 102–3 = 1.5 ´ 10–1 = 0.15

SUBTRACT
Yes Add Results Yes
Exponents Round
signed normalized?
equal? result
significands
Change No
sign of Y No
Yes Shift RETURN
Increment
No Z 0 Significand significand
smaller
No =0? left
exponent
ADD X = 0? Y = 0?
No
Yes RETURN Decrement
Yes
Shift exponent
No
significand Significand
Z Y Z X
right overflow?
Yes No Exponent
RETURN underflow?
Shift
No significand
Significand Yes
right
=0?
Report
Yes underflow
Increment
exponent
Put other RETURN
number in Z
RETURN
Yes
Report Exponent No
overflow overflow?
RETURN
Figure 10.22 Floating-Point Addition and Subtraction (Z X ± Y)

MULTIPLY
No No
X = 0? Y = 0? Add
Exponents
Yes Yes
Z 0 Subtract Bias
RETURN
Exponent Yes Report
Overflow? Overflow
No
Exponent Yes Report

Underflow? Underflow
No
Multiply
Significands
Normalize
Round RETURN
Figure 10.23 Floating-Point Multiplication (Z X Y)

DIVIDE
No No
X = 0? Y = 0? Subtract
Exponents
Yes Yes
Z 0 Z ∞ Add Bias
RETURN
Exponent Yes Report
Overflow? Overflow
No
Exponent Yes Report

Underflow? Underflow
No
Divide
Significands
Normalize
Round RETURN
Figure 10.24 Floating-Point Division (Z X/Y)

x = 1.000.....00 ´ 21 x = .100000 ´ 161
–y = 0.111.....11 ´ 21 –y = .0FFFFF ´ 161
z = 0.000.....01 ´ 21 z = .000001 ´ 161
= 1.000.....00 ´ 2–22 = .100000 ´ 16–4
(a) Binary example, without guard bits (c) Hexadecimal example, without guard bits
x = 1.000.....00 0000 ´ 21 x = .100000 00 ´ 161

–y = 0.111.....11 1000 ´ 21 –y = .0FFFFF F0 ´ 161
z = 0.000.....00 1000 ´ 21 z = .000000 10 ´ 161
= 1.000.....00 0000 ´ 2–23 = .100000 00 ´ 16–5
(b) Binary example, with guard bits (d) Hexadecimal example, with guard bits
Figure 10.25 The Use of Guard Bits

+
Precision Considerations
Rounding
 IEEE standard approaches:
 Round to nearest:
 The result is rounded to the nearest representable
number.
 Round toward +∞ :
 The result is rounded up toward plus infinity.
 Round toward -∞:
 The result is rounded down toward negative infinity.
 Round toward 0:
 The result is rounded toward zero.

+
Interval Arithmetic
 Provides an efficient method for  Minus infinity and rounding
monitoring and controlling errors in
floating-point computations by to plus are useful in
producing two values for each result implementing interval
arithmetic
 The two values correspond to the
lower and upper endpoints of an
interval that contains the true result
Truncation
 The width of the interval indicates
the accuracy of the result  Round toward zero
 If the endpoints are not
representable then the interval
 Extra bits are ignored
endpoints are rounded down and up
respectively  Simplest technique
 If the range between the upper and  A consistent bias toward zero in
lower bounds is sufficiently narrow the operation
then a sufficiently accurate result has
been obtained  Serious bias because it affects
every operation for which
there are nonzero extra bits
+
IEEE Standard for Binary Floating-Point Arithmetic
Infinity
Is treated as the limiting case of real arithmetic, with the infinity

values given the following interpretation:
- ∞ < (every finite number) < + ∞
For example:
5 + (+ ∞ ) = + ∞ 5÷ (+ ∞ ) = +0
5 - (+ ∞ ) = - ∞ (+ ∞ ) + (+ ∞ ) =+∞
5 + (- ∞ ) = - ∞ (- ∞ ) + (- ∞) =-∞
5 - (- ∞ ) =+∞ (- ∞ ) - (+ ∞ ) =-∞
5 * (+ ∞ ) = + ∞ (+ ∞ ) - (- ∞ ) =+∞
Table 10.7
Operations that Produce a Quiet NaN

gap
2–126 2–125 2–124 2–123

0
(a) 32-bit format without subnormal numbers
uniform
spacing
2–126 2–125 2–124 2–123

0
(b) 32-bit format with subnormal numbers
Figure 10.26 The Effect of IEEE 754 Subnormal Numbers

+ Summary Computer
Arithmetic
Chapter 10
 Integer arithmetic
 ALU
 Negation
 Integer representation
 Addition and subtraction
 Sign-magnitude
 Multiplication
representation
 Division
 Twos complement
representation  Floating-point arithmetic
 Range extension  Addition and subtraction
 Fixed-point representation  Multiplication and division
 Floating-point representation  Precision consideration
 Principles  IEEE standard for binary
 IEEE standard for binary floating-point arithmetic
floating-point representation

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How are integers represented in computers?

How are integers represented in computers?

What are the different methods for representing negative numbers?

What are the different methods for representing negative numbers?

+

 Part of the computer that actually performs arithmetic and

 All of the other elements of the computer system are there

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 10.1 ALU Inputs and Outputs

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 In the binary number system arbitrary numbers can be

 For purposes of computer storage and processing we do not

 Only binary digits (0,1) may be used to represent numbers

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

•Addition and subtraction require a

Because of these drawbacks,

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Range –2n–1 through 2 n–1 – 1

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

(a) An eight-position two's complement value box

(b) Convert binary 10000011 to decimal

(c) Convert decimal –120 to binary

Figure 10.2 Use of a Value Box for Conversion

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

 Range of numbers that can be expressed is extended by

 In sign-magnitude notation this is accomplished by moving

 This procedure will not work for twos complement negative

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Programmer can use the

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

+18 = 00010010 (twos complement)

 The negative of the negative of that number is itself:

-18 = 11101110 (twos complement)

0 = 00000000 (twos complement)

Bitwise complement = 11111111

Overflow is ignored, so:

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

-128 = 10000000 (twos complement)

Bitwise complement = 01111111

Monitor MSB (sign bit)

It should change during negation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Figure 10.3 Addition of Numbers in Twos Complement Representation

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

If two numbers are added,

To subtract one number

another (minuend), take

(a) M = 2 = 0010 (b) M = 5 = 0101

(c) M =–5 = 1011 (d) M = 5 = 0101

(e) M = 7 = 0111 (f) M = –6 = 1010

Figure 10.4 Subtraction of Numbers in Twos Complement Representation (M – S)

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Figure 10.5 Geometric Depiction of Twos Complement Integers

Figure 10.6 Block Diagram of Hardware for Addition and Subtraction

Figure 10.7 Multiplication of Unsigned Binary Integers

© 2016 Pearson Education, Inc., Hoboken, NJ. All rights reserved.

Add Shift and Add

(a) Block Diagram

0 1011 1101 1011 Add First