A REVIEW OF LOW POWER PROCESSOR

DESIGN
Nalini.D(1) ,Pradeep Kumar.P(2) ,Sundar Ganesh C S(3)
(1),(2) Dept of Electrical and Electronics Engineering, PSG College of Technology, Coimbatore ,India
(3) Assistant Professor (SR.G), Dept of Robotics and Automation Engineering, PSG College of Technology, Coimbatore
,India
Email-Id:[email protected],[email protected],[email protected]
Abstract
Power has become an important aspect in the design of general purpose processors. This paper gives a review of
various technologies used for low power processor design. Scaling the technology is an attractive way to improve the
energy efficiency of the processor. In a scaled technology a processor would dissipate less power for the same
performance or higher performance for the same power. Some micro architectural changes, such as pipelining and
caching, can significantly improve efficiency. Another attractive technique for reducing power dissipation is scaling the
supply and threshold voltages. Unfortunately this makes the processor more sensitive to variations in process and
operating conditions. Dynamic voltage scaling is one of the more effective and widely used methods for power-aware
computing. DVS approach uses dynamic detection and correction of circuit timing errors to tune processor supply
voltage and eliminate the need for voltage margins. Razor, a voltage-scaling technology based on Dynamic detection
and correction of circuit timing errors, permits design optimizations that tune the energy in a microprocessor pipeline to
typical circuit operational levels. This eliminates the voltage margins that traditional worst-case design methodologies
require and allows digital systems to run correctly and robustly at the edge of minimum power consumption.

Keywords: Scaled technology, Dynamic voltage scaling (DVS), Error detection and correction
Introduction Though there are multiple frequency and global components,
Processor is the tradeoffs between all voltage levels is while cross-coupling
heart of the computer. the performance challenging and noise is a
There are lot many parameter's, Research requires characterizing predominantly local
processor's in the is being carried out to the processor to ensure effect. To ensure
market. When a satisfy all the above correct operation at the correct operation under
processor is designed performance required operating all possible variations,
using processor cores parameters. points. We call the designers typically use
i..e Hardware A critical minimum supply corner analysis to select
Description Languages concern for embedded voltage that produces a conservative supply
like Verilog-HDL and systems is the need to correct operation the voltage. This means
VHDL ( Very High deliver high levels of critical supply voltage. adding margins to the
Speed Integrated performance given This voltage must be critical voltage to
Circuit Hardware ever-diminishing power sufficient to ensure account for uncertainty
Description Language ) budgets. This is evident correct operation in the in the circuit models
it is called soft core in the evolution of the face of numerous and for the worst-case
processor. It is used for mobile phone: in the environmental and combination of
writing a particular last 7 years mobile process-related variabilities. However,
version of processor. phones have shown a variabilities that can such a combination of
This helps the designer 50X improvement in affect circuit variabilities might be
to check and select the talk-time per gram of performance. These very rare or even
processor for particular battery1, while at the include unexpected impossible in a
application. RISC same time taking on voltage drops in the particular chip, making
(Reduced Instruction new computational power supply network, this approach overly
Set Computer) is an tasks that only recently temperature conservative. And, with
efficient Computer appeared on desktop fluctuations, gate process scaling,
Architecture which can computers, such as 3D length and doping environmental and
be used for the Low graphics, audio/video, concentration process variabilities
power and high speed internet access, and variations, and cross- will likely increase,
applications of the gaming. As the breadth coupling noise. These worsening the required
processor. RISC of applications for variabilities can be data voltage margins. To
Processors are these devices widens, a dependent, meaning support more-
important in application single operating point that they exhibit their aggressive power
of pipelining. The heart is no longer sufficient worst-case impact on reduction, designers
of the processor is the to efficiently meet their circuit performance can use embedded
Instruction Set processing and only under certain inverter delay chains to
Architecture (ISA) used power consumption instruction and data tune the supply voltage
for developing it. The requirements. sequences and that they to an individual
total worthiness of the Lowering clock comprise both local and processor chip. The
processor depends on frequency to the global components. For inverter chain’s delay
utilizing the Instruction minimum required instance, local process serves to predict the
Set Architecture. level exploits periods variations will affect circuit’s critical-path
However a lot of low processor specific regions of the delay, and a voltage
of research is being utilization and allows a die in different and controller tunes the
carried out in the field corresponding independent ways, supply voltage during
of processor's to satisfy reduction in supply while global process processor operation to
the performance issues. voltage. Because variations affect the meet a predetermined
But now a days it is dynamic energy scales entire die’s circuit delay through the
mandatory to use a quadratically with performance and create inverter chain. This
machine which is supply voltage, DVS variation from one die approach to DVS has
efficient in the terms of can significantly reduce to the next. Similarly, the advantage that it
speed, power, energy use. Enabling temperature and supply dynamically adjusts the
performance and size. systems to run at drop have local and operating voltage to
account for global proportional to the the design must utilize to minimize dynamic
variations in supply supply voltage, Vdd: low voltage levels, power.
voltage drop, f Vdd which reduces circuit
temperature fluctuation, The energy E necessary performance.
and process variations. to operate a digital Dynamic
However, it cannot circuit for a time voltage scaling has
account for local duration T is the sum of emerged as a powerful
variations, such as local two energy technique to reduce
supply-voltage drops, components: circuit energy demands.
intradie process E = SCV2dd + Vdd IleakT In a DVS system, the
variations, and cross- where the first application or operating
coupled noise. term models the system identifies
Therefore, the approach dynamic power lost periods of low
requires adding safety from charging and processor utilization
margins to the critical discharging the that can tolerate
voltage. Also, an capacitive loads within reduced frequency. Fig 1: Clock
inverter chain’s delay the circuit and the With reduced gating for power
doesn’t scale with second term models the frequency, similar reduction.
voltage and static power lost in reductions are possible Clock gating is a
temperature in the same passive leakage current in the supply voltage. mainstream low power
way as the critical path —that is, the small Since dynamic power design technique
delays of the actual amount of current that scales quadratically targeted at reducing
design. The latter leaks through with supply voltage, dynamic power by
delays can contain transistors even when DVS technology can disabling the clocks to
complex gates and they are turned off. The significantly reduce inactive flip-flops.
pass-transistor logic, dynamic power loss energy consumption
again requiring extra depends on the total with little impact on
voltage safety margins. number of signal perceived system
In future technologies, transitions, S, the total performance.
the local component of capacitance load of the
environmental and circuit wire and gates, Conventional
process variation is C, and the square of the processor design
likely to become more supply voltage. The To minimize
prominent, the static power loss this power, Technology
sensitivity of circuit depends on the supply scaling, voltage scaling,
performance to these voltage, the rate of clock frequency
variations is higher at current leakage through scaling, reduction of
lower operating the circuit, Ileak, and the switching activity, etc., Fig 2: Generation of
voltages, thereby duration of operation were widely used. gated clock when
increasing the during which leakage The two most common negative latch is used.
necessary margins and occurs, T. The traditional, mainstream To save more power,
reducing the scope for dependence of both techniques are: positive or negative
energy savings. speed and energy 1. Clock Gating: latch can also be used
dissipation on supply Clock gating is a as shown in Fig. 2 and
Speed, Energy and voltage creates a technique which is Fig. 3. This saves
Voltage Scaling tension in circuit shown in Fig. 1 for power in such a way
Both circuit design: To make a power reduction, in that even when target
speed and energy system fast, the design which the clock is device’s clock is ‘ON’,
dissipation depend on must utilize high disconnected from a controlling device’s
voltage. The speed or voltage levels, which device it drives when clock is ‘OFF’. Also
clock frequency, f, of a increases energy the data going into the when the target
digital circuit is demands; to make a device is not changing. device’s clock is ‘OFF’,
system energy efficient, This technique is used then also controlling
device’s clock is ‘OFF’. 1) Dual VDD
In this more power can A Dual VDD
be saved by avoiding Configuration Logic
unnecessary switching Block and a Dual VDD
at clock net . routing matrix is shown
in Fig.5.

Fig 6: High VDD for

Fig 4: Variation of
critical paths and low
threshold voltage with
VDD for non-critical
Fig 3: Generation of respect to the delay and
paths.
gated clock when leakage current.
2) Clustered Voltage
positive latch is used. Above figure
Fig 5: Dual VDD Scaling (CVS)
2. Multi-Vth shows the variation of
architecture. This is a
optimization/ (Multi threshold voltage with
In Dual VDD technique to reduce
Threshold respect to the delay and
architecture, the supply power without
-MTCMOS): leakage current. As Vt
voltage of the logic and changing circuit
MTCMOS is the increases, delay
routing blocks are performance by making
replacement of faster increases along with a
programmed to reduce use of two supply
Low-Vth (Low decrease in leakage
the power consumption voltages. Gates of the
threshold voltage) cells, current. As Vt
by assigning low-VDD critical path are run at
which consume more decreases, delay
to non-critical paths in the lower supply to
leakage power, with decreases along with an
the design, while reduce power, as shown
slower High-Vth (high increase in leakage
assigning high-VDD to in Fig. 7. To minimize
threshold voltage) cells, current. Thus an
the timing critical paths the number of
which consume less optimum value of Vt
in the design to meet interfacing level
leakage power. Since should be selected
timing constraints as converters needed, the
the High-Vth cells are according to the
shown in Fig. 6. circuits which operate
slower, this swapping presence of the gates in
However, whenever at reduced voltages are
can only be done on the critical path. As
two different supply clustered leading to
timing paths that have technologies have
voltages co-exist, static clustered voltage
positive slack and thus shrunk, leakage power
current flows at the scaling.
can be allowed to slow consumption has grown
interface of the VDDL
down. Hence multiple exponentially, thus
part and the VDDH
threshold voltage requiring more
part. So level
techniques use both aggressive power
converters can be used
Low Vt and High Vt reduction techniques to
to up convert a low
cells. It uses lower be used.
VDD to a high VDD.
threshold gates on Several
critical path while advanced low power
higher threshold gates techniques have been
off the critical path . developed to address
these needs. The most
commonly adopted
techniques today are in
below:
 which a device Razor is an analysis to identify this
operates, while it is error-tolerant DVS critical voltage. To the
operational, such that technology. Its error- critical voltage, they
the minimum voltage tolerance mechanisms add the following
and/or frequency eliminate the need for voltage margins to
needed for proper voltage margins that ensure that all circuits
operation of a designing for “always operate correctly even
particular mode is used correct” circuit in the worst-case
is termed as DVFS, operations requires. operating environment:
Dynamic Voltage and The improbability of Process
Frequency Scaling the worst-case margins ensure that
Razor approach conditions that drive performance
Razor, a new traditional circuit uncertainties resulting
approach to DVS, is design underlies the from manufacturing
based on dynamic technology. variations in transistor
Fig 7: Gates of the detection and Voltage margins dimensions and
critical paths are run at correction of speed composition do not
lower supply. path failures in digital prevent slower devices
Here only one designs. Its key idea is from completing
voltage transition is to tune the supply evaluation within a
allowed along a path voltage by monitoring clock cycle. Designers
and level conversion the error rate during find the margin
takes place only at operation. Because this necessary to
flipflops. error detection provides accommodate slow
3) Multi-voltage (MV) in-place monitoring of devices by using
MV deals with the actual circuit delay, pessimistically slow
the operation of it accounts for both devices to evaluate the
different areas of a global and local delay critical path’s latency.
design at different variations and doesn’t Ambient
voltage levels. Only suffer from voltage margins accommodate
specific areas that scaling disparities. It slower circuit
require a higher voltage therefore eliminates the operations at high
to meet performance need for voltage Fig 8: Critical voltage temperatures. The
targets are connected to margins to ensure margins and to meet margin ensures correct
the higher voltage always-correct circuit worst case reliability operation at the worst-
supplies. Other portions operation in traditional requirements case temperature,
of the design operate at designs. In addition, a Above figure which is typically 85-
a lower voltage, key Razor feature is shows margins for 95°C.
allowing for significant that operation at factors that can affect Noise
power savings. Multi- subcritical supply the voltage required to margins safeguard
voltage is generally a voltages doesn’t reliably operate a against a variety of
technique used to constitute a processor’s underlying noise sources that
reduce dynamic power, catastrophic failure but circuitry for a given introduce uncertainty in
but the lower voltage instead represents a frequency setting. First, supply and signal
values also cause trade-off between the of course, the voltage voltage levels, such as
leakage power to be power penalty incurred must be sufficiently di/dt noise in the supply
reduced. from error correction high to fully evaluate voltage and cross-
4) Dynamic Voltage and the additional the longest circuit coupling noise in logic
and Frequency power savings obtained computation path in a signals. The sum of
Scaling (DVFS) from operating at a single clock cycle. these voltages defines
Modifying the lower supply voltage. Circuit designers the minimum
operating voltage Error-Tolerant DVS typically use static supply voltage that
and/or frequency at circuit-level timing ensures correct circuit
operation in even the As Fig 10 FPGA multiplier block Razor relies on
most adverse shows, the multiplier at 90 MHz and 27°C. a combination of
conditions. circuit fails quite The gradual architectural and
The sum of these gracefully, taking rise in error rate is due circuit-level techniques
voltages defines the nearly 180 mV to go to the dependence for efficient error
minimum supply from the point of the between circuit inputs detection and
voltage that ensures first error (1.54 V) to and evaluation latency. correction of delay path
correct circuit operation an error rate of 1.3 Initially, only circuit failures. Fig 11
in even the most percent (1.36 V). At inputs that require a illustrates the concept
adverse conditions. 1.52 V, the error rate is complete critical-path for a pipeline stage. A
Error rates approximately one reevaluation result in a so-called shadow latch,
Fig 9 illustrates error every 20 seconds timing error. As the controlled by a delayed
the relationship —or one voltage continues to clock, augments each
between voltage and error per 1.8 billion drop, the number of flipflop in the design.
error rates for an 18 × multiply operations. internal multiplier In a given clock cycle,
18-bit Noise margin, circuit paths that cannot if the combinational
Ambient margin, complete within the logic, stage L1, meets
Process margin, clock cycle increases, the setup time for the
Critical voltage along with the error main flip-flop for the
(determined by critical rate. Eventually, clock’s rising edge,
circuit path) ,Worst- voltage drops to the then both the main flip-
case voltage point where none of the flop and the shadow
requirement multiplier circuit paths can latch will latch the
block running with complete in the clock correct data. In this
random input vectors at period, and the error case, the error signal at
90 MHz and 27°C. The rate reaches 100 the XOR gate’s output
error rates are given as percent. Clearly, the remains low, leaving
a percentage on a log worst-case conditions the pipeline’s operation
scale. are highly improbable. unaltered. If
The graph also shows The circuit under test combinational logic L1
two important design Fig 9. Error-rate test for experienced no errors doesn’t complete its
points: 18 × 18-bit multiplier until voltage has computation in time,
• no margin— block. Shaded area in dropped 150 mV (1.54 the main flip-flop will
the lowest the test schematic V) below the full latch an incorrect value,
voltage that can indicates the multiplier margin voltage. If a while the shadow latch
still guarantee circuit under test. processor pipeline can will latch the late-
error-free tolerate a small rate of arriving correct value.
circuit multiplier errors, it can The error signal would
operation at operate with a much then go high,
27°C, and lower supply voltage. prompting restoration
• full margin— For instance, at 330 of the correct value
the voltage at which the mV below the full from the shadow latch
circuit runs without margin voltage (1.36 into the main flip-flop,
errors at 85°C in the V), the multiplier and the correct value
presence of worst-case would complete 98.7 becomes available to
process variation and percent of all stage L2.
signal noise. operations without
Traditional fault- error, for a total energy
avoidance design savings (excluding
methodology sets the error recovery) of 35
circuit voltage at the percent.
full margin point. Fig 10. Measured error Razor error detection
rates for an 18 × 18-bit and correction
 forward progress, subcritical voltage, the
which is essential to flip-flop cannot fail and
avoid perpetual failure doesn’t need
of an instruction at a replacement with a
particular pipeline Razor flip-flop. It is
stage. found that in the
Circuit-level prototype Alpha
implementation issues processor, only 192
Razor-based flip-flops out of 2,408
DVS requires that the required Razor, which
error detection and significantly reduced
correction circuitry’s the Razor approach’s
delay and power power overhead. For
Fig 11: Pipeline stage overhead remain this prototype
augmented with razor minimal during Fig 12: Reduced- processor, the total
latches and control errorfree operation. overhead Razor flip- simulated power
lines. Otherwise, this flop and metastability overhead in error-free
To guarantee circuitry’s power detection circuits. operation (owing to
that the shadow latch overhead would cancel Hence, the Razor flip- Razor flipflops) was
will always latch the out the power savings flop introduces only a less than 1 percent,
input data correctly, from more-aggressive slight increase in the while the delay
designers constrain the voltage scaling. In critical path’s overhead was
allowable operating addition, it’s necessary capacitive loading and negligible. Using a
voltage so that under to minimize error has minimal impact on delayed clock at the
worst-case conditions correction overhead to the design’s shadow latch raises the
the logic delay doesn’t enable efficient performance and possibility that a short
exceed the shadow operation at moderate power. In most cycles, path in the
latch’s setup time. If an error rates. There are a flip-flop’s input will combinational logic
error occurs in stage L1 several methods to not transition, and the will corrupt the data in
during a particular reduce the Razor flip- circuit will incur only the shadow latch. To
clock cycle, the data in flop’s power and delay the power overhead prevent corruption of
L2 during the following overhead, as shown in from switching the the shadow latch data
clock cycle is incorrect Fig 12. The multiplexer delayed clock, thereby by the next cycle’s
and must be flushed at the reducing Razor’s power data, designers add a
from the pipeline. Razor flip-flop’s input overhead. Generating minimum-path-length
However, because the causes a significant the delayed clock constraint at each
shadow latch contains delay and power locally reduces its Razor flip-flop’s input.
the correct output data overhead; therefore, we routing capacitance, These minimum-path
from stage L1, the moved it to the which further constraints result in the
instruction needn’t feedback path of the minimizes additional addition of buffers
reexecute through this main flipflop’s master clock power. Simply during logic synthesis
failing stage. Thus, a latch, as Fig 12 shows. inverting the main to slow down fast
key Razor feature is clock will result in a paths; therefore, they
that if an instruction clock delayed by half introduce a certain
fails in a particular the clock cycle. Also, power overhead. The
pipeline stage, it re- many noncritical flip- minimum-path
executes through the flops in the design constraint is equal to
following pipeline don’t need Razor. If the clock delay tdelay plus
stage while incurring a maximum delay at a the shadow latch’s hold
one-cycle penalty. The flip-flop’s input is time, thold. A large clock
proposed approach guaranteed to meet the delay increases the
therefore guarantees a required cycle time severity of the short-
failing instruction’s under the worst-case path constraint and
therefore increases the input, a Razor flip-flop cycles. When a Razor
power overhead can tolerate any flip-flop generates an
resulting from the need number of errant values error signal, pipeline
for additional buffers. in a single cycle and recovery logic must
On the other hand, a still guarantee forward take two specific
small clock delay progress. If all stages actions. First, it
reduces the margin ail each cycle, the generates a bubble
between the main flip- pipeline will continue signal to nullify the
flop and the shadow to run but at half the computation in the
latch, hence reducing normal speed. In following stage. This
the amount by which aggressively clocked signal indicates to the
designers can drop the designs, implementing next and subsequent
supply voltage below global clock gating can stages that the pipeline
the critical supply significantly impact slot is empty. Second,
voltage. In the Fig 13: Pipeline processor cycle time. recovery logic triggers
prototype 64-bit Alpha recovery using global the flush train by
design, the clock delay clock gating. (a) asserting the ID of the
was half the clock Pipeline organization stage generating the
period. This simplified and (b) pipeline timing error signal. In the
generation of the for an error occurring following cycle, the
delayed clock while in the execute (EX) Razor flip-flop injects
continuing to meet the stage. Asterisks denote the correct value from
short-path constraints, a failing stage the shadow latch data
resulting in a simulated computation. IF = back into the pipeline,
power overhead instruction fetch; ID = allowing the errant
(because of buffers) of instruction decode; instruction to continue
less than 3 percent. MEM = memory; WB with its correct inputs.
Recovering pipeline = writeback. Additionally, the flush
state after timing- Above figure train begins
error detection illustrates pipeline Fig 14: Pipeline propagating the failing
A pipeline recovery using a global recovery using stage’s ID in the
recovery mechanism clock-gating approach. counterflow pipelining. opposite direction of
guarantees that any In the event that any (a) Pipeline instructions. At each
timing failures that do stage detects a timing organization and (b) stage that the active
occur will not corrupt error, pipeline control pipeline timing for an flush train visits, a
the register and logic stalls the entire error occurring in the bubble replaces the
memory state with an pipeline for one cycle execute (EX) stage. pipeline stage. When
incorrect value. There by gating the next Asterisks denote a the flush ID reaches the
are two approaches to global clock edge. The failing stage start of the pipeline, the
recovering pipeline additional clock period computation. IF = flush control logic
state. The first is a allows every stage to instruction fetch; ID = restarts the pipeline at
simple method based recompute its result instruction decode; the instruction
on clock gating, while using the Razor shadow MEM = memory; WB following the failing
the second is a more latch as input. = writeback. instruction. In the event
scalable technique Consequently, recovery Fig 14 that multiple stages
based on counterflow logic replaces any illustrates this generate error signals
pipelining. previously forwarded approach, which places in the same cycle, all
errant values with the negligible timing the stages will initiate
correct value from the constraints on the recovery, but only the
shadow latch. Because baseline pipeline design failing instruction
all stages reevaluate at the expense of closest to the end of the
their result with the extending pipeline pipeline will complete.
Razor shadow latch recovery over a few Later recovery
sequences will flush 1. T. Pering, T. Low ure (MICRO-
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