ZooStorm (Mitac) 8258D PDF

SERVICE MANUAL FOR
8258D
BY: Sanny.Gao
Technical Maintenance Department /GTK MTC
Apr.2006/R01
8258D N/B Maintenance
Contents
1. Hardware Engineering Specification …………………………………………………………………… 4

1.1 Introduction ……………………………………………………………………………………………………………. 4
1.2 System Overview ………………………………………………………………………………………………………. 5
1.3 System Architecture …….…………………………………………………………………………………………….. 8
1.4 ICH7-M Pin Definition ………………………………………………………………………………………………. 17
1.5 Keyboard Controller W83L950G Pin Definition ……..…………………………………………………………….. 19
1.6 Power Consumption of Suspend Mode ………………………………………………………………………………. 22
1.7 Audio Performance ……………………………………………………………………………………………………. 22
1.8 Reference Documents …………………………………………………………………………………………………. 24
1.9 Appendix ……………………………………………………………………………………………………………….. 25
2. System View and Disassembly ………………………………………………………………………….. 29
2.1 System View ……………………………………………………………………………………………………………. 29

2.2 Tools Introduction …………………………………………………………………………………………………..…. 32
2.3 System Disassembly ……………………………………………………………………………………………………. 33
3. Definition & Location of Connectors/Switches ………………………………………………………… 51

3.1 Mother Board ……………………………………………………………………..…………………………………… 51
3.2 Daughter Board ……………………………………...………………………………………………………………… 54
4. Definition & Location of Major Components ………………………………………………………….. 56
4.1 Mother Board …………………………………………………………………………………………………..……… 56
1
Contents
5. Pin Description of Major Component …….……………………………………………………………. 58
5.1 Intel Yonah Processor CPU ……..……………………………………………………………………………………. 58

5.2 Intel 945PM North Bridge ……………………………………………………………………………………………. 63
5.3 Intel ICH7-M South Bridge …………………………………………………………………………………………… 69
6. System Block Diagram …………………………………………………………………………………… 80
7. Maintenance Diagnostics ………………………………………………………………………………… 81
7.1 Introduction ……………………………………………………………………………………………………………. 81

7.2 Maintenance Diagnostics ……………………………………………………………………………………………… 82
7.3 Error Codes ……………………………………………………………………………………………………………. 83
8. Trouble Shooting ………………………………………………………………………………………… 84
8.1 No Power ………………………………………………………………………………………………………………. 86

8.2 No Display ……………………………………………………………………………………………………………… 92
8.3 VGA Controller Failure LCD No Display …………………………………………………………………………… 95
8.4 Memory Test Error ………………………………………….………………………………………………………… 97
8.5 Keyboard (K/B) or Touch Pad (T/P) Test Error ……………..…………………………………………………...… 99
8.6 Hard Disk Drive Test Error ………………………..…………………………………………………………………. 101
8.7 ODD Test Error …………………………………………………………………..……………………………..…….. 103
8.8 USB Port Test Error …………………………………………………………………………………………………… 105
8.9 Audio Test Error ………………………………………………………………………………………..……………... 107
8.10 LAN Test Error ………………………………………………………………………………………..……….…….. 111
2
Contents
8.11 1394 & Card Reader Slot Test Error …………………………………………………………………..………….… 113
8.12 Mini Express (Wireless) Socket Test Error ………………………..…………………………………………….…. 115
8.13 Mini Express (Tuner Card) Socket Test Error ……..………………………………………………………..…...… 117
8.14 Express Card Socket Test Error ……..…………………………………………………………………………….… 119
9. Spare Parts List ………………………………………………………………………………………….. 121
10. System Exploded Views ………………………………………………………………………………... 133
11. Reference Material ………………………………………………………………………………….….. 135
3
1. Hardware Engineering Specification
1.1 Introduction
1.1.1 General Description

The 8258D motherboard is Intel Napa Platform with Mobile Yonah on Intel’s advance 65 nm process technology
with copper interconnect. The processor provides a high-performance low-power mobile processor based on the
Intel Mobile processor architecture.
8258D platform implements Intel945PM / ICH7-M core logic and ATI M56 graphic. The Intel 945PM
chipset-based Memory Controller Hub (MCH) and the Intel 82801GBM I/O Controller Hub 7 Mobile (ICH7-M)
and the ATI M56 is G3 family PCI-Express interface mobile GPU.
The MCH component provides the host interface controller, system memory interface (SDRAM), Direct Media
interface, external graphics interface PCI Express architecture. The ICH7-M integrates a number of I/O device
controllers and interfaces for legacy and high-speed device. The ATI M56 provides PCI-Express I/F support all of
Microsoft DirectX 9.1 enabling next-generation application that require Pixel shader 4X.
4
1.2 System Overview-1
Features
Intel Mobile Yonah Processor with 2 MB L2 cache
CPU Package Micro-FCPGA 479
FSB 533/667 MHz
Chipset North Intel945PM

South ICH7-M
IEEE1394 controller OZ128 (integrated)
Up to 2 GB
Memory Type DDR2 533/667
Slots 2 (DDR2 SO-DIMM 200-pin)
BIOS ROM 512 KB/4 MB Flash EPROM
ATI M56
VRAM Total size support 128 MB/256 MB, 256 MB will be the first priority.
Graphics 15.4" WXGA/WSXGA + wide LCD
controller Resolution: 1280x800 & 1680x1050
LCD 2
1 CCFT typical 185cd/m
16.77 million colors with dithering
Azalia I/F
Codec ALC883
Sound Sound Volume Hot-Key (Fn + F3: Volume down, Fn + F4 : Volume up)
control
Internal Speaker 1.5 W (Main) + 2 W (Woofer)
AMP TPA0212 for R/L and LM4991 for Woofer
KBC W83L950G
5

Continue to the previous page
Memory Card Controller OZ128
LAN/Modem RJ45x1(Left side) / RJ11x1（ Left side)
FDD External USB I/F Option
2.5” Type SATA x 1
HDD I/F
Capacity 60 GB/80 GB/100 GB/120 GB HDD(9.5 mm)5400 rpm
5” Slim Type PATA100 x1
ODD I/F
Device COMBO/DVD Dual, Super Multi (12.7 mm) optical
Mini PCI-E slot Wireless LAN Mini PCI-E Interface IEEE802.11a+b+g
Mini PCI-E slot TV Tuner Card Mini PCI-E Interface
Bluetooth USB Interface
MDC slot Azalia I/F, 56 Kbps(V.90) Fax Modem (MDC)
Card Reader x1 (Front side)
USB USB2.0, Right side x2, Rear side x2
IEEE1394 (4-pin) x1 (Front side)
LAN (RJ45) x1 (Left side)
Line out & S/PDIF x1 combine line out (Front side)
Memory Card Slot x2
External I/O PC Card x1 (Left side), PCI-E Card Bus support
Interface IrDA Consumer IR
x10 IR Receiver x10 MD01 RF Receiver
Line in x1 (stereo, Front side)
Mic In x1 (Mono, Left side), 3/4 voice volume, speaker can't howling
S-video x1(Back side) TV-out (PAL/NTSC) x 1
VGA DVI Port 30-pin (Left side)
DC-in x1 (Rear side)
Switches Power button, LID, ECO Button, Touch pad Left /Right.
6

Switches Power button, LID, ECO Button, Touch pad Left /Right.
US/UK/Japanese keyboard layout(Use the Orignal KBD that other model used)
19 mm key pitch / 3 mm stroke
Hot key spec:
Fn+F1 : Wireless LAN ON/OFF,
Fn+F2 : Bluetooth ON/OFF,
Keyboard
Fn+F3/F4 : Volume down/up,
Fn+F5 : LCD/CRT/TV output change
Fn+F6/F7: Brightness up/down,
Fn+F11: Display ON/OFF,
Fn+F12: Standby
Status LEDs AC/BAT, Charger, HDD/ODD, Num Lock, Caps Lock, WLAN, Bluetooth
Power Management ACPI 2.0
Power supply 90 W Universal AC Adapter (100-240 V)
Li-ion Battery 4800/7200 mAh (6-cell/9-cell)
Battery
Battery Life: 2 hours for 6 cells battery pack
Touch Pad TM61PDM1G214
7
1.3 System Architecture
1.3.1 Function Description
1.3.1.1 CPU
Intel Mobile Yonah processor
• First dual core processor for mobile

• Support Intel architecture with dynamic execution
• On-die, primary 32-KB instruction cache and 32-KB write back data cache
• On-die, 2 MB L2 cache with advanced transfer cache architecture
• Data prefetech logic
• Streaming SIMD Extension 2 (SSE2) and Streaming SIMD Extension 3 (SSE3)
• 533 MHz and 667 MHz, source-synchronous FSB
• Advanced power management features including enhanced Intel Speed-Step technology
• Digital temperature sensor
8
• Micro-FCPGA and Micro-FCBGA package technologies

• Execute disable bit support for enhanced security
1.3.1.2 Core Logic
Intel 945PM
• Host interface supports 533/667 MHz processor system bus support
• Support DDR2 at 533 MHz, 667 MHz and maximum memory supported 2 GB
• PCI Express based graphics interface (one x16 PCI express port)
• Direct Media Interface (DMI)
• 100 MHz differential reference clock (shared by PCI Express Gfx and DMI)
• ACPI 2.0 support
• Package Micro-FCBGA 1446 balls
ICH7-M
• PCI Express interface
9
• PCI 2.3 interface (6 PCI bus master support)

• Serial ATA controller
• Bus master IDE controller
• Direct Media Interface (DMI)
• USB1.1 and 2.0 host controllers
• LAN controller via LAN connect interface (LCI)
• SMBus 2.0 controller
• AC97 2.3 controller
• Azalia controller
• LPC interface
• ACPI 2.0 support
• FWH interface
• RTC
• 652-ball BGA package
10
1.3.1.3 VGA ATI M56
PCI Express interface
Frame buffer memory interface
Integrate dual-link LVDS/TMDS transmitter interface
Digital video output interface
Support turbo cache function
Configurable LVDS/TMDS transmitter interface
Video DACs and PLL analog signal
Power rail interface
1.3.1.4 Memory
• Support DDR2 533/667 MHz SO-DIMM expandable to 2 GB (2 DDR2-SO-DIMM slots)
11
1.3.1.5 I/O Ports
DVI Port
• Standard DVI compatible port
Figure 1-1 DVI connector
7 Pins S-video port for TV-Out
• Support up 1024*768 resolution
• Support PAL and NTSC system
12
RJ-11
• Connection to modem daughter board connector

• Support 56 Kbps/V.92
RJ-45
• The fast Ethernet MAC controller features an IEEE802.3 and IEEE802.3x compliant MAC with external
LAN physical layer chip (BCM4401E/BCM5789) supporting full duplex 10 Base-T, 100 Base-T Ethernet
• Support wake-up on-LAN function in system enter to S3
USB Ports
• Four industry standard USB 2.0 ports (backward compatible to USB 1.1)
• Support maximum transfer rate up to 480 Mbits/s
Card Reader Port
• Integrated EMV smart card reader and 7-in-1 flash Media and SDIO readers
• Support SD, MMC, Memory Stick, Memory Stick Duo, Memory Stick Pro
• 4 in 1 combo connector
13
IEEE 1394a Port
• The bus transfer rate of 100, 200, 400 Mbits/s is supported

• The asynchronous and isochronous data transfers are supported
• One IEEE1394a port supported
Express Card Slot
• One slot supporting the Express card /54
• OZ2710 (Power switch)
• Mixed-and-match 1.5 V/3.3 V Express card
Display
• 15.4” WXGA/WSXGA+ TFT Display; Resolution: 1280x800, 1680x1050
• Dual View of LCD+DVI/LCD+TV independent display

• External Video refresh rate of up to 112 Hz supported
- Vertical refresh frequencies to meet VESA requirements
- Simultaneous video in specified video modes - switchable with hot key
14
IDE Interface
• Support dual independent IDE channels, one is hard disk, the other is optical device
• Supports Ultra ATA 100/66/33, BMIDE and PIO modes
1.3.1.6 Read Only Memory (BIOS Flash FHB)
• Fully compatible with industry standard software including Windows XP home & professional edition
• Fully supports APM V1.2 and latest ACPI specification
• 512 K x 8 (4 Mbits) and 1 M x 8 (8 Mbits) flash BIOS
• Insyde BIOS core
1.3.1.7 Power Management Features
• Local standby mode (individual devices such as HDD, graphics controller, LCD etc..)
• CPU idle mode (including ACPI modes C0, C1, C2, C3 and C4)
• Suspend mode (including S1 and S3 ACPI modes)
• Fully APM-base legacy power

15
• Fully ACPI V1.0band 2.0 compliant
• Hibernate for Windows XP
• Thermal management
1.3.1.8 Keyboard Controller
• Winbond W83L950G
1.3.1.9 7 LEDs Indicator
• AC/BAT & charger & ODD/HDD & NUM Lock & Cap Lock Status & WLAN & Bluetooth
1.3.1.10 Touch Pad Module
• Synaptics TM61PDM1G214
1.3.1.11 CIR
• Support consumer IR
16
1.4 ICH7-M Pin Definitions-1

Pin Name Pin # Mux Function Default Function Power Plane Signal Name Type Operation
GPIO0 AB18 BM_BUSY# GPI 3.3V -PM_BMBUSY INPUT
GPIO1 C08 REQ5# GPI 5V Pull Up INPUT
GPIO2 G08 PIRQE# GPI 5V -PCI_INTE INPUT
GPIO3 F07 PIRQF# GPI 3.3V -PCI_INTF INPUT
GPIO4 F08 PIRQG# GPI 3.3V -PCI_INTG INPUT
GPIO5 G07 PIRQH# GPI 3.3V -PCI_INTH INPUT
GPIO6 AC21 Unmuxed GPI 3.3V Pull Up INPUT
GPIO7 AC18 Unmuxed GPI 3.3V -SCI INPUT
GPIO8 E21 Unmuxed GPI VccSus3_3 -EXTSMI INPUT
GPIO9 E20 Unmuxed GPI VccSus3_3 Pull Up INPUT
GPIO10 A20 Unmuxed GPI VccSus3_3 Pull Up INPUT
GPIO11 B23 SMBALERT# Native VccSus3_3 -SMBALERT INPUT
GPIO12 F19 Unmuxed GPI VccSus3_3 Pull Up INPUT
GPIO13 E19 Unmuxed GPI VccSus3_3 -WAKEUP INPUT
GPIO14 R04 Unmuxed GPI VccSus3_3 MB_ID0 INPUT
GPIO15 E22 Unmuxed GPI VccSus3_3 MB_ID1 INPUT
GPIO16 AC22 GNT6# Native 3.3V DPRSLPVR OUTPOT
GPIO17 D08 GNT5# GPO 3.3V TP OUTPOT
Can not to use. In
STP_PCI#/
mobile this GPO is
GPOI18
AC20 not implemented GPO 3.3V -STOP_PCI OUTPOT
(Desktop
and is used instead
Only)
as STP_PCI#
GPIO19 AH18 SATA1GP GPI 3.3V SPK_OFF INPUT
Can not to use. In
STP_CPU#
mobile this GPO is
/GPIO20
AF21 not implemented GPO 3.3V -STOP_CPU OUTPOT
(DeskTop
and is used instead
Only)
as STP_CPU#
GPIO21 AF19 SATA0GP GPI 3.3V Pull Low INPUT
GPIO22 A13 REQ4# Native 3.3V Pull Up INPUT
GPO23 AA05 LDRQ1# Native 3.3V -ICH_LDRQ1 INPUT
17
1.4 ICH7-M Pin Definitions-2

continue to the previous page
Pin Name Pin # Mux Function Default Function Power Plane Signal Name Type Operation
Unmuxed. Not
GPIO24 R03 cleared by CF9h GPO VccSus3_3 TP OUTPOT
reset event.
GPIO25 D20 Unmuxed. GPO VccSus3_3 TP OUTPOT
GPIO26 A21 EL_RSVD GPO VccSus3_3 TP OUTPOT
GPIO27 B21 EL_STATE0 GPO VccSus3_3 TP OUTPOT
GPIO28 E23 EL_STATE1 GPO VccSus3_3 TP OUTPOT
GPIO29 C03 OC5# Native VccSus3_3 -USBOC5 INPUT
GPIO30 A02 OC6# Native VccSus3_3 -USB_OC6 INPUT
GPIO31 B03 OC7# Native VccSus3_3 -USB_OC7 INPUT
CLKRUN#/ In mobile this GPIO
GPIO32 is not implemented
AG18 GPO 3.3V -CLKRUN OUTPOT
(DeskTop and is used instead
Only) as CLKRUN#
GPIO33 AC19 AZ_DOCK_EN# GPO 3.3V -WLAN_PD OUTPOT
GPIO34 U02 AZ_DOCK_RST# GPO 3.3V ENABKL_SB OUTPOT
GPIO35 AD21 SATACLKREQ# GPO 3.3V -SATACLKREQ OUTPOT
GPIO36 AH19 SATA2GP GPI 3.3V Pull Low INPUT
GPIO37 AE19 SATA3GP GPI 3.3V BT_ON INPUT
GPIO38 AD20 Unmuxed GPI 3.3V -TV_PD INPUT
GPIO39 AE20 Unmuxed GPI 3.3V -KBD_US/JP INPUT
GPIO40 N/A Not Implement N/A N/A N/A
GPIO48 A14 GNT4# Native 3.3V TP OUTPOT
GPIO49 AG24 CPUPWRGD Native V_CPU_IO HPWRGD OUTPOT
18
1.5 Keyboard Controller W83L950G Pin Definitions-1
Pin Port Signal Name Type Connect To Description

39~54 GP17~GP0 KO[0..15] O Internal keyboard Keyboard Matrix
55~62 GP37~GP30 KI[7..0] I Internal keyboard Keyboard Matrix
65~68 GP85~GP82 LAD[0..3] I/O SB ICH7-M LPC BUS
70 GP80 PCI_KBC_CLK I CLKGEN LPC CLK
69 GP81 SERIRQ O SB ICH7-M Serial IRQ
64 GP86 -PCI_RESET I SB ICH7-M LPC Reset
63 GP87 LFRAME# I/O SB ICH7-M LPC FRAME
to turn on VS PWM We use this signal to control "VS" power on/off. HI : ON, LOW :
17 GP50 MAINPWR1 O power plan OFF
15 GP52 SUSB# I SB ICH7-M STR Indicator signal
14 GP53 ADEN# I DC to DC Adaptor in
23 GP42 PWR_ON O DC to DC (+3V,+5V…) Control system power on
22 GP43 CHG_ON O Charger Switch
Connect to South Bridge to system configuration interrupt
19 GP46 SCI O SB ICH7-M (ACPI mode)
3 GP76 KBC_SDA I/O trough 33 ohm to BAT_D SMBUS DATA for LM86 thermal sensor & BATT THERMAL
2 GP77 KBC_SCL I/O trough 33 ohm to BAT_C SMBUS CLK for LM86 thermal sensor BATT THERMAL
27 GP40 -FAN_0 O CPU FAN Control CPU FAN ON & Turn ON/OFF Duty
26 GP41 -ECOBTN_LED O MB TO DB CONN Turn on ECO Function LED Indicate
13 GP54 FAN_SPD I CPU FAN Return FAN (CPU FAN) Speed.
12 GP55 VRMPWRGD I From Vcore Wehen +CPU_CORE power good
16 GP51 -LID_SW I Suspend switch Indicated the battery capacity is not enough to power on system
18 GP47 -NUM_LOCK O LED Keyboard NUMBERl Lock indicator
21 GP44 -RCIN O SB ICH7-M Keyboard Reset for CPURST# gerneration
20 GP45 A20GATE O SB ICH7-M GATE A20 output
9 GP70 T_DATA I/O Touch PAD Connect to touch Pad DATA
8 GP71 LEARNING O Charger Circuit AC and Battery power source switch
19

7 GP72 -SB_PWRBTN O SB ICH7-M Power Button Signal to South Bridge
6 GP73 T_CLK I/O Touch PAD Connect to Touch Pad clock
5 GP74 SB_PWRGD O SB ICH7-M System Power Good
4 GP75 -SUSC I SB ICH7-M System inter S4~S5,Positive Logic.
38 GP20 -AC_LED O LED AC LED Indictor
37 GP21 -WAKE_UP O SB ICH7-M Connect to South Bridge to wake up system
36 GP22 -BATT_G O LED The indicator when battery in charging
35 GP23 -BATT_R O LED The indicator when battery in charging
Connect to South Bridge to system management interrupt (Non-
34 GP24 -EXTSMI O SB ICH7-M
ACPI mode)
33 GP25 -CAP_LOCK O LED Keyboard CAP lock indicator
32 GP26 -SCROLL_LOCK O LED Keyboard Scroll lock indicator
31 GP27 -BAT_LED O LED Battery status indicator
11 GP56 BLADJ O Inverter Back / Light Adjust Control
10 GP57 I_CTR O Charger Circuit Change charger current
1 GP60 -KBC_PWRBTN I Power Button Power Switch Signal to KBC
80 GP61 -ECOBTN_SW I MB TO DB CONN Turn on ECO function
PWR_ON_1.5V/
Connector LDO/SB- TO turn SB +1.5V / to turn SB -RSMRST/turn on
79 GP62 -RSMRST / O
RSMRST/MAINPWR2 +3VS,+1.8VS,+1.2VS,+0.9VS
MAINPWR2
78 GP63 BAT_TEMP I Battery CNN Report Battery Thermal
77 GP64 BAT_VOLT I Battery CNN Report Battery Voltage
76 GP65 I_LIMIT I Connector to Charger For Batt Charge On/off
75 GP66 -IR_POWERBTN I/O From IR reciver IC From remote control power on
Connector Transister for
74 GP67 IR_PWRON O Turn on CIR power
CIR Power turn on
20

28 XIN KBC CLK I Crystal Clock input
29 XOUT KBC CLK O Crystal Clock output
72 VREF +3VA I Voltage KBC Power Vref
71 VCC +3VA I Voltage KBC Power
21
1.6 Power Consumption of Suspend Mode

• Suspend to RAM < 80 mA
• Suspend to Disk/Soft-Off /Mechanical Off < 5 mA
1.7 Audio Performance

• 8258D meets all the following items
Digital Playback (PC-D-A) for Line Output

Test Items Mobile System
Full Scale Output Voltage ≧ 0.7 Vrms (3.3 V audio)
Sample Frequency Accuracy ≦ 0.1%
Frequency Response (44.1 ks/sec) 20 Hz～ 15 KHz
Frequency Response (48 ks/sec) 20 Hz～ 15 KHz
Dynamic Range (SNR) ≧ 70 dBFSA
THD+N ≦ -55 dBFS
Cross-talk ≦ 50 dB
22
Analog Pass-Through (A-A) for Microphone Input to Line Output

Frequency Response 100 Hz～ 12 KHz
THD+N ≦ -50 dBFS
Digital Recording (A-D-PC) for Microphone Input

Full Scale Input Voltage ≧ 100 mVrms
Sample Frequency Accuracy ≦ 0.1%
Frequency Response(22.05ks/sec) 100 Hz～ 8.8 KHz
THD+N ≦ -50 dBFS
23
1.8 Reference Documents
Documents Revision
RS-Mobile Yanah Processor Electrical, Mechanical and Thermal Specification (EMTS) 0.7
RS-Volume 1 of 2 Intel ® 955XM, 945PM/GM and 940GML Express Chipset (Code name Calistoga) 1
External Design Spec
Intel® I/O Controller Hub 7 (ICH7) Family External Design Specification (EDS) – Volume 1 1.5V1
RS-Intel®945G Express Chipset GMCH (Graphics Memory Controller Hub) External Design Specification 1.5
(EDS) Addendum
Mobile Yonah Processor and Intel ®955XM, 945PM/GM and 940GML Express Chipset ( Code Name 0.9
Calistoga)- 8258D Platform DG
RS-Mobile Intel® 945PM/GM/GMS and 945GML Express Chipset External Design Specification (EDS) 1
Volume 1
ATI G3 family Graphic processor for Mobile PCI Express Datasheet (M56) 0.2
ATI G3 family Graphic processor for Mobile PCI Express Design Guide (M56)
PCI7411CardBus and Ultra-Media controller with integrated 1394a-2000 OHCI two ports PHY /Link-layer 2004.Jun
controller with dedicated flash Media socket Data manual
Realtek single chip Fast Ethernet controller with power management. 1.02
PC2001 System Design Guide 0.7
PCI Local Bus Specification 2.2
24
1.9 Appendix
1.9.1 Appendix A: Voltage Identification Definition
25
1.9.2 Appendix B: Frequency Table for FS [2: 0]
CPU PCIEX PCI REF USB DOT

FS LC B6b2 FS LB B6b1 FS LA B6b0 Spread %
(MHz) (MHz) (MHz) (MHz) (MHz) (MHz)
0 0 0 266.66 100.00 33.33 14.318 48.00 96.00 0.5%Down

0 0 0 133.33 100.00 33.33 14.318 48.00 96.00 0.5%Down
0 0 1 200.00 100.00 33.33 14.318 48.00 96.00 0.5%Down
0 0 1 166.66 100.00 33.33 14.318 48.00 96.00 0.5%Down
0 1 0 333.33 100.00 33.33 14.318 48.00 96.00 0.5%Down
0 1 0 100.00 100.00 33.33 14.318 48.00 96.00 0.5%Down
0 1 1 400.00 100.00 33.33 14.318 48.00 96.00 0.5%Down
1 1 1 200.00 100.00 33.33 14.318 48.00 96.00 0.5%Down
26
1.9.3 Appendix C: LCD Cable Pin Definition
• Each differential pair needs meet maximum impedance 100 Ω

• DC impedance have to meet maximum impedance 5 mΩ in each line
QD15TL0201
Signal Name M/B Pin Number LCD Module Pin Number
LCDVCC 1 2
LCDVCC 2 3
PID0 3
PID1 4
GND 5
GND 6 1
TXOUT10- 7 8
TXOUT11- 8 11
TXOUT10+ 9 9
TXOUT11+ 10 12
GND 11 10
GND 12 13
TXOUTCLK1- 13 17
TXOUT12- 14 14
TXOUTCLK1+ 15 18
TXOUT12+ 16 15
GND 17 16
GND 18 19
TXOUT20- 19
TXOUT21- 20
TXOUT20+ 21
TXOUT21+ 22
GND 23
GND 24
TXOUTCLK2- 25
TXOUT22- 26
TXOUTCLK2+ 27
27
TXOUT22+ 28
GND 29
GND 30
LTN154P1-02
LCDVCC 1 2
LCDVCC 2 3
PID0 3
PID1 4/5 short circuit
GND 4/5 short circuit
GND 6 1
TXOUT10- 7 8
TXOUT11- 8 11
TXOUT10+ 9 9
TXOUT11+ 10 12
GND 11 10
GND 12 13
TXOUTCLK1- 13 17
TXOUT12- 14 14
TXOUTCLK1+ 15 18
TXOUT12+ 16 15
GND 17 16
GND 18 19
TXOUT20- 19 20
TXOUT21- 20 23
TXOUT20+ 21 21
TXOUT21+ 22 24
GND 23 22
GND 24 25
TXOUTCLK2- 25 29
TXOUT22- 26 26
TXOUTCLK2+ 27 30
TXOUT22+ 28 27
GND 29 28
GND 30
28
2. System View and Disassembly
2.1 System View
2.1.1 Front View
Top Cover Latch

CIR
Card Reader Connector

IEEE1394 Connector
External MIC In Connector
Line In Connector
Line Out/SPDIF Connector
2.1.2 Left-side View

DVI Connector
Ventilation Openings
RJ11 Connector
RJ45 Connector
Express Card Socket
29
2.1.3 Right-side View
ODD
USB Ports*2

2.1.4 Rear View
Power Connector
TV Connector
S-Video Port

USB Ports*2
Kensington Lock
30
2.1.5 Bottom View

Subwoofer Speaker
Hard Disk Drive
CPU & DDR2 SO-DIMM & Mini
Express Card (Wireless & Tuner Card)
Battery Park

2.1.6 Top-open View

LCD Screen
Stereo Speaker Set

Internal MIC
Device LED Indicators
Touch Pad
Keyboard
○
Power Button

31
2.2 Tools Introduction
1. Minus screw driver for notebook assembly & disassembly.
2 mm
2 mm
2. Auto screw driver for notebook assembly & disassembly.
Bit Size
#0
Screw Size Tooling Tor. Bit Size

1. M2.0 Auto-Screw driver 2.0-2.5 kg/cm2 #0
32
2.3 System Disassembly

The section discusses at length each major component for disassembly/reassembly and show corresponding
illustrations.Use the chart below to determine the disassembly sequence for removing components from the
notebook.
NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the
notebook is not turned on or connected to AC power.
2.3.1 Battery Pack

2.3.2 Keyboard
2.3.3 CPU
Modular Components
2.3.4 HDD Module
2.3.5 ODD
2.3.6 Mini Express (Wireless) Card
NOTEBOOK 2.3.7 DDR2-SDRAM
2.3.8 LCD Assembly
LCD Assembly Components 2.3.9 LCD Panel
2.3.10 Inverter Board
2.3.11 System Board
Base Unit Components
2.3.12 Modem Card
33
2.3.1 Battery Pack

Disassembly
1. Carefully put the notebook upside down.
2. Slide two release lever outwards to the “unlock” ( ) position (), while take the battery pack out of the
compartment (). (Figure 2-1)

Figure 2-1 Remove the battery pack
Reassembly
1. Replace the battery pack into the compartment. The battery pack should be correctly connected when you hear a
clicking sound.
2. Slide the release lever to the “lock” ( ) position.
34
2.3.2 Keyboard
Disassembly
1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Push the rod firmly and slide the easy start buttons cover to the right (). Then lift the easy start buttons cover
up from the left side (). (Figure 2-2)
3. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-3)
Figure 2-2 Remove the keyboard cover Figure 2-3 Remove the keyboard
Reassembly
1. Reconnect the keyboard cable and fit the keyboard back into place.
2. Replace the keyboard cover.
3. Replace the battery pack. (Refer to section 2.3.1 Reassembly)
35
2.3.3 CPU
Disassembly
1. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove eight screws fastening the CPU cover. (Figure 2-4)
3. Remove seven spring screws that secure the heatsink upon the CPU and disconnect the fan’s power cord from
system board. (Figure 2-5)
Figure 2-4 Remove eight screws Figure 2-5 Free the heatsink
36
4. To remove the existing CPU, loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU.
(Figure 2-6)
Figure 2-6 Remove the CPU
Reassembly
1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into
the holes. Tighten the screw by a flat screwdriver to locking the CPU.
2. Connect the fan’s power cord to the system board, fit the heatsink upon the CPU and secure with seven spring
screws.
3. Replace the CPU cover and secure with eight screws.
37
2.3.4 HDD Module

Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove two screws fastening the HDD compartment cover. (Figure 2-7)
3. Remove one screw fastening the HDD module. Slide the HDD module out of the compartment. (Figure 2-8)
Figure 2-7 Remove the HDD Figure 2-8 Remove HDD module
compartment cover
38
4. Remove four screws to separate the hard disk drive from the bracket, remove the hard disk drive. (Figure 2-9)
Figure 2-9 Remove hard disk drive
Reassembly
1. Attach the bracket to hard disk drive and secure with four screws.
2. Slide the HDD module into the compartment and secure with one screw.
3. Place the HDD compartment cover and secure with two screws.
39
2.3.5 ODD
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to section 2.3.1 Disassembly)
2. Remove one screw fastening the ODD. (Figure 2-10)
3. Insert a small rod, such as a straightened paper clip, into ODD’s manual eject hole () and push firmly to
release the tray. Then gently pull out the ODD by holding the tray that pops out (). (Figure 2-10)

Figure 2-10 Remove the ODD
Reassembly
1. Push the ODD into the compartment and secure with one screw.
40
2.3.6 Mini Express (Wireless) Card

Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (Refer to sections 2.3.1 Disassembly)
2. Remove eight screws fastening the wireless card compartment cover. (Figure 2-11)
3. Disconnect the wireless card’s antennae first. Then remove two screws and remove the wireless card.
(Figure 2-12)
Figure 2-11 Remove eight screws Figure 2-12 Remove the wireless card
Reassembly
1. To install the wireless card and secure with two screws. Then make sure that the antennae fully populated.
2. Tighten eight screws to secure the wireless card compartment cover to the housing.
3. Replace the battery pack. (Refer to section 2.3.1 reassembly)
41
2.3.7 DDR2-SDRAM
Disassembly
1. Carefully put the notebook upside down. Remove the battery pack. (See section 2.3.1 Disassembly)
2. Remove eight screws fastening the CPU cover. (Refer to step 2 of section 2.3.3 Disassembly)
Figure 2-13 Remove the SO-DIMM
3. Pull the retaining clips outwards () and remove the SO-DIMM (). (Figure 2-13)
Reassembly
1. To install the DDR2, match the DDR2's notched part with the socket's projected part and firmly insert the
SO-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the DDR2 into
position.
2. Replace the CPU cover and secure with eight screws. (Refer to step 3 of section 2.3.3 Reassembly)
3. Replace the battery pack. (See section 2.3.1 Reassembly)
42
2.3.8 LCD ASSY

Disassembly
1. Remove the battery pack and keyboard. (See sections 2.3.1 and 2.3.2 Disassembly)
2. Remove four screws fastening the CPU cover. (Refer to step 2 of section 2.3.3 Disassembly)
3. Separate the antenna from the system board. (Figure 2-14)
4. Remove two hinge covers, disconnect two cables from the system board then carefully pull the antenna wires out.
(Figure 2-15)
Figure 2-14 Separate the antenna Figure 2-15 Remove two hinge covers
and disconnect two cables
43
5. Remove four screws, then free the LCD assembly. (Figure 2-16)
Figure 2-16 Free the LCD assembly
Reassembly
1. Attach the LCD assembly to the base unit and secure with four screws.
2. Replace the antenna wires back into wireless card compartment.
3. Reconnect three cables to the system board. Then replace two hinge covers.
4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)
44
2.3.9 LCD Panel

Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.8 Disassembly)
2. Remove two screws on the corners of the panel. (Figure 2-17)
3. Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out. Repeat the process
until the cover is completely separated from the housing.
4. Remove six screws and disconnect the cable. (Figure 2-18)
Figure 2-17 Remove LCD cover Figure 2-18 Remove six screws and
disconnect the cable
45
5. Remove eight screws that secure the LCD brackets. (Figure 2-19)
6. Disconnect the cable to free the LCD panel. (Figure 2-20)
Figure 2-19 Remove eight screws Figure 2-20 Free the LCD panel
Reassembly
1. Replace the cable to the LCD panel.
2. Attach the LCD panel’s brackets back to LCD panel and secure with eight screws.
3. Replace the LCD panel into LCD housing and secure with six screws.
4. Reconnect one cable to inverter board.
5. Fit the LCD cover and secure with two screws and rubber pads.
6. Replace the LCD assembly, keyboard and battery pack. (See sections 2.3.8, 2.3.2 and 2.3.1 Reassembly)
46
2.3.10 Inverter Board

Disassembly
1. Remove the battery, keyboard and LCD assembly. (Refer to section 2.3.1, 2.3.2 and 2.3.8 Disassembly)
2. Remove the LCD cover and LCD panel. (Refer to the steps 1-4 of section 2.3.9 Disassembly )
3. Remove three screws fastening the inverter board, then free the inverter board. (Figure 2-21)
Figure 2-21 Free the inverter board
Reassembly
1. Fit the inverter board back into place and secure with three screws.
2. Replace the LCD panel and LCD cover. (Refer to section 2.3.9 Reassembly)
3. Replace the LCD assembly. (Refer to section 2.3.8 Reassembly)
4. Replace the keyboard and battery pack. (Refer to sections 2.3.2 and 2.3.1 Reassembly)
47
2.3.11 System Board

Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, ODD, wireless card, DDR2 and LCD assembly.
(Refer to sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7 and 2.3.8 Disassembly)
2. Remove fifteen screws, disconnect one cable from the touch pad cover. (Figure 2-22)
3. Disconnect the left speaker’s cable and touch pad cable from the system board and remove four screws. Then
free the cover assembly. (Figure 2-23)
Figure 2-22 Remove fifteen Screws Figure 2-23 Disconnect two cables and
remove four screws
48
4. Disconnect one cable and remove four screws. (Figure 2-24)

5. Disconnect two daughter board cables and the subwoofer speaker cable from the system board. Then free the
system board and the daughter board. (Figure 2-25)
Figure 2-24 Disconnect one cable and Figure 2-25 Free the system board
remove four screw
Reassembly
1. Replace the daughter board and the subwoofer speaker back to the system board and reconnect three cables.
2. Replace the system board back into the housing. Then secure with four screws and reconnect one cable.
3. Replace the cover assembly and secure with four screws to fix the system board. Reconnect the left speaker’s
cable and touch pad cable.
4. Turn over the base unit. Secure with fifteen screws and reconnect one cable.
5. Replace the LCD assembly, DDR2, wireless card, ODD, hard disk drive, CPU, keyboard and battery pack.
(Refer to previous section reassembly)
49
2.3.12 Modem Card

Disassembly
1. Remove the battery, keyboard, CPU, hard disk drive, ODD, wireless card, DDR2, LCD assembly and system
board. (Refer to sections 2.3.1, 2.3.2, 2.3.3, 2.3.4, 2.3.5, 2.3.6, 2.3.7, 2.3.8 and 2.3.11Disassembly)
2. Disconnect the cable and remove two screws, then free the modem card. (Figure 2-26)
Figure 2-26 Remove the modem card
Reassembly
1. Replace the modem card back into the system board and secure with two screws, then reconnect the cable.
2. Replace the system board, LCD assembly, DDR2, wireless card, ODD, hard disk drive, CPU, keyboard and
battery pack. (Refer to previous section reassembly)
50
3. Definition & Location of Connectors/Switches
3.1 Mother Board (Side A-1)
J709
J717 J714 PJ701, J707 : MB to DB Connector
J702 J708
J702 : DVI Connector
J704
J704 : Fan Connector
J705 : Battery Connector
J706 : Subwoofer Connector
J708 : MDC Jump Wire Connector
J709 : RJ11 & RJ45 Connector
J710 : ODD Connector
J711, J712 : DDR2 SO-DIMM Socket
J713 : MDC Connector
J705 J711 J712
J707 J714 : Mini Express (Wireless) Connector
J713
PJ701
J706 J715 : SATA HDD Connector
J717 : Mini Express (Tuner Card) Connector
J710
J715
51
3.1 Mother Board (Side A-2)

------ Continued to previous page ------
J718 : 3 In 1 Card Reader Socket

J719 : 1394 Port
J720 : External MIC In Connector
J721 : Line In Connector
J722 : Line Out/SPDIF Connector
J718
J719
J720
J721
J722
52
3.1 Mother Board (Side B)
¾ J1 : LCD Connector
MIC
J8 ¾ J2 : Left Audio Channel Connector
¾ J3 : LCD Inverter Board Connector
J1
J2 ¾ J4 : Internal Keyboard Connector
¾ J6 : Touch Pad Connector
J9 J3
¾ J7 : Blue Tooth Connector
¾ J8 : Express Card Socket
SW1 ¾ J9 : CMOS Battery Connector
¾ SW1 : Touch Pad Left Button

SW2
J6 ¾ SW2 : Touch Pad Right Button
J4
J7
53
3.2 Daughter Board (Side A)
FPJ701 : Power Jack

FPJ701
FJ702 FPDJ701, FJ703 : DB to MB Connector
FJ701
FJ701 : S-Video Port
FJ702, FJ704 : USB Port
FJ704
FJ703
FPDJ701
54
3.2 Daughter Board (Side B)
FJ1 : Right Audio Channel Connector

FSW1
FSW2 FJ1
FSW1 : LID Switch Button
FSW2 : ECO Button
FSW3
FSW3 : Power Switch Button
55
4. Definition & Location of Major Components
4.1 Mother Board (Side A)
U704 : Intel Yonah Processor
U706 : Intel 945P/GM North Bridge

U709
U709 : Graphics Controller ATI M56
U713
U717
U713 : 82573E/82562GZ LAN Controller
U714 : W83L950G Keyboard Controller
U717 : OZ128 Card Reader/1394 Link
Controller
U719
U719 : Intel ICH7-M South Bridge
U722 : Audio Codec ALC260

U704 U706
U714
U722
56
4. Definition & Location of Major Components
4.1 Mother Board (Side B)
¾ U14 : System BIOS
U14
57
5. Pin Descriptions of Major Components
5.1 Intel Yonah Processor CPU (1)

CPU Pin Description CPU Pin Description (Continued)
Signal Name Type Description Signal Name Type Description
A[31:3]# I/O A[31:]#(Address) define a 2*32- byte physical memory address BPM[2:1]# I/O BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance
space. In sub-phase 1 of the address phase, these pins transmit the BPM[3,0]# monitor signals. They are outputs from the processor that indicate the
address of a transaction. Must connect the appropriate pins of both status of breakpoints and programmable counters used for monitoring
agents on the Intel Core TM Duo processor and the Intel Core TM processor performance. BPM[3:0]# should connect the appropriate
Solo processor FSB. A[31:3]# are source synchronous signals and are pins of all Intel Pentium M processor system bus agents. This
latched into the receiving buffers by ADSTB[1:0]#. Address signals includes debug or performance monitoring tools.
are used as straps which are sampled before RESET# is deasserted. BPRI# I BPRI# (Bus Priority Request) is used to arbitrate for ownership of the
A20M# I If A20M#(Address-20 Mask) is asserted, the processor masks processor system bus. It must connect the appropriate pins of both
physical address bit 20(A20#) before looking up a line in any internal processor system bus agents. Observing BPRI# active (as asserted by
cache and before driving a read/write transaction on the bus. the priority agent) causes the other agent to stop issuing new requests,
Asserting A20M# emulates the 8086 processor’s address wrap-around unless such requests are part of an ongoing locked operation. The
at the 1-Mbyte boundary. Assertion of A20M# is only supported in priority agent keeps BPRI# asserted until all of its requests are
real mode. completed, then releases the bus by deasserting BPRI#.
A20M# is an asynchronous signal. However, to ensure recognition of BR0# I/O BR0# is used by the processor to request the bus. The arbitration is
this signal following an Input/Output write instruction, it must be done between the Intel Pentium M processor (Symmetric Agent) and
valid along with the TRDY# assertion of the corresponding the Mobile Intel 945 Express chipset family (High Priority Agent).
Input/Output Write bus transaction. BSEL[2:0] O BSEL[2:0] (Bus SELECT) are used to select the processor input
ADS# I/O ADS#(Address Strobe) is asserted to indicate the validity of the clock frequency. The table defines the possible combinations of the
transaction address on the A[31:3]# and REQ[4:0]# pins. All bus signals and the frequency associated with each combination. The
agents observe the ADS# activation to begin parity checking, protocol required frequency is determined by the processor, chipset and clock
checking, address decode, internal snoop, or deferred reply ID match synthesizer. All agents must operate at the same frequency. The
operations associated with the new transaction. processor operates at 667 MHz or 533 MHz system bus frequency
ADSTB# I/O Address strobes are used to latch A[31:3]# and REQ[4:0]# on their (166MHz or 133MHz BCLK[1:0] frequency, respectively).
rising and falling edges. Strobes are associated with signals as shown BSE[2:0] Encoding for BCLK Frequency
below. BCLK
BSEL[2] BSEL[1] BSE[0]
Signals Associated Strobe Frequency
REQ[4:0]#, A[16:3]# ADSTB[0]# L L L Reserved
A[31:17]# ADSTB[1]# L L H 133MHz
BCLK[1:0] I The differential pair BCLK (Bus Clock) determines the system bus L H L Reserved
frequency. All processor system bus agents must receive these signals L H H 166MHz
to drive their outputs and latch their inputs. COMPP3:0] Analog COMP[3:0] must be terminated on the system board using precision
BNR# I/O BNR# (Block Next Request) is used to assert a bus stall by any bus (1% tolerance) resistors. Refer to the platform design guides for more
agent that is unable to accept new bus transactions. During a bus stall, implementation details.
the current bus owner cannot issue any new transactions.
58

CPU Pin Description (Continued) CPU Pin Description (Continued)
D[63:0]# I/O D[63:0]# (Data) are the data signals. These signals provide a 64-bit DINV[3:0]# I/O DINV[3:0]# (Data Bus Inversion) are source synchronous and
data path between the processor system bus agents, and must connect indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals
the appropriate pins on both agents. The data driver asserts DRDY# are activated when the data on the data bus is inverted. The bus agent
to indicate a valid data transfer. will invert the data bus signals if more than half the bits, within the
D[63:0]# are quad-pumped signals and will thus be driven four covered group, would change level in the next cycle.
times in a common clock period. D[63:0]# are latched off the falling DINV[3:0]# Assignment To Data Bus
edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 Bus Signal Data Bus Signals
data signals correspond to a pair of one DSTBP# and one DSTBN#. DINV[3]# D[63:48]#
The following table shows the grouping of data signals to data DINV[2]# D[47:32]#
strobes and DINV#. DINV[1]# D[31:16]#
Quad-Pumped Signal Groups DINV[0]# D[15:0]#
Data Group DSTBN#/DSTBP# DINV# DPRSTP# I DPRSTP# when asserted on the platform causes the processor to
D[15:0]# 0 0 transition from the Deep Sleep State to the Deeper Sleep Stated. In
D[31:16]# 1 1 order to return to the Deep Sleep State, DPRSTP# must be deasserted.
D[47:32]# 2 2 DPRSTP# is driven by the Intel ICH7M chipset.
D[63:48]# 3 3 DPSLP# I DPSLP# when asserted on the platform causes the processor to
Furthermore, the DINV# pins determine the polarity of the data transition from the Sleep state to the Deep Sleep state. In order to
signals. Each group of 16 data signals corresponds to one DINV# return to the Sleep state, DPSLP# must be deasserted. DPSLP# is
signal. When the DINV# signal is active, the corresponding data driven by the ICH7M chipset.
group is inverted and therefore sampled active high. DRDY# I/O DRDY# (Data Ready) is asserted by the data driver on each data
DBR# O DBR# (Data Bus Reset) is used only in processor systems where no transfer, indicating valid data on the data bus. In a multi-common
debug port is implemented on the system board. DBR# is used by a clock data transfer, DRDY# may be deasserted to insert idle clocks.
debug port interposer so that an in-target probe can drive system This signal must connect the appropriate pins of both processor
reset. If a debug port is implemented in the system, DBR# is a no system bus agents.
connect. DBR# is not a processor signal. DSTBN[3:0]# I/O Data strobe used to latch in D[63:0]#.
DBSY# I/O DBSY# (Data Bus Busy) is asserted by the agent responsible for Signals Associated Strobe
driving data on the processor system bus to indicate that the data bus D[15:0]#, DINV[0]# DSTBN[0]#
is in use. The data bus is released after DBSY# is deasserted. This D[31:16]#, DINV[1]# DSTBN[1]#
signal must connect the appropriate pins on both processor system D[47:32]#, DINV[2]# DSTBN[2]#
bus agents. D[63:48]#, DINV[3]# DSTBN[3]#
DEFER# I DEFER# is asserted by an agent to indicate that a transaction cannot
be guaranteed in-order completion. Assertion of DEFER# is normally
the responsibility of the addressed memory or Input/Output agent.
This signal must connect the appropriate pins of both processor
system bus agents.
59

DSTBP[3:0]# I/O Data strobe used to latch in D[63:0]#. IGNNE# I IGNNE# (Ignore Numeric Error) is asserted to force the processor to
Signals Associated Strobe ignore a numeric error and continue to execute noncontrol
D[15:0]#, DINV[0]# DSTBP[0]# floating-point instructions. If IGNNE# is deasserted, the processor
D[31:16]#, DINV[1]# DSTBP[1]# generates an exception on a noncontrol floating-point instruction if a
D[47:32]#, DINV[2]# DSTBP[2]# previous floating-point instruction caused an error. IGNNE# has no
D[63:48]#, DINV[3]# DSTBP[3]# effect when the NE bit in control register 0 (CR0) is set.
FERR#/PBE# O FERR# (Floating-point Error)/PBE#(Pending Break Event) is a IGNNE# is an asynchronous signal. However, to ensure recognition
multiplexed signal and its meaning is qualified by STPCLK#. When of this signal following an Input/Output write instruction, it must be
STPCLK# is not asserted, FERR#/PBE# indicates a floating point valid along with the TRDY# assertion of the corresponding
when the processor detects an unmasked floating-point error. FERR# Input/Output Write bus transaction.
is similar to the ERROR# signal on the Intel 80387 coprocessor, and INIT# I INIT#(Initialization), when asserted, resets integer registers inside the
is included for compatibility with systems using MS-DOS* type processor without affecting its internal caches or floating-point
floating-point error reporting. When STPCLK# is asserted, an registers, The processor then begins execution at the power-on Reset
assertion of FERR#/PBE# indicates that the processor has a pending vector configured during power-on configuration. The processor
break event waiting for service. The assertion of FERR#/PBE# continues to handle snoop requests during INIT# assertion. INIT# is
indicates that the processor should be returned to the Normal state. an asynchronous signal. However, to ensure recognition of this signal
When FERR#/PBE# is asserted, indicating a break event, it will following an Input/Output Write Instruction, it must be valid along
remain asserted until STPCLK# is deasserted. Assertion of PREQ# with the TRDY# assertion of the corresponding Input/Output Write
when STPCLK# is active will also cause an FERR# break event. bus transaction, INIT# must connect the appropriate pins of both FSB
For additional information on the pending break event functionality, agents.
including identification of support of the feature and enable/disable If INIT# is sampled active on the active to inactive transition of
RESET#, then the processor executes its Built-in Selt-Test(BIST).
information, refer to Volume 3 of the Intel Architecture Software
Developer’s Manual and AP-485, For termination requirements LINT[1:0] I LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins
please contact your Intel representative. of all APIC Bus agents. When the APIC is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1
GTLREF I GTLREF determines the signal reference level for AGTL+ input pins.
becomes NMI, a nonmaskable interrupt. INTR and NMI are
GTLREF should be set at 2/3 VCCP . GTLREF is used by the
backward compatible with the signals of those names on the Pentium
AGTL+ receivers to determine if a signal is a logical 0 or logical
processor. Both signals are asynchronous.
1.Plese contact your Intel representative for more information
Both of these signals must be software configured using BIOS
regarding GTLREF implementation.
programming of the APIC register space and used either as
HIT# I/O HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction
NMI/INTR or LINT[1:0]. Because the APIC is enabled by default
HITM# I/O snoop operation results. Either system bus agent may assert both
after Reset, operation of these pins as LINT[1:0] is the default
HIT# and HITM# together to indicate that it requires a snoop stall,
configuration.
which can be continued by reasserting HIT# and HITM# together.
LOCK# I/O LOCK# indicates to the system that a transaction must occur
IERR# O IERR# (Internal Error) is asserted by a processor as the result of an
atomically. This signal must connect the appropriate pins of both
internal error. Assertion of IERR# is usually accompanied by a
processor system bus agents. For a locked sequence of transactions,
SHUTDOWN transaction on the processor system bus. This LOCK# is asserted from the beginning of the first transaction to the
transaction may optionally be converted to an external error signal end of the last transaction.
(e.g., NMI) by system core logic. The processor will keep IERR#
asserted until the assertion of RESET#, BINIT#, or INIT#.
60

LOCK# I/O When the priority agent asserts BPRI# to arbitrate for ownership of RESET# I On observing active RESET#, both system bus agents will deassert
the processor system bus, it will wait until it observes LOCK# their outputs within two clocks. All processor straps must be valid
deasserted. This enables symmetric agents to retain ownership of the within the specified setup time before RESET# is deasserted.
processor system bus throughout the bus locked operation and ensure There is a 55 (normal) on die pull up resistor on this signal.
the atomicity of lock. RS[2:0]# I RS[2:0]# (Response Status) are driven by the response agent (the
PRDY# O Probe Ready signal used by debug tools to determine processor debug agent
readiness. responsible for completion of the current transaction), and must
PREQ# I Probe Request signal used by debug tools to request debug operation connect the appropriate pins of both processor system bus agents.
of the processor. RSVD Reserved/ These pins are RESERVED and must be left unconnected on the
PROCHOT# I/O As an output, PROCHOT# (Processor Hot) will go active when the No Connect board.
processor temperature monitoring sensor detects that the processor However, it is recommended that routing channels to these pins on
has reached its maximum safe operating temperature. This indicates the board be kept open for possible future use. Please refer to the
that the processor Thermal Control Circuit has been activated, if platform design guides for more details.
enabled. As an input, assertion of PROCHOT# by the system will SLP# I SLP# (Sleep), when asserted in Stop-Grant state, causes the processor
activate the TCC, if enabled. TCC will remain active until the system to enter the Sleep state. During Sleep state, the processor stops
deasserts PRCCHOT#. providing internal clock signals to all units, leaving only the
By default PROCHOT# is configured as an output only. Bidirectional Phase-Locked Loop (PLL) still operating. Processors in this state will
PROCHOT# must be enabled via the BIOS. not recognize snoops or interrupts. The processor will recognize only
This signal may require voltage translation on the motherboard. assertion of the RESET# signal, deassertion of SLP#, and removal of
PSI# O Processor Power Status Indicator signal. This signal is asserted when the BCLK input while in Sleep state. If SLP# is deasserted, the
the processor is in a lower state (HFM and LFM) and lower state processor exits Sleep state and returns to Stop-Grant state, restarting
(Deep Sleep and Deeper Sleep). its internal clock signals to the bus and processor core units. If
PWRGOOD I PWRGOOD (Power Good) is a processor input. The processor DPSLP# is asserted while in the Sleep state, the processor will exit
requires this signal as a clean indication that the clocks and power the Sleep state and transition to the Deep Sleep state.
supplies are stable and within their specifications. ‘Clean’ implies that SMI# I SMI# (System Management Interrupt) is asserted asynchronously by
the signal will remain low (capable of sinking leakage current), system logic. On accepting a System Management Interrupt, the
without glitches, from the time that the power supplies are turned on processor saves the current state and enter System Management Mode
until they come within specification. The signal must then transition (SMM). An SMI Acknowledge transaction is issued, and the
monotonically to a high state. processor begins program execution from the SMM handler.
The PWRGOOD signal must be supplied to the processor; it is used If SMI# is asserted during the deassertion of RESET# the processor
to protect internal circuits against voltage sequencing issues. It should will tristate its outputs.
be driven high throughout the boundary scan operation. STPCLK# I STPCLK# (Stop Clock), when asserted, causes the processor to enter
REQ[4:0] I/O REQ[4:0]#(Request Command) must connect the appropriate pins of a low power Stop-Grant state. The processor issues a Stop-Grant
both FSB agents. They are asserted by the current bus owner to the Acknowledge transaction, and stops providing internal clock signals
currently active transaction type. These signals are source to all processor core units except the system bus and APIC units. The
synchronous to ADSTB[0]#. processor continues to snoop bus transactions and service interrupts
RESET# I Asserting the RESET# signal resets the processor to a known state while in Stop-Grant state. When STPCLK# is deasserted, the
and invalidates its internal caches without writing back any of their processor restarts its internal clock to all units and resumes execution.
contents. For a power-on Reset, RESET# must stay active for at least The assertion of STPCLK# has no effect on the bus clock; STPCLK#
two milliseconds after VCC and BCLK have reached their proper is an asynchronous input.
specifications.
61

TCK I TCK (Test Clock) provides the clock input for the processor Test Bus Vsssense O Vsssense together with Vccsense are voltage feedback signals to
(also known as the Test Access Port). IMVP6 that control the 2.1m loadline at the processor die. It should
TDI I TDI (Test Data In) transfers serial test data into the processor. TDI be used to sense ground near the silicon with little noise.
provides the serial input needed for JTAG specification support.
TDO O TDO (Test Data Out) transfers serial test data out of the processor.
TDO
provides the serial output needed for JTAG specification support.
TEST1, I TEST1 must have a stuffing option of separate pull down resistor to
Vss.
TEST2 I TEST2 must have a 51±5% pull down resistor to Vss.
THERMDA Other Thermal Diode Anode.
THERMDC Other Thermal Diode Cathode.
THERMTRIP# O The processor protects itself from catastrophic overheating by use of
an internal thermal sensor. This sensor is set well above the normal
operating temperature to ensure that there are no false trips. The
processor will stop all execution when the junction temperature
exceeds approximately 125°C. This is signalled to the system by the
THERMTRIP# (Thermal Trip) pin.
TMS I TMS (Test Mode Select) is a JTAG specification support signal used
by debug tools.
TRDY# I TRDY# (Target Ready) is asserted by the target to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY#
must connect the appropriate pins of both FSB agents.
TRST# I TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST#
must be driven low during power on Reset.
Vcc I Processor core power supply.
Vcca I Vcca provides isolated power for the internal processor core PLL’s.
Vccp I Processor I/O Power Supply.
VID[6:0] O VID[6:0] (Voltage ID) pins are used to support automatic selection of
power supply voltages (Vcc). Unlike some previous generations of
processors, these are CMOS signals that are driven by the Intel
Pentium M processor. The voltage supply for these pins must be valid
before the VR can supply Vcc to the processor. Conversely, the VR
output must be disabled until the voltage supply for the VID pins
becomes valid. The VID pins are needed to support the processor
voltage specification variations. The VR must supply the voltage that
is requested by the pins, or disable itself.
62
5.2 Intel 945PM North Bridge (1)

Host Interface Signals Host Interface Signals (Continued)
HADS# I/O Address Strobe: HDRDY# I/O Data Ready:
GTL+ The processor bus owner asserts HADS# to indicate the first of two GTL+ This signal is asserted for each cycle that data is transferred.
cycles of a request phase. The (G)MCH can assert this signal for HEDRDY# O Early Data Ready:
snoop cycles and interrupt messages. GTL+ This signal indicates that the data phase of a read transaction will start
HBNR# I/O Block Next Request: on the bus exactly one common clock after assertion.
GTL+ HBNR# is used to block the current request bus owner from issuing HDINV[3:0]# I/O Dynamic Bus Inversion:
new requests. This signal is used to dynamically control the processor GTL+ These signals are driven along with the HD[63:0] signals. They
bus pipeline depth. indicate if the associated signals are inverted or not.
HBPRI# O Priority Agent Bus Request: HDINV[3:0]# are asserted such that the number of data bits driven
GTL+ The (G)MCH is the only Priority Agent on the processor bus. It electrically low (low voltage) within the corresponding 16 bit group
asserts this signal to obtain the ownership of the address bus. This never exceeds 8..
signal has priority over symmetric bus requests and will cause the HDINV[x]# Data Bits
current symmetric owner to stop issuing new transactions unless the HDINV3# HD[63:48]
HLOCK# signal was asserted. HDINV2# HD[47:32]
HBREQ0# I/O Bus Request 0: HDINV1# HD[31:16]
GTL+ The (G)MCH pulls the processor’s bus HBREQ0# signal low during HDINV0# HD[15:0]
HCPURST#. The processor samples this signal on the HA[31:3]# I/O Host Address Bus:
active-toinactive transition of HCPURST#. The minimum setup time GTL+ HA[31:3]# connect to the processor address bus.
for this signal is 4 HCLKs. The minimum hold time is 2 HCLKs and During processor cycles, the HA[31:3]# are inputs. The (G)MCH
the maximum hold time is 20 HCLKs. HBREQ0# should be tristated drives HA[31:3]# during snoop cycles on behalf of DMI and PCI
after the hold time requirement has been satisfied. Express* initiators.
HCPURST# O CPU Reset: HA[31:3]# are transferred at 2x rate.
GTL+ The HCPURST# pin is an output from the (G)MCH. The (G)MCH HADSTB[1:0]# I/O Host Address Strobe:
asserts HCPURST# while RSTIN# is asserted and for approximately GTL+ These signals are the source synchronous strobes used to transfer
1 ms after RSTIN# is de-asserted. The HCPURST# allows the HA[31:3]# and HREQ[4:0] at the 2x transfer rate.
processors to begin execution in a known state. HD[63:0]# I/O Host Data:
Note that the Intel® ICH7 must provide processor frequency select GTL+ These signals are connected to the processor data bus. Data on
strap setup and hold times around HCPURST#. This requires strict HD[63:0] is transferred at 4x rate. Note that the data signals may be
synchronization between (G)MCH HCPURST# de-assertion and the inverted on the processor bus, depending on the HDINV[3:0]#
ICH7 driving the straps. signals.
HDBSY# I/O Data Bus Busy: HHIT# I/O Hit:
GTL+ This signal is used by the data bus owner to hold the data bus for GTL+ This signal indicates that a caching agent holds an unmodified version
transfers requiring more than one cycle. of the requested line. In addition, HHIT# is driven in conjunction with
HDEFER# O Defer: HHITM# by the target to extend the snoop window.
GTL+ HDEFER# indicates that the (G)MCH will terminate the transaction
currently being snooped with either a deferred response or with a
retry response.
63

Host Interface Signals (Continued) Host Interface Signals (Continued)
HDSTBP[3:0]# I/O Differential Host Data Strobes: HTRDY# O Host Target Ready:
HDSTBN[3:0]# GTL+ These signals are the differential source synchronous strobes used to GTL+ This signal indicates that the target of the processor transaction is able
transfer HD[63:0]# and HDINV[3:0]# at 4x transfer rate. to enter the data transfer phase.
These signals are named this way because they are not level sensitive. HRS[2:0]# O Host Response Status:
Data is captured on the falling edge of both strobes. Hence they are GTL+ These signals indicate the type of response as shown below:
pseudo-differential, and not true differential. 000 = Idle state
Strobe Data Bits 001 = Retry response
HDSTBP3#, HDSTBN3# HD[63:48] HDINV3# 010 = Deferred response
HDSTBP2#, HDSTBN2# HD[47:32] HDINV2# 011 = Reserved (not driven by (G)MCH)
HDSTBP1#, HDSTBN1# HD[31:16] HDINV1# 100 = Hard Failure (not driven by (G)MCH)
HDSTBP0#, HDSTBN0# HD[15:00] HDINV0# 101 = No data response
HHITM# I/O Hit Modified: 110 = Implicit Write back
GTL+ This signal indicates that a caching agent holds a modified version of 111 = Normal data response
the requested line and that this agent assumes responsibility for BSEL[2:0] I Bus Speed Select:
providing the line. In addition, HHITM# is driven in conjunction with COMS At the de-assertion of RSTIN#, the value sampled on these pins
HHIT# to extend the snoop window. determines the expected frequency of the bus.
HLOCK# I/O Host Lock: HRCOMP I/O Host RCOMP:
GTL+ All processor bus cycles sampled with the assertion of HLOCK# COMS This signal is used to calibrate the Host GTL+ I/O buffers.
and HADS#, until the negation of HLOCK# must be atomic (i.e., no This signal is powered by the Host Interface termination rail (VTT).
DMI or PCI Express accesses to DRAM are allowed when HLOCK# HSCOMP I/O Slew Rate Compensation:
is asserted by the processor). COMS This is the compensation signal for the Host Interface.
HPCREQ# I Precharge Request: HSWING I Host Voltage Swing:
GTL+ The processor provides a “hint” to the (G)MCH that it is OK to close A This signal provides the reference voltage used by FSB RCOMP
2X the DRAM page of the memory read request with which the hint is circuits. HSWING is used for the signals handled by HRCOMP.
associated. The (G)MCH uses this information to schedule the read HDVREF I Host Reference Voltage:
request to memory using the special “AutoPrecharge” attribute. This A Voltage input for the data, address, and common clock signals of the
causes the DRAM to immediately close (Precharge) the page after the Host GTL interface.
read data has been returned. This allows subsequent processor HACCVREF I Host Reference Voltage:
requests to more quickly access information on other DRAM pages, A Reference voltage input for the Address, and Common clock signals
since it will no longer be necessary to close an open page prior to of the Host GTL interface.
opening the proper page. Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
HPCREQ# is asserted by the requesting agent during both halves of voltage of the Host Bus (VTT).
Request Phase. The same information is provided in both halves of
the request phase.
HREQ[4:0]# I/O Host Request Command:
GTL+ These signals define the attributes of the request. HREQ[4:0]# are
2X transferred at 2x rate. They are asserted by the requesting agent
during both halves of Request Phase. In the first half, the
signals define the transaction type to a level of detail that is sufficient
to begin a snoop request. In the second half, the signals carry
additional information to define the complete transaction type.
64

DDR2 DRAM Channel A Interface DDR2 DRAM Channel A Interface (Continued)
SCLK_A[5:0] O SDRAM Differential Clock: SDQS_A[7:0]# I/O Data Strobe Complements:
SSTL-1.8 (3 per DIMM). SCLK_Ax and its complement SCLK_Ax# signal SSTL-1.8 These are the complementary DDR2 strobe signals.
make a differential clock pair output. The crossing of the positive 2X
edge of SCLK_Ax and the negative edge of its complement SCKE_A[3:0] O Clock Enable:
SCLK_Ax# are used to sample the command and control signals on SSTL-1.8 (1 per Rank). SCKE_Ax is used to initialize the SDRAMs during
the SDRAM. power-up, to power-down SDRAM ranks, and to place all SDRAM
SCLK_A[5:0]# O SDRAM Complementary Differential Clock: ranks into and out of self-refresh during Suspend-to-RAM.
SSTL-1.8 (3 per DIMM). These are the complementary Differential DDR2 SODT_A[3:0] O On Die Termination:
Clock signals. SSTL-1.8 Active On-die Termination Control signals for DDR2 devices.
SCS_A[3:0]# O Chip Select:
SSTL-1.8 (1 per Rank). These signals select particular SDRAM components
during the active state. There is one chip select for each SDRAM
rank.
SMA_A[13:0] O Memory Address: DDR2 DRAM Channel B Interface
SSTL-1.8 These signals are used to provide the multiplexed row and column Signal Name Type Description
address to the SDRAM. SCLK_B[5:0] O SDRAM Differential Clock:
SBS_A[2:0] O Bank Select: SSTL-1.8 (3 per DIMM). SCLK_Bx and its complement SCLK_Bx# signal
SSTL-1.8 These signals define which banks are selected within each SDRAM make a differential clock pair output. The crossing of the positive
rank. edge of SCLK_Bx and the negative edge of its complement
DDR2: 1-Gb technology is 8 banks. SCLK_Bx# are used to sample the command and control signals on
SRAS_A# O Row Address Strobe: the SDRAM.
SSTL-1.8 This signal is used with SCAS_A# and SWE_A# (along with SCLK_B[5:0]# O SDRAM Complementary Differential Clock:
SCS_A#) to define the SDRAM commands. SSTL-1.8 (3 per DIMM). These are the complementary Differential DDR2
SCAS_A# O Column Address Strobe: Clock signals.
SSTL-1.8 This signal is used with SRAS_A# and SWE_A# (along with SCS_B[3:0]# O Chip Select:
SCS_A#) to define the SDRAM commands. SSTL-1.8 (1 per Rank). These signals select particular SDRAM components
SWE_A# O Write Enable: during the active state. There is one chip select for each SDRAM
SSTL-1.8 This signal is used with SCAS_A# and SRAS_A# (along with rank.
SCS_A#) to define the SDRAM commands. SMA_B[13:0] O Memory Address:
SDQ_A[63:0] I/O Data Lines: SSTL-1.8 These signals are used to provide the multiplexed row and column
SSTL-1.8 The SDQ_A[63:0] signals interface to the SDRAM data bus. address to the SDRAM.
2X SBS_B[2:0] O Bank Select:
SDM_A[7:0] O Data Mask: SSTL-1.8 These signals define which banks are selected within each SDRAM
SSTL-1.8 When activated during writes, the corresponding data groups in rank.
2X the SDRAM are masked. There is one SDM_Ax bit for every data DDR2: 1-Gb technology is 8 banks.
byte lane. SRAS_B# O Row Address Strobe:
SDQS_A[7:0] I/O Data Strobes: SSTL-1.8 This signal is used with SCAS_B# and SWE_B# (along with
SSTL-1.8 For DDR2, SDQS_Ax and its complement SDQS_Ax# signal SCS_B#) to define the SDRAM commands.
2X make up a differential strobe pair. The data is captured at the crossing
point of SDQS_Ax and its complement SDQS_Ax# during read and
write transactions.
65

DDR2 DRAM Channel B Interface (Continued) Analog Display Signals (Intel® 82945G GMCH Only)
SCAS_B# O Column Address Strobe: RED O RED Analog Video Output:
SSTL-1.8 This signal is used with SRAS_B# and SWE_B# (along with A This signal is a CRT Analog video output from the internal color
SCS_B#) to define the SDRAM commands. palette DAC. The DAC is designed for a 37.5 Ω routing impedance;
SWE_B# O Write Enable: however, the terminating resistor to ground will be 75 Ω (e.g., 75
SSTL-1.8 This signal is used with SCAS_B# and SRAS_B# (along with
Ω resistor on the board, in parallel with a 75 Ω CRT load).
SCS_B#) to define the SDRAM commands.
RED# O REDB Analog Output:
SDQ_B[63:0] I/O Data Lines:
A This signal is an analog video output from the internal color palette
SSTL-1.8 The SDQ_B[63:0] signals interface to the SDRAM data bus.
DAC. It should be shorted to the ground plane.
2X
GREEN O GREEN Analog Video Output:
SDM_B[7:0] O Data Mask:
A This signal is a CRT Analog video output from the internal color
SSTL-1.8 When activated during writes, the corresponding data groups in
2X the SDRAM are masked. There is one SDM_Bx bit for every data palette DAC. The DAC is designed for a 37.5 Ω routing impedance:
byte lane. however, the terminating resistor to ground will be 75 Ω (e.g., 75
SDQS_B[7:0] I/O Data Strobes: Ω resistor on the board, in parallel with a 75 ΩCRT load).
SSTL-1.8 For DDR2, SDQS_Bx and its complement SDQS_Bx# signal GREEN# O GREENB Analog Output:
2X make up a differential strobe pair. The data is captured at the crossing A This signal is an analog video output from the internal color palette
point of SDQS_Bx and its complement SDQS_Bx# during read and DAC. It should be shorted to the ground plane.
write transactions. BLUE O BLUE Analog Video Output:
SDQS_B[7:0]# I/O Data Strobe Complements: A This signal is a CRT Analog video output from the internal color
SSTL-1.8 These are the complementary DDR2 strobe signals. palette DAC. The DAC is designed for a 37.5 Ω routing impedance;
2X however, the terminating resistor to ground will be 75 Ω (e.g., 75
SCKE_B[3:0] O Clock Enable:
Ω resistor on the board, in parallel with a 75 Ω CRT load).
SSTL-1.8 (1 per Rank). SCKE_Bx is used to initialize the SDRAMs during
power-up, to power-down SDRAM ranks, and to place all SDRAM BLUE# O BLUEB Analog Output:
ranks into and out of self-refresh during Suspend-to-RAM. A This signal is an analog video output from the internal color palette
SODT_B[3:0] O On Die Termination: DAC. It should be shorted to the ground plane.
SSTL-1.8 Active On-die Termination Control signals for DDR2 devices. REFSET O Resistor Set:
A Set point resistor for the internal color palette DAC. A 255 Ω 1%
resistor is required between REFSET and motherboard ground.
HSYNC O CRT Horizontal Synchronization:
PCI Express* Interface Signals 2.5V This signal is used as the horizontal sync (polarity is programmable)
Signal Name Type Description CMOS or “sync interval”. 2.5 V output.
EXP_RXN[15:0] I/O PCI Express* Receive Differential Pair VSYNC O CRT Vertical Synchronization:
EXP_RXP[15:0] PCIE 2.5V This signal is used as the vertical sync (polarity is programmable). 2.5
EXP_TXN[15:0] O CMOS V output.
PCI Express* Transmit Differential Pair
EXP_TXP[15:0] PCIE DDC_CLK I/O Monitor Control Clock:
2.5V This signal may be used as the DDC_CLK for a secondary
EXP_ICOMPO I PCI Express* Output Current and Resistance Compensation
A CMOS multiplexed digital display connector.
EXP_COMPI I DDC_DATA I/O Monitor Control Data:
PCI Express* Input Current Compensation
2.5V This signal may be used as the DDC_Data for a secondary
A
CMOS multiplexed digital display connector.
Unless otherwise specified, PCI Express signals are AC coupled, so the only voltage specified is a
maximum 1.2 V differential swing.
66

Clock, Reset, and Miscellaneous Clock, Reset, and Miscellaneous (Continued)
HCLKP I Differential Host Clock In: XORTEST I/O XOR Test:
HCLKN HCSL These pins receive a differential host clock from the external clock GTL+ This signal is used for Bed of Nails testing by OEMs to execute XOR
synthesizer. This clock is used by all of the (G)MCH logic Chain test.
that is in the Host clock domain. Memory domain clocks are also LLLZTEST I/O All Z Test:
derived from this source. GTL+ As an input this signal is used for Bed of Nails testing by OEMs to
GCLKP I Differential PCI Express* Clock In: execute XOR Chain test. It is used as an output for XOR chain
GCLKN HCSL These pins receive a differential 100 MHz Serial Reference clock testing.
from the external clock synthesizer. This clock is used to generate the
clocks necessary for the support of PCI Express.
DREFCLKN I Display PLL Differential Clock In
DREFCLKP HCSL
RSTIN# I Reset In:
HVIN When asserted, this signal will asynchronously reset the (G)MCH DDR2 DRAM Reference and Compensation
logic. This signal is connected to the PCIRST# output of the Intel® Signal Name Type Description
ICH7. All PCI Express graphics attach output signals will also
SRCOMP[1:0] I/O System Memory RCOMP
tri-state compliant to PCI Express* Specification, Revision 1.0a.
This input should have a Schmitt trigger to avoid spurious resets. SOCOMP[1:0] I/O DDR2 On-Die DRAM Over Current Detection (OCD) Driver
This signal is required to be 3.3 V tolerant. A Compensation
PWROK I Power OK: SMVREF[1:0] I SDRAM Reference Voltage:
HVIN When asserted, PWROK is an indication to the (G)MCH that core A These signals are reference voltage inputs for each SDQ_x, SDM_x,
power has been stable for at least 10 us. SDQS_x, and SDQS_x# input signals.
EXTTS# I External Thermal Sensor Input:
CMOS This signal may connect to a precision thermal sensor located on or
near the DIMMs. If the system temperature reaches a dangerously
high value, then this signal can be used to trigger the start of system
thermal management. This signal is activated when an increase in
temperature causes a voltage to cross some threshold in the sensor. Direct Media Interface (DMI)
EXP_EN I PCI Express SDVO Concurrent Select: Signal Name Type Description
CMOS 0 = Only SDVO or PCI Express operational DMI_RXP[3:0] I/O Direct Media Interface:
1 = SDVO and PCI Express operating simultaneously via PCI DMI_RXN[3:0] DMI These signals are receive differential pairs (Rx).
Express port DMI_TXP[3:0] O Direct Media Interface:
NOTES: For the 82945P MCH, this signal should be pulled low. DMI_TXN[3:0] DMI These signals are transmit differential pairs (Tx).
EXP_SLR I PCI Express* Lane Reversal/Form Factor Selection:
CMOS (G)MCH’s PCI Express lane numbers are reversed to differentiate
Balanced Technology Extended (BTX) or ATX form factors.
0 = (G)MCH’s PCI Express lane numbers are reversed (BTX
Platforms)
1 = Normal operation (ATX Platforms)
ICH_SYNC# O ICH Sync:
HVCMOS This signal is connected to the MCH_SYNCH# signal on the ICH7.
67

Intel® Serial DVO (SDVO) Interface (Intel® 82945G GMCH Only) Intel® Serial DVO (SDVO) Interface (Intel® 82945G GMCH Only)
Signal Name Type Description (Continued)
SDVOB_CLK- O Serial Digital Video Channel B Clock Complement: Signal Name Voltage Description
PCIE This signal is multiplexed with EXP_TXN12. SDVOB_INT+ I Serial Digital Video Input Interrupt:
SDVOB_CLK+ O Serial Digital Video Channel B Clock Clock: PCIE This signal is multiplexed with EXP_RXP14.
PCIE This signal is multiplexed with EXP_TXP12. SDVOC_INT- I Serial Digital Video Input Interrupt Complement:
SDVOB_RED- O Serial Digital Video Channel C Red Complement: PCIE This signal is multiplexed with EXP_RXN10.
PCIE This signal is multiplexed with EXP_TXN15. SDVOC_INT+ I Serial Digital Video Input Interrupt:
SDVOB_RED+ O Serial Digital Video Channel C Red: PCIE This signal is multiplexed with EXP_RXP10.
PCIE This signal is multiplexed with EXP_TXP15. SDVO_STALL- I Serial Digital Video Filed Stall Complement:
SDVOB_GREEN O Serial Digital Video Channel B Green Complement: PCIE This signal is multiplexed with EXP_RXN13.
- PCIE This signal is multiplexed with EXP_TXN14. SDVO_STALL+ I Serial Digital Video Filed Stall:
SDVOB_GREEN O Serial Digital Video Channel B Green: PCIE This signal is multiplexed with EXP_RXP13.
+ PCIE This signal is multiplexed with EXP_TXP14. SDVO_CTRLCL I/O Serial Digital Video Device Control Clock.
SDVOB_BLUE- O Serial Digital Video Channel B Blue Complement: K COD
PCIE This signal is multiplexed with EXP_TXN13. SDVO_CTRLDA I/O Serial Digital Video Device Control Data.
SDVOB_BLUE+ O Serial Digital Video Channel B Blue: TA COD
PCIE This signal is multiplexed with EXP_TXP13.
SDVOC_RED-/ O Serial Digital Video Channel C Red Complement Channel B
SDVOB_ALPHA PCIE Alpha Complement:
- This signal is multiplexed with EXP_TXN11.
SDVOC_RED+/ O Serial Digital Video Channel C Red Complement Channel B Power and Ground
SDVOB_ALPHA PCIE Alpha: Name Voltage Description
+ This signal is multiplexed with EXP_TXP11. VCC 1.5V Core Power
SDVOC_GREEN O Serial Digital Video Channel C Green Complement: VTT 1.2V Processor System Bus Power
- PCIE This signal is multiplexed with EXP_TXN10. VCC_EXP 1.5V PCI Express* and DMI Power
SDVOC_GREEN O Serial Digital Video Channel C Green:
+ PCIE This signal is multiplexed with EXP_TXP10. VCCSM 1.8V System Memory Power
SDVOC_BLUE- O Serial Digital Video Channel C Blue Complement: VCC2 2.5V 2.5V COMS Power
PCIE This signal is multiplexed with EXP_TXN9. VCCA_EXPPL 1.5V PCI Express PLL Analog Power
SDVOC_BLUE+ O Serial Digital Video Channel C Blue: L
PCIE This signal is multiplexed with EXP_TXP9. VCCA_DPLLA 1.5V Display PLL A Analog Power
SDVOC_CLK- O Serial Digital Video Channel C Clock Complement: (GMCH
PCIE This signal is multiplexed with EXP_TXN8. ONLY)
SDVOC_CLK+ O Serial Digital Video Channel C Clock: VCCA_DPLLB 1.5V Display PLL B Analog Power
PCIE This signal is multiplexed with EXP_TXP8. (GMCH
SDVO_TVCLKI I Serial Digital Video TV-OUT Synchronization Clock ONLY)
N- PCIE Complement: VCCA_HPLL 1.5V Host PLL Analog Power
This signal is multiplexed with EXP_RXN15. VCCA_SMPLL 1.5V System Memory PLL Analog Power
SDVO_TVCLKI I Serial Digital Video TV-OUT Synchronization Clock: VCCA_DAC 2.5V Display DAC Analog Power
N+ PCIE This signal is multiplexed with EXP_RXP15.
VSS 0V Ground
SDVOB_INT- I Serial Digital Video Input Interrupt Complement:
PCIE This signal is multiplexed with EXP_RXN14. VSSA_DAC 0V Ground
68
5.3 Intel ICH7-M South Bridge (1)

PCI Interface Signals PCI Interface Signals (Continued)
Signal Name Type Description Name Type Description
IRDY# I/O Initiator Ready: AD[31:0] I/O PCI Address/Data:
IRDY# indicates the ICH7's ability, as an initiator, to complete the AD[31:0] is a multiplexed address and data bus. During the first clock
current data phase of the transaction. It is used in conjunction with of a transaction, AD[31:0] contain a physical address (32 bits).
TRDY#. A data phase is completed on any clock both IRDY# and During subsequent clocks, AD[31:0] contain data. The Intel® ICH7
TRDY# are sampled asserted. During a write, IRDY# indicates the will drive all 0s on AD[31:0] during the address phase of all PCI
ICH7 has valid data present on AD[31:0]. During a read, it indicates Special Cycles.
the ICH7 is prepared to latch data. IRDY# is an input to the ICH7 C/BE[3:0]# I/O Bus Command and Byte Enables:
when the ICH7 is the target and an output from the ICH7 when the The command and byte enable signals are multiplexed on the same
ICH7 is an initiator. IRDY# remains tri-stated by the ICH7 until PCI pins. During the address phase of a transaction, C/BE[3:0]#
driven by an initiator. define the bus command. During the data phase C/BE[3:0]# define
TRDY# I/O Target Ready: the Byte Enables.
TRDY# indicates the Intel® ICH7's ability as a target to complete the C/BE[3:0]# Command Type
current data phase of the transaction. TRDY# is used in conjunction 0000b Interrupt Acknowledge
with IRDY#. A data phase is completed when both TRDY# and 0001b Special Cycle
IRDY# are sampled asserted. During a read, TRDY# indicates that 0010b I/O Read
the ICH7, as a target, has placed valid data on AD[31:0]. During a 0011b I/O Write
write, TRDY# indicates the ICH7, as a target is prepared to latch data. 0110b Memory Read
TRDY# is an input to the ICH7 when the ICH7 is the initiator and an 0111b Memory Write
output from the ICH7 when the ICH7 is a target. TRDY# is tri-stated 1010b Configuration Read
from the leading edge of PLTRST#. TRDY# remains tri-stated by the 1011b Configuration Write
ICH7 until driven by a target. 1100b Memory Read Multiple
STOP# I/O Stop: 1110b Memory Read Line
STOP# indicates that the ICH7, as a target, is requesting the initiator 1111b Memory Write and Invalidate
to stop the current transaction. STOP# causes the ICH7, as an All command encodings not shown are reserved. The ICH7 does not
initiator, to stop the current transaction. STOP# is an output when the decode reserved values, and therefore will not respond if a PCI master
ICH7 is a target and an input when the ICH7 is an initiator. generates a cycle using one of the reserved values.
PAR I/O Calculated/Checked Parity: DEVSEL# I/O Device Select:
PAR uses “even” parity calculated on 36 bits, AD[31:0] plus The ICH7 asserts DEVSEL# to claim a PCI transaction. As an output,
C/BE[3:0]#. “Even” parity means that the ICH7 counts the number of the ICH7 asserts DEVSEL# when a PCI master peripheral attempts
one within the 36 bits plus PAR and the sum is always even. The an access to an internal ICH7 address or an address destined DMI
ICH7 always calculates PAR on 36 bits regardless of the valid byte (main memory or graphics). As an input, DEVSEL# indicates the
enables. The ICH7 generates PAR for address and data phases and response to an ICH7-initiated transaction on the PCI bus. DEVSEL#
only guarantees PAR to be valid one PCI clock after the is tri-stated from the leading edge of PLTRST#. DEVSEL# remains
corresponding address or data phase. The ICH7 drives and tristates tri-stated by the ICH7 until driven by a target device.
PAR identically to the AD[31:0] lines except that the ICH7 delays FRAME# I/O Cycle Frame:
PAR by exactly one PCI clock. PAR is an output during the address The current initiator drives FRAME# to indicate the beginning and
phase (delayed one clock) for all ICH7 initiated transactions. PAR is duration of a PCI transaction. While the initiator asserts FRAME#,
an output during the data phase (delayed one clock) when the ICH7 is data transfers continue. When the initiator negates FRAME#, the
the initiator of a PCI write transaction, and when it is the target of a transaction is in the final data phase. FRAME# is an input to the
read transaction. ICH7 checks parity when it is the target of a PCI ICH7 when the ICH7 is the target, and FRAME# is an output from
write transaction. If a parity error is detected, the ICH7 will set the the ICH7 when the ICH7 is the initiator. FRAME# remains tristated
appropriate internal status bits, and has the option to generate an by the ICH7 until driven by an initiator.
NMI# or SMI#.
69

PCI Interface Signals (Continued) Serial ATA Interface Signals
Signal Name Type Description Name Type Description
PERR# I/O Parity Error: SATA0TXP O Serial ATA 0 Differential Transmit Pair:
An external PCI device drives PERR# when it receives data that has a SATA0TXN These are outbound high-speed differential signals to Port 0.
parity error. The ICH7 drives PERR# when it detects a parity error. SATA0RXP I Serial ATA 0 Differential Receive Pair:
The ICH7 can either generate an NMI# or SMI# upon detecting a SATA0RXN These are inbound high-speed differential signals from Port 0.
parity error (either detected internally or reported via the PERR# SATA1TXP O Serial ATA 1 Differential Transmit Pair:
signal). SATA1TXN These are outbound high-speed differential signals to Port 1.
REQ[0:3]# I PCI Requests: SATA1RXP I Serial ATA 1 Differential Receive Pair:
REQ[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The REQ[4]# and SATA1RXN These are inbound high-speed differential signals from Port 1.
GPIO22 REQ5# pins can instead be used as a GPIO.
SATA2TXP O Serial ATA 2 Differential Transmit Pair:
REQ[5]#/GPIO1
SATA2TXN These are outbound high-speed differential signals to Port 2.
GNT[0:3]# O PCI Grants:
SATA2RXP I Serial ATA 2 Differential Receive Pair:
GNT[4]#/ The ICH7 supports up to 6 masters on the PCI bus. The GNT4# and
SATA2RXN These are inbound high-speed differential signals from Port 2.
GPIO48 GNT5# pins can instead be used as a GPIO. Pull-up resistors are not
GNT[5]#/ required on these signals. If pull-ups are used, they should be tied to SATA3TXP O Serial ATA 3 Differential Transmit Pair:
GPIO17# the Vcc3_3 power rail. GNT5#/GPIO17 has an internal pull-up. SATA3TXN These are outbound high-speed differential signals to Port 3.
PCICLK I NOTE: PCI Clock: SATA3RXP I Serial ATA 3 Differential Receive Pair:
This is a 33 MHz clock. PCICLK provides timing for all transactions SATA3RXN These are inbound high-speed differential signals from Port 3.
on the PCI Bus. SATARBIAS O Serial ATA Resistor Bias:
PCIRST# O PCI Reset: These are analog connection points for an external resistor to ground.
This is the Secondary PCI Bus reset signal. It is a logical OR of the SATARBIAS# I Serial ATA Resistor Bias Complement:
primary interface PLTRST# signal and the state of the Secondary Bus These are analog connection points for an external resistor to ground.
Reset bit of the Bridge Control register (D30:F0:3Eh, bit 6). SATA0GP/ I Serial ATA 0 General Purpose:
PLOCK# I/O PCI Lock: GPIO21 This is an input pin which can be configured as an interlock switch
This signal indicates an exclusive bus operation and may require corresponding to SATA Port 0. When used as an interlock switch
multiple transactions to complete. The ICH7 asserts PLOCK# when it status indication, this signal should be drive to ‘0’ to indicate that the
performs non-exclusive transactions on the PCI bus. PLOCK# is switch is closed and to ‘1’ to indicate that the switch is open.
ignored when PCI masters are granted the bus in desktop If interlock switches are not required, this pin can be configured as
configurations. GPIO21.
SERR# I/OD System Error: SATA1GP/ I Serial ATA 1 General Purpose:
SERR# can be pulsed active by any PCI device that detects a system GPIO19 Same function as SATA0GP, except for SATA Port 1.
error condition. Upon sampling SERR# active, the ICH7 has the If interlock switches are not required, this pin can be configured as
ability to generate an NMI, SMI#, or interrupt. GPIO19.
PME# I/OD PCI Power Management Event: SATA2GP/ I Serial ATA 2 General Purpose:
PCI peripherals drive PME# to wake the system from low-power GPIO36 Same function as SATA0GP, except for SATA Port 2.
states S1–S5. PME# assertion can also be enabled to generate an SCI If interlock switches are not required, this pin can be configured as
from the S0 state. In some cases the ICH7 may drive PME# active GPIO36.
due to an internal wake event. The ICH7 will not drive PME# high,
but it will be pulled up to VccSus3_3 by an internal pull-up resistor.
70

Serial ATA Interface Signals (Continued) Platform LAN Connect Interface Signals
Name Type Description Name Type Description
SATA3GP/ I Serial ATA 3 General Purpose: LAN_CLK I LAN I/F Clock:
GPIO37 Same function as SATA0GP, except for SATA Port 3. This signal is driven by the Platform LAN Connect component. The
If interlock switches are not required, this pin can be configured as frequency range is 5 MHz to 50 MHz.
GPIO37. LAN_RXD[2:0] I Received Data:
SATALED# OC Serial ATA LED: The Platform LAN Connect component uses these signals to transfer
This is an open-collector output pin driven during SATA command data and control information to the integrated LAN controller. These
activity. It is to be connected to external circuitry that can provide the signals have integrated weak pull-up resistors.
current to drive a platform LED. When active, the LED is on. When LAN_TXD[2:0] O Transmit Data:
tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is The integrated LAN controller uses these signals to transfer data and
required. control information to the Platform LAN Connect component.
NOTE: An internal pull-up is enabled only during PLTRST# LAN_RSTSYNC O LAN Reset/Sync:
assertion. The Platform LAN Connect component’s Reset and Sync signals are
SATACLKREQ OD Serial ATA Clock Request: multiplexed onto this pin.
#/GPIO35 (Native)/ This is an open-drain output pin when configured as
I/O (GP) SATACLKREQ#. It is to connect to the system clock chip. When
active, request for SATA Clock running is asserted. When tri-stated,
it tells the Clock Chip that SATA Clock can be stopped. An external
pull-up resistor is required.
Other Clock
Name Type Description
CLK14 I Oscillator Clock:
This clock is used for 8254 timers. It runs at 14.31818 MHz. This
Serial Peripheral Interface (SPI) Signals clock is permitted to stop during S3 (or lower) states.
Name Type Description CLK48 I 48 MHz Clock:
This clock is used to run the USB controller. Runs at 48.000 MHz.
SPI_CS# I/O SPI Chip Select:
This clock is permitted to stop during S3 (or lower) states.
Also used as the SPI bus request signal.
SATA_CLKP I 100 MHz Differential Clock:
SPI_MISO I SPI Master IN Slave OUT:
SATA_CLKN These signals are used to run the SATA controller at 100 MHz. This
Data input pin for Intel® ICH7.
clock is permitted to stop during S3/S4/S5 states.
SPI_MOSI O SPI Master OUT Slave IN:
DMI_CLKP, I 100 MHz Differential Clock:
Data output pin for ICH7.
DMI_CLKN These signals are used to run the Direct Media Interface. Runs at 100
SPI _ARB I SPI Arbitration:
MHz.
SPI arbitration signal is used to arbitrate the SPI bus with Intel PRO
82573E Gigabit Ethernet Controller when Shared Flash is
implemented.
SPI_CLK O SPI Clock:
SPI clock signal, during idle the bus owner will drive the clock signal
low. 17.86 MHz.
71

IDE Interface Signals IDE Interface Signals (Continued)
DCS1# O IDE Device Chip Selects for 100 Range: DIOW#/ O Disk I/O Write (PIO and Non-Ultra DMA):
For ATA command register block. This output signal is connected to (DSTOP) This is the command to the IDE device that it may latch data from the
the corresponding signal on the IDE connector. DD lines. Data is latched by the IDE device on the deassertion edge
DCS3# O IDE Device Chip Select for 300 Range: of DIOW#. The IDE device is selected either by the ATA register file
For ATA control register block. This output signal is connected to the chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA
corresponding signal on the IDE connector. acknowledge (DDAK#).
DA[2:0] O IDE Device Address: Disk Stop (Ultra DMA): ICH7 asserts this signal to terminate a burst.
These output signals are connected to the corresponding signals on IORDY/ I I/O Channel Ready (PIO):
the IDE connector. They are used to indicate which byte in either the (DRSTB/ This signal will keep the strobe active (DIOR# on reads, DIOW# on
ATA command block or control block is being addressed. WDMARDY#) writes) longer than the minimum width. It adds wait-states to PIO
DD[15:0] I/O IDE Device Data: transfers.
These signals directly drive the corresponding signals on the IDE Disk Read Strobe (Ultra DMA Reads from Disk): When reading from
connector. There is a weak internal pull-down resistor on DD7. disk, ICH7 latches data on rising and falling edges of this signal from
DDREQ I IDE Device DMA Request: the disk.
This input signal is directly driven from the DRQ signal on the IDE Disk DMA Ready (Ultra DMA Writes to Disk): When writing to
connector. It is asserted by the IDE device to request a data transfer, disk, this is deasserted by the disk to pause burst data transfers.
and used in conjunction with the PCI bus master IDE function and are
not associated with any AT compatible DMA channel. There is a
weak internal pulldown resistor on this signal.
DDACK# O IDE Device DMA Acknowledge:
This signal directly drives the DAK# signal on the IDE connector. System Management Interface Signals
DDACK# is asserted by the Intel® ICH7 to indicate to IDE DMA
slave devices that a given data transfer cycle (assertion of DIOR# or
DIOW#) is a DMA data transfer cycle. This signal is used in INTRUDER# I Intruder Detect:
conjunction with the PCI bus master IDE function and are not This signal can be set to disable system if box detected open.
associated with any AT-compatible DMA channel. This signal’s status is readable, so it can be used like a GPIO if the
DIOR#/ O DIOR# /Disk I/O Read (PIO and Non-Ultra DMA): Intruder Detection is not needed.
(DWSTB/ This is the command to the IDE device that it may drive data onto the SMLINK[1:0] I/OD System Management Link:
RDMARDY#) DD lines. Data is latched by the ICH7 on the deassertion edge of SMBus link to optional external system management ASIC or LAN
DIOR#. The IDE device is selected either by the ATA register file controller. External pull-ups are required. Note that SMLINK0
chip selects (DCS1# or DCS3#) and the DA lines, or the IDE DMA corresponds to an SMBus Clock signal, and SMLINK1 corresponds
acknowledge (DDAK#). to an SMBus Data signal.
Disk Write Strobe (Ultra DMA Writes to Disk): This is the data write LINKALERT# I/OD SMLink Alert:
strobe for writes to disk. When writing to disk, ICH7 drives valid data Output of the integrated LAN and input to either the integrated ASF
on rising and falling edges of DWSTB. or an external management controller in order for the LAN’s
Disk DMA Ready (Ultra DMA Reads from Disk): This is the DMA SMLINK slave to be serviced.
ready for reads from disk. When reading from disk, ICH7 deasserts
RDMARDY# to pause burst data transfers.
72

USB Interface Signals EEPROM Interface Signals
USBP0P, I/O Universal Serial Bus Port [1:0] Differential: EE_SHCLK O EEPROM Shift Clock:
USBP0N, These differential pairs are used to transmit Data/Address/Command Serial shift clock output to the EEPROM.
USBP1P, signals for ports 0 and 1. These ports can be routed to UHCI EE_DIN I EEPROM Data In:
USBP1N controller #1 or the EHCI controller. Transfers data from the EEPROM to the Intel® ICH7. This signal
NOTE: No external resistors are required on these signals. The Intel® has an integrated pull-up resistor.
ICH7 integrates 15 kΩ pull-downs and provides an output driver EE_DOUT O EEPROM Data Out:
impedance of 45 Ω which requires no external series resistor. Transfers data from the ICH7 to the EEPROM.
USBP2P, I/O Universal Serial Bus Port [3:2] Differential: EE_CS O EEPROM Chip Select:
USBP2N, These differential pairs are used to transmit data/address/command Chip select signal to the EEPROM.
USBP3P, signals for ports 2 and 3. These ports can be routed to UHCI
USBP3N controller #2 or the EHCI controller.
NOTE: No external resistors are required on these signals. The ICH7
integrates 15 KΩ ?pull-downs and provides an output driver
impedance of 45 Ω which requires no external series resistor.
Interrupt Signals
USBP4P, I/O Universal Serial Bus Port [5:4] Differential: Name Type Description
USBP4N, These differential pairs are used to transmit Data/Address/Command
USBP5P, signals for ports 4 and 5. These ports can be routed to UHCI SERIRQ I/O Serial Interrupt Request:
USBP5N controller #3 or the EHCI controller. This pin implements the serial interrupt protocol.
NOTE: No external resistors are required on these signals. The ICH7 PIRQ[D:A]# I/OD PCI Interrupt Requests:
integrates 15 KΩ?pull-downs and provides an output driver In non-APIC mode the PIRQx# signals can be routed to interrupts 3,
impedance of 45 Ω which requires no external series resistor. 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering
section. Each PIRQx# line has a separate Route Control register.
USBP6P, I/O Universal Serial Bus Port [7:6] Differential:
In APIC mode, these signals are connected to the internal I/O APIC in
USBP6N, These differential pairs are used to transmit Data/Address/Command
the following fashion: PIRQA# is connected to IRQ16, PIRQB# to
USBP7P, signals for ports 6 and 7. These ports can be routed to UHCI
IRQ17, PIRQC# to IRQ18, and PIRQD# to IRQ19. This frees the
USBP7N controller #4 or the EHCI controller.
legacy interrupts.
NOTE: No external resistors are required on these signals. The ICH7
PIRQ[H:E]#/ I/OD PCI Interrupt Requests:
integrates 15 KΩ?pull-downs and provides an output driver
GPIO[5:2] In non-APIC mode the PIRQx# signals can be routed to interrupts 3,
impedance of 45 Ω which requires no external series resistor. 4, 5, 6, 7, 9, 10, 11, 12, 14 or 15 as described in the Interrupt Steering
OC[4:0]# I Overcurrent Indicators: section. Each PIRQx# line has a separate Route Control register.
OC5#/GPIO29 These signals set corresponding bits in the USB controllers to indicate In APIC mode, these signals are connected to the internal I/O APIC in
OC6#/GPIO30 that an overcurrent condition has occurred. the following fashion: PIRQE# is connected to IRQ20, PIRQF# to
OC7#/GPIO31 OC[7:4]# may optionally be used as GPIOs. IRQ21, PIRQG# to IRQ22, and PIRQH# to IRQ23. This frees the
NOTE: OC[7:0]# are not 5 V tolerant. legacy interrupts. If not needed for interrupts,
USBRBIAS O USB Resistor Bias: these signals can be used as GPIO.
Analog connection point for an external resistor. Used to set transmit IDEIRQ I IDE Interrupt Request:
currents and internal load resistors. This interrupt input is connected to the IDE drive.
USBRBIAS# I USB Resistor Bias Complement:
Analog connection point for an external resistor. Used to set transmit
currents and internal load resistors.
73

Power Management Interface Signals Power Management Interface Signals (Continued)
PWRBTN# I Power Button: SUSCLK O Suspend Clock:
The Power Button will cause SMI# or SCI to indicate a system This clock is an output of the RTC generator circuit to use by other
request to go to a sleep state. If the system is already in a sleep state, chips for refresh clock.
this signal will cause a wake event. If PWRBTN# is pressed for more RSMRST# I Resume Well Reset:
than 4 seconds, this will cause an unconditional transition (power This signal is used for resetting the resume power plane logic.
button override) to the S5 state. Override will occur even if the VRMPWRGD I VRM Power Good:
system is in the S1-S4 states. This signal has an internal pullup This should be connected to be the processor’s VRM Power Good
resistor and has an internal 16 ms de-bounce on the input. signifying the VRM is stable. This signal is internally ANDed with
RI# I Ring Indicate: the PWROK input.
This signal is an input from a modem. It can be enabled as a wake PLTRST# O Platform Reset:
event, and this is preserved across power failures. The Intel® ICH7 asserts PLTRST# to reset devices on the platform
SYS_RESET# I System Reset: (e.g., SIO, FWH, LAN, (G)MCH, IDE, TPM, etc.). The ICH7 asserts
This pin forces an internal reset after being debounced. The ICH7 will PLTRST# during power-up and when S/W initiates a hard reset
reset immediately if the SMBus is idle; otherwise, it will wait up to sequence through the Reset Control register (I/O Register CF9h). The
25 ms ± 2 ms for the SMBus to idle before forcing a reset on the ICH7 drives PLTRST# inactive a minimum of 1 ms after both
system. PWROK and VRMPWRGD are driven high. The ICH7 drives
LAN_RST# I LAN Reset: PLTRST# active a minimum of 1 ms when initiated through the Reset
When asserted, the internal LAN controller will be put into reset. This Control register (I/O Register CF9h).
signal must be asserted for at least 10 ms after the resume well power NOTE: PLTRST# is in the VccSus3_3 well.
(VccSus3_3 and VccSus1_5) is valid. When de-asserted, this signal is SLP_S3# O S3 Sleep Control:
an indication that the resume well power is stable. SLP_S3# is for power plane control. This signal shuts off power to all
NOTE: LAN_RST# should be tied to RSMEST#. non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to
WAKE# I PCI Express* Wake Event: Disk), or S5 (Soft Off) states.
Sideband wake signal on PCI Express asserted by components SLP_S4# O S4 Sleep Control:
requesting wakeup. SLP_S4# is for power plane control. This signal shuts power to all
MCH_SYNC# I MCH SYNC: non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft
This input is internally ANDed with the PWROK input. Off) state.
Connected to the ICH_SYNC# output of (G)MCH. NOTE: This pin must be used to control the DRAM power to use the
THRM# I Thermal Alarm: ICH7’s DRAM power-cycling feature. Refer to Chapter 5.14.10.2 for
Active low signal generated by external hardware to generate an details.
SMI# or SCI. SLP_S5# O S5 Sleep Control:
THRMTRIP# I Thermal Trip: SLP_S5# is for power plane control. This signal is used to shut power
When low, this signal indicates that a thermal trip from the processor off to all non-critical systems when in the S5 (Soft Off) states.
occurred, and the ICH7 will immediately transition to a S5 state. The PWROK I Power OK:
ICH7 will not wait for the processor stop grant cycle since the When asserted, PWROK is an indication to the ICH7 that core power
processor has overheated. has been stable for 99 ms and that PCICLK has been stable for 1 ms.
SUS_STAT#/ O Suspend Status: An exception to this rule is if the system is in S3HOT, in which
LPCPD# This signal is asserted by the ICH7 to indicate that the system will be PWROK may or may not stay asserted even though PCICLK may be
entering a low power state soon. This can be monitored by devices inactive. PWROK can be driven asynchronously. When PWROK is
with memory that need to switch from normal refresh to suspend negated, the ICH7 asserts PLTRST#.
refresh mode. It can also be used by other peripherals as an indication NOTE: PWROK must deassert for a minimum of three RTC clock
that they should isolate their outputs that may be going to periods for the ICH7 to fully reset the power and properly generate
powered-off planes. This signal is called LPCPD# on the LPC I/F. the PLTRST# output.
74

Processor Interface Signals Processor Interface Signals (Continued)
A20M# O Mask A20: NMI O Non-Maskable Interrupt:
A20M# will go active based on either setting the appropriate bit in the NMI is used to force a non-Maskable interrupt to the processor. The
Port 92h register, or based on the A20GATE input being active. ICH7 can generate an NMI when either SERR# is asserted or
CPUSLP# O CPU Sleep: IOCHK# goes active via the SERIRQ# stream. The processor detects
This signal puts the processor into a state that saves substantial power an NMI when it detects a rising edge on NMI. NMI is reset by setting
compared to Stop-Grant state. However, during that time, no snoops the corresponding NMI source enable/disable bit in the NMI Status
occur. The Intel® ICH7 can optionally assert the CPUSLP# signal and Control register (I/O Register 61h).
when going to the S1 state. SMI# O System Management Interrupt:
FERR# I Numeric Coprocessor Error: SMI# is an active low output synchronous to PCICLK. It is asserted
This signal is tied to the coprocessor error signal on the processor. by the ICH7 in response to one of many enabled hardware or software
FERR# is only used if the ICH7 coprocessor error reporting function events.
is enabled in the OIC.CEN register (Chipset Config Registers:Offset STPCLK# O Stop Clock Request:
31FFh: bit 1). If FERR# is asserted, the ICH7 generates an internal STPCLK# is an active low output synchronous to PCICLK. It is
IRQ13 to its interrupt controller unit. It is also used to gate the asserted by the ICH7 in response to one of many hardware or
IGNNE# signal to ensure that IGNNE# is not asserted to the software events. When the processor samples STPCLK# asserted, it
processor unless FERR# is active. FERR# requires an external weak responds by stopping its internal clock.
pull-up to ensure a high level when the coprocessor error function is RCIN# I Keyboard Controller Reset CPU:
disabled. The keyboard controller can generate INIT# to the processor. This
NOTE: FERR# can be used in some states for notification by the saves the external OR gate with the ICH7’s other sources of INIT#.
processor of pending interrupt events. This functionality is When the ICH7 detects the assertion of this signal, INIT# is generated
independent of the OIC register bit setting. for 16 PCI clocks.
IGNNE# O Ignore Numeric Error: NOTE: The ICH7 will ignore RCIN# assertion during transitions to
This signal is connected to the ignore error pin on the processor. the S3, S4, and S5 states.
IGNNE# is only used if the ICH7 coprocessor error reporting A20GATE I A20 Gate:
function is enabled in the OIC.CEN register (Chipset Config A20GATE is from the keyboard controller. The signal acts as an
Registers:Offset 31FFh: bit 1). If FERR# is active, indicating a alternative method to force the A20M# signal active. It saves the
coprocessor error, a write to the Coprocessor Error register (I/O external OR gate needed with various other chipsets.
register F0h) causes the IGNNE# to be asserted. IGNNE# remains CPUPWRGD/ O CPU Power Good:
asserted until FERR# is negated. If FERR# is not asserted when the GPIO49 This signal should be connected to the processor’s PWRGOOD input
Coprocessor. Error register is written, the IGNNE# signal is not to indicate when the CPU power is valid. This is an output signal that
asserted. represents a logical AND of the ICH7’s PWROK and VRMPWRGD
INIT# O Initialization: signals.
INIT# is asserted by the ICH7 for 16 PCI clocks to reset the This signal may optionally be configured as a GPIO.
processor.
ICH7 can be configured to support processor Built In Self Test
(BIST).
INIT3_3V# O Initialization 3.3 V: Firmware Hub Interface Signals
This is the identical 3.3 V copy of INIT# intended for Firmware Hub. Name Type Description
INTR O Processor Interrupt: FWH[3:0]/ I/O Firmware Hub Signals:
INTR is asserted by the ICH7 to signal the processor that an interrupt LAD[3:0] These signals are multiplexed with the LPC address signals.
request is pending and needs to be serviced. It is an asynchronous FWH4/ O Firmware Hub Signals:
output and normally driven low. LFRAME# This signal is multiplexed with the LPC LFRAME# signal.
75

General Purpose I/O Signals General Purpose I/O Signals (Continued)
Name Type Tolerance Power Well Description Name Type Tolerance Power Well Description
GPIO49 I/O V_CPU_IO V_CPU_IO Multiplexed with CPUPWRGD GPIO1 I/O 5V Core Multiplexed with REQ5#.
GPIO48 I/O 3.3 V Core Multiplexed with GNT4# GPIO0 I/O 3.3 V Core Unmultiplexed.
GPIO[47:40] N/A 3.3 V N/A Not implemented. NOTES:
GPIO[39:38] I/O 3.3 V Core Unmultiplexed. 1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an
SMI# or an SCI, but not both.
GPIO37 I/O 3.3 V Core Multiplexed with SATA3GP. 2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals
GPIO36 I/O 3.3 V Core Multiplexed with SATA2GP. are not driven high into powered-down planes. Some ICH7 GPIOs may be connected to pins on
GPIO35 I/O 3.3 V Core Multiplexed with SATACLKREQ#. devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core
power (PWROK low) or a Power Button Override event will result in the Intel ICH7 driving a pin
GPIO34 I/O 3.3 V Core Unmultiplexed. to a logic 1 to another device that is powered down..
GPIO33 I/O 3.3 V Core Unmultiplexed.
GPIO31 I/O 3.3 V Resume Multiplexed with OC7#
GPIO30 I/O 3.3 V Resume Multiplexed with OC6# PCI Express* Signals
GPIO29 I/O 3.3 V Resume Multiplexed with OC5#
PETp[1:4], O PCI Express* Differential Transmit Pair 1:4
GPIO28 I/O 3.3 V Resume Unmultiplexed.
PETn[1:4]
GPIO27 I/O 3.3 V Resume Unmultiplexed. PERp[1:4], I PCI Express Differential Receive Pair 1:4
GPIO26 I/O 3.3 V Resume Unmultiplexed. PERn[1:4]
GPIO25 I/O 3.3 V Resume Unmultiplexed. PETp[5:6], O PCI Express* Differential Transmit Pair 5:6
PETn[5:6] Reserved: ICH7
GPIO24 I/O 3.3 V Resume Unmultiplexed. Not cleared by CF9h reset (Intel® ICH7R
event. Only)
GPIO23 I/O 3.3 V Core Multiplexed with LDRQ1# PERp[1:4], I PCI Express Differential Receive Pair 5:6
GPIO22 I/O 3.3 V Core Multiplexed with REQ4# PERn[5:6] Reserved: ICH7
GPIO21 I/O 3.3 V Core Multiplexed with SATA0GP. (ICH7R Only)

GPIO19 I/O 3.3 V Core Multiplexed with SATA1GP.
GPIO18 I/O 3.3 V Core Unmultiplexed. SM Bus Interface Signals
GPIO17 I/O 3.3 V Core Multiplexed with GNT5#. Name Type Description
GPIO16 I/O 3.3 V Core Unmultiplexed. SMBDATA I/OD SMBus Data:
GPIO[15:12] I/O 3.3 V Resume Unmultiplexed. External pull-up resistor is required.
SMBCLK I/OD SMBus Clock:
GPIO11 I/O 3.3 V Resume Multiplexed with SMBALERT# External pull-up resistor is required.
GPIO[10:8] I/O 3.3 V Resume Unmultiplexed. SMBALERT#/ I SMBus Alert:
GPIO[7:6] I/O 3.3 V Core Unmultiplexed. GPIO11 This signal is used to wake the system or generate SMI#. If not used
for SMBALERT#, it can be used as a GPIO.
GPIO[5:2] I/OD 5V Core Multiplexed with PIRQ[H:E]#.
76

AC’97/Intel® High Definition Auto Link Signals Power and Ground Signals
Name Type Description Name Description
ACZ_RST# O AC’97/Intel® High Definition Audio Reset: Vcc3_3 3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3,
Master hardware reset to external codec(s). S4, S5 or G3 states.
ACZ_SYNC O AC ’97/Intel High Definition Audio Sync: Vcc1_05 1.05 V supply for core well logic (20 pins). This power may be shut off in S3, S4,
48 kHz fixed rate sample sync to the codec(s). Also used to encode S5 or G3 states.
the stream number. Vcc1_5_A 1.5 V supply for Logic and I/O (30 pins). This power may be shut off in S3, S4, S5
ACZ_BIT_CLK I/O AC ’97 Bit Clock Input: or G3 states.
12.288 MHz serial data clock generated by the external codec(s). This Vcc1_5_B 1.5 V supply for Logic and I/O (53 pins). This power may be shut off in S3, S4, S5
signal has an integrated pull-down resistor (see Note below). or G3 states.
Intel High Definition Audio Bit Clock Output: V5REF Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut
24.000 MHz serial data clock generated by the Intel High Definition off in S3, S4, S5 or G3 states.
Audio controller (the Intel® ICH7). This signal has an integrated VccSus3_3 3.3 V supply for resume well I/O buffers (24 pins). This power is not expected to
pull-down resistor so that ACZ_BIT_CLK doesn’t float when an Intel be shut off unless the system is unplugged in desktop configurations.
High Definition Audio codec (or no codec) is connected but the VccSus1_05 1.05 V supply for resume well logic (5 pins). This power is not expected to be shut
signals are temporarily configured as AC ’97. off unless the system is unplugged in desktop configurations.
ACZ_SDOUT O AC ’97/Intel High Definition Audio Serial Data Out: This voltage may be generated internally (see Function Straps for strapping
Serial TDM data output to the codec(s). This serial output is option). If generated internally, these pins should not be connected to an external
double-pumped for a bit rate of 48 Mb/s for Intel High Definition supply.
Audio. V5REF_Sus Reference for 5 V tolerance on resume well inputs (1 pin). This power is not
NOTE: ACZ_SDOUT is sampled at the rising edge of PWROK as a expected to be shut off unless the system is unplugged in desktop configurations.
functional strap. See Function Straps for more details. There is a weak VccRTC 3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This
integrated pull-down resistor on the ACZ_SDOUT pin. power is not expected to be shut off unless the RTC battery is removed or
ACZ_SDIN[2:0] I AC ’97/Intel High Definition Audio Serial Data In [2:0]: completely drained.
Serial TDM data inputs from the three codecs. The serial input is Note: Implementations should not attempt to clear CMOS by using a jumper to
single-pumped for a bit rate of 24 Mb/s for Intel® High Definition pull VccRTC low. Clearing CMOS in an Intel® ICH7-based platform can be done
Audio. These signals have integrated pulldown resistors, which are by using a jumper on RTCRST# or GPI.
always enabled. VccUSBPLL 1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB
not used.
VccDMIPLL 1.5 V supply for core well logic (1 pins. This signal is used for the DMI PLL. This
power may be shut off in S3, S4, S5 or G3 states.
LPC Interface Signals VccSATAPLL 1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL.
Name Type Description This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if
LAD[3:0]/ I/O LPC Multiplexed Command, Address, Data: SATA not used.
FWH[3:0] For LAD[3:0], internal pull-ups are provided. V_CPU_IO Powered by the same supply as the processor I/O voltage (3 pins). This supply is
LFRAME#/ O LPC Frame: used to drive the processor interface signals listed in Process Interface Signals.
FWH4 LFRAME# indicates the start of an LPC cycle, or an abort. Vss Grounds (194 pins).
LDRQ[0]# I LPC Serial DMA/Master Request Inputs:
LDRQ[1]#/ LDRQ[1:0]# are used to request DMA or bus master access. These
GPIO23 signals are typically connected to external Super I/O device. An
internal pull-up resistor is provided on these signals.
LDRQ1# may optionally be used as GPIO.
77

Functional Strap Definitions Functional Strap Definitions (Continued)
Signal Usage When Sampled Description Signal Usage When Sampled Description
GNT3# Top-Block Rising Edge of The signal has a weak internal pull-up. If the ACZ_SDOU XOR Chain Rising Edge of Allows entrance to XOR Chain testing when TP3
Swap Override PWROK signal is sampled low, this indicates that the T Entrance/PCI PWROK pulled low at rising edge of PWROK. See
system is strapped to the “top-block swap” mode Express* Port Chapter 25 for XOR Chain functionality
(Intel® ICH7 inverts A16 for all cycles targeting Config bit 1 information.
FWH BIOS space). The status of this strap is When TP3 not pulled low at rising edge of
readable via the Top Swap bit (Chipset Config PWROK, sets bit 1 of RPC.PC (Chipset Config
Registers:Offset 3414h:bit 0). Note that software Registers:Offset 224h). See Section 7.1.34 for
will not be able to clear the Top-Swap bit until details.
the system is rebooted without GNT3# being This signal has a weak internal pull-down.
pulled down. ACZ_SYNC PCI Express Rising Edge of This signal has a weak internal pull-down.
GNT2# Reserved This signal has a weak internal pull-up. Port Config bit PWROK Sets bit 0 of RPC.PC (Chipset Config
NOTE: This signal should not be pulled low. 0 Registers:Offset 224h). See Section 7.1.34 for
REQ[4:1]#XOR Chain Rising Edge of See Chapter 25 for functionality information. details.
Selection PWROK GPIO25 Reserved Rising Edge of This signal has a weak internal pull-up.
LINKALER Reserved This signal requires an external pull-up resistor. RSMRST# NOTE: This signal should not be pulled low.
T# GPIO16 Reserved This signal has a weak internal pull-down.
SPKR No Reboot Rising Edge of The signal has a weak internal pull-down. If the NOTE: This signal should not be pulled high.
PWROK signal is sampled high, this indicates that the SATALED# Reserved This signal has a weak internal pull-up enabled
system is strapped to the “No Reboot” mode only when PLTRST# is asserted.
(ICH7 will disable the TCO Timer system reboot NOTE: This signal should not be pulled low.
feature). The status of this strap is readable via TP3 XOR Chain Rising Edge of See Chapter 25 for functionality information.
the NO REBOOT bit (Chipset Config Entrance PWROK This signal has a weak internal pull-up.
Registers:Offset 3410h:bit 5). NOTE: This signal should not be pulled low
INTVRMEN Integrated Always Enables integrated VccSus1_05 VRM when unless using XOR Chain testing.
VccSus1_05 sampled high.
VRM Enable/
Disable
EE_CS Reserved This signal has a weak internal pull-down.
NOTE: This signal should not be pulled high. Direct Media Interface Signals
EE_DOUT Reserved This signal has a weak internal pull-up. Name Type Description
NOTE: This signal should not be pulled low. O
DMI[0:3]TXP, Direct Media Interface Differential Transmit Pair 0:3
GNT5#/ Boot BIOS Rising Edge of This field determines the destination of accesses DMI[0:3]TXN
GPIO17#, Destination PWROK to the BIOS memory range. Signals have weak DMI[0:3]RXP, I Direct Media Interface Differential Receive Pair 0:3
GNT4#/ Selection internal pull-ups.Also controllable via Boot DMI[0:3]RXN
GPIO48 BIOS Destination bit (Chipset Config
DMI_ZCOMP O Impedance Compensation Input:
Registers:Offset 3410h:bit 11:10)
Determines DMI input impedance.
(GNT5# is MSB)
DMI_IRCOMP I Impedance/Compensation Compensation Output:
01-SPI
Determines DMI output impedance and bias current.
10-PCI
11-LPC
78

Miscellaneous Signals
INTVRMEN I Internal Voltage Regulator Enable:
This signal enables the internal 1.05 V Suspend regulator when
connected to VccRTC. When connected to Vss, the internal regulator
is disabled.
SPKR O Speaker:
The SPKR signal is the output of counter 2 and is internally
“ANDed” with Port 61h bit 1 to provide Speaker Data Enable. This
signal drives an external speaker driver device, which in turn drives
the system speaker. Upon PLTRST#, its output state is 0.
NOTE: SPKR is sampled at the rising edge of PWROK as a
functional strap. See Function Straps for more details. There is a weak
integrated pull-down resistor on SPKR pin.
RTCRST# I RTC Reset:
When asserted, this signal resets register bits in the RTC well.
NOTES:
1. Unless CMOS is being cleared (only to be done in the G3 power
state), the RTCRST# input must always be high when all other
RTC power planes are on.
2. In the case where the RTC battery is dead or missing on the
platform, the RTCRST# pin must rise before the RSMRST# pin.
TP0 I Test Point 0:
This signal must have an external pull-up to VccSus3_3.
TP1 O Test Point 1:
Route signal to a test point.
TP2 O Test Point 2:
TP3 I/O Test Point 3:
Real Time Clock Interface

RTCX1 Special Crystal Input 1:
This signal is connected to the 32.768 KHz crystal. If no external
crystal is used, then RTCX1 can be driven with the desired clock rate.
RTCX2 Special Crystal Input 2:
This signal is connected to the 32.768 KHz crystal. If no external
crystal is used, then RTCX2 should be left floating.
79
6. System Block Diagram U704

U707
Clock Generator
ICS9LPR325
Intel Pentium M
LM86
Yonah 533/667 Thermal Sensor
Video RAM
128/256 MB CPU
LM86
Thermal Sensor
DVI
DVI-I
RGB Channel A
U709 U706
Y/C VGA PCI-E x 16 200 Pins DDR2
S-Video North Bridge SO-DIMM Socket * 2
LVDS ATI M56
TFT LCD Calistoga 945PM
Channel B
Line in
RJ-11
PCI Bus Bluetooth External Microphone
Jack
DMI MDC
USB2.0 Internal Microphone
USB * 4
USB2.0 Azalia U722 U720

Mini Express Internal Speaker
(Wireless) Audio Codec Amplifier
U719
TPA0212
U717 IDE ALC883 Line out/SPDIF
ODD
Card South Bridge
Reader/1394 SATA U15
Subwoofer Jack
Link SATA HDD ICH7-M Amplifier LM4991
OZ128
Mini Express USB2.0 J509
(Tuner Card) RJ-11 Jack
LPC BUS M.D.C
3 in 1 Card IEEE1394 USB2.0
Express Internal Keyboard
Reader Slot Card
U713 U714 Touch Pad
Giga LAN
Keyboard BIOS
Power Button
CIR
Winbond ECO Button
RJ-45 Jack U14 W83L950G

FAN1 for CPU
System BIOS
Cover Switch
80
7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system BIOS runs a series of internal checks on the hardware. This Power
on Self Test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can
alert you to the problems of your computer.
If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs
before the display is initialized, then the screen cannot display the error message. Error codes or system beeps are
used to identify a post error that occurs when the screen is not available.
The value for the diagnostic port is written at the beginning of the test. Therefore, if the test failed, the user can
determine where the problem occurred by reading the last value written to the port-80H by the debug card plug at
Mini PCI slot.
81
7.2 Maintenance Diagnostics
7.2.1 Diagnostic Tool for Mini PCI-E Slot
82
7.3 Error Codes

Following is a list of error codes in sequent display on the Mini PCI-E debug board.
Code POST Routine Description Code POST Routine Description

0xA0 First memory check point 0x20 Disable Fast Dispatch
0x01 Enable MCHBAR Program the DRAM Row Attributes and DRAM Row Boundary
0x21
0x02 Check for DRAM initialization interrupt and reset fail registers
0x03 Verify all DIMMs are DDR or DDR2 and unbuffered 0x22 Program the DRAM Bank Architecture register
0x04 Detect an improper warm reset and handle 0x23 Program the DRAM Timing & and DRAM Control registers
0x05 Detect if ECC SO-DIMMs are present in the system 0x24 Program ODT
0x06 Verify all DIMMs are single or double sided and not asymmetric 0x25 Perform steps required before memory init
0x07 Verify all DIMMs are x 8 or x 16 width Program the receive enable reference timing control register
0x26
0x08 Find a common CAS latency between the DIMMS and the MCH Program the DLL Timing Control Registers , RCOMP settings
0x09 Determine the memory frequency and CAS latency to program 0x27 Enable DRAM Channel I/O Buffers
0x10 Determine the smallest common TRAS for all DIMMs 0x28 Enable all clocks on populated rows
0x11 Determine the smallest common TRP for all DIMMs 0x29 Perform JEDEC memory initialization for all memory rows
0x12 Determine the smallest common TRCD for all DIMMs 0x30 Perform steps required after memory init
0x13 Determine the smallest refresh period for all DIMMs 0x31 Program DRAM throttling and throttling event registers
0x14 Verify burst length of 8 is supported by all DIMMs 0x32 Setup DRAM control register for normal operation and enable
0x15 Determine the smallest tWR supported by all DIMMs 0x33 Enable RCOMP
0x16 Determine DIMM size parameters 0x34 Clear DRAM initialization bit in the ICH
0x17 Program the correct system memory frequency 0x35 Initialization Sequence Completed, program graphic clocks
0x18 Determine and set the mode of operation for the memory channels 0xAF Disable access to the XMM registers
0x19 Program clock crossing registers
83
8. Trouble Shooting
8.1 No Power (*1)
8.2 No Display (*2)
8.3 VGA Controller Test Error LCD No Display
8.4 Memory Test Error
8.5 Keyboard (K/B) or Touch Pad (T/P) Test Error
8.6 Hard Disk Drive Test Error
8.7 ODD Test Error
8.8 USB Port Test Error
8.9 Audio Test Error
8.10 LAN Test Error
8.11 1394 & Card Reader Slot Test Error
8.12 Mini Express (wireless) Socket Test Error
8.13 Mini Express (Tuner Card) Socket Test Error
8.14 Express Card Socket Test Error

84
*1: No Power Definition

Base on ACPI Spec, We define no power as while we press the power button, the system can’t leave S5 status
or none the PG signal send out from power supply.
Judge condition:
Check whether there are any voltage feedback control to turn off the power.
Check whether no CPU power will cause system can’t leave S5 status.
If there are not any diagram match these condition, we should stop analyzing the schematic in power supply sending
out the PG signal. If yes, we should add the effected analysis into no power chapter.
*2: No Display Definition

Base on the digital IC three basic working conditions: working power, reset, Clock. We define no display as
while system leave S5 status but can’t get into S0 status.
Judge condition:
Check which power will cause no display.

Check which reset signal will cause no display.
Check which Clock signal will cause no display.
Base on these three conditions to analyze the schematic and edit the no display chapter.
Keyword:
S5: Soft Off
S0: Working
For detail please refer the ACPI specification.
85
8.1 No Power-1
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Check following parts and signals:

No Power
Main Board
Parts Signals
Board-level
Is the Troubleshooting PJ701 PQ10 ADINP
notebook connected No FPDJ701 PD4 ALWAYS
to power (either AC adaptor AC FPJ701 PD5 D/VMAIN
or battery)? Where from FPU703 PD6
power source problem Power -LEARNING
PU4 PD705
Yes Connect AC adaptor (first use AC to I_LIMIT
power it)? PL1 PQ711
-ADEN
or battery. PL2 PU7
+CPU_CORE
Try another known good

battery or AC adapter.
Check following parts and signals:
Parts: Signals:
Power No Replace
OK? Motherboard J705 BATT
PU1 DBATT
Battery PQ706
BATT_T
Yes PQ709
BATT_V
PQ7
PQ8 BATT_C
Replace the faulty AC PD701 BATT_D
adaptor or battery. PD702
86
8.1 No Power-2
P30 P21
PQ710 Q708
Main Voltage Map Daughter Board +3VS MC_VCC
P12
FPDJ701 PJ701 L16
VDDR4
Charge FPU702, FPL704
P36 DJS9 P36 P30 L735 P17
PD701, PL701
FPR701, FPD701 ~DJS11 +3VS_SATA
PQ706, PL702
P35 +F3V_P +F3V +3V L734
P20
BATT +2.5V_LAN
Daughter Board FPDJ701 PJ701 FPDJ701 PJ701
Discharge P20
L731
PQ709
FPL702
+1.2V_LAN
P36 FPJO1 PL1, PL2 P29 PD5 P29 P36 FPL703
P36 P29
FPJO2 PR67, PQ10 PD6 FPU703 PU702
POWER IN FPJA1 PJA1 ADINP D/VMAIN FD/VMAIN PJO701
P33
PU701
P30
L716
P11
+2.5V +2.5VS +AVDD

FPJ701 PD705
P11
PD706 FPU701, FPL701 P36 DJS705 P36 P30 L714
P30
Discharge FPR704, FPD702 ~DJS707 PQ9 +A2VDD
+F5V_P +F5V +5V +5VS
P29 P11
L715
ALWAYS +VDDD1
P17
L733
PJ701 +5VS_HDD L12
P11
+VDD2D1
FPDJ701 L739 P22
PL705, PL706, PU2, PU3 P34 P11
P36 PU5, PU705~712, PL708 AVDD L11
+CPU_CORE +PVDD
F_ALWAYS
L736 P23 P11
L717
P24 PJ701 FPDJ701 P33 P33
AMPVDD +TPVDD
L43 PL710, PU714~716, PD708, PL709 PJO703~706
+3VA_KBC P36
+1.05V_P +VCCP L27 P27
P11
FPR708 +5VS_TP L17
P18 +3VA +F3VA FPR706 +TXVDDR
D7 FPU703 P23
PL713, PL714 PU722, PU719 P31 L737
+VCC_RTC PU7 PD709, PL715
P36
VGA_CORE +5VS_SUBAMP
FPR705
+5VA +F5VA
PU718
P31 PJO715 P33
PU723, PL712 PJO716
P36 +1.5VS +1.2VS
VCC
R238
P16
R267
Daughter Board DDR2_VREF
PU8, PU6 P32 PQ715
PL4, PU9 P30
PD9, PL3 PQ712
+1.8V +1.8VS
P32 P32
PJO4, PJO5
NOTE : +0.9V_P +0.9VS
P32
P33 : Page 33 on M/B Board circuit diagram.
+0.9VREF
87
8.1 No Power-3
Power Controller
72
+3VA D/VMAIN
Daughter Board P32 +1.8V
+3VA_KBC PU9
P28 P25 71 4 -SUSC
ISL88550A +0.9VS
FJO11
FJ703 J707 C371 P24
R404 0.1U
10K
R405
-PWRSW 1K -KBC_POWERBTN 1
-F_PWRSW
P25 P28 P28 P25
C402 Daughter Board
0.1U J707 FJ703 FJ703 J707
FSW3
NTC010-DC1G-C100T FD/VMAIN
P36 +F3V_P +F3V +3V
U714 FPU703
23 PWR_ON F_PWR_ON
+3VA ISL6232 +F5V_P +F5V +5V
SB_PWRGD 5
Keyboard
+3V P30
Q6
R335
BIOS PQ710 +3VS
-TEMP_OVER DTC144TKA
10K
P24 -KBC_RESET 25 FDC604P
P4 MN RESET
C366
0.1U
U10 R334
100K
W83L950G
VCC IMP811 GND 17 MAINPWR1
P33
C365 PU714 +1.05V_P
0.1U
D/VMAIN ISL6224
+3V
+5V
P30
P18
R337
4.7K
15 -SUSB PQ9 +5VS
U719 PWRBTN# -SB_PWRBTN 7 FDC604P
South VRMPWRGD VRMPWRGD 12 C913
22P
29 XOUT
Bridge -LFRAME -LFRAME 63
2
R979 X703
1M
ICH7-M 8MHz
1
28 XIN
C914
22P
88
8.1 No Power-4
PJO2 PD705 ALWAYS

OPEN-SMT4 BAV70LT1
P36 P29
Daughter Board PL2
PJO3 PD5
FPDJ701 PJ701 120Z/100M
OPEN-SMT4 PQ10 B340A
AQ4419 PD706
ADINP BAV70LT1
PL1 PR67 8 PD6
FPJ701 FPJA1 PJA1 120Z/100M .01 3 7 B340A
1 2 6
5 D/VMAIN
POWER IN 2~4 1
PC58 PC61
D
PC47
S
PC55 PD4 PC49 PC50 PR51 PR66 PC46
0.1U
G
PC56 PC53 BZV55C24 0.1U 1000P 1000P 1000P 0.1U
FPJO1, FPJO 1000P PR740 10K 10K
0.1U 0.1U
SPARKGAP_6 470K
PR741
100K
PQ711
PJO702 2N7002
OPEN-SMT4
3 4
P29 PR143
PC54 5 1M
2
0.1U PU4
1 6
MAX4173FEUT-T
PR742
10
P24
U714
76 I_LIMIT
Keyboard PC749
1U
BIOS
W83L950G 8 -LEARNING
89
8.1 No Power-5
Charge
PQ706
AO4419
PD701 PL701 8 PL702
B340A 120Z/100M 3 7 22UH
ADINP 2 6
1 5 BATT
D
S
PC722 PC4 PC723 PC5 PC20 PC8 PC7 PC10 PR719
G
0.01U 1000P 10U 10U 10U 10U PR718
0.01U 0.1U 20K
PR7 PR6 2M
4.7K PR8 PD702
4.7K
PR723 100K B340A
0
PJOL701
PQ1
MMBT2222A
PR720
13.7K PR722
PQ705 PD2 287K PR721
DTA144WK BAS32L 976K
CHG_ON PQ704 PJOH701

2N7002
P24
9 8
E1 C1
PC721 10 7
0.1U E2 P35 GND
11 6
C2 RT
12
VCC PU1 CT
5
13 4
OUTPUTCTRL DTC
14
TL594C 3 PR19
REF FEEDBACK PJS1
2.49K
15 2
2IN- 1IN-
PC2 16 1
2IN+ 1IN+
0.01U
PC1 PR4 PC3 PR5 PC720
0.1U 10K 0.1U 6.19K 1U PR20 PC18 PR21
10K PR22
100K 1000P
0
PR3
124K
PR24
0.02
PR1
GND GNDB
I_CTR 0
P24
90
8.1 No Power-6
Discharge PQ709
AO4409
8
7 3
6 2
BATT 5 1 D/VMAIN
D
PC729
S
PC728
G
1000P 0.01U
4
PD706
PR727 BAV70LT1
PR726 100K
33K ALWAYS
D
14 -ADEN G
PQ7
2N7002
J705
S PL703
120Z/100M
DBATT
PL704
120Z/100M P35
1,2
+3VA_KBC
P24 DBATT PC724 PC42
3
0.1U 0.1U
+3VA
U714
Battery Connector
PR118
D6 499K
BAV70LT1 R340 PR121 PR120
33 10K 0_DFS
1
78 BATT_T 5
77 BATT_V
Keyboard PR119 PC110
R341 100K 0.1U
C369 C368 33
0.1U 0.1U PC109 PR117
BIOS 0.1U 100K
+5VA
+5VA +5VA
1 1
2
2
PD1 PD3
W83L950G R357 R356 BAV99 BAV99
10K 10K R339 PR25
3
3
33 0_DFS
2 KBC_SCL BATT_C 3
3 KBC_SDA BATT_D 4
R338 PR26
33 0_DFS
PJO1 PJP1
SPARKGAP-6 SPARKGAP-6
91
8.2 No Display-1
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display
Monitor No Replace monitor

or LCD module
or LCD.
OK?
Yes Board-level
Troubleshooting
Make sure that CPU module,
DIMM memory are installed
Properly. Refer to port 378H
System
Yes error code description
BIOS writes
section to find out
error code to port
Display Yes which part is causing
Correct it. 378H?
OK? the problem.
No No
Replace
1.Try another known good CPU module, Motherboard
DIMM module and BIOS.
2.Remove all of I/O device (HDD,
ODD…….) from motherboard Check system clock,
except LCD or monitor. reset circuit and
reference power
1. Replace faulty part.

Display Yes 2. Connect the I/O device to the M/B
OK? one at a time to find out which part
To be continued
is causing the problem.
No clock, reset and power checking
92
8.2 No Display-2
+3VS +3V
****** System Clock Check ******
C820 R835 R836 R371 R407
G Q11
22P X2 19 10K 10K 2.2K 2.2K
2N7002
17 SMBDATA D S SMB_DATA
1 G
Q12
X1 R842 2N7002 D SMB_CLK
16 SMBCLK S
C821 14.318MHz 1M
22P 2
X1
20 37 R849 33 CLK_ICHPCI
P18
41 R862 33 CLK_USB48
P7 P8
22 R843 33 CLK_ICH14
-CLK_MCH_BCLK R191 33 10 U719
CLK_MCH_BCLK R189 33 11 52 R898 0 CLK_PCIE_ICH
U706 -CLK_MCH_3GPLL R217 33 51 53 R900 0 -CLK_PCIE_ICH
CLK_MCH_3GPLL R218 33 50
P6 70 R879 0 SATA_CLK South Bridge
North Bridge
R82
MCH_BSEL2 1K 69 R882 0 -SATA_CLK
ICH7-M
R84
71 R210 0_DFS -SATACLKREQ
MCH_BSEL1 1K
Intel 915PM R83 U707 13 R838 0 -HCLK_CPU

MCH_BSEL0 1K
14 R839 0 HCLK_CPU
+VCCP
28 -PCIE_CLKREQ1 7
Clock
56 R895 0 -CLK_PCIE_S1 11 P25 Mini Express
R192 R211 R866
Generator
1K 1K 1K 55 R896 0 CLK_PCIE_S1 13 J717 Connector
R857 R862 (Tuner Card)
P4 CPU_BSEL0
2.2K 33
41 ICS9LPR325
U704 57 -PCIE_CLKREQ2 7
CPU_BSEL1 45
CPU 58 R891 0 -CLK_PCIE_S2 11 P25 Mini Express
R193
CPU_BSEL2
2.2K
23 R892 0 Connector
Yonah 59 CLK_PCIE_S2 13
J714 (Wireless)
34 R982 0 DEBUG_CLK 51
32 R818 33 PCI_OZ_CLK 45 U717

CLK_PCIE_PEG R889 0 60 P21
P11
U709 -CLK_PCIE_PEG R886 0 61 OZ128
CLK_27MSS R852 33 44
ATI M56 R803 100 CLK_27M R863 33
62 R884 33 -CLKREQ_CARD 16
J8
43
63 R885 33 CLK_PCIE_CARD 19
P21 Mini PCI
R846
33 64 R883 33 -CLK_PCIE_CARD 18 Connector
P27 U14 31 PCICLK_FWH 27
R875
W39V040FA R816 2 0 -CLK_PCIE_LAN
10K P20 U713
R876 FSA FSB FSC CPU PCI* SRC USB DOT
3 0 CLK_PCIE_LAN
R847
33
LAN 1 0 0 133.3 33.33 100 48 96
P24 U714 70 PCI_KBC_CLK 33
-CLK_REQ_LAN Controller
1 1 0 166.7 33.33 100 48 96
72 UNIT: MHz
W83L950G
93
8.2 No Display-3
****** Power Good & Reset Circuit Check ******
+3VA P25 J707 FJ703 P29 FJO11
P21
R404
10K FSW3 U717
R405 -PCI_RESET 5
1 -KBC_POWERBTN
1K
-PWRSW 30 30 -F_PWRSW 1 2
OZ128
P24 C402
3 4
5
0.1U
-PLT_RST 5
P20U713
23 PWR_ON Power Daughter Board P18
LAN Controller
Module +3VS
U716 J714
U714 +3VA NC7S08
Mini Express
1 5
25 -KBC_RESET 2 4 -PLT_RST 2
A VCC
4 -BUF_PLT_RST 22 P25 Connector
RESET VCC B P25 Y
3
1 P24 3 GND (Wireless)
KBC R334 GND MN R1026
100K C366 C365
+3V 100K
J717
U10 0.1U 0.1U U719 22
P25 Mini Express
W83L950G IMP811 R337 -PLT_RST -PLT_RST
4.7K To North Bridge
Connector
7 -SB_PWRBTN (Tuner Card)
South
5 SB_PWRGD -PLT_RST -PLT_RST P11 U709
Bridge
64 ATI M56
-PCI_RESET
-PLT_RST 2 P14 U718

P7 U706 ICH7-M
North Bridge OZ2710
P4 U704 -HCPURST
Intel 945PM
CPU HPWRGD R463
100 P27U14
Yonah -PLT_RST 2
System BIOS
R317
J713 11 -ACZ_RST1
39
+5VS
MDC P22
+5VS R256
P22
U722 R319
39 10K J710
-ACZ_RST0 -ACZ_RST R255 Q4 -CD_RST 5
11
Audio Codec 10K DTC144TKA ODD
P17
Connector
ALC883 -PLT_RST Q5
DTC144TKA
94
8.3 VGA Controller Test Error LCD No Display-1

There is no display or picture abnormal on LCD although power-on-self-test is passed.
VGA Controller Test Error

LCD No Display
Check if Yes
1. Confirm LCD panel or monitor is good J1, J3 are cold Re-soldering.
and check the cable are connected solder?
properly. Board-level
2. Try another known good monitor or Troubleshooting
LCD module. No
One of the following parts on the mother-board may be

Display Yes Replace faulty defective, use an oscilloscope to check the following signal or
OK? LCD or monitor. replace the parts one at a time and test after each replacement.
No Parts Signals
Replace
U706 Q2 ENABKL
Remove all the I/O device & cable from Motherboard L3 Q702 BLADJ
motherboard except LCD panel or L4 Q703 -LIDSW
extended monitor. L6 Q1 VGA_BLON
L703 J1
TXOUTCLK[1,2]+/-
U719 J3
TXOUT[10..22]+/-
U709
Connect the I/O device & cable to PEG_TXN/P[0..15]
Yes U714
Display PEG_RXN/P[0..15]
the M/B one at a time to find out
OK?
which part is causing the problem.
No
95
8.3 VGA Controller Test Error LCD No Display-2

There is no display or picture abnormal on LCD although power-on-self-test is passed.
L703
Q703
AO3413
J1
120Z/100M
+3VS 29,30
S D
R703
R732 C720 C721 C719
VGA_FPVDDEN 0 C717 G
100K 1000P 0.1U 1000P
0.1U
Q702
R734
2N7002
10K
P17
P11 P12
C83,C87..
R789,R790 0_DFS TXOUTCLK1+/- R17,R18 0_DFS 16,18
P8 0.1U PEG_TXN[0..15]
R147,R149 0_DFS TXOUTCLK2+/- R21,R22 0_DFS 4,6
U706 C52,C79..
0.1U
R797,R798 0_DFS TXOUT10+/- R15,R16 0_DFS 22,24
PEG_TXP[0..15]
U709 R799,R900 0_DFS TXOUT11+/- R9,R11 0_DFS 21,23
LCD Connector
North Bridge C52,C79.. R801,R802 0_DFS TXOUT12+/- R8,R10 0_DFS 15,17
0.1U
PEG_RXN[0..15] R139,R140 0_DFS TXOUT20+/- R19,R20 0_DFS 10,12
Intel 945PM C127,C133..

ATI M56 R143,R145 0_DFS TXOUT21+/- R12,R13 0_DFS 9,11
LCD
0.1U R141,R142 0_DFS TXOUT22+/- R3,R14 0_DFS 3,5
PEG_RXP[0..15]
+3VS
R733
0
LCD_ID0 PID0 28
LCD_ID1 PID1 27
+3VS
VGA_BLON
R973
10K +3VS
R31
U719
P18 0 U2 J3 Inverter Board
NC7S08
South Bridge ENABKL_SB 1 5
L4
A VCC 120Z/100M
ICH7-M -SUSB 2
3
B P17 Y
4 ENPBLT 4
GND L3
11 BLADJ 120Z/100M 6
L6
P24 D/VMAIN_INV 120Z/100M 1,2
P17
D/VMAIN S D
Q2
C2 R23
U714 2N7002 Q1
Inverter
R24 0.1U 100K G
AO3401
100K
Keyboard BIOS
+F3V Daughter Board
W83L950G P25 J707 FJ703 P28
FR2
10K FR1 FSW1 C5
16 -LIDSW 28 28 -F_LIDSW 100 0.1U
1 3
2 4
FC1
0.1U LID Switch
96
8.4 Memory Test Error-1

Extend DDR2 SO-DIMM is test error or system hangs up.
Memory Test Error
1. Check if on board SDRAM chips are no cold

One of the following components or signals on the motherboard
solder.
may be defective, use an oscilloscope to check the signals or
2. Check the extend SDRAM module is installed
Board-level replace the parts one at a time and test after each replacement.
properly. (J711, J712)
3. Confirm the SDRAM socket (J711, J712) is Troubleshooting
ok, no band pins. Parts: Signals:
U706 +1.8V SMBDATA
U707 +3VS SMBCLK
Yes J711 DDR2_VREF M_CLK _DDR[0..3]
Test J712
Correct it. DDRA/B_MA[0..13] -M_CLK _DDR[0..3]
OK? R266 -DDR_CKE[0..3] DDRA/B_DQS[0..7]
R239 -DDR_CS[0..3] DDRA/B_DM[0..7]
No R268 DDR_ODT[0..3] DDRA/B_DQ[0..63
R283 DDRA/B_BS[0..2]
R244 -DDRA/B_CAS
If your system host bus clock running at R276 -DDRA/B_RAS
Replace
400/533/667 MHZ then make sure that R300 -DDRA/B_WE
Motherboard R284
SO-DIMM module meet require of -DDRA/B_DQS[0..7]]
PC3200/PC4200/PC5400.
Yes Replace the faulty

Test
DDR2 SO-DIMM
OK?
module.
No
97
8.4 Memory Test Error-2

Extend DDR2 SO-DIMM is test error or system hangs up.
+0.9VS
R239,R268….
56
J711
DDRA/B_BS[0..2], -DDRA/B_CAS, -DDRA/B_RAS, -DDRA/B_WE, -PM_WXTTS[0,1] DDRA_BS[0..2], -DDRA_CAS, -DDRA_RAS, -DDRA_WE
DDRA/B_MA[0..13], -DDR_CKE[0..3], -DDR_CS[0..3], DDR_ODT[0..3] DDRA_MA[0..13], -DDR_CKE[0,1], -DDR_CS[0,1], DDR_ODT[0,1] P16

-DDRA/B_DQS [0..7], DDRA/B_DQS[0..7] -DDRA_DQS [0..7], DDRA_DQS[0..7]
DDRA/B_DM[0..7], DDR_A/B_DQ[0..63] DDRA_DM[0..7], DDR_A_DQ[0..63]
M_CLK_DDR[0..3], -M_CLK_DDR[0..3] M_CLK_DDR[0,1], -M_CLK_DDR[0,1], -PM_WXTTS0
SMBDATA
P7 P8
DIMM0
SMBCLK
+1.8V
U706
R265
75
DDR2_VREF
R238
North Bridge U707 75 R264 C315 C314
P6 75 2.2U 0.1U
17 SMBDATA
Clock J712
Generator DDR2_VREF
Intel 945PM 16 SMBCLK
ICS9LPR325 R267
C285
2.2U
C284
0.1U P16
75
SMBCLK
SMBDATA
DDRB_BS[0..2], -DDRB_CAS, -DDRB_RAS, -DDRB_WE
DIMM1
DDRB_MA[0..13], -DDR_CKE[2,3], -DDR_CS[2,3], DDR_ODT[2,3]
-DDRB_DQS [0..7], DDRB_DQS[0..7]
DDRB_DM[0..7], DDR_B_DQ[0..63]
M_CLK_DDR[2,3], -M_CLK_DDR[2,3], -PM_WXTTS1
98
8.5 Keyboard (K/B) or touch pad (T/P) Test Error-1

Error message of keyboard or touch pad test error is shown or any key does not work.
Keyboard or touch pad

Test Error
Check Yes
Board-level J4, J6 Re-soldering.
Troubleshooting for cold solder?
Is K/B or T/P No
cable connected to notebook Correct it.
properly? No
Yes One of the following parts or signals on the motherboard

may be defective, use an oscilloscope to check the signals
or replace the parts one at a time and test after each
Replace replacement.
Try another known good Keyboard
or touch pad. Motherboard
Parts Signals
U719 KI[0..7]
U714 KO[0..15]
Yes J4 SERIRQ
Test Replace the faulty J6 -KBD_US/JP
Ok? Keyboard or touch pad. X703
-LFRAME
SW1
LPC_LAD[0..3]
No SW2
SW_LEFT
L22
L23 SW_RIGHT
R979 T_CLK
T_DATA
99
8.5 Keyboard (K/B) or touch pad (T/P) Test Error-2

Error message of keyboard or touch pad test error is shown or any key does not work.
+3VS
72
+3VA
71
R164 J4 Internal
10K Keyboard Connector
+3VA_KBC
71..80 KI[0..7] 17..24
C371 P24
0.1U
49..68 KO[0..15] 1..16
R163
-KBD_US/JP 0_DFS 25
+3VS
P24
P18 R1085
8.2K
SERIRQ 69
U719 U714
-KBD_US/JP +5VS
+5VS
South Bridge -LFRAME 63 Keyboard
BIOS L27
120Z/100MHZ
J6
LPC_LAD[0..3] 65..68
ICH7-M R354 R355 1,2
10K 10K
W83L950G 6 T_CLK L22 120Z/100M T_CLK_C 5,6
P27
9 T_DATA L23 120Z/100M T_DATA_C 3,4
SW1 R162
SW_LEFT 0_DFS
2 1 9,10
4 3
5 R161
28 SW_RIGHT 0_DFS
11,12
R979
CP1 C206
1M
47P*4 0.1U
2 1 29 SW2
2 1
X703 4 3
C914 C913 5
22P 8MHz touch pad
22P
100
8.6 Hard Disk Drive Test Error-1

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
Hard Disk Drive Test Error
1. Check if BIOS setup is OK?. Board-level

2. Try another working drive. Troubleshooting
One of the following parts or signals on the motherboard may
be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Re-boot Yes
Replace the faulty parts.
OK? Parts: Signals:
U719 +5VS
No
J715 +5VS_HDD
L733 +3VS
L735 +3VS_SATA
Check the system driver for proper Replace
R201 SATAHDD_RXP
installation. Motherboard SATAHDD_RXN
C912
C917 SATAHDD_TXP
SATAHDD_TXN
Re - Test Yes
End
OK?
No
101
8.6 Hard Disk Drive Test Error-2

Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing
data to hard disk.
J715
+3VS_SATA
+3VS L735
120Z/100M C917
0.1U P17
+5VS_HDD
P18
SATA HDD Connector

+5VS L733
120Z/100M C919 C918
U719 0.1U 0.1U
South Bridge SATAHDD_RXP

C940 3900P
SATAHDD_RXN
C942 3900P
ICH7-M C941 3900P

SATAHDD_TXP
SATAHDD_TXN
C912 3900P
102
8.7 ODD Test Error-1

An error message is shown when reading data from ODD.
ODD
Test Error
1. Try another known good compact disk. Board-level

2. Check install for correctly. Troubleshooting
One of the following parts or signals on the motherboard may
be defective, use an oscilloscope to check the signals or replace
the parts one at a time and test after each replacement.
Test Yes
Replace the faulty parts. Parts: Signals:
OK?
U719 +5VS
No U722 +3VS
J710 -CD_LED
L28 IDE_PDD[0..15]
Check the ODD for proper Replace L31 -CD_RST
installation. Motherboard R201 -IDE_PDCS[1,3]
R221 IDE_PDAP0..2]
R437 IDE_IRQ14
D16 -IDE_PDDACK
D18 IDE_PIORDY
Re - Test Yes C207 -IDE_PDIOR
End C208 -IDE_PDIOW
OK?
IDE_PDDREQ
No
103
8.7 ODD Test Error-2

An error message is shown when reading data from ODD. +3VS
R438 J710
10K
D18 D16
R437
BAT54A
68 LTST-C191TBKT-5A
3 2 -CD_LED 37
+3VS
L28
120Z/100MHZ
38..42
+5VS L31 P17
C442
47U C207120Z/100MHZ C208
1000P 1U
IDE_PDD[0..15] IDE_PDD[0..15] 6..20
+5VS
P18
-CD_RST R291 R201
Refer to Section 8.2 (No display 3) 4.7K 10K -CD_RST 5
IDE_PDA[0..2]
ODD Connector
IDE_PDA[0..2] 31,33,34
U719
IDE_IRQ14 IDE_IRQ14 29
-IDE_PDDACK -IDE_PDDACK 28
IDE_PIORDY IDE_PIORDY 27
South Bridge
-IDE_PDIOW -IDE_PDIOW 25
IDE_PDDREQ IDE_PDDREQ 22
-IDE_PDIOR -IDE_PDIOR 24
ICH7-M
-IDE_PDCS[1,3] -IDE_PDCS[1,3] 35,36
R221 10K LDE_PDIAG 32

+5VS
18 CD_L C971 1U R1068 6.8K CDROM_LEFT 1

P22
U722 19 CD_GND C972 1U R1067 0_DFS CDROM_COMM 3
Audio Codec 20 CD_R C970 1U R1069 6.8K CDROM_RIGHT 2
ALC883
R399 R400
R401 6.8K
0_DFS
6.8K
104
8.8 USB Test Error-1

An error occurs when a USB I/O device is installed.
USB Test Error
Check if the USB device is installed

properly.
Board-level Check the following parts for cold solder or one of the following
Troubleshooting parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time
Test Yes
Correct it. and test after each replacement.
OK?
No Parts: Signals:
U719 +F5V
Replace another known good USB FU701 +F3V
device. FU702 -SUSC
FJ704 -F_SUSC
Replace FJ702 -USB_OC01
Motherboard FL701 -F_USB_OC01
FL702 -USB_OC23
FL4 -F_USB_OC23
Re-test Yes FL5
Correct it. D/USBP[0..3]+
OK? FL8 D/USBP[0..3]-
FL9 F_USBP[0..3]+
No FR702 F_USBP[0..3]-
FR704
105
8.8 USB Test Error-2

An error occurs when a USB I/O device is installed.
+F3V
P25 J707 FJ703 P28 FU702 Daughter Board
FL702
RT9702A FR703
120Z/100M
+F5V 4
10K
5
FR704 VIN VOUT
0
P16
-F_SUSC 1 3 FC706 FC705
-SUSC CE FLG
P24 From U714 GND 150U 470P
2
-USB_OC01 -F_USB_OC01
FC703 FJ704
1U
+VCC_USB_2 1,A1
P18 FL9 P28
D/USBP0- F_USBP0- 90Z/100M 2
4 1
USB Port
D/USBP0+ F_USBP0+ 3 2 3
FL8
D/USBP1- F_USBP1- 90Z/100M
A2
4 1
D/USBP1+ F_USBP1+ 3 2 A3
U719 +F3V
FU701
FL701
RT9702A FR701
120Z/100M
+F5V 4
10K
5
South Bridge FR702 VIN
P16 VOUT
-F_SUSC 0 3 FC702 FC701
-SUSC 1 CE FLG
P24 From U714 GND 150U 470P
2
-USB_OC23 -F_USB_OC23
ICH7-M FC704 FJ702
1U
+VCC_USB_3 1,A1
FL4 P28
D/USBP2- F_USBP2- 90Z/100M 2
4 1
USB Port
D/USBP2+ F_USBP2+ 3 2 3
FL5
D/USBP3+ 90Z/100M
F_USBP3+ A2
4 1
D/USBP3- F_USBP3- 3 2 A3
106
8.9 Audio Test Error-1

No sound from speaker after audio driver is installed.
Audio Test error
1. Check if speaker cables are

connected properly.
2. Make sure all the drivers are Board-level Check the following parts for cold solder or one of the following parts on the
installed properly. Troubleshooting motherboard may be defective,use an oscilloscope to check the following signal
or replace parts one at a time and test after each replacement.
1.If no sound cause 2. If no sound cause 3. If no sound cause

Test Yes of line out, check of MIC, check of ODD, check
Correct it. the following the following the following
OK?
parts & signals: parts & signals: parts & signals:
No
Parts: Signals: Parts: Signals: Parts: Signals:
Try another known good U719 ROUT+/- U719 +5VS U719 CDROM_LEFT
speaker, ODD. U720 -DEVICE_DECT U722 +3VS U722 CDROM_RIGHT
Replace U15 -DECT_HP_OPT J720 MIC1_VREFR J710 CDROM_COMM
Motherboard U722 SPDIFOUT MIC1 MIC1_VREFL R399
J722 SPK_OFF L713 MIC1_R R400
L1 L714 MIC1_L R401
Re-test Yes L2 L37 R1067
Correct it.
OK? L736 L727 R1068
L747 R1104 R1069
No L748 R1105 C970
R1110 R1107 C971
R1133 R1108 C972
107
8.9 Audio Test Error-2 (Audio In)

L37
600Z/100M P22
1
R1104 R431
2 MIC1
0_DFS 2464_VREF L727
4.7K
+5VS 28 MIC1_VREFL 2464_VREF
600Z/100M JO716 Internal
AVDD
R1108 To next page
SPARKGAP_6 MIC
25,38 32 MIC1_VREFR 4.7K
AVDD1,2
MIC_INT 5
L739
C967 C968 C997 4
120Z/100M
10U 0.1U 0.1U
L744 600Z/100M 3 P22
C989 R1105
51 6
1U
21 MIC1_L L743 600Z/100M 2 J720
1
1,9 R422
+3VS DVDD1,2 C991
R1107 0_DFS
External
1U
C969 22 MIC1_R 51
AGND
MIC
10U
48
P22
C970
SPDIFOUT SPDIFOUT
To next page
J710
R1069
1U 6.8K
20 CDROM_RIGHT 2
C971 R1068
P18
ACZ_SDIN0 R397 39 8 U722 18 1U 6.8K CDROM_LEFT 1
P17
ODD
R322 39 ACZ_SDOUT0 5 C972 R1067 Connector
19 1U 0_DFS CDROM_COMM 3
U719 R320 39 ACZ_SYNC0 10

Audio Codec R399
100K
R400
6.8K
R401
6.8K
R319 39 -ACZ_RST0 11
ACZ_BITCLK0
R975 39 R396 0_DFS 6
C248 L746 J721 P22
South Bridge C400 ALC883 24 LINE_INR
1U 600Z/100M 5
SPK_OFF 10P 4
3
C418 L745
6 Line In
ICH7-M To next page 23 LINE_INL 1U 600Z/100M
2
1
C401 R470
1U 0_DFS
SB_SPKR R398 0 PC_BEEP 12
PCBEEP R1117 R1066 AGND
AOUT_R 4.42K 0_DFS
36 AMP_RIGHT
To next page
R1118 R1112
AOUT_L 4.42K 0_DFS
35 AMP_LEFT
To next page
SUB_RIGHT
To next page
SUB_LEFT
27 To next page
C429 10U
26,42
AGND
108
8.9 Audio Test Error-3 (Audio Out)

+5VS AMPVDD P25 J707 FJ703 P28 Daughter Board

L736 FJ1 P28
120Z/100M 21 ROUT+ 14,16 14,16 F_ROUT+ FL2 600Z/100M 1
ROUT+
7,18,19
VDD,PVDD[0,1] Internal Speaker
16 ROUT- 20,22 20,22 F_ROUT- FL3 600Z/100M 2 R
ROUT- Connector
C966 C961
0.1U 0.1U
J2 P23
4 L1 600Z/100M 1
LOUT+
Internal Speaker
9 L2 600Z/100M 2 L
LOUT- Connector
P23
AMPVDD
C990
1U C992 C987
AMP_RIGHT 20
From previous page
RHPIN 100U 100U J722 P23
R1119 R469 L45
23 4.7K 10K 600Z/100M
RLINEIN
R1106 5
C422
0.01U 39K L747
R1133 600Z/100M L46 600Z/100M 4
U720 22
2
AMPVDD AMPVDD
3
R424 R1110 L748 -DECT_HP_OPT L749 600Z/100M 1

C993 R1199 R1111 C1021
R423
4.7K
D13
BAT54A
100K Audio 100P 1K 1K 100P
22 600Z/100M C996
100P
C998
100P SPDIFOUT L750
2 From previous page 600Z/100M
Q17 LED
DTC144TKA -OPTIN 1
3 -SPK_OFF 22
Amplifier AMPVDD
7
8 Drive
SPK_OFF R1 C420 9 IC
SPK_OFF 1U R434
From previous page 10K L44
-OPTIN 600Z/100M
TPA0212 SPDIF Connector
-DECT_HP_OPT
Q19
DTC144TKA
-DEVICE_DECT -DEVICE_DECT
R432 +3VS
To next page
0_DFS
C959
1U C430 R433
AMP_LEFT 6 10K
LHPIN AMPVDD 1U
From previous page R1103
5 100K
LLINEIN 3
GAIN1 -DECT_HP_OPT
C419 R1099 R1 Q709
0.01U 39K 2 DTC144TKA
GAIN0
R1101 -DEVICE_DECT
100K
109
8.9 Audio Test Error-4 (Audio Out)

C395
390P
R392
18K
+5VS_SUBAMP
C398 R390
0.15U 22.1K
8
6 _
SUB_RIGHT C423
From page before previous 7
470P
2464VREF2 5 +
U13B
R426
4
LMV358
4.22K
R394
22.1K
SUB_OUTR R761
J706
C394 R388 0_DFS
3 5 1
0.22U 4.42K +IN VO1
P23
R430 R762 P23 SUBWOOF AMP
100 0_DFS 2
4 8 Connector
2464_VREF
From page before previous C426 R427
-IN
U15 VO2
0.22U 4.42K
C399
10U
2 BYPASS +5VS_SUBAMP +5VS
L737
R429
22.1K
SUB_OUTL R428
0_DFS
LM4991 120Z/100M
3 1 6
SHDWN VDD
D11
+5VS_SUBAMP BAT54C C425
C396 C421 C964
2 1 4.7U
0.1U AMP_SHUTDOWN 1U 100U
7,9
GND,GND1
8
DEVICE_DECT
2464VREF1 3
C428 R391 + 7
0.15U 22.1K
2 _
SUB_LEFT
From page before previous U13A
AMPVDD +3VS
4
LMV358
R387
C427 100K
390P SPK_OFF
R471 Q14
From previous page
18K DTC144TKA
AMPVDD
R425
10K
Q13
DTC144TKA -DEVICE_DECT
From previous page
110
8.10 LAN Test Error-1

An error occurs when a LAN device is installed.
LAN Test Error
1.Check if the driver is installed properly. Check the following parts for cold solder or one of the following
2.Check if the notebook connect with the parts on the mother-board may be defective, use an oscilloscope
LAN properly. to check the following signal or replace the parts one at a time and
test after each replacement.
Board-level
Troubleshooting
Parts: Signals:
Test Yes U710 +3V

Correct it. U713 +1.2V_LAN
OK?
U719 +2.5V_LAN
J709 MDI[0,1]+/-
No U12 PMDI[0,1]+/-
X702 EE_CS
L731 EE_SHCLK
Check if BIOS setup is ok. L734 EE_DIN
Replace R222 EE_DOUT
R223 LAN_TXD[0..2]
Motherboard
R224 LAN_RXD[0..2]
R868
Re-test Yes R225
Correct it.
OK? R229
No
111
8.10 LAN Test Error-2

An error occurs when a LAN device is installed.
+1.2V_LAN
L731
+3V
120Z/100M
+3V +2.5V_LAN L734
C866 C871 C900 C901 120Z/100M
0.01U 0.01U 0.01U 0.01U +3V
C924 C889
0.01U 0.01U
U12 J709
+3V
93C46 R958 0_DFS MDI0+ R225 0 PMDI0+ 11 20 MDO2+ 4
EE_CS P20
P18 1
CS VCC
8 19 MDO2- 5
P20
RJ45 LAN Connector

EE_SHCLK 2 P20 23 MDO3+ 7
SK
EE_DOUT 3
P18 22 MDO3- 8
DI
R957 0_DFS MDI0- R229 0 PMDI0- 12 17 PJRX+ 3
EE_DIN 4 5
DO GND U713 16 PJRX- 6
14 PJTX+ 1
U710 13 PJTX- 2
R954 0_DFS MDI1+ R228 0 PMDI1+ 8

U719 +3V LAN NS892402 15 MCT1
R411
Controller 18 MCT2
1K
South Bridge LAN_CLK R990 0
R956 0_DFS MDI1- R230 0 PMDI1- 9
21 MCT3
24 MCT4
LAN_RSTSYNC R989 0
C1010 0.1U PCIE_TXN3

82573E/82562GZ R868 R224 R223 R222
75 75 75 75
ICH7-M
C1011 0.1U PCIE_TXP3
XTAL1
-PLT_RST
C296
1000P
-PCIE_WAKE XTAL2
LAN_TXD[0..2] R986..R988 0
LAN_RXD[0..2] R991..R993 0
C898 X702 C920
22P 25MHZ 22P
112
8.11 1394 & Card Reader Slot Test Error-1

An error occurs when a 1394 & card device is installed.
1394 & Card Reader Slot Test Error
1. Check if the 1394 or card device is Check the following parts for cold solder or one of the following
Board-level parts on the mother-board may be defective, use an oscilloscope
installed properly.
Troubleshooting to check the following signal or replace the parts one at a time and
2. Confirm 1394 or card driver is
installed ok. test after each replacement.
Parts: Signals
Test Yes
Correct it U719 -PCI_RESET
OK? U717 -PCI_DEVSEL
J718 -PCI_FRAME
No J719 -PCI_IRDY
X704 -PCI_TRDY
L740 -PCI_STOP
Try another known good Replace L741 -CLKRUN
1394 or card device. Motherboard L742 -PCI_GNT0
Q708 SD_DAT[0..3]
R1078 MS_DATA[0..3]
R1079 -SD_CD
Yes R1080 SD_CMD
Re-test Change the faulty R1081 SD_MS_CLK
OK? part then end. R1121 SD_WP
C1003 -MS_CD
No C1004 MS_BS
113
8.11 1394 & Card Reader Slot Test Error-2

An error occurs when a 1394 & card device is installed.
L740 J718
120Z/100M +3VS C937
67..80 0.1U
+3VS S
C986 C977 8 -MC_3V R1005 0_DFS
1U 0.1U MC_VCC P21
G
Q708
R999 AO3413 D
0_DFS 6,13
16,90
3 IN 1 Card Reader Slot

+1.8VS C951 C954 C950 C953
C923 C981 C982 1U 0.1U 1U 0.1U
1U 0.1U 0.1U
P21
5
92,93.. MS_DATA[0..3] R1043..R1046 33 15,17..
-PCI_RESET
Refer Section 8.2 (No display-3) 105,106.. SD_DAT[0..3] R1039,R1040.. 33 2,3..
82 87 MS_BS R1041 33 20
XI
98 MS_CD 16
1 2 83 115 SD_WP 11
XO
111 SD_MS_CLK R1042 33 7,14
C984 X704 C983
SD_CMD 4
15P 24.576MHZ 15P
U717 108 R1047 33
112 -SD_CD 1
GND GND
+3VS
Card Reader
R1011 R367 R1063 R373 R1032 R1009 R1033 R1085 R1034
8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K
P18 /1394 J719
-PCI_INTA 14 R1098
-PCI_REQ0 17 71 TPB0N 0 TPB-
Controller 1
P21
PCI_PAR 44 R1095
-CLKRUN 10 TPB0P 0 TPB+
72 2
U719 -PCI_GNT0 18
-PCI_STOP
1394 Socket
43
-PCI_DEVSEL 42 OZ128 R1089
TPA0N 0
-PCI_IRDY 40 74 TPA- 3
South Bridge -PCI_FRAME 39

R1094
0
75 TPA0P TPA+ 4
SERIRQ 6
R1078 R1079 R1081 R1080 5,6
-PCI_TRDY 41 56.2 56.2 56.2 56.2
ICH7-M PCI_AD[0..31], -PCI_C/BE[0..3] 19..65 76 TPBIAS0 R468 0_DFS
R996 R1121 C1004 R467 0_DFS

100 C1003
PCI_AD18 9 5.11K 820P
1U
114
8.12 Mini Express (Wireless) Socket Test Error-1

An error occurs when a wireless card device is installed.
Mini Express (Wireless) Socket

Test Error
Board-level
Troubleshooting
1. Check if the wireless card device is
installed properly.
2. Confirm wireless driver is installed ok.
Check the following parts for cold solder or one of the following
parts on the mother-board may be defective, use an oscilloscope
to check the following signal or replace the parts one at a time and
Test Yes Replace test after each replacement.
OK? Correct it
Motherboard
No
Parts: Signals
Try another known good U707 +3VS DEBUG_CLK

wireless card device. U719 PCIE_RXN2 SMBCLK
J714 PCIE_RXP2 SMBDATA
D22 PCIE_TXN2
R453 PCIE_TXP2
Re-test Yes Change the faulty C1008 LPC_LAD[0..3]
OK? C1009 -LFRAME
part then end.
R212 -ICH_LDRQ0
No R891 -PCIE_CLKREQ2
R892 CLK_PCIE_S2
R980 -CLK_PCIE_S2
115
8.12 Mini Express (Wireless) Socket Test Error-2

An error occurs when a wireless card device is installed.
+3VS
J714
R1074
P6 10K
57 R212 0_DFS -PCIE_CLKREQ2 7
U707 58 R892 0 CLK_PCIE_S2 13

P25
59 R891 0 -CLK_PCIE_S2 11
Clock
Generator 34 R980 33 DEBUG_CLK R982 0 51
16 SMBCLK R1021 0_DFS 30
ICS9LPR325 17 SMBDATA R1023 0_DFS 32
+3VS
Mini Express (Wireless) Connector

R379 R1085
10K 8.2K
PCIE_RXN2 23
PCIE_RXP2 25
P18
C1008 0.1U PCIE_TXN2 31
C1009 0.1U PCIE_TXP2 33
LPC_LAD0 R1024 0 37
U719 LPC_LAD1 R1025 0 39
LPC_LAD2 R1022 0 41
LPC_LAD3 R984 0 43
South Bridge
-LFRAME R985 0 45
-ICH_LDRQ0 R983 0 47
ICH7-M SERIRQ R981 0 49
-WLAN_PD R1072 0_DFS 20
D/USBP5- 36
D/USBP5+ 38
116
8.13 Mini Express (Tuner Card) Socket Test Error-1

An error occurs when a tuner card device is installed.
Mini Express (Tuner Card) Socket

Test Error
Board-level
Troubleshooting
1. Check if the tuner card device
is installed properly.
2. Confirm tuner card driver is
installed ok.
OK? Correct it
Motherboard
No
Parts: Signals
Try another known good U707 +3VS

tuner card device. U719 PCIE_RXN1
J717 PCIE_RXP1
C1006 PCIE_TXN1
C1007 PCIE_TXP1
Re-test Yes Change the faulty R966 -PCIE_CLKREQ1
OK? R197 CLK_PCIE_S1
part then end.
R896 -CLK_PCIE_S1
No R895 SMBCLK
R943 SMBDATA
R917
117
8.13 Mini Express (Tuner Card) Socket Test Error-2

An error occurs when a tuner card device is installed.
+3VS
J717
R966
P6 10K
28 R197 0_DFS -PCIE_CLKREQ1 7
U707 55 R896 0 CLK_PCIE_S1 13

P25
56 R895 0 -CLK_PCIE_S1 11
Clock
Generator
ICS9LPR325
Mini Express (Tuner Card) Connector

17 SMBDATA R917 0_DFS 32
PCIE_RXN1 23
PCIE_RXP1 25
P18
C1006 0.1U PCIE_TXN1 31
C1007 0.1U PCIE_TXP1 33
U719
+3VS
South Bridge
R380
10K
ICH7-M
-TV_PD R944 0_DFS 20
D/USBP4- 36
D/USBP4+ 38
118
8.14 Express Card Socket Test Error-1

An error occurs when a express card device is installed.
Express Card Socket

Test Error
Board-level
Troubleshooting
1. Check if the express card device
is installed properly.
2. Confirm express card driver is
installed ok.
OK? Correct it
Motherboard
No
Parts: Signals
Try another known good U707 +3V -PCIE_WAKE

express card device. U718 CARD_3VS -CPPE
U719 CARD_3V -CPUSB
J8 CARD_1.5VS -CPERST
C1012 PCIE_RXN4 SMBCLK
Re-test Yes Change the faulty C1013 PCIE_RXP4 SMBDATA
OK? R883 PCIE_TXN4
part then end.
R884 PCIE_TXP4
No R885 -CLKREQ_CARD
R1003 CLK_PCIE_CARD
R959 CLK_PCIE_CARD
119
8.14 Express Card Socket Test Error-2

An error occurs when a express card device is installed.
+3VS
R1003
47K J8
P6 62 R884 0_DFS -CLKREQ_CARD 16
U707 63 R885 0 CLK_PCIE_CARD 19
64 R883 0 -CLK_PCIE_CARD 18
Clock
Generator P21
ICS9LPR325 17 SMBDATA R959 0_DFS 8
+3V +3V_EX +3VS CARD_3VS CARD_3V CARD_1.5VS
R1038 5,7 14,15

+1.5VS 0_DFS
C947 C945
12
Express Card Connector

0.1U 1U 16
10,12 9,10
4,6 P21
C932 C934 C948 C949 C946 C944 C935 C936 C933 C931
0.1U 10U 0.1U 1U 1 0.1U 1U 0.1U 1U 0.1U 1U +3V_EX
U718
P18 11,13 R1002 R1000
OZ2710 3 -CPERST
47K 47K
-PLT_RST 13
R1036 0_DFS 2
14 -CPUSB 4
32KOUT R1035 0_DFS 8 -CPPE
15 17
U719 PCIE_RXN4 21
PCIE_RXP4 22
C1012 0.1U PCIE_TXN4 24

South Bridge C1013 0.1U PCIE_TXP4 25
+3V +3V_EX
ICH7-M
R411 R1001
1K 47K
-PCIE_WAKE R1004 0_DFS 11
D/USBP6- 2
D/USBP6+ 3
120
9. Spare Parts List --1

Part Number Description Location(s) Part Number Description Location(s)
526280600015 LTXXNON;8258D1XXXX/T5XX/0XXXH/3X 271061102113 TF041-TH-RES;1K ,1/16W,1% ,040 PR14,PR18,PR706,PR729,R1109,R
416280600005 LT PF;15.4",WXGA,AU,W/Z TV,8258D 271061103114 TF041-TH-RES;10K ,1/16W,1% ,040 PR121,PR21,PR4,PR54,PR57
442600000077 TF041-TOUCHPAD MODULE;TM61PDM1G2 271061103307 TF041-TH-RES;10K ,1/16W,5% ,040 PR748,PR757,PR763,PR780,PR80
411806000001 TF041-PWA;PWA-8258D-HYNIX,MOTHER 271061104108 TF041-TH-RES;100K ,1/16W,1% ,040 PR117,PR119,PR15,PR17,PR20,P
340804300001 TF041-HOLDER;EXP CARD,TYCO,SABLE 271061104306 TF041-TH-RES;100K ,1/16W,5% ,040 PR741,PR770,PR82,PR94,PR97,R
242600000567 TF041-LABEL;32*7MM,POLYESTER FIL 271061105307 TF041-TH-RES;1M ,1/16W,5% ,040 PR743,PR781,PR96,PR98,R842,R9
242600000564 TF041-LABEL;25*6,HI-TEMP,COMMON 271061106308 TF041-TH-RES;10M ,1/16W,5% ,040 R332
242600000566 TF041-LABEL;BLANK,7MM*7MM,PRC 271061142104 TF041-TH-RES;1.47K,1/16W,1%,0402 R102
312078206131 TF041-EC;820U,2.5V,6100mA,20%,D8 PC737,PC743,PC750,PC763,PC78 271061151110 TF041-TH-RES;150 ,1/16W, 1%,040 R37
365350000004 SOLDER WIRE;LEAD_FREE,ECO,RMA98S 271061152502 TF041-TH-RES;1.5K ,1/16W,5% ,040 R58
370102010611 TF041-SPC-SCREW;M2L6,K-HD(+1),D 271061154107 TF041-TH-RES;150K ,1/16W,1% ,04 PR12,R26
371102010310 TF041-SCREW;M2L3,K-HD(+),D3.8,t= 271061168101 TF041-TH-RES;16.2,1/16W,1%,0402, R57
411806000003 TF041-PWA;PWA-8258D-HYNIX,MOTHER 271061181105 TF041-TH-RES;180,1/16W,1%,0402,S R134,R136,R138,R793,R794,R795
481806000002 TF041-F/W ASSY;KBD CTRL,8258D U714 271061183103 TF041-TH-RES;18K,1/16W,1%,0402,S PR799,R392,R471
270110000011 TF041-TL-THERMISTOR;10K,1%,0603, PR746 271061201107 TF041-TH-RES;200 ,1/16W, 1%,040 R121,R922
270110000017 TF041-TH-THERMISTOR;470K,5%,0603 PR747 271061202104 TF041-TH-RES;2K ,1/16W,1% ,040 PR36,R101,R314,R40
271002103308 TF041-TH-RES;10K ,1/10W,5% ,080 PR51,PR66 271061203112 TF041-TH-RES;20K ,1/16W,1% ,040 R741,R96,R977
271012000308 TF041-TH-RES;0 ,1/8W,5% ,1206 PR723 271061220105 TF041-TH-RES;22 ,1/16W,1% ,040 R1110,R1133,R972
271013102304 TF041-TH-RES;1K ,1/4W ,5% ,1206 PR74 271061221107 TF041-TH-RES;221,1/16W,1%,0402,S R160,R89
271013221302 TF041-TH-RES;220 ,1/4W,5% ,1206 PR16,PR703,PR734,PR761,PR83,P 271061222308 TF041-TH-RES;2.2K ,1/16W,5% ,040 R128,R193,R371,R407,R857
271045019001 TF041-TH-RES; .01,1W,1%,2512,SMT PR67 271061223106 TF041-TH-RES;22.1K,1/16W,1% ,040 PR785,R390,R391,R394,R429
271061000003 TF041-TH-RES;0 ,1/16W,0402,SM PR1,PR10,PR22,PR40,PR42,PR63 271061238101 TF041-TH-RES;23.7,1/16W,1%,0402, R1059
271061010102 TF041-TH-RES;1,1/16W,1%,0402,SMT R1132 271061240102 TF041-TH-RES;24.9,1/16W,1% ,0402 R1097,R158,R417,R86
271061100103 TF041-TH-RES;10,1/16W,1%,0402,SM PR30,PR31,PR32,PR41,PR50,PR5 271061251102 TF041-TH-RES;255,1/16W,1%,0402,S R114
271061101109 TF041-TH-RES;100 ,1/16W,1% ,040 R1092,R1158,R1160,R1161,R1163 271061270104 TF041-TH-RES;27.4 ,1/16W, 1%,04 R34,R42,R45
121

271061330311 TF041-TH-RES;33 ,1/16W,5% ,040 R1039,R1040,R1041,R1042,R1043 271061800101 TF041-TH-RES;80.6,1/16W,1%,0402, R207,R208
271061334103 TF041-TH-RES;332K,1/16W,1%,0402, R326 271061822307 TF041-TH-RES;8.2K ,1/16W,5% ,040 R1006,R1007,R1008,R1009,R1011
271061390309 TF041-TH-RES;39, 1/16W, 5%,0402 R317,R318,R319,R320,R321,R322 271071000312 TF041-TH-RES;0 ,1/16W,5% ,060 PR759,PR767,PR87,PR92,R1071,R
271061393103 TF041-TH-RES;39K ,1/16W,1% ,0402 R1099,R1106 271071100103 TF041-TH-RES;10 ,1/16W,1% ,060 PR85,R48,R56
271061442213 TF041-TH-RES;4.42K,1/16W,1% ,040 R1117,R1118,R388,R427 271071102107 TF041-TH-RES;1K ,1/16W,1% ,060 PR86
271061470502 TF041-TH-RES;47 ,1/16W,5% ,040 R129 271071103108 TF041-TH-RES;10K ,1/16W,1% ,060 PR62,PR754,PR89
271061471308 TF041-TH-RES;470 ,1/16W,5% ,040 R202 271071113115 TF041-TH-RES;11.8K ,1/16W,1% ,06 PR9
271061472312 TF041-TH-RES;4.7K ,1/16W,5% ,040 R1104,R1108,R1119,R168,R291,R 271071122105 TF041-TH-RES;1.2K ,1/16W,1% ,060 PR733
271061473502 TF041-TH-RES;47K ,1/16W,5% ,040 R1000,R1002,R1003 271071124117 TF041-TH-RES;124K ,1/16W,1% ,060 PR3
271061474304 TF041-TH-RES;470K ,1/16W,5% ,040 PR740 271071133102 TF041-TH-RES;13.7K,1/16W,1% ,060 PR720
271061491101 TF041-TH-RES;499,1/16W,1%,0402,S R791 271071134102 TF041-TH-RES;130K ,1/16W,1% ,060 PR101
271061492102 TF041-TH-RES;4.99K,1/16W,1% ,040 R115,R123,R124,R204,R205,R232 271071134103 TF041-TH-RES;137K ,1/16W,1% ,060 PR755
271061494101 TF041-TH-RES;499K ,1/16W,1% ,04 PR118 271071153105 TF041-TH-RES;15K ,1/16W,1% ,060 PR797
271061510306 TF041-TH-RES;51, 1/16W, 5%,0402 R1105,R1107,R46 271071162113 TF041-TH-RES;1.62K,1/16W,1% ,060 PR760
271061512107 TF041-TH-RES;5.11K ,1/16W,1% ,0 PR55,PR59,R1121 271071163104 TF041-TH-RES;1.69K,1/16W,1% ,060 PR753
271061540102 TF041-TH-RES;54.9 ,1/16W,1% ,040 R122,R43,R44,R88,R946,R947,R95 271071178112 TF041-TH-RES;1.78K,1/16W,1% ,060 PR103
271061560106 TF041-TH-RES;56.2,1/16W,1%,0402, R1078,R1079,R1080,R181 271071181103 TF041-TH-RES;180 ,1/16W,1% ,060 PR731
271061560306 TF041-TH-RES;56 ,1/16W,5% ,040 R1084,R1096,R239,R240,R241,R2 271071203106 TF041-TH-RES;20K ,1/16W,1% ,060 PR719,PR769
271061561103 TF041-TH-RES;562,1/16W,1%,0402,S R182 271071205102 TF041-TH-RES;2M ,1/16W,1% ,060 PR718
271061592103 TF041-TH-RES;5.9K,1/16W,1%,0402, R1120 271071213104 TF041-TH-RES;21.5K,1/16W,1% ,060 PR72,PR735
271061612101 TF041-TH-RES;6.19K,1/16W,1% ,040 PR5 271071228306 TF041-TH-RES;2.2 ,1/16W,5% ,060 PR47,PR71
271061680305 TF041-TH-RES;68,1/16W,5%,0402,SM R436,R437,R440,R445,R452,R453 271071241105 TF041-TH-RES;243,1/16W,1%,0603,S R172
271061681308 TF041-TH-RES;680 ,1/16W,5% ,040 R35 271071242104 TF041-TH-RES;2.49K,1/16W,1% ,060 PR19
271061682304 TF041-TH-RES;6.8K ,1/16W,5% ,04 PR33,R1068,R1069,R400,R401 271071287114 TF041-TH-RES;287K ,1/16W,1% ,060 PR722
271061750105 TF041-TH-RES;75,1/16W,1%,0402,SM R185,R186,R222,R223,R224,R238 271071292101 TF041-TH-RES;2.94K ,1/16W,1% ,06 PR49
122

271071333102 TF041-TH-RES;33K ,1/16W,1% ,060 PR726 272072224405 TF041-TH-CAP;0.22U ,16V ,10%,060 PC106,PC22,PC51,PC52
271071452101 TF041-TH-RES;4.53K ,1/16W,1% ,06 PR29,PR728 272072823406 TF041-TH-CAP;0.082U,CR,16V ,10%, PC25
271071471105 TF041-TH-RES;475 ,1/16W,1% ,040 R173,R174 272073104712 TF041-TH-CAP;0.1U,25V,10%,0603,X C2,PC1,PC10,PC109,PC114,PC33
271071472309 TF041-TH-RES;4.7K ,1/16W,5% ,060 PR6,PR7 272073105404 TF041-TH-CAP;1UF ,25V,10%,0603, PC115,PC116,PC720,PC76,PC761
271071512103 TF041-TH-RES;5.1K ,1/16W,1% ,060 PR768 272075103415 TF041-TH-CAP;0.01U ,50V,10%,060 PC113,PC21
271071641102 TF041-TH-RES;649,1/16W,1% ,0603, R918 272075222407 TF041-TH-CAP;2200P,50V ,10%,0603 PC732
271071662101 TF041-TH-RES;6.65K ,1/16W,1% ,0 PR88 272101015402 TF041-TH-CAP;1U,6.3V,+-10%,0402, C100,C113,C150,C158,C184,C185
271071683103 TF041-TH-RES;68.1K ,1/16W,1% ,06 PR732 272101104442 TF041-TH-CAP;0.1U,CR,10V,10%,040 C1006,C1007,C1008,C1009,C1010
271071711101 TF041-TH-RES;715 ,1/16W,1% ,0603 R177 272101105710 TF041-TH-CAP;1U,6.3V,80-20% ,040 C1003,C208,C3,C401,C420,C421,C
271071974102 TF041-TH-RES;976K ,1/16W,1% ,060 PR721 272101224702 TF041-TH-CAP;0.22U ,10V ,+80-20% C394,C426,C90,C91,PC788,PC95
271072223101 TF041-TH-RES;22K ,1/10W,1% ,0603 PR796 272101474703 TF041-TH-CAP; 0.47U ,CR,10V,+80- C141,C93
271072402211 TF041-TH-RES;40.2K ,1/10W,1% ,06 PR93 272102224401 TF041-TH-CAP;.022U,16V,+-10%,040 C65,C66,C67,C68,C70,C94,PC733
271072611101 TF041-TH-RES;619 ,1/10W,1% ,0603 R952 272103103407 TF041-TH-CAP;0.01U ,CR,25V ,10%, C1020,C1035,C1036,C1037,C1038
271125029102 TF041-TH-RES;.02,1W,1%,RL3720WT- PR24 272105100402 TF041-TH-CAP;10P ,50V ,+-10%,040 C400,C952
271621472306 TF041-TH-RP;4.7K*8,10P,1/32W,5% RP1 272105101313 TF041-TH-CAP;100P ,50V ,5%,0402, C1021,C993,C996,C998
272001106404 TF041-TH-CAP;10U,6.3V ,10%,0805, C1019,C102,C112,C12,C122,C151 272105102421 TF041-TH-CAP;1000P,CR,50V,10%,04 C110,C115,C124,C172,C178,C207
272001106708 TF041-TH-CAP;10U,10V,+80-20%,080 C399,C429,C929,C934,C967,C969 272105103704 TF041-TH-CAP;0.01U ,50V,+80-20%, C346,C419,C422,C866,C870,C871
272002224405 TF041-TH-CAP;0.22U,16V,0805,10%, PC45,PC60 272105150403 TF041-TH-CAP;15P,50V,+-10%,0402, C983,C984
272005105402 TF041-TH-CAP;0.1U,CR,50V,10%,X7R PC102,PC78,PC94 272105220407 TF041-TH-CAP;22P,50V,+-10%,0402, C820,C821,C898,C913,C914,C920
272011106417 TF041-TH-CAP;10U,10V,+/-10%,1206 PC117,PC118,PC39,PC67,PC68,P 272105222304 TF041-TH-CAP;220P ,50V ,5% ,0402 PC29
272013106504 TF041-TH-CAP;10U,25V,+/-20%,1206 PC20,PC5,PC7,PC744,PC746,PC7 272105222504 TF041-TH-CAP;2200P,50V,+-20%,040 C49,C74
272030102411 TF041-TH-CAP;1000P,2KV,10%,1808, C296 272105331303 TF041-TH-CAP;330P,CR,50V,5%,0402 PC731
272071154402 TF041-TH-CAP;0.15U,10V,10%,0603, C398,C428 272105391301 TF041-TH-CAP;390P,CR,50V,5%,0402 C395,C427
272071225406 TF041-TH-CAP;2.2U ,CR,6.3V ,10%, C149,C256,C257,C259,C285,C293 272105392502 TF041-TH-CAP;3900P,50V,+/-20%,04 C912,C940,C941,C942
272071475403 TF041-TH-CAP;4.7U,6.3V,10%,0603, C144,C156,C425,C431,C433,C925 272105471408 TF041-TH-CAP;470P ,50V,10%,0402, C309,C423,C833,C849,C859
123

272105821405 TF041-TH-CAP;820P,50V,+-10%,0402 C1004 284500086004 TF041-TH-IC;LM86 NOPB,MSO8,TEMPE U4
272430227501 TF041-TH-CAP;220uF,2V,±20%,15mo PC70,PC779 284500089004 TF041-TH-IC;LM89-1,TEMPERATURE M U5
272431227551 TF041-TH,CAP;220U,2V,+-20%,9mohm PC84,PC85 284504991002 TF041-TH-IC;LM4991LD,AUDIO AMP,4 U15
272431337540 TF041-TH-CAP;330U,2V,+/-20%,6moh PC41,PC63 284509325001 TF041-TH-IC;ICS9LPR325,CLOCK GEN U707
272601107521 TF041-TH-EC;100U,6.3V,+-20%,9.3* C754,C964,C987,C992 284582563004 TF041-TH-IC;82562GZ,LCI PHY,BGA1 U713
272625470405 TF041-TH-CP;47P*4 ,8P,50V ,10%,1 CP1 286100212002 TF041-TH-IC;TPA0212,AMPLIFIER,TS U720
273000150354 TF041-TH-FERRIET CHIP;120OHM/100 L10,L28,L31,L6,L703,L733,L735, 286100358032 TF041-TH-IC;LMV358MM NOPB,DUAL O U13
273000500183 TF041-TH-FERRITE CHIP;120OHM/100 L11,L12,L13,L14,L15,L16,L17,L1 286104173002 TF041-TH-IC;MAX4173F,I-SENSE AMP PU4
273000500184 TF041-TH-FERRITE CHIP;600OHM/100 L1,L2,L37,L44,L45,L46,L727,L74 286300128001 TF041-TH-IC;OZ128,B1 VERSION,PCI U717
273000500267 TF041-TH-CHOKE COIL;400uH MIN,12 L722 286300594004 TF041-TH-IC;TL594C,PWM CONTROL,S PU1
273000500295 TF041-TH-CHOKE COIL;22UH,+-30%,6 PL702 286302710001 TF041-TH-IC;OZ2710,EXPRESS SWITC U718
273000500308 TF041-TH-CHOKE COIL;0.36UH,1.1mo PL707,PL708 286305508001 TF041-TH-IC;APL5508-25DC-TRL,LDO PU702
273000500315 TF041-TH-CHOKE COIL;1UH,+-20%,3. PL715 286306208002 TF041-TH-IC;ISL6208CBZ-T,PWM DRI PU3,PU5
273000990297 TF041-TH-INDUCTOR;1UH,+-20%,0805 L720 286306227003 TF041-TH-IC;ISL6227CAZ, PWM CONT PU7
273000994008 TF041-TH-INDUCTOR;PCMC063T-2R2MN PL3,PL709 286308562002 TF041-TH-IC; CM8562P,LINEAR REGU PU718
273001050266 TF041-TH-TRANSFORMER;10/100 BASE U710 286369229003 TF041-TH-IC;G692L293Tf,RESET CIR U10
274011431481 TF041-TH-XTAL;14.318MHZ,20PPM,16 X1 286506224001 TF041-TH-IC; ISL6224CAZ,PWM CONT PU714
274018000304 TF041-TH-XTAL;8Mhz,30PPM,16PF,8* X703 288000038001 TF041-TH-CIR;RECEIVER,3P,38KHZ,I U724
274024574001 TF041-TH-XTAL;24.576MHZ,30PPM,16 X704 288100032014 TF041-TH-DIODE;BAS32L,VRRM75V,ME PD2
274025004001 TF041-TH-XTAL;25MHZ,30PPM,20PF,8 X702 288100054035 TF041-TH-DIODE;BAT54C,SCHOTTKY D D1,D11,D2,D7,D8,D9
274032761001 TF041-TH-XTAL;32.768KHZ,10PPM,12 X2 288100099015 TF041-TH-DIODE;BAV99,70V,450MA,S PD1,PD3
281307085005 TF041-TH-IC;NC7SZ08P5,2-INPUT & U2,U701,U703,U716 288100140014 TF041-TH-DIODE;B140,40V,1A,SMA,D PD708,PD709
283468470002 TF041-TH-IC;EEPROM,M93C46-WMN6T, U12 288100541004 TF041-TH-DIODE;BAT54ALT1,COM. AN D12,D13,D16,D19,PD707,PD8
283780430003 TF041-TH-IC;HY5PS561621AFP-25,HY U6,U7,U705,U708,U711,U712,U8 288100701003 TF041-TH-DIODE;BAV70LT1,70V,225M D6,PD705,PD706
284500056001 TF041-TL-IC;ATI-M56P,33X33MM,BGA U709 288104148020 TF041-TH-DIODE;RLS4148,200MA,500 D701
124

288105524006 TF041-TH-DIODE;BZV55-C24,ZENER,5 PD4 291000013044 TF041-TH-CON;HDR,MA,15P*2,88107- J1
288200144029 TF041-TH-TRANS;DTC144WK,NPN,SOT- PQ701,PQ8 291000020227 TF041-TH-CON;HDR,MA,2P*1,1.25MM, J9
288200144030 TF041-TH-TRANS;DDTC144TKA,N-MOSF Q13,Q14,Q16,Q17,Q19,Q22,Q3,Q4 294011200500 TF041-TH-LED;RED,H0.8,0603,LTST- D17
288200144034 TF041-TH-TRANS;DDTA144WKA,PNP,SM PQ705 294011200514 TF041-TH-LED;BLUE,H0.55,LTST-C19 D15,D18,D20,D21,D22
288200604008 TF041-TH-TRANS;FDC604P_NL,P-MOSF PQ710,PQ9 297040100033 TF041-TH-SW;PUSH BUTTOM,5P,SPST, SW1,SW2
288202222021 TF041-TH-TRANS;PMBT2222A,NPN,SOT PQ1 316804300005 TF041-TH-PCB;PWA-Sable GT/M+CD+D R03
288203401003 TF041-TH-TRANS;AO3401,P-MOSFET,S Q1 331000000810 TF041-TL-CON;DVI-I,H2.6,C16205-3 J702
288203409004 TF041-TH-TRANS;AO3409,P-MOS,-2.6 Q706 331000004111 TF041-TH-CON;IEEE1394,MA,4P*1,0. J719
288203413002 TF041-TH-TRANS;AO3413,P-MOSFET,S Q15,Q703,Q708 331000007084 TF041-TH-CON;BATTERY,2.5mm,7A,7P J705
288203415002 TF041-TH-TRANS;AO3415,P-MOSFET,4 PQ722,PU701 331000008124 TF041-TH-CON;STEREO JACK,W/SPDIF J722
288203416001 TF041-TH-TRANS;AO3416,N-MOSFET V PQ712,PQ715 339115000074 TF041-MICROPHONE;-62dB+-2dB,D6.0 MIC1
288204119001 TF041-TH-TRANS;NTMFS4119N,N-MOSF PU719 342687600006 TF041-TH,FINGER;EMI GROUNDING SM TP74,TP75
288204406003 TF041-TH-TRANS;AO4406,N-MOS,.016 PU707,PU708,PU709,PU711,PU7 342687600013 TH041-TH,FINGER;EMI GROUNDING SM TP705,TP79,TP80,TP81
288204409003 TF041-TH-TRANS;AO4409,P-MOSFET,S PQ709 342804300004 TF041-STAND OFF;MDC,M2.0 H6MM,SA MTG701,MTG702
288204419002 TF041-TH-TRANS;AO4419,P-MOSFET,9 PQ10,PQ706 342804300005 TF041-STAND OFF;MINIPCI EXP,H4.3 MTG703,MTG704,MTG705,MTG7
288204430004 TF041-TH-TRANS;AO4430,N-MOS,18A, PU705,PU706,PU710,PU712,PU7 361200003064 TF041-SOLDER PASTE;SN96.5/AG3.0/
288206900001 TF041-TH-TRANS;FDS6900AS_NL,34mO PU723 242600000565 TF041-LABEL;BLANK,11*5MM,COMMON
288227002024 TF041-TH-TRANS;2N7002LT1,N-CHANN PQ16,PQ17,PQ18,PQ19,PQ2,PQ2 242600000562 TF041-LABEL;6*6MM,GAL,BLANK,COMM
291000000054 TF041-TH-CON;WTB,S/T,12P,0.8MM,H J713 242600000632 TF041-LABEL;27*7MM,XF-5811;POLYI
291000000817 TF041-TH-CON;WTB,8P,1.0MM,H2.2,R J7 242600000560 TF041-LABEL;PAL,20*5MM,COMMON
291000002303 CON;3 IN 1 REVERSE TYPE,23P,SMT, J718 242600000566 TF041-LABEL;BLANK,7MM*7MM,PRC
291000002605 TF041-TH-CON;26P,1MM,H5.4,175901 J8 361200001024 TF041-CLEANNER;YC-336,LIQUID,STE
291000004781 TF041-TH-CON;S/T,478P,1.27MM,H4. U704 291000020001 TF041-TH-CON;HDR,1.25MM,85204-04 J11,J708
291000005201 TF041-TH-CON;S/T,52P,0.8MM,H7.2, J714,J717 284500883002 TF041-TH-IC,ALC883-GR,AUDIO CODE U722
291000012612 TF041-TL-CON;HDR,ACES,85202-2602 J4 291000002205 TF041-TH-CON;SATA HDD,FM,15P+7P, J715
125

291000151220 TF041-TH-CON;FPC/FFC,12P,0.5MM,H J6 284500945001 TF041-TH-IC;945PM,NORTH BRIDGE,3 U706
291000622026 TF041-TH-DIMM SOCKET;DDR2,200P,0 J712 288247081001 TF041-TH-TRANS;NTMFS4708NT1G,POW PU722
271071753102 TF041-TH-RES;75K ,1/16W,1% ,060 PR76 291000010229 TF041-TH-CON;HDR,MA,2P*1,1.25MM, J2,J706
271071473103 TF041-TH-RES;47K ,1/16W,1% ,060 PR78 291000010327 TF041-TL-CON;HDR,MA,3P*1,1.25MM, J704
272003107501 TF041-TH-EC;100U,25V,20%,D6.3,L8 PC745 291000001104 TF041-TH-CON;INVERTER,1.0mm,1A,1 J3
272075471415 TF041-TH-CAP;470P ,50V,10%,0603, PC105 291000011504 TF041-TH-CON;HDR,MA,15P*2,1MM,H4 J707
272072473414 TF041-TH-CAP;.047U,16V ,10%,0603 PC107,PC11 291000810003 TF041-TH-CON;PHONE JACK,2 IN 1,7 J709
272075102419 TF041-TH-CAP;1000P,CR,50V,10%,06 PC103 331040050029 TF041-TH-CON;CDROM,C1240T-250A1- J710
286388550001 TF041-TH-IC;ISL88550A,PWM,28 LD PU9 288204702004 TF041-TH-TRANS;AO4702, N-MOSFET, PU6
288100034012 TF041-TH-DIODE;SSA34,40V,3A,SMA PD5,PD6,PD701,PD702,PD703,PD 272030102414 TF041-TH-CAP;1000P,3KV,10%,1808, C168,C170
271071103118 TF041-TH-RES;10.5K,1/16W,1% 0603 PR105 273000500309 TF041-TH-CHOKE COIL;90OHM/100MHZ L741,L742
286100358026 TF041-TH-IC;LM358,DUAL OP/AMP,SO U1 273000994009 TF041-TH-INDUCTOR;PCMC063T-4R7MN PL712
310142180001 TF041-TH-VARISTOR;18V,3±2 pF,≦ D27,D28 271072422101 TF041-TH-RES;4.22K,1/10W,1%,0603 PR730,R426
271071104108 TF041-TH-RES;100K ,1/16W,1% ,060 PR44,PR60,PR77 291000920610 TF041-TH-CON;STEREO JACK,6P,W9.5 J720,J721
272421476513 TF041-TH-CAP;47U,6.3V,±20%,TCJT C442 481806000001 TF041-F/W ASSY;SYS/VGA BIOS,8258 U14
272105120310 TF041-TH-CAP;12P ,CR,50V ,5% ,0 C363,C364 273000610037 TF041-TH,FERRITE CHIP;120OHM/100 PL1,PL2,PL4,PL701,PL703,PL70
271071357213 TF041-TH-RES;35.7K,1/16W,1% ,060 PR106 622200030002 PE FILM;SKIN,PACKING,PRC
271071304104 TF041-TH-RES;300K ,1/16W,1% ,060 PR38 622200000025 TAPE;SOLDER PREVENT,1/2,LL-N15A3
286306260002 TF041-TH-IC;ISL6260,IMVP-VI,QFN4 PU2 331000016033 TF041-TH-CON;R/A,DIP TYPE,2mm,3A PJ701
271061332317 TF041-TH-RES;3.3K ,1/16W,5% ,040 PR798 343804300006 TF041-HEATSINK-SOUTH/CP-SABLE-GT
291000622025 TF041-TH-DIMM SOCKET;DDR2,200P,0 J711 346804300008 TF041-INSULATOR;EXP CARD,MB,SABL
271061243120 TF041-TH-RES;24.9K,1/16W,1%,0402 PR784 346804300009 TF041-INSULATOR;MINIPCI EXP,MB,S
271072338101 TF041-TH-RES;3.3,1/10W,1%,0603,S PR99 346804300010 TF041-INSULATOR;DDR,MB,SABLE GT
271071332102 TF041-TH-RES;3.3K ,1/16W,1% ,060 PR100 346804300012 TF041-INSULATOR;SPEAKER,SLD,MB,S
284500007017 TF041-TH-IC;ICH7M,SOUTH BRIDGE,3 U719 346804300013 TF041-INSULATOR;CHP,SABLE GT
126

346804300029 TF041-INSULATOR;SAFETY-MDC,SABLE 272005105402 TF041-TH-CAP;0.1U,CR,50V,10%,X7R FPC709,FPC725
346806000008 TF041-SPONGE;RTC BATTERY,8258D 272011106417 TF041-TH-CAP;10U,10V,+/-10%,1206 FPC708,FPC718
348205015030 TF041-GASKET;2,05,015,030 272013106504 TF041-TH-CAP;10U,25V,+/-20%,1206 FPC703,FPC704,FPC705,FPC706
370102010611 TF041-SPC-SCREW;M2L6,K-HD(+1),D 272071475406 TF041-TH-CAP;4.7U,10V,10%,0603,X FPC711,FPC712
371102010310 TF041-SCREW;M2L3,K-HD(+),D3.8,t= 272072224405 TF041-TH-CAP;0.22U ,16V ,10%,060 FPC731
371102010521 TF041-SCREW;M2L5,BIN(+1),D4.1,t1 272073104712 TF041-TH-CAP;0.1U,25V,10%,0603,X FPC1,FPC707,FPC727
346806000007 TF041-INSULATOR;MB,TP,8258D 272075271408 TF041-TH-CAP;270P ,50V,+-10%,060 FPC722,FPC723
346806000023 TF041-SPONGE;MODEM PORT,8258D 272075470315 TF041-TH-CAP;47P ,CR,50V ,5%,060 FPC733
348205015010 TF041-GASKET;2,05,015,010 272101015402 TF041-TH-CAP;1U,6.3V,+-10%,0402, FPC721,FPC724
348205035015 TF041-GASKET;2,05,035,015 272101016401 TF041-TH-CAP;.1U ,CR,10V,10%,04 FPC710
346806000025 TF041-INSULATOR;MB,DDR,8258D 272101105710 TF041-TH-CAP;1U,6.3V,80-20% ,040 FC703,FC704
411806000017 TF041-PWA;PWA-8258D/DD-INTERSIL 272102104708 TF041-TH-CAP;0.1U ,16V,+80-20%, FC1,FPC715,FPC716,FPC728
411806000019 TF041-PWA;PWA-8258D/DD-INTERSIL 272105102421 TF041-TH-CAP;1000P,CR,50V,10%,04 FPC702,FPC717,FPC732
271013221302 TF041-TH-RES;220 ,1/4W,5% ,1206 FPR1,FPR710 272105103704 TF041-TH-CAP;0.01U ,50V,+80-20%, FPC701
271045087104 TF041-TH-RES;.008 ,1W ,1% ,2512, FPR701,FPR704 272105471408 TF041-TH-CAP;470P ,50V,10%,0402, FC701,FC705
271061000003 TF041-TH-RES;0 ,1/16W,0402,SM FR702,FR704 272105826402 TF041-TH-CAP;82P ,50V ,10%,0402, FC2,FC3,FC4,FC5,FC7,FC8
271061100312 TF041-TH-RES;10 ,1/16W,5% ,040 FPR707 272431157520 TF041-TH-CAP;150U,KOCAP,6.3V,20% FC702,FC706
271061101109 TF041-TH-RES;100 ,1/16W,1% ,040 FR1,FR16,FR17 273000150354 TF041-TH-FERRIET CHIP;120OHM/100 FL701,FL702
271061103307 TF041-TH-RES;10K ,1/16W,5% ,040 FPR703,FR2,FR701,FR73 273000500184 TF041-TH-FERRITE CHIP;600OHM/100 FL2,FL3
271061104306 TF041-TH-RES;100K ,1/16W,5% ,040 FPR724,FPR725 273000994023 TF041-TH-INDUCTOR;1.8UH,20%,1608 FL1,FL6,FL7
271061105307 TF041-TH-RES;1M ,1/16W,5% ,040 FPR723,FPR727 286309702004 TF041-TH-IC;RT9702APB,POWER DIST FU701,FU702
271061750105 TF041-TH-RES;75,1/16W,1%,0402,SM FR10,FR11,FR7 288100140014 TF041-TH-DIODE;B140,40V,1A,SMA,D FPD701,FPD702
271071228306 TF041-TH-RES;2.2 ,1/16W,5% ,060 FPR713,FPR720 288227002024 TF041-TH-TRANS;2N7002LT1,N-CHANN FPQ1,FPQ2,FPQ701,FPQ702
271071304104 TF041-TH-RES;300K ,1/16W,1% ,060 FPR732 294011200514 TF041-TH-LED;BLUE,H0.55,LTST-C19 FD6,FD7
271071394305 TF041-TH-RES;390K ,1/16W,5% ,060 FPR731 297040100033 TF041-TH-SW;PUSH BUTTOM,5P,SPST, FSW2,FSW3
127

312374706131 TF041-TH-EC;470U,6.3V,20%,D8.0,L FPC714,FPC719 365350000049 TF041-SOLDER WIRE;RMA98SUPER,M70
316804300004 TF041-TH-PCB;PWA-Sable GT/DD-Int R01 365350000004 SOLDER WIRE;LEAD_FREE,ECO,RMA98S
242668300017 LABEL;4*3MM,HI-TEMP,260'C,HOPE 297140200013 TF041-TH-SW;COVER SWITCH,SPST,.1 FSW1
271061302104 TF041-TH-RES;3K,1/16W,1%,0402,SM FPR729 331000016032 TF041-TH-CON;V/T,DIP TYPE,2mm,3A FPDJ701
273000994009 TF041-TH-INDUCTOR;PCMC063T-4R7MN FPL701,FPL704 242600000566 TF041-LABEL;BLANK,7MM*7MM,PRC
331000008134 TF041-TH-CON;R/A,4P*2,2MM,H15.64 FJ702,FJ704 346806000009 TF041-INSULATOR;SPEAKER TRB,SLD,
291000000713 TF041-TH-CON;MINI DIN,7P,R/A,C10 FJ701 348110010010 TF041-GASKET;1,10,010,010
288206900001 TF041-TH-TRANS;FDS6900AS_NL,34mO FPU701,FPU702 348210030010 TF041-GASKET;2,10,030,010
273000500309 TF041-TH-CHOKE COIL;90OHM/100MHZ FL4,FL5,FL8,FL9 346806000011 TF041-INSULATOR;TRBOARD,SOLDER,8
271071100103 TF041-TH-RES;10 ,1/16W,1% ,060 FPR706 346806000015 TF041-SPONGE;POWER LED,8258D
310142180001 TF041-TH-VARISTOR;18V,3±2 pF,≦ FD13,FD14 340804300009 TF041-SPEAKER ASSY;L,VECO,SABLE
271071000312 TF041-TH-RES;0 ,1/16W,5% ,060 FR20,FR21 340804300011 TF041-SPEAKER ASSY;R,VECO,SABLE
271071203106 TF041-TH-RES;20K ,1/16W,1% ,060 FPR717 340806000003 TF041-COVER ASSY;KB,8258D
271071114104 TF041-TH-RES;110K,1/16W,1% 0603, FPR716 340806000004 TF041-COVER ASSY;8258D
272075561405 TF041-TH-CAP;560P ,CR,50V ,10%,0 FPC734 340806000005 TF041-COVER ASSY;CPU,8258D
286306232002 TF041-TH-IC;ISL6232,PWM ,QSOP,28 FPU703 340806000006 TF041-COVER ASSY;HDD,8258D
242600000562 TF041-LABEL;6*6MM,GAL,BLANK,COMM 340806000007 TF041-HOUSING ASSY;8258D
361200001024 TF041-CLEANNER;YC-336,LIQUID,STE 340806000008 TF041-WOOFER ASSY;8258D
361200003064 TF041-SOLDER PASTE;SN96.5/AG3.0/ 340806000009 TF041-BRACKET ASSY;TP,8258D
271061107412 TF041-TH-RES;107K,1/16W,1%,0402, FPR719 342803700011 TF041-STANDOFF;IO DVI,8090
271061333103 TF041-TH-RES;33K ,1/16W,1% ,040 FPR718 344806000014 TF041-COVER;HINGE,R,8258D
291000010229 TF041-TH-CON;HDR,MA,2P*1,1.25MM, FJ1 344806000015 TF041-COVER;HINGE,L,8258D
291000011504 TF041-TH-CON;HDR,MA,15P*2,1MM,H4 FJ703 370102030305 TF041-SPC-SCREW;M2L3,K-HD(+1)D3.
331910000012 TF041-TH-CON;DC POWER JACK,2DC-G FPJ701 370102610408 TF041-SPC-SCREW;M2.6L4,NIW,K-HD,
273000610037 TF041-TH,FERRITE CHIP;120OHM/100 FPL702,FPL703 370102631204 TF041-SPC-SCREW;M2.6L6,K-HD,NIW/
128

371102010263 TF041-SCREW;M2L2.5,K-HD(+1),D4.0 271071224305 TF041-TH-RES;220K ,1/16W,5% ,060 R21
422806000002 TF041-WIRE ASSY;BLUE,BILTN,MPT,8 271071303103 TF041-TH-RES;30K,1/16W,1%,0603,S R1
422806000004 TF041-FFC;TP,8258D 271071333102 TF041-TH-RES;33K ,1/16W,1% ,060 R7
371103010661 TF041- SCREW;M3L6,K-HD(+2),D6.35 271071364102 TF041-TH-RES;360K ,1/16W,1%,060 R6
346804300031 TF041-AL-FOIL;KB,SABLE GT 271071395101 TF041-TH-RES;3.9M ,1/16W,1% ,060 R9
422804300014 TF041-WIRE ASSY;MDC-MODEM,ISMT,S 271071591103 TF041-TH-RES;590,1/16W,1%,0603,S R15
422804300022 TF041-WIRE ASSY;HW SIGNAL,MB TO 271071823106 TF041-TH-RES;82K,1/16W,1%,0603,S R2
422804300035 TF041-WIRE ASSY;TV,PENG TANG,SAB 272003105402 TF041-TH-CAP;1U ,CR,25V ,10%,0 C7
371102610252 TF041-SCREW;M2.6L2.5,K-HD(+1),D4 272010181303 TF041-TH-CAP;180P,2KV,5%,1206,NP C3
344806000023 TF041-DUMMY CARD;NEWCARD,8258D 272023106505 TF041-TH-CAP;10U,25V,M,1210,T2.5 C1
412806000002 TF041-PCB ASSY;FAX MODEM 56K,145 272030000301 TF041-TH-CAP;15P,3KV,5%,1808,NPO C4
343804300002 TF041-SPRING SCREW;HEATSINK;SABL 272071105411 TF041-TH-CAP;1U ,10V ,10%,0603,X C13
343804300005 TF041-SPRING SCREW;HEATSINK;NORT 272072105403 TF041-TH-CAP;0.1U ,CR,16V,10%,0 C15,C8
340806000014 TF041-HEATSINK ASSY;CPU,MPT,8258 272072224405 TF041-TH-CAP;0.22U ,16V ,10%,060 C9
413000021237 TF041-TFT LCD;B154EW01 V.8,15.4" 272072473409 TF041-TH-CAP;0.047U,16V ,10%,060 C14
412806000001 TF041-PCB ASSY;D/A BD,DA-1A08-D1 272073105404 TF041-TH-CAP;1UF ,25V,10%,0603, C2
365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/CU0. 272073223408 TF041-TH-CAP;0.022U,CR,25V ,10%, C16
411806000004 TF041-PWA;PWA-8X58 I/V BD,DA-1A0 272073332405 TF041-TH-CAP;3300P,CR,25V ,10%,0 C12
242804400009 TF041-TH-LABEL;BAR CODE,20*10,BL 272073682404 TF041-TH-CAP;6800P,CR,25V ,10%,0 C6
271071000312 TF041-TH-RES;0 ,1/16W,5% ,060 R5 272075103414 TF041-TH-CAP;0.01U ,CR,50V ,10%, C5
271071103310 TF041-TH-RES;10K ,1/16W,5% ,060 R4 272075150308 TF041-TH-CAP;15P ,CR,50V ,5% ,0 C11
271071104108 TF041-TH-RES;100K ,1/16W,1% ,060 R8 272075181308 TF041-TH-CAP;180P ,50V ,5% ,0603 C10
271071105312 TF041-TH-RES;1M ,1/16W,5% ,060 R12 273001050279 TF041-TH-XFMR;CI8.5,20T/2000T,16 T1
271071183103 TF041-TH-RES;18K ,1/16W,1% ,060 R20 286009910003 TF041-TH-IC;OZ9910S,CCFL CTRL ,S U2
271071184304 TF041-TH-RES;180K ,1/16W,5% ,060 R14 288100099015 TF041-TH-DIODE;BAV99,70V,450MA,S D1,D2
129

288206602003 TF041-TH-TRANS;AO6602L,N&P-MOSFE U1,U3 370102010207 TF041-SPC-SCREW;M2L2,NIW/NLK,K-H
291000020229 TF041-TH-CON;HDR,MA,2P*1,3.5MM,R CN2 340806000011 TF041-BEZEL ASSY;GBAS,D-D+R9,UJ8
291000021109 TF041-TH-CON;HDR,MA,11P*1,ACES,8 CN1 346803400016 TF041-INSULATOR;BEZEL,8050QR
295000010397 TF041-TH-FUSE;FAST,1.5A,63VDC,12 F1 346800200015 TF041-MYLAR BEZEL,POLARIS
316681300005 TF041-PCB;PWA-8050 INVERTER BD,G R0C 332800003018 TF041-POWER CORD;250V/2.5A,3P,LP
361200003064 TF041-SOLDER PASTE;SN96.5/AG3.0/ 242670800148 TF041-LABEL;WINXP,ARTEMIS
340804300002 TF041-HINGE;L,JARLLY,SABLE GT 242679900009 TF041-LABEL;BAR CODE,(25*10MM)*1
340804300004 TF041-HINGE;R,JARLLY,SABLE GT 242806000007 TF041-LABEL;NON-BRAND,RATING,825
340806000001 TF041-COVER ASSY;LCD,8258D 442687900007 TF041;AC ADPT ASSY;19V,4.74A,DEL
340806000002 TF041-HOUSING ASSY;LCD,8258D 531080830004 TF041-KBD;88,UI,K011818P5,8350MP
342804300001 TF041-BRACKET;LCD,R,SABLE GT 565180600001 TF041-S/W;CD ROM,SYSTEM DRIVER,8
342804300002 TF041-BRACKET;LCD,L,SABLE GT 561580600001 TF041-MANUAL;QSG,EN,N-B,8258D
370102010317 TF041-SCREW;M2L3,K-HD(+1),D3.3,T 441806000002 TF041-BATT ASSY;LI-ION,11.1V/4.4
370102610408 TF041-SPC-SCREW;M2.6L4,NIW,K-HD, 222687630001 TF041-PE BUBBLE BAG;BATTERY,GRAM
370102631204 TF041-SPC-SCREW;M2.6L6,K-HD,NIW/ 225680620003 TF041-TAPE;ADHESIVE,DOUBLE-FACE,
371102010263 TF041-SCREW;M2L2.5,K-HD(+1),D4.0 225686920001 TF041-TAPE;INSULATING,POLYESTER
422804300003 TF041-WIRE ASSY;LCD WXGA,YI YI,S 225686920002 TF041-TAPE;ADHENSIVE,DOUBLE-FACE
422804300007 TF041-WIRE ASSY;INVERTER,YI YI,S 242683200024 TF041-LABEL;5*20,BLANK,COMMON
346802800025 TF041-INSULATOR;INVERTER,LCD,865 242686000009 TF041-LABEL;LOT NUMBER,HOOK
346802800016 TF041-MYLAR;COVER,LCD,8650 242687600004 TF041-LABEL;MIRRIR PAPER,WHITE,E
422803700012 TF041-WLEN ASSY,CABLE,8090 242806000003 TF041-LABEL;BATT,LI-ION,11.1V/4.
370103011402 TF041-SPC-SCREW;M3L3,NIW,K-HD(+) 333020000025 TF041-SHRINK TUBE;300V,125,I.D=2
340806000013 TF041-SHIELDING ASSY;HDD,8258D 333025000015 TF041-SHRINK TUBE;300V,125,I.D=2
523410484035 TF041- 8X Dual DVD R9 DEVICE,UJ8 338536010059 TF041-BATTERY;LI,3.6V/2.2AH,CGR1
342672200010 TF041-BRACKET;CD-ROM,8500 342686000018 TF041-TH-CONTACT PLATE;W5L63T0.1
130

342686900015 TF041-CONTACT PLATE;W5L63T0.13mm 242804400010 TF041-TH-LABEL;BAR CODE,20*5,BLA
342801200002 TF041-CONTACT PLATE;W5L27T0.13,T 271045059102 TF041-TH-RES;0.050,1W, 1%,2512,S R24,R24A,R24C
344806000013 TF041-COVER;BATTERY,8258D 271048107101 TF041-TH-RES;0.010,2W,1%,2512,SM R6
344806000022 TF041-HOUSING;BATTERY,8258D 271071000312 TF041-TH-RES;0 ,1/16W,5% ,060 C16,R31
346683200043 TF041-INSULATOR;5,BATTERY ASSY ; 271071101309 TF041-TH-RES;100 ,1/16W,5% ,060 R11,R12,R14,R15,R16,R20,R21
346686000020 TF041-INSULATOR;BATT ASSY,ONE RO 271071103310 TF041-TH-RES;10K ,1/16W,5% ,060 R5,R7,R8
346686900016 TF041-INSULATOR;BATT ASSY,BATT+, 271071104108 TF041-TH-RES;100K ,1/16W,1% ,060 R18,R22,R23,R9
346686900018 TF041-INSULATOR;BATT,ASSY,L129W1 271071105312 TF041-TH-RES;1M ,1/16W,5% ,060 R10,R3
346686900019 TF041-INSULATOR;FIBRE,T=1.2mm,L= 271071201306 TF041-TH-RES;200 ,1/16W,5% ,060 R1A,R1B
346686900020 TF041-INSULATOR;FIBER,T=0.25,2CE 271071204104 TF041-TH-RES;200K ,1/16W,1% ,060 R17B
361400004013 TF041-ADHESIVE;ABS+PC PACK,G485, 271071224305 TF041-TH-RES;220K ,1/16W,5% ,060 R1
361400004017 TF041-ADHESIVE;HEAT,TRANSFER,ES2 271071331306 TF041-TH-RES;330 ,1/16W,5% ,060 R25
411806000007 TF041-PWA;PWA-8X58/BATT,LI,PANAS 271071494101 TF041-TH-RES;499K ,1/16W,1% ,060 R17A
310111103041 TF041-THERMISTOR;10K,1%,RA,DISK, RT1 272073105404 TF041-TH-CAP;1UF ,25V,10%,0603, C14A,C14B,C4A,C4B
332100020010 TF041-WIRE;#20,UL1007,125MM,BLAC CN5 272073226401 TF041-TH-CAP;.22U ,25V ,10%,0603 C1,C2,C20A,C24,C25
332100020014 TF041-WIRE;#20,UL1007,L=93.5MM,R CN7 272075010401 TF041-TH-CAP; 0.001U CR 50V 10% C13
332100026018 TF041-WIRE;#26,UL1007,90mm,BLUE, CN2 272075102424 TF041-TH-CAP ;0.1U CR 50V 10% 06 C10,C11,C12,C15,C3,C5,C6,C7,C8
332110026167 TF041-WIRE;#26,UL1007,40MM,ORANG CN3 272075470407 TF041-TH-CAP; 0.0047U CR 50V 10% C4
333020000026 TF041-SHRINK TUBE;UL,600V,105'C, 283240260001 TF041-TH-IC;EEPROM,M24C02-WMN6T, IC2
335152000127 TF041-TH-FUSE;LR4-73X,POLY SWITC 286002040002 TF041-TH-IC;BQ2040,GAS GAUGE,SO, IC1
335152000128 TF041-FUSE; 128 DC-7A/50V 139 ℃, F2 286301414005 TF041-TH-IC;MM1414,PROTECTION,TS IC4
335152000134 TF041-FUSE;THERMAL FUSE,G7F510,9 286400812001 TF041-TH-IC;S-812C,DECECTOR,SOT- IC3
361400003017 TF041-JET-MELT ADHESIVES;3478-Q, 288100056026 TF041-TH-DIODE;UDZ5V6B-F,ZENER,U ZD3,ZD4
365350000009 LF-SOLDER WIRE;SN96.5/AG3.0/CU0. 288100717001 TF041-TH-DIODE;SDMG0340LA,SCHOTT D3
411802800040 TF041-PWA;PWA-8650/BATT,LI,3S2P, 288101355004 TF041-TH-DIODE;1N4448HWS-F,80V,1 D2
131

288111544002 TF041-TH-DIODE;S1G-F,400V,1.0A,S D1
288200144035 TF041-TH-TRANS;DDTA144EKA,PNP,SM Q1
288204409003 TF041-TH-TRANS;AO4409,P-MOSFET,S Q3,Q5
316805500002 TF041-PCB;PWA-8200/BATTERY BD,G R0C
361200003064 TF041-SOLDER PASTE;SN96.5/AG3.0/
331000007063 TF041-CONNECTOR;7 PIN,DIP,ALLTOP CON
221802820001 TF041-CARTON;EZ PACKING,8650
221802850004 TF041-CARD BOARD;TOP/BTM,8650
221802850001 TF041-CARD BOARD;FRAME,8650
221802850002 TF041-PARTITION;EZ IN CARTON,865
224685330001 TF041-PALLET;1250*1080*130,3D-Ar
227806000001 TF041-END CAP;L/R,8258
222667220005 TF041-PE BAG;L560XW345,CERES
222803410001 TF041-PROTECTING CLOTH;LCD,BenQ,
242600000559 TF041-LABEL;BAR CODE,125*65,COMM
221802850003 TF041-PARTITION;PALLET,8650
222685320003 TF041-PE BAG;120x170MM,W/SEAL,3D
222300820002 TF041-PE BAG;50*70MM,W/SEAL,COMM
222680830001 TF041-PE BUBBLE BAG;300X150mm,25
222672730003 TF041-PE BUBBLE BAG;250*240mm,AM
421687800001 TF041-CABLE ASSY;PHONE LINE;UK-6
565180340001 TF041-S/W;CD*1,DVD,WIN-DVD,INTER
565180340002 TF041-S/W;CD-ROM,NERO
370102030305 TF041-SPC-SCREW;M2L3,K-HD(+1)D3.
412600000048 TF041-PCB ASSY;BLUETOOTH,GUBTCR4 P/N: 526280600015
132
11. Reference Material
Intel Yonah CPU Intel, INC
Intel 915PM North Bridge Intel, INC
Intel ICH7-M South Bridge Intel, INC
Winbond W83L951DG KBC Winbond, INC
8258D Hardware Engineering Specification Technology Corp/MITAC
Explode Views Technology Corp/MITAC

SERVICE MANUAL FOR 8258D
Sponsoring Editor : Ally Yuan
Author : Sanny Gao
Publisher : MiTAC Technology Corp.
Address : No.269, Road 2, Export Processing Zone, Kunshan, P.R.C
Tel : 086-512-57367777 Fax : 086-512-57385099
First Edition : Apr.2006
E-mail : Ally.Yuan @ mic.com.tw
Web : http: //www.mitac.com http: //www.mtc.mitacservice.com

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What components does the service manual cover?

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SERVICE MANUAL FOR

1. Hardware Engineering Specification …………………………………………………………………… 4

2. System View and Disassembly ………………………………………………………………………….. 29

2.1 System View ……………………………………………………………………………………………………………. 29

3. Definition & Location of Connectors/Switches ………………………………………………………… 51

4. Definition & Location of Major Components ………………………………………………………….. 56

4.1 Mother Board …………………………………………………………………………………………………..……… 56

5. Pin Description of Major Component …….……………………………………………………………. 58

5.1 Intel Yonah Processor CPU ……..……………………………………………………………………………………. 58

6. System Block Diagram …………………………………………………………………………………… 80

7. Maintenance Diagnostics ………………………………………………………………………………… 81

7.1 Introduction ……………………………………………………………………………………………………………. 81

8. Trouble Shooting ………………………………………………………………………………………… 84

8.1 No Power ………………………………………………………………………………………………………………. 86

9. Spare Parts List ………………………………………………………………………………………….. 121

10. System Exploded Views ………………………………………………………………………………... 133

11. Reference Material ………………………………………………………………………………….….. 135

1. Hardware Engineering Specification

1.1.1 General Description

1.2 System Overview-1

Chipset North Intel945PM

1.2 System Overview-2

1.2 System Overview-3

1.3 System Architecture

1.3.1 Function Description

Intel Mobile Yonah processor

• First dual core processor for mobile

• Micro-FCPGA and Micro-FCBGA package technologies

1.3.1.2 Core Logic

• Host interface supports 533/667 MHz processor system bus support

• Direct Media Interface (DMI)

• ACPI 2.0 support

• Package Micro-FCBGA 1446 balls

• PCI Express interface

• PCI 2.3 interface (6 PCI bus master support)

1.3.1.3 VGA ATI M56

PCI Express interface

Frame buffer memory interface

Integrate dual-link LVDS/TMDS transmitter interface

Digital video output interface

Support turbo cache function

Configurable LVDS/TMDS transmitter interface

Video DACs and PLL analog signal

Power rail interface

• Support DDR2 533/667 MHz SO-DIMM expandable to 2 GB (2 DDR2-SO-DIMM slots)

1.3.1.5 I/O Ports

• Standard DVI compatible port

Figure 1-1 DVI connector

7 Pins S-video port for TV-Out

• Support up 1024*768 resolution

• Support PAL and NTSC system

• Connection to modem daughter board connector

• Support wake-up on-LAN function in system enter to S3

Card Reader Port

IEEE 1394a Port