A) COMPUERTAS EXPLICACION

TOTEM POLE

R1(1)

R1
1k

Q1
BC548

D1
DIODE
?
Q2
BC548

BUFFER

U3:A
1 2
0 ?
74HC07

SCHIMTT TRIGER
R3
10k
U1(V+)

U1
7
1

R2(1)
R2 3
6
10k
2 ?
4
5

LM741

U1(V-)

TRI STATE

1
1

2 3
1 ?
U2:A
74HC125
B) TIEMPO DE PROPAGACION

U1:A(A) U1:A
1 U1:B
3 5 U1:C
2 4 8 U1:D
6 10 12
74HC386 9 11
74HC386 13
U2:A(B) 74HC386
74HC386

U2:A
U2:B A
2
1 5 U2:C
U2:D B
3 4 8
6 10 11
C
74HC02 9 13
74HC02 12
D
74HC02
74HC02

U3:A U3:B U3:C U3:D

74HC04 74HC04 74HC04 74HC04

D) FAN-IN FAN-OUT
U2:D(B)

U1:A(A) U1:A
1 U1:B
A
3 4
2 6
B
5
74HC08
C
74HC08
U1:C
D
9
8
10

74HC08
U1:D
12
11
13

74HC08
U2:A
A
1
3
B
2
C
74HC08
U2:B
D
4
6
5

74HC08
U2:C
9
8
10

74HC08
E) LEYES DE ALGEBRA DE BOOLE

A B C D
0

0
1

U1:A U1:B
74HC04 74HC04
2

U2:A
1
2 12
13 U5:A
2
74HC11 1
U3:A 3
1
3 74HC02 U4:B U4:B(Y)
2 4
6
74HC32 5 ?
U4:A
1 74HC00
3 U3:B
2 4
6
74HC00 5

74HC32

U6:A
1
3
2 U6:B
4
74HC08 6
U3:C 5
9
8 74HC08 U7:A U7:A(Y)
10 1
3
74HC32 2 ?
U3:D
12 74HC32
11
13

74HC32
F) IMPLEMENTACION DE FUNCIONES LOGICAS

Diagrama de tiempos 1

Diagrama de tiempos 2

Diagrama de tiempos 3
Circuito completo
0

0
13

1
U1:D U1:C U1:B U1:A
74HC04 74HC04 74HC04 74HC04
12

2
U4:D
12 U5:B
11 4 U6:A
13 6 1
5 3
74HC08 2
74HC32 U5:C U5:C(Y)
74HC08 9
8
U6:B 10 ?
4
6 74HC32
5

74HC08

U2:A
1 U3:A
3 1
2 3
2
74HC32 U2:C (D0)
74HC08 9
8
U3:B 10 ?
4 U2:B
6 4 U3:C 74HC32
5 6 9
5 8
74HC08 10
74HC32
74HC08

U3:D
12
11
13 U2:D
12
74HC08 11
U4:A 13 U4:B
1 4
3 74HC32 6
2 5
U5:A (D0)
74HC08 74HC08 1
3
U4:C 2 ?
9
8 74HC32
10

74HC08

G) SIMULACION DE ESQUEMAS LAY-OUT

0
13

U1:D U1:C U1:B U1:A

U2:A
1
3
2 U4:A
1 U5:A
4077 3 1
U3:A 2 3
1 2 ?
3 74HC32
2 74HC08

74HC386
Diagrama de tiempos

H) PROBLEMAS DE APLICACIÓN LOGICA

1
13

U1:D U1:C U1:B

U2:A
1 U3:A
3 1
2 3
2 U4:A U4:A(Y)
74HC386 1
74HC08 3
2 ?
U3:B
4 74HC32
6
5

74HC08
U5:A
1
2 12
13 U4:B (D0)
4
74HC11 6
U2:B 5 ?
5
4 74HC32
6

74HC386
Diagrama de tiempos

I) COMPUERTAS TRI-STATE

A B C D
0
0
0
0

10

U3:C(A)
9 8
1

U3:C
74LS125 R15
2 3 1.2k

U4:A R9
74LS126
4

1.2k
U3:B(A) U5:A
5 6 2 3
R17(2)
10

74LS126
U3:B R16 R14(2)
U4:C 74LS125 1.2k
9 8 R17
R14 1.2k
13

13

74LS126
1

1.2k
U1:A(A)
2 3 5 6 12 11 5 6 12 11
?
U1:A U4:B U4:D U6:B U3:D
74LS125 R10 74LS126 R11 R13 R12 74LS126 R18 74LS125 74LS125
1.2k 1.2k 1.2k 1.2k
1.2k
J) COMPUERTAS OPEN-COLECTOR

0 0 0 0
R1(1)
13

1
U1:D U1:C U1:B U1:A
74HC04 74HC04 74HC04 74HC04 R1
510
12

2
U2:A
2
1
3

74LS01

U2:B
5
4
6 (D0)

74LS01
?
U2:C
8
10
9

74LS01

U2:D
11
13
12

74LS01

Diagrama de tiempos
K) APORTE DEL ALUMNO
0

0
13

3
U1:D U1:C U1:B
74HC04 74HC04 74HC04
12

4 U2:A
1
3
2 U3:A
1
74HC32 3
U2:B 2
4
6 74HC08 U3:C U3:C(Y)
5 9
8
74HC32 10 ?
U2:C
9 U3:B 74HC08
8 4
10 6
5
74HC32
74HC08

Diagrama de tiempos
UNIVERSIDAD MAYOR DE SAN ANDRÉS
FACULTAD DE INGENIERÍA
CARRERA DE INGENIERIA ELECTRÓNICA

DOCENTE: Ing. OROPEZA ROBERTO

GRUPO: “D – 16”

LA PAZ-BOLIVIA
2017