UNIT I

Introduction to Embedded Systems.

Core of Embedded System

Characteristics and quality attributes of

embedded systems

What is an embedded system? (Shibu pg. 4)

An Embedded System is an electronic system
designed to perform a specific function and is a
combination of both hardware and firmware
(software).
▪ e.g. Washing machine and Air Conditioner

What is a Firmware? (Shibu pg. 59)

Firmware refers to the control algorithm (Program
instructions) and or the configuration settings that an
embedded system developer dumps into the code
(program) memory of the embedded system.
Criteria General Purpose Computer Embedded system
Contents It is a combination of generic It is a combination of special
hardware and a general purpose purpose hardware and
OS for executing a variety of embedded OS for executing
applications specific set of applications.
OS It contains GPOS It may or may not contain OS
Alterations Applications are alterable by Applications are non-alterable
user by user
Key factor Performance is a key factor Application specific
requirements are key factors
Power More Less
consumption
Response time Not Critical Critical for some applications

Classification of Embedded Systems: (Shibu pg. 6)

On Generation
▪ First, Second, Third and Fourth Generation
▪ 1G-> 8bit Uc; simple H/W and S/W
▪ e.g. digital telephone keypad
▪ 2G-> 8/16bit Uc; they are complex and powerful than 1G Up & Uc
▪ e.g. SCADA systems
▪ 3G->16/32bit Uc; they use DSPs, ASICs etc.
▪ e.g. Robotics etc
▪ 4G-> 32/64bit Uc; they use Soc, Multi-core Up
▪ e.g. smart phones

Classification of Embedded Systems: (Shibu pg 6)

On Complexity & Performance
▪ Small, medium & large scale embedded systems.
▪ Small Scale:
▪ Simple application need; Performance not time-critical; low performance low cost 8/16 bit Up/Uc;
▪ e.g. electronic toy
▪ Medium Scale:
▪ Slightly complex h/w & S/w requirement.: built around medium performance low cost 16/32 bit Uc/Up;
Usually contains OS
▪ E.g. Industrial machines
▪ Large Scale
▪ Highly complex hw/ sw ; built around 32 & 64Bit Risc Uc/Up or PLD etc
▪ Response time is critical.; E.g. Mission Critical applications.

On deterministic Behavior
▪ Applicable for “real time” systems.
▪ Task execution of the system may be deterministic or non-deterministic.
▪ Also Based on execution behaviour Real Time embedded systems are divided into hard
real-time and soft real-time.

On Triggering
▪ Embedded systems which are “Reactive” in nature can be based on triggering.
▪ Reactive Systems can be: Event Triggered and Time Triggered.

Applications of Embedded Systems can be
countless (Shibu pg. 8)

Consumer Electronics

Household appliances

Automotive Industry

Home automation and Security system

Telecom

Computer Peripherals

Computer Networking Systems

Healthcare

Banking and Retails

Data Collection / Storage / Representation (Shibu pg. 8)

Collecting data from the sensors, or other analog data capturing
devices. Eg. Digital camera.

Data Communication

Embedded systems used for satellite communications / wifi / Bluetooth
etc

Digital Signal processing

Embedded Systems like hearing aid uses digital signal processing

Monitoring

Embedded Systems used in Health care domain like pulse monitoring or
ECG machine etc.

Control

Embedded Systems which use sensors and actuators to control the
environmental changes E.g. Air Conditioners

Application specific user interface

Application specific user interface can be an embedded system used for
a car’s dashboard.

Embedded systems are domain and application
specific and are built around a central core. The
core of the embedded system falls into any of
the following categories:

General purpose and Domain Specific
Processors

Microprocessors

Microcontrollers

Digital Signal Processors

Application Specific Integrated Circuits. (ASIC)

Programmable logic devices(PLD’s)

Commercial off-the-shelf components (COTs)
 General Purpose Computing System Embedded System
A system which is a combination of a generic A system which is a combination of special
hw and a general purpose OS for executing a purpose hw and embedded OS for executing a
variety of applications. specific set of applications.
Contains a GPOS May or may not contain an OS for functioning.
Applications are alterable (i.e. Programmable) Firmwares are pre-programmed and non-
by the user. alterable after production of the device.
Performance is the key deciding factor. Applications specific requirements are the key
deciding factors.
Less / not at all tailored for operating power Highly tailored to take advantage of the power
requirements. saving modes.
Response requirements are not time-critical For certain category of embedded systems
response time is highly critical.
No need to be deterministic in execution Execution behaviour is deterministic for
behaviour embedded systems like Hard Real time
systems.
 Microprocessors Microcontrollers
A silicon chip representing a central processing A highly integrated chip that contains CPU,
unit (CPU), which is capable of performing RAM, Special and General Purpose Register
arithmetic as well as logical operations arrays, on chip ROM/FLASH memory for
according to a predefined set of instructions program storage, timer and interrupt control
units and dedicated I/O ports.
It is a dependent unit, requires CPU and It is self-contained unit and doesn’t depend on
peripheral hardware like external timers, data external peripherals usually for its functioning.
memory chips etc for functioning.
Most of the time general purpose in design and Mostly application-oriented or domain-specific.
operation.
Doesn’t contain built in I/O port to handle Contains built in I/O port to handle individual
individual port pins. port pins.
Targeted for High end market where Targeted for embedded market where
performance is important. performance may or may not be critical
Limited power saving options. Lot of power saving options.
 RISC CISC
Reduced Instruction Set Computing Complex Instruction Set Computing
It contains lesser number of instructions. It contains greater number of instructions.
Orthogonal instruction set (allows each Non-orthogonal set (all instructions are not
instruction to operate on any register and use allowed to operate on any register and
any addressing mode. ) use any addressing mode.)
Operations are performed on registers only, Operations are performed either on registers or
only memory operations are load and store. memory depending on instruction.
A larger number of registers are available. The number of general purpose registers are
very limited.
Programmer needs to write more code to Instructions are like macros in C language. A
execute a task since instructions are simpler programmer can achieve the desired
ones. functionality with a single instruction which in
turn provides the effect of using more simpler
single instruction in RISC.
It is single, fixed length instruction. It is variable length instruction.
With Harvard Architecture Can be Harvard or Von-Neumann Architecture
 Harvard architecture Von-Neumann architecture
It has separate buses for instruction as It shares single common bus for
well as data fetching. instruction and data fetching.
Easier to pipeline, so high performance Low performance as compared to
can be achieve. Harvard architecture.
Comparatively high cost. It is cheaper.
Since data memory and program Accidental corruption of program
memory are stored physically in different memory may occur if data memory and
locations, no chances exist for accidental program memory are stored physically
corruption of program memory. in the same chip.

Endianness

Endianness specifies the order which the data is stored in the
memory by processor operations in a multi byte system.

Based on Endiannes processors can be of two types: Little
Endian Processors & Big Endian Processors
▪ Little-endian means lower order data byte is stored in
memory at the lowest address and the higher order data
byte at the highest address.
▪ Big-endian means the higher order data byte is stored in
memory at the lowest and the lower order data byte at the
highest address.

Application Specific Integrated Circuits.
(ASIC)

ASICs is a microchip design to perform a specific
and unique applications.

As a single chip ASIC consumes a very small area
in the total system. Thereby helps in the design of
smaller system with high capabilities or
functionalities.

The developers of such chips may not be
interested in revealing the internal detail of it .

Programmable logic devices(PLD’s)

A PLD is an electronic component. It used to build digital circuits which
are reconfigurable.

A logic gate has a fixed function but a PLD does not have a defined
function at the time of manufacture.

PLDs offer customers a wide range of logic capacity, features, speed,
voltage characteristics.

A variety of tools are available for the designers of PLDs which are
inexpensive and help to develop, simulate and test the designs.

PLDs having following two major types:
▪ CPLD(Complex Programmable Logic Device):
▪ CPLDs offer much smaller amount of logic up to 1000 gates.
▪ FPGAs(Field Programmable Gate Arrays):
▪ It offers highest amount of performance as well as highest logic density, the most features.

Advantages of using a PLD:

More flexibility during the design cycle.

Do not require long lead times for prototypes

can be reprogrammed even after a piece of equipment is shipped to a
customer

Commercial off-the-shelf components(COTs)

A Commercial off the Shelf product is one which is
used 'as-is'.

The COTS components itself may be develop
around a general purpose or domain specific
processor or an ASICs or a PLDs.

The major advantage of using COTS is that they are
readily available in the market, a developer can cut
down his/her development time to a great extent

Disadvantage may be that vendor or manufacturer
may discontinue production of a particular COTS
product

Sensors and Actuators

Sensor

A Sensor is used for taking Input from the environment.

It is a transducer that converts energy from one form to
another for any measurement or control purpose
▪ E.g. A temperature sensor

Actuator

Actuator is used for output/to take an action.

It is a transducer that may be either mechanical or
electrical which converts signals to corresponding physical
actions.
▪ E.g. A Relay

Communication Interfaces

Inter Integrated Circuit (I2C) (Shibu pg. 45)

Serial Peripheral Interface (SPI) (Shibu pg. 47)

Universal Asynchronous Receiver Transmitter

(UART) (Shibu pg. 48) (Mazidi pg. 237)

There are two types of quality attributes are:-

Operational Quality Attributes
▪ Response
▪ Throughput
▪ Reliability
▪ Maintainability
▪ Security
▪ Safety

Non-Operational Quality Attributes.
▪ Testability and Debug-ability
▪ Evolvability
▪ Portability
▪ Time to prototype and market
▪ Per unit and total cost

The other embedded systems constitute of components like:

Reset Circuit
▪ The reset circuit ensures that the device is not operational on a high voltage
level where its not guaranteed to operate when in ON state.
▪ The reset signal brings the internal registers and hw system to a known state
where the Uc can operate.

Brownout protection Unit
▪ The brown-out protection circuit prevents the Uc from unexpected program
execution behaviour when the supply voltage to the Uc falls below a specified
voltage.

Oscillator Unit

RTC ( Real Time Clock)

Watchdog Timer
▪ The Watchdog timer monitors the firmware execution and resets the processor
in case the execution time for the task is exceeding the maximum allowed limit.

PCB (Printed Circuit Board)

UNIT – II

Embedded Systems – Application and Domain

Specific

Embedded Hardware

Peripherals

Washing machine is one of the examples of Application specific embedded systems

It contains sensors, actuators, control unit, timers and application-specific user interface
etc.

The basic controls consists of timer, cycle selector mechanism, water temperature selector,
load size selector, start/stop button.

The mechanism includes the motor, transmission, clutch, pump, agitator, inner tub, outer
tub and water inlet valve.

The integrated control panel consists of μc based
board with I/O interface and a control algorithm
running in it.

Input interface consists of wash type selector,
namely Wash, Spin & Rinse, cloth type selector
namely Light, Medium & Heavy, washing time etc.

The output interface consists of LED/LCD displays, status
indication LEDs etc. connected to the μc.

The other types of I/O interfaces are sensor interfaces,
like water temp sensor, water level sensor and other
actuator interfaces including motor control for agitator &
tub movement control, inlet water flow control etc.

The major application domains of embedded systems are consumer, industrial,
automotive, telecom etc.

Automotive Embedded System (AES) are the one where electronics take control over the
mechanical system. Ex. Simple viper control

Some of the uses of embedded controllers in a vehicle are listed below:

Air Conditioner

Engine Control

Fan Control

Headlamp Control

Automatic break system control

Wiper control

Air bag control

Power Windows

AES are normally built around microcontrollers
or DSPs or a hybrid of the two and are generally
known as Electronic Control Units (ECUs).

Types Of Electronic Control Units(ECU):

High-speed Electronic Control Units (HECUs):
▪ HECUs are deployed in critical control units requiring fast
response.
▪ They Include fuel injection systems, antilock brake systems,
engine control, electronic throttle, steering controls,
transmission control and central control units.

Low Speed Electronic Control Units (LECUs):
▪ They are deployed in applications where response time is not so
critical. They are built around low cost microprocessors and
microcontrollers and digital signal processors.
▪ Audio controller, passenger and driver door locks, door glass
control etc.

Automotive Communication Buses

Embedded system used inside an automobile communicate with each other using serial buses.
This reduces the wiring required. Following are the different types of serial Interfaces used in
automotive embedded applications:
▪ Controller Area Network (CAN):
▪ CAN bus was originally proposed by Robert Bosch. It supports medium speed and high speed data
transfer.
▪ CAN is an event driven protocol interface with support for error handling in data transmission.
▪ Local Interconnect Network (LIN):
▪ LIN bus is single master multiple slave communication interface with support for data rates up to 20 Kbps
and is used for sensor/actuator interfacing.
▪ LIN bus follows the master communication triggering to eliminate the bus arbitration problem.
▪ LIN bus applications are mirror controls, fan controls, seat positioning controls
▪ Media-Oriented System Transport(MOST):
▪ MOST is targeted for automotive audio/video equipment interfacing.
▪ A MOST bus is a multimedia fiber optics point–to-point network implemented in a star , ring or
daisy chained topology over optical fiber cables.
▪ MOST bus specifications define the physical as well as application layer , network layer and media
access control.

A memory map is a table that shows the name and address
range of each memory device and peripheral that is located
in the memory space.

A Memory Map is the processor's "address book."

The I/O map contains one entry for each of the peripheral.

To create an I/O map, simply create a table of peripheral
names and address ranges, organized in such a way that the
lowest addresses are at the bottom.

The I/O map is also useful when creating the header file for
your board.

Polling

In this technique the processor polls the device (asks
question) repeatedly at regular intervals to check if
the device has completed the given task or has any
new task to execute.

Interrupts

A peripheral interrupts a processor for some task.

When a fresh interrupt signal is received, the
processor temporarily sets aside its current work and
executes a small piece of software called the interrupt
service routine (ISR). When the ISR completes, the
processor returns to the work that was interrupted.

The Interrupt Map is a table that contains a list of interrupt types and the devices
to which they refer.

In order for the processor to execute the correct ISR, a mapping must exist
between interrupt pins and ISRs (Interrupt Service Routines). This mapping
usually takes the form of an interrupt vector table.

The vector table is usually just an array of pointers to functions, located at some
known memory address. The processor uses the interrupt type (a unique number
associated with each interrupt pin) as its index into this array. The value stored at
that location in the vector table is usually just the address of the ISR to be
executed.

Three main type of memories:

RAM, ROM and Hybrid
RAM ROM Hybrid Memory Devices
(Random Access Memory) (Read only Memory)
Memory can be read and Memory will be read only. Combines both RAM, ROM
written to.
Volatile Memory, retains the Non-Volatile memory, the Non-Volatile memory
contents as long as contents are retained
electricity is supplied. even after electricity is
switched.
Data at any memory location Data at any memory location It has certain features of
can be read or written. can be only read. RAM and some of ROM
Data access to RAM is very Data access to ROM is slow Slower than RAM
fast compared to RAM
Two Types of RAM Three Types of ROM Three Types of Hybrid
a) SRAM (Static RAM) a) Masked ROM Memory Devices.
b) DRAM (Dynamic RAM) b) PROM a) EEPROM
c) EPROM b) Flash
c) NVRAM

Two Types:

SRAM & DRAM

SRAM (Static RAM)

Contents of SRAM are lost after power is off.

DRAM (Dynamic RAM)

Extremely short Data lifetime, even with power.

DRAM Controller is used to refresh and retain the
contents of a DRAM for a longer duration.

Three Types: Masked ROM, PROM, EPROM

Masked ROM:

Hardwired memory devices

Contains Pre-programmed instructions, cannot be
modified or appended, hence low in cost.

PROM (PROGRAMMABLE ROM )

one-time-programmable (OTP) device.

un-programmed state the data is entirely made up of 1’s.

EPROM (ERASABLE-AND-PROGRAMABLE ROM)
Same as PROM, but can be erased and reprogrammed.
Erased by exposing to UV light.

Three Types: EEPROM, Flash Memory & NVRAM

EEPROM

EEPROMs stand for Electrically Erasable and
Programmable ROM.

Erased Electronically, one byte at a time.

Flash

Flash memory devices are high density, low cost,
nonvolatile, fast (to read, but not to write), and
electrically reprogrammable.

Can only be erased one sector at a time.

NVRAM

Stands for Non Volatile RAM, Just as SRAM with Battery Backup

More Expensive than SRAM.

DMA is a technique for transferring blocks of data
directly between two hardware devices.

If DMA controller absent Processor has to transfer the
data between devices.

Working of DMA

The Processor provides the DMA Controller with source
and destination address & total number of bytes of the
block of data which needs transfer.

After copying each byte each address is incremented &
remaining bytes are reduced by one.

When number of bytes reaches zeros the block transfer
ends & DMA Controller sends an Interrupt to Processor.

Memory Testing and its purpose

The purpose of a memory test is to confirm that each storage
location in a memory device is working.

Memory testing is performed to check the address and data
lines are correctly wired and memory chips are working
properly.

The basic idea is to write some data values at each address in
memory and read back to verify. If a value is written at a given
memory location and read back properly then the memory
device passes the test.

Only through careful selection of data values can make sure
passing result to be meaningful. It can be difficult to detect all
memory problems with a simple test.

The wires that connect from microcontroller to Memory chip are:
Address line to select the memory location, Data Line to transfer the data and
Control Line to do read or write operation.

Catastrophic Failure is a memory problem that occurs due to physical and
electrical damage, it is uncommon and easily detectable.

A common source of memory problems is associated with the circuit board.
Typical circuit board problems are:
1. Circuit board wiring between Processor & Memory device.
▪ Usually caused due to an error in design, error in production board,
damaged after manufacturing.
▪ Two wiring problems: Open Wire & Shorted wire.
2. Missing Memory chip.
A missing memory chip is detectable by eyes.
but due to the capacitive nature of unconnected electrical wires, some
memory tests will not detect missing memory chips.
To test it, if we write a value and read it as soon as its written we might not
find that the chip is missing. Instead we will write all values at first and then
sequentially read it back, and if by doing so we get the correct values being
read then we can say the memory chip is intact and not missing.
3. Improperly inserted Memory chip.
The chip will be wrongly inserted or connected.
Will either not be connected to the socket at all or will be connected at the
wrong place
System behaves same as though there is a wiring problem or a missing chip.
Detected by any test.

Strategy for memory testing:

It would be best to have three individual memory tests
▪ A data bus test: Checks electrical wiring problems
▪ Walking 1's test
▪ An address bus test: Checks improperly inserted chips
▪ A device test: Checks to detect missing chips and catastrophic
failures and problems with the control bus wiring
▪ Increment test

These tests have to be executed in a proper order which is:
data bus test first, followed by the address bus test, and then the
device test. That's because the address bus test assumes a
working data bus, and the device test results are meaningless
unless both the address and data buses are known to be good.

Data Bus Test

It is used to check data bus wiring.

In this test we need to confirm that the received data is same as the data sent by processor.

Here we write all possible data values and verify that the memory device stores each one
successfully.

Walking 1’s test: 00000001
▪ This test is used to independently test every bit. 00000010
▪ A single data bit is set to 1 and “walked” through the entire data word. 00000100
▪ If the data bus is working properly the function will return 0.
00001000
▪ Because data bus is being tested any address in the memory will do.
▪ The figure shows consecutive data values for walking 1’s test.
00010000

Address Bus Test. 00100000

It is used to check data bus wiring. 01000000

The address Bus problem leads to overlapping memory locations. 10000000

In the address bus test we need to confirm that each of the address pins can be set to 0 & 1 without affecting any
of the others.

The smallest set of addresses that will cover all possible combinations is the set of “power of two” addresses.

After writing one of the addresses we must check none of the other has been over written.

Device Test

It is used to test the integrity of the memory device.

For thorough and complete device test every memory location has to be visited twice.

The thing to test is that every bit in the device can hold 0 & 1.

A simple increment test for the same is as follows:
▪ The first column represents the memory location.
▪ The second column represents the data that is written at the memory location as given in the
column 1 in incremental fashion.
▪ The third column represents the data in column 2 in inverted format.
▪ During the first pass the data in column 1 is verified and during the second pass data in column
2 is verified.
Address Data 1 Data 2
000h 00000001 11111110
001h 00000010 11111101

002h 00000100 11111011

… … …

0FFh 00000000 11111111


ROM and Hybrid Devices cannot be Re-Written.

Two Techniques used:

Checksums
▪ The checksum of the data in the memory device is computed and stored along with the data. The
moment when we have to confirm the validity of the data, we just have to recalculate the
checksum and compare it with previous checksum. If the two checksums match, the data is
assumed to be valid.
▪ The simplest checksum algorithm is to add up all the data bytes discarding carries.
▪ Usually stored at a fixed location in the memory.
▪ A simple sum-of-data checksum cannot detect many of the most common data errors.

CRC – Cyclic Redundancy Check.
▪ CRC’s are frequently used in Embedded Applications that requires the storage or transmission of
large blocks of data.
▪ A division operation occurs between the message at numerator and the generator polynomial at
denominator. The generator polynomial is a fixed smaller length binary string. The remainder of
the division operation is the CRC Checksum.

Control and status registers are the basic interface between and
embedded processor and peripheral device.

These registers are a part of peripheral hardware and their location size
and individual meanings are feature of the peripheral.
For example, The registers vary from device to device: example the
registers within a serial controller are very different from those in a timer.

Depending upon the design of the processor and target board ,
peripheral devices are located either in the processor’s memory space or
within the I/O space.

It is common for Embedded Systems to include some peripherals of each
type. These are called Memory-Mapped and I/O-mapped peripherals. Of
the two types, memory-mapped peripherals are generally easier to work
with and are increasingly popular.

Memory-mapped control and status registers can be used just like
ordinary variables.

Example TCON, TMOD etc for Timer SCON for Serial Etc.

The goal of designing a device driver is to hide the hardware completely.

There are three benefits of good device driver:

Modularization, it makes the structure of the overall software is easier to
understand.

There exists only one module that interacts directly with the peripheral’s
registers making communication easier.

Software changes that result from hardware changes are localized to the
device driver.

Components of a device driver:

A data structure that overlays the memory-mapped control and status
registers of the device.

A set of variables to track the current state of the hardware and device driver.

Initialize the hardware.

A set of routines that provide an API for users of the device driver.

Interrupt service routines.

It is special purpose hardware that protects the system from
software hangs.

Watchdog timer always counts down from some large
number to zero.

This process takes a few seconds to reset, in the meantime,
it is possible for embedded software to “kick” the watchdog
timer, to reset its counter to the original large number.

If the timer expires i.e. counter reaches zero, the watchdog
timer will assume that the system has entered a state of
software hang, then resets the embedded processor and
restarts the software.