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Microprocessors and Microcontrollers

QUESTION 1:
Which of the following statements is TRUE regarding the directionality of the buses on a
microprocessor that has the following composition?

A0-A7: Dedicated Address Bus

A8-A11: Multiplexed Address/Data Bus

D0-D3: Dedicated Data Bus

a. A0-A7: Unidirectional, A8-A11: Unidirectional, and D0-D3: Bidirectional

b. A0-A7: Bidirectional, A8-A11: Bidirectional, and D0-D3: Unidirectional

c. A0-A7: Bidirectional, A8-A11: Unidirectional, and D0-D3: Bidirectional

d. A0-A7: Unidirectional, A8-A11: Bidirectional, and D0-D3: Bidirectional

Correct Answer: d

Detailed Solution:

Since A0-A7 is a dedicated address bus, it is unidirectional where the address contents are sent
from the microprocessor to the memory unit. However, A8-A11 is bidirectional because of the
fact that it is a multiplexed address/data bus, where both the address and data can be sent
alternately. Similarly, D0-D3 is bidirectional as it is a dedicated data bus.
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QUESTION 2:
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The number range in the decimal number system that can be represented using a 6 bit 2’s
complement representation is

a. -32 to 32

b. -32 to 31

c. -31 to 32

d. -32 to 32

Correct Answer: b

Detailed Solution:

The range of 6-bit 2’s complement number is -32 to 31

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QUESTION 3:
A processor has the size of its Read Only Memory (ROM) to be 8kB. If ROM chips of size 1kb
are only available, how many such chips are required to realize the ROM of the processor?
Also, what is the minimum number of address lines required to realize the ROM? (Notation:
b – bit, B – Byte)

a. 64, 13
b. 8, 13
c. 64, 8
d. 8, 8

Correct Answer: a

Detailed Solution:

8kB (eight kilo bytes) can be written as 8k×8 bits, which is equal to 2 3 ×210×8 bits. If the size of
available ROM chips is 1kb (one kilo bits), which is 210×1 bits, a total of (23×210×8) / (210×1) = 64
such chips is necessary to realize the ROM. Since the number of locations in the ROM is 2 3 ×210,
which is 213, 13 address lines are required to realize the ROM of size 8kB.

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QUESTION 4:
Which of the following sequence of operations conforms to an instruction cycle?

a. Fetch, Execute, Decode

b. Execute, Fetch, Decode

c. Fetch, Decode, Execute

d. Decode, Fetch, Execute

Correct Answer: c

Detailed Solution:

The first operation in an instruction cycle is Fetch, where the processor fetches the instruction,
as well as the corresponding data. The second operation in an instruction cycle is Decode,
where the processor decodes the instruction that has been fetched. The third operation in an
instruction cycle is Execute, where the processor executes the instruction with the instruction
that has been decoded.

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QUESTION 5:
A microprocessor has a 16-bit address bus A15–A0, where A15 is the MSB and A0 is the LSB,
and a 64KB of memory. Unfortunately, two address lines, namely A13 and A6 have become
faulty and are stuck at logic 0. In such a situation, which of the following address locations
cannot be accessed in the memory?

a. 0000H
b. 1FFFH
c. 1F1FH
d. None of the above

Correct Answer: b

Detailed Solution:

Since the address lines A13 and A6 have become faulty and are stuck at logic 0, they can never
be logic 1. Thus, any address value with logic 1 present at these two address lines cannot be
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accessed in the memory. Following enumeration elaborates the address locations of each
option and mentions its accessibility. Here, the bold digits correspond to the address lines A13
and A6. A correct option needs to have at least one of these two values to be logic 1.

Address Range: A15A14A13A12 …. A3A2A1A0

0000H = (0000 0000 0000 0000)2: Accessible

1FFFH = (0001 1111 1111 1111)2: Not Accessible

1F1FH = (0001 1111 0001 1111)2: Accessible

Since the address 1FFFH has logic 1 at the address line A6, it cannot be accessible.

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QUESTION 6:
The decimal equivalent of (F4C)16 is

a. 4214

b. 3916

c. 3924

d. 3950

Correct Answer: b

Detailed Solution:

F × 162 + 4 × 16 + C
= 15 × 256 + 4 × 16 + 12 = 3916
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QUESTION 7:
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A processor has a memory address range of 00000H – 3FFFFH. If the processor has a read only
memory (ROM) of size 64k bytes with a starting address of 0000 H, and assuming that it is
mapped onto a 2-fold folding addressing scheme, determine the range, as well as the size, of
the remaining memory in the processor. Also, determine the number of address lines in the
processor.

a. 10000H – 3FFFFH, 192k bytes, 17

b. 10000H – 3FFFFH, 192k bytes, 18

c. 20000H – 3FFFFH, 128k bytes, 18

d. 20000H – 3FFFFH, 128k bytes, 17

Correct Answer: c

Detailed Solution:

With a starting address of 0000H and a size of 64k bytes, the memory address range of the ROM
is 0000H – FFFFH. Since the ROM is mapped using a 2-fold folding addressing scheme, the
memory address range extends to 00000H – 1FFFFH. Thus, the remaining memory addressing
range of the processor will be 20000H – 3FFFFH, and its size is 128k bytes. Since the memory
address range of the processor is 00000H – 3FFFFH, the maximum size of the memory is 256k
bytes, which states the number of address lines to be 18.

QUESTION 8:
The decimal equivalent of (1001.011)2 is

a. 9.375

b. 9.325

c. 10.375

d. 10.325

Correct Answer: a

Detailed Solution:
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1 × 23 + 0 × 22 + 0 × 2 + 1 × 20 + 0 × 0.5 + 1 × 0.25 + 1 × 0.125

QUESTION 9:
What is the binary equivalent of the fractional decimal number (27.1875)10?
a. (11011.1101)2
b. (11011.0011)2
c. (11101.1001)2
d. (11011.0001)2

Correct Answer: b

Detailed Solution:

At first, split the decimal number to non-fractional part and the fractional part
27.1875 = 27 (non-fraction) + 0.1875(fraction)
Binary equivalent of 27 = 11011
To convert the fraction
0.1875 × 2 = 0.375
0.375 × 2 = 0.75
0.75× 2 = 1.5
0.5× 2 = 1.0
Thus (0.1875)10 = (0.0011)2

Combining we have 27.1875 = 11011.0011

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QUESTION 10:
The fractional binary number (0.11)2 has a decimal value of
a. (¼)10
b. (½)10
c. (¾)10
d. None of the above

Correct Answer: c

Detailed Solution:

The decimal equivalent would be (1×0.51)+ (1×0.52) = ¾

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QUESTION 11:
Possible values of x and y satisfying (2x)5 = (3y)6 are
a. x=9, y=1
b. x =8, y=1
c. x =1, y=9
d. None of these

Correct Answer: d

Detailed Solution:

(2x)5 = (3y)6

2*5 + x = 3*6 + y

x–y = 8

Further, since digits for a number system with base d can only range from 0,1,….,d-1.

For base 5 , possible x could be 0,1,2,3,4

For base 6 , possible y could be 0,1,2,3,4,5

Hence, we can see no possible combination of x and y can make the equation true.

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QUESTION 12:
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Which of the following represents the Sum of Products expression for the function
f(W, X, Y, Z) = ∑(0,1,3,5,14) + d(8,15)
a. W’Y’Z + W’X’Z + W’X’Y’ + X’Y’Z’
b. W’Y’Z + W’X’Y’ + WXY + X’Y’Z’
c. W’Y’Z + W’X’Z + WXY + W’X’Y’
d. W’Y’Z + W’X’Z + WXY + W’X’Y

Correct Answer: c

Detailed Solution:

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QUESTION 13:
What are the minimum number of 2-input NOR gates required for implementing a 2-input XNOR
function?
a. 3
b. 4
c. 5
d. 6

Correct Answer: b

Detailed Solution:
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QUESTION 14:
Which of the following statements is true?
a. Carry Look Ahead adders are faster than Ripple Carry Adder and require more logic
resources compared to Ripple Carry Adder.
b. Carry Look Ahead adders are slower than Ripple Carry Adder and require less logic resources
compared to Ripple Carry Adder.
c. Carry Look Ahead adders are faster than Ripple Carry Adder and require less logic resources
compared to Ripple Carry Adder.
d. Carry Look Ahead adders are slower than Ripple Carry Adder and require more logic
resources compared to Ripple Carry Adder.

Correct Answer: a

Detailed Solution:

Carry Look Ahead adders are faster than Ripple Carry Adder and require more logic
resources compared to Ripple carry adder

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QUESTION 15:
While executing a particular instruction following control signals are activated at different clock
cylces. Identify the possible executed instruction.
t1 : Enablepc , Memoryread
t2 : LoadIR
t3: Decode, Incrementpc
t4 : LoadW, EnableIR, EnableW , Memorywrite
t5: EnableW, Memorywrite , EnableR3
a. Load R3,2000
b. Store R3,2000
c. Store R2,3000
d. Load R2,3000

Correct Answer: b

Detailed Solution:

Store R3,2000 stores the value of R3 in memory address location 2000. For that we need to activate
memory write signal and enable R3 register as shown in clock cycle t5.

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