Week 8

Memory and Memory Interfacing

 Semiconductor Memory Fundamentals
• In the design of all computers, semiconductor memories are used as
primary storage for data and code.
• They are connected directly to the CPU and they are the memory
that the CPU asks for information (code or data)
• Among the most widely used are RAM and ROM
• Memory Capacity
– The number of bits that a semiconductor memory chip can store
is called its chip capacity (bits or bytes)
• Memory Organization
– Each memory chip contains 2x locations where x is the number
of address pins on the chip
– Each location contains y bits, where y is the number of data pins
on the chip
– The entire chip will contain 2x * y bits
– Ex. Memory organization of 4K x 4: 212 = 4096 locations, each
location holding 4 bits
• Memory Speed (access time)
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Memory

• Each memory device has at least one chip select (CS)

or chip enable (CE) or select (S) pin that enables the
memory device.
– This enables read and/or write operations.
• Each memory device has at least one control pin.
– For ROMs, an output enable (OE) or gate (G) is present. The
OE pin enables and disables a set of tristate buffers.
– For RAMs, a read-write (R/W) or write enable (WE) and read
enable (OE) are present

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 Memory Types
•ROM (Read Only Memory
™ ROM is the type of memory that does not lose its contents when
power is turned off. It is also called nonvolatile memory.
™PROM (Programmable Memory)
¾User programmable (one-time programmable) memory
¾If the information burned into PROM is wrong, it needs to be
discarded since internal fuses are blown permanently.
¾Special equipment needed: ROM burner or ROM programmer
™EPROM (Erasable Programmable ROM) 2,000 times
¾Allows making changes in the contents of PROM after it is burned
¾One can program the memory chip and erase it thousands of times
¾Erasing its contents can take up to 20 minutes; the entire chip is
erased
¾All EPROM chips have a window that is used to shine ultraviolet
(UV) radiation to erase its contents
¾Also referred to as UV-EPROM

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 Memory Types

™ EEPROM (Electrically Erasable ROM) 500,000 times

¾ Method of erasure is electrical
¾ Moreover, one can select which byte to be erased
¾ Cost per bit is much higher than for UV-EPROM
™ Flash Memory EPROM
¾ First, the process of erasure of the entire contents takes less
than a second, or one might say in a flash, hence its name:
flash memory
¾ When flash memory’s contents are erased, the entire device is
erased.
¾ Even though flash memories are writeable, like EPROMs they
find their widest use in microcomputer systems for storage of
firmware
™ RAM (Random Access Memory) infinite times
¾ RAM memory is called volatile memory since cutting off the
power to the IC will mean the loss of data.
¾ Also referred to as R/WM (Read And Write Memory)

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Minmode 8088 Microcomputer system memory circuitry

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Minmode 8086 Microcomputer system memory circuitry

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Maxmode 8088 Microcomputer system memory circuitry

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Memory Interface

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Bank Write Control Logic

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Bank Read Control Logic

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Address Bus Configuration with Address Decoding

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Address Latch Circuit

ALE

BHE

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Generation of MEMRD & MEMWR in Minmode

Control Signal Generation Circuit

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8088 Memory and I/O address spaces

We first look at the memory addressing

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Address Selection

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74F139 2-line to 4-line decoder

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Memory Address Decoding

3-8 Decoder
(for example: 74LS138)

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Address Decoder Circuit

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 Example on Address Decoding
A circuit containing 32KB of RAM is to be interfaced to an 8088 based system,
so that the first address of the RAM is at 48000H. What is the entire range of
the RAM Address? How is the address bus used to enable the RAMs? What
address lines should be used?

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Example on Address Decoding

Memory Address Decoder for 48000 to 4FFFF Range

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Memory Address Decoding

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Memory Address Decoding

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 512 K of SRAM 00000-7FFFF
Memory Addressing

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Partial Address Decoding
Not all the address lines need to be used.(A14-A19 not used).
So FFFF0, 3BFF0, 07FF0 pr C3FF0 get the same data.
(+) The purpose is get the job done in minimum hardware.
(-) Feature expansion of the memory is impossible, and may cause invalid
data reads due to overlapping memory segment reads (a fatal error)

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 Partial Address Decoding

Foldback memory exists

A0-
A0-A12

A13 A13

A14

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Generating Wait States in Hardware

9Ready signal can be

generated by special
hardware using the SEL’
signal from the address
decoder.
9The circuit above will
generate two clock periods
of zero signal for the
READY output.
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A complete RAM/EPROM Memory

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Examples: Find different addressing for CS (A0-A13 used by memories)

10x1 10/xx xxxx xxxxxxxx x011 0x/xx xxxx xxxxxxxx

01xx x0/xx xxxx xxxxxxxx (A19 and A18=0) or A16=1 or A14=1

xx1x xx/xx xxx x xxxxxxxx 29

ROM

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ROM

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EPROM

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EPROM Critical Timing

This EPROM would need a READY generation to work with a 8086 with
5Mhz.
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 RAM types
• SRAM (Static RAM)
– Storage cells are made of flip-flops and therefore they do not require refreshing
to keep their data
– Cells handling one bit requires 6 or 4 transistors each, which is too many
– SRAMS are widely used for cache memory and battery-backed memory
systems.
– Speeds as fast as 10ns. But limited in size ~256Kx8
• DRAM (Dynamic RAM)
– Uses MOS capacitors to store a bit
– Requires constant refreshing due to leakage (every 2ms – 4ms)
– Advantages
• High density (capacity) ~1GBX8
• Cheaper cost per bit
• Lower power consumption
– Disadvantage
• While it is being refreshed, data cannot be accessed
• Larger access times
• Too may pins due to large size

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SRAM

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SRAM

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DRAM

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DRAM
ƒ In DRAM, the 8
address lines are
latched accordingly
by the strobe of the
RAS and CAS
signals.
ƒ For example: To
load a 16 bit address
into the DRAM 8 bits
of the address are first
latched by pulling
RAS low, then other 8
bits are presented to
A0-A7 and CAS is
pulled low.

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DRAM Internal

Refresh time example:

For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us
(4ms/256).
For the 8086, a read or write occurs every 800ns.
This allows 19 memory reads/writes per refresh or 5% of the time.
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DRAM Addressing

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 DRAM Packaging

Larger DRAMs are available which are organized as 1M X 1, 4M X 1, 16M X 1, 64M X 1, 256M X 1.
DRAMs are typically placed on SIMM (Single In-line Memory Modules) boards.
30-pin SIMMs come in 1M X 8, 1M X 9 (parity), 4M X 8, 4M X 9.
72-pin SIMMs come in 1/2/3/8/16M X 32 or 1M X 36 (parity).

Pentiums have a 64-bit wide data bus.

The 30-pin and 72-pin SIMMs are not used on these systems.
Rather, 64-bit DIMMs (Dual In-line Memory Modules) are the standard.
These organize the memory 64-bits wide.
The board has DRAMs mounted on both sides and is 168 pins 41
DRAM Refresh

ƒ DRAM can be
refreshed by an
external circuitry
including an 8 bit
counter
RAS only ƒHOLD/HLDA used
Refresh
ƒ Only the columns of
the matrix (256 x 256
for a 64K bit matrix is
needed to be
refreshed.
ƒ The refresh rate can
be adjusted using a
555 timer circuitry.
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DRAM in PC

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Parity circuits

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Parity circuits

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Parity Error Detection Circuit

64Kx8
64Kx8

64Kx1

Parity Detect

Parity Generate 46
Checksum byte (used for ROM)
9 Add the bytes together and drop the carries
9Take the 2’s complement of the total sum, and that is the checksum byte,
which becomes the last byte of the stored information.
9 To perform the checksum operation add all the bytes, including the
checksum byte. The result must be zero. If it is not zero, one or more bytes
of data have been changed (corrupted)
Example: Assume that we have 5 bytes of hexadecimal data: 1A, 14, 82, FC, 3E.
a) Find the checksum byte
b) Perform the checksum operation to ensure integrity
c) If the 3rd byte is changed to 44 show how the error is detected?

a) The checksum is: 1A+14+82+FC+3E = 1EA drop 1 Æ EA , take 2’s comp => 16
b) 1A+14+82+FC+3E+16 = 00
c) 1A+14+44+FC+3E+16 = 1C2 Æ Error!

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IBM PC Memory Map
• 00000h – 9FFFFh: RAM (640 Kb)
– The first 1K used for the interrupt vector table (00000h to 003FFh)
– 00400h to 004FFh is set aside for the BIOS temporary area
– 00500h to 005FFh is set aside for the temporary storage of certain
parameters in DOS and BASIC
– A certain number of Kbytes is occupied by the operating system itself
• A0000h – BFFFFh: Video Display RAM (128 Kb)
– A total of 128 Kbytes is allocated for video
– Of that 128K, only a portion is used for VDR, the amount depending on
which type of video adapter card is installed in the system
• C0000h – FFFFFh: ROM (256 Kb)
– 256 K is set aside for ROM
– Used in
• BIOS ROM, Basic language compiler ROM, hard disk controller, other
peripheral board ROMS and the rest for expansion by the user

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IBM PC Memory Map

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IBM PC Memory Map

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